JP2015508193A5 - - Google Patents
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- Publication number
- JP2015508193A5 JP2015508193A5 JP2014553538A JP2014553538A JP2015508193A5 JP 2015508193 A5 JP2015508193 A5 JP 2015508193A5 JP 2014553538 A JP2014553538 A JP 2014553538A JP 2014553538 A JP2014553538 A JP 2014553538A JP 2015508193 A5 JP2015508193 A5 JP 2015508193A5
- Authority
- JP
- Japan
- Prior art keywords
- slave device
- request
- bus
- write data
- remote
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 claims 6
- 230000008685 targeting Effects 0.000 claims 4
- 230000000903 blocking effect Effects 0.000 claims 1
- 239000004065 semiconductor Substances 0.000 claims 1
Applications Claiming Priority (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US201261589582P | 2012-01-23 | 2012-01-23 | |
| US61/589,582 | 2012-01-23 | ||
| US13/669,629 | 2012-11-06 | ||
| US13/669,629 US20130191572A1 (en) | 2012-01-23 | 2012-11-06 | Transaction ordering to avoid bus deadlocks |
| PCT/US2013/022785 WO2013112612A1 (en) | 2012-01-23 | 2013-01-23 | Transaction ordering to avoid bus deadlocks |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2015508193A JP2015508193A (ja) | 2015-03-16 |
| JP2015508193A5 true JP2015508193A5 (enExample) | 2016-02-18 |
Family
ID=48798191
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2014553538A Pending JP2015508193A (ja) | 2012-01-23 | 2013-01-23 | バスデッドロックを回避するためのトランザクション順序付け |
Country Status (7)
| Country | Link |
|---|---|
| US (1) | US20130191572A1 (enExample) |
| EP (2) | EP2899642A1 (enExample) |
| JP (1) | JP2015508193A (enExample) |
| KR (1) | KR20140125391A (enExample) |
| CN (1) | CN104067250A (enExample) |
| TW (1) | TWI489288B (enExample) |
| WO (1) | WO2013112612A1 (enExample) |
Families Citing this family (36)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8885510B2 (en) | 2012-10-09 | 2014-11-11 | Netspeed Systems | Heterogeneous channel capacities in an interconnect |
| US20160062930A1 (en) * | 2013-03-25 | 2016-03-03 | Mitsubishi Electric Corporation | Bus master, bus system, and bus control method |
| US9471726B2 (en) | 2013-07-25 | 2016-10-18 | Netspeed Systems | System level simulation in network on chip architecture |
| US9473388B2 (en) | 2013-08-07 | 2016-10-18 | Netspeed Systems | Supporting multicast in NOC interconnect |
| US9294354B2 (en) * | 2013-10-24 | 2016-03-22 | Netspeed Systems | Using multiple traffic profiles to design a network on chip |
| US9699079B2 (en) | 2013-12-30 | 2017-07-04 | Netspeed Systems | Streaming bridge design with host interfaces and network on chip (NoC) layers |
| US9473415B2 (en) | 2014-02-20 | 2016-10-18 | Netspeed Systems | QoS in a system with end-to-end flow control and QoS aware buffer allocation |
| US9742630B2 (en) | 2014-09-22 | 2017-08-22 | Netspeed Systems | Configurable router for a network on chip (NoC) |
| US9571341B1 (en) | 2014-10-01 | 2017-02-14 | Netspeed Systems | Clock gating for system-on-chip elements |
| US9602464B2 (en) * | 2014-12-12 | 2017-03-21 | Intel Corporation | Apparatus, system and method for allocating identifiers to components of a control system |
| US9660942B2 (en) | 2015-02-03 | 2017-05-23 | Netspeed Systems | Automatic buffer sizing for optimal network-on-chip design |
| US9444702B1 (en) | 2015-02-06 | 2016-09-13 | Netspeed Systems | System and method for visualization of NoC performance based on simulation output |
| US9568970B1 (en) | 2015-02-12 | 2017-02-14 | Netspeed Systems, Inc. | Hardware and software enabled implementation of power profile management instructions in system on chip |
| US9928204B2 (en) | 2015-02-12 | 2018-03-27 | Netspeed Systems, Inc. | Transaction expansion for NoC simulation and NoC design |
| US10050843B2 (en) | 2015-02-18 | 2018-08-14 | Netspeed Systems | Generation of network-on-chip layout based on user specified topological constraints |
| US10348563B2 (en) | 2015-02-18 | 2019-07-09 | Netspeed Systems, Inc. | System-on-chip (SoC) optimization through transformation and generation of a network-on-chip (NoC) topology |
| US9825809B2 (en) | 2015-05-29 | 2017-11-21 | Netspeed Systems | Dynamically configuring store-and-forward channels and cut-through channels in a network-on-chip |
| US9864728B2 (en) | 2015-05-29 | 2018-01-09 | Netspeed Systems, Inc. | Automatic generation of physically aware aggregation/distribution networks |
| US10218580B2 (en) | 2015-06-18 | 2019-02-26 | Netspeed Systems | Generating physically aware network-on-chip design from a physical system-on-chip specification |
| US10025741B2 (en) * | 2016-01-13 | 2018-07-17 | Samsung Electronics Co., Ltd. | System-on-chip, mobile terminal, and method for operating the system-on-chip |
| US10452124B2 (en) | 2016-09-12 | 2019-10-22 | Netspeed Systems, Inc. | Systems and methods for facilitating low power on a network-on-chip |
| KR20180062807A (ko) | 2016-12-01 | 2018-06-11 | 삼성전자주식회사 | 시스템 인터커넥트 및 이를 포함하는 시스템 온 칩 |
| US20180159786A1 (en) | 2016-12-02 | 2018-06-07 | Netspeed Systems, Inc. | Interface virtualization and fast path for network on chip |
| US10313269B2 (en) | 2016-12-26 | 2019-06-04 | Netspeed Systems, Inc. | System and method for network on chip construction through machine learning |
| US10063496B2 (en) | 2017-01-10 | 2018-08-28 | Netspeed Systems Inc. | Buffer sizing of a NoC through machine learning |
| US10084725B2 (en) | 2017-01-11 | 2018-09-25 | Netspeed Systems, Inc. | Extracting features from a NoC for machine learning construction |
| US10469337B2 (en) | 2017-02-01 | 2019-11-05 | Netspeed Systems, Inc. | Cost management against requirements for the generation of a NoC |
| US10298485B2 (en) | 2017-02-06 | 2019-05-21 | Netspeed Systems, Inc. | Systems and methods for NoC construction |
| US20190020586A1 (en) * | 2017-07-14 | 2019-01-17 | Qualcomm Incorporated | Selective insertion of a deadlock recovery buffer in a bus interconnect for deadlock recovery |
| US11144457B2 (en) | 2018-02-22 | 2021-10-12 | Netspeed Systems, Inc. | Enhanced page locality in network-on-chip (NoC) architectures |
| US10547514B2 (en) | 2018-02-22 | 2020-01-28 | Netspeed Systems, Inc. | Automatic crossbar generation and router connections for network-on-chip (NOC) topology generation |
| US10896476B2 (en) | 2018-02-22 | 2021-01-19 | Netspeed Systems, Inc. | Repository of integration description of hardware intellectual property for NoC construction and SoC integration |
| US10983910B2 (en) | 2018-02-22 | 2021-04-20 | Netspeed Systems, Inc. | Bandwidth weighting mechanism based network-on-chip (NoC) configuration |
| US11176302B2 (en) | 2018-02-23 | 2021-11-16 | Netspeed Systems, Inc. | System on chip (SoC) builder |
| US11023377B2 (en) | 2018-02-23 | 2021-06-01 | Netspeed Systems, Inc. | Application mapping on hardened network-on-chip (NoC) of field-programmable gate array (FPGA) |
| FR3094810B1 (fr) * | 2019-04-03 | 2023-01-13 | Thales Sa | Système sur puce comprenant une pluralité de ressources maitre |
Family Cites Families (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0535822B1 (en) * | 1991-09-27 | 1997-11-26 | Sun Microsystems, Inc. | Methods and apparatus for locking arbitration on a remote bus |
| US5673399A (en) * | 1995-11-02 | 1997-09-30 | International Business Machines, Corporation | System and method for enhancement of system bus to mezzanine bus transactions |
| US6260093B1 (en) * | 1998-03-31 | 2001-07-10 | Lsi Logic Corporation | Method and apparatus for arbitrating access to multiple buses in a data processing system |
| US6745272B2 (en) * | 2001-04-04 | 2004-06-01 | Advanced Micro Devices, Inc. | System and method of increasing bandwidth for issuing ordered transactions into a distributed communication system |
| US7743223B2 (en) * | 2003-08-18 | 2010-06-22 | Cray Inc. | Decoupling of write address from its associated write data in a store to a shared memory in a multiprocessor system |
| TWI321841B (en) * | 2005-04-29 | 2010-03-11 | Taiwan Semiconductor Mfg | System on chip development with reconfigurable multi-project wafer technology |
| US8082426B2 (en) * | 2008-11-06 | 2011-12-20 | Via Technologies, Inc. | Support of a plurality of graphic processing units |
| NL2003699A (en) * | 2008-12-18 | 2010-06-21 | Brion Tech Inc | Method and system for lithography process-window-maximixing optical proximity correction. |
| US8698823B2 (en) * | 2009-04-08 | 2014-04-15 | Nvidia Corporation | System and method for deadlock-free pipelining |
| US8285912B2 (en) * | 2009-08-07 | 2012-10-09 | Arm Limited | Communication infrastructure for a data processing apparatus and a method of operation of such a communication infrastructure |
| US20130054852A1 (en) * | 2011-08-24 | 2013-02-28 | Charles Fuoco | Deadlock Avoidance in a Multi-Node System |
-
2012
- 2012-11-06 US US13/669,629 patent/US20130191572A1/en not_active Abandoned
-
2013
- 2013-01-23 KR KR1020147023269A patent/KR20140125391A/ko not_active Withdrawn
- 2013-01-23 WO PCT/US2013/022785 patent/WO2013112612A1/en not_active Ceased
- 2013-01-23 JP JP2014553538A patent/JP2015508193A/ja active Pending
- 2013-01-23 EP EP15158870.4A patent/EP2899642A1/en not_active Withdrawn
- 2013-01-23 CN CN201380006136.7A patent/CN104067250A/zh active Pending
- 2013-01-23 EP EP13707467.0A patent/EP2807569B1/en not_active Not-in-force
- 2013-01-23 TW TW102102519A patent/TWI489288B/zh not_active IP Right Cessation
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