KR20140125391A - 버스 데드록들을 피하기 위한 트랜잭션 순서화 - Google Patents

버스 데드록들을 피하기 위한 트랜잭션 순서화 Download PDF

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Publication number
KR20140125391A
KR20140125391A KR1020147023269A KR20147023269A KR20140125391A KR 20140125391 A KR20140125391 A KR 20140125391A KR 1020147023269 A KR1020147023269 A KR 1020147023269A KR 20147023269 A KR20147023269 A KR 20147023269A KR 20140125391 A KR20140125391 A KR 20140125391A
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South Korea
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request
address
slave
remote
interconnects
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Korean (ko)
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프루드비 엔. 누니
자야 프라카쉬 수브라마니암 가나산
배리 조 울포드
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퀄컴 인코포레이티드
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4027—Coupling between buses using bus bridges
    • G06F13/4031—Coupling between buses using bus bridges with arbitration
    • G06F13/4036—Coupling between buses using bus bridges with arbitration and deadlock prevention

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  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)
  • Bus Control (AREA)
  • Mobile Radio Communication Systems (AREA)
  • Small-Scale Networks (AREA)
  • Information Transfer Systems (AREA)
KR1020147023269A 2012-01-23 2013-01-23 버스 데드록들을 피하기 위한 트랜잭션 순서화 Withdrawn KR20140125391A (ko)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US201261589582P 2012-01-23 2012-01-23
US61/589,582 2012-01-23
US13/669,629 US20130191572A1 (en) 2012-01-23 2012-11-06 Transaction ordering to avoid bus deadlocks
US13/669,629 2012-11-06
PCT/US2013/022785 WO2013112612A1 (en) 2012-01-23 2013-01-23 Transaction ordering to avoid bus deadlocks

Publications (1)

Publication Number Publication Date
KR20140125391A true KR20140125391A (ko) 2014-10-28

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KR1020147023269A Withdrawn KR20140125391A (ko) 2012-01-23 2013-01-23 버스 데드록들을 피하기 위한 트랜잭션 순서화

Country Status (7)

Country Link
US (1) US20130191572A1 (enExample)
EP (2) EP2899642A1 (enExample)
JP (1) JP2015508193A (enExample)
KR (1) KR20140125391A (enExample)
CN (1) CN104067250A (enExample)
TW (1) TWI489288B (enExample)
WO (1) WO2013112612A1 (enExample)

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US9825809B2 (en) 2015-05-29 2017-11-21 Netspeed Systems Dynamically configuring store-and-forward channels and cut-through channels in a network-on-chip
US10218580B2 (en) 2015-06-18 2019-02-26 Netspeed Systems Generating physically aware network-on-chip design from a physical system-on-chip specification
US10025741B2 (en) * 2016-01-13 2018-07-17 Samsung Electronics Co., Ltd. System-on-chip, mobile terminal, and method for operating the system-on-chip
US10452124B2 (en) 2016-09-12 2019-10-22 Netspeed Systems, Inc. Systems and methods for facilitating low power on a network-on-chip
KR20180062807A (ko) 2016-12-01 2018-06-11 삼성전자주식회사 시스템 인터커넥트 및 이를 포함하는 시스템 온 칩
US20180159786A1 (en) 2016-12-02 2018-06-07 Netspeed Systems, Inc. Interface virtualization and fast path for network on chip
US10313269B2 (en) 2016-12-26 2019-06-04 Netspeed Systems, Inc. System and method for network on chip construction through machine learning
US10063496B2 (en) 2017-01-10 2018-08-28 Netspeed Systems Inc. Buffer sizing of a NoC through machine learning
US10084725B2 (en) 2017-01-11 2018-09-25 Netspeed Systems, Inc. Extracting features from a NoC for machine learning construction
US10469337B2 (en) 2017-02-01 2019-11-05 Netspeed Systems, Inc. Cost management against requirements for the generation of a NoC
US10298485B2 (en) 2017-02-06 2019-05-21 Netspeed Systems, Inc. Systems and methods for NoC construction
US20190020586A1 (en) * 2017-07-14 2019-01-17 Qualcomm Incorporated Selective insertion of a deadlock recovery buffer in a bus interconnect for deadlock recovery
US10983910B2 (en) 2018-02-22 2021-04-20 Netspeed Systems, Inc. Bandwidth weighting mechanism based network-on-chip (NoC) configuration
US10896476B2 (en) 2018-02-22 2021-01-19 Netspeed Systems, Inc. Repository of integration description of hardware intellectual property for NoC construction and SoC integration
US10547514B2 (en) 2018-02-22 2020-01-28 Netspeed Systems, Inc. Automatic crossbar generation and router connections for network-on-chip (NOC) topology generation
US11144457B2 (en) 2018-02-22 2021-10-12 Netspeed Systems, Inc. Enhanced page locality in network-on-chip (NoC) architectures
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Also Published As

Publication number Publication date
WO2013112612A1 (en) 2013-08-01
TWI489288B (zh) 2015-06-21
EP2807569B1 (en) 2017-09-13
TW201346575A (zh) 2013-11-16
JP2015508193A (ja) 2015-03-16
US20130191572A1 (en) 2013-07-25
EP2807569A1 (en) 2014-12-03
CN104067250A (zh) 2014-09-24
EP2899642A1 (en) 2015-07-29

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PA0105 International application

Patent event date: 20140820

Patent event code: PA01051R01D

Comment text: International Patent Application

PG1501 Laying open of application
PC1203 Withdrawal of no request for examination
WITN Application deemed withdrawn, e.g. because no request for examination was filed or no examination fee was paid