JP2015508193A - バスデッドロックを回避するためのトランザクション順序付け - Google Patents

バスデッドロックを回避するためのトランザクション順序付け Download PDF

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JP2015508193A
JP2015508193A JP2014553538A JP2014553538A JP2015508193A JP 2015508193 A JP2015508193 A JP 2015508193A JP 2014553538 A JP2014553538 A JP 2014553538A JP 2014553538 A JP2014553538 A JP 2014553538A JP 2015508193 A JP2015508193 A JP 2015508193A
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request
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slave
interconnect
remote
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JP2015508193A5 (enExample
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プルドゥヴィ・エヌ・ノーネイ
ジャヤ・プラカシュ・スブラマニアム・ガナサン
バリー・ジョー・ウォルフォード
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クアルコム，インコーポレイテッド
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4027—Coupling between buses using bus bridges
    • G06F13/4031—Coupling between buses using bus bridges with arbitration
    • G06F13/4036—Coupling between buses using bus bridges with arbitration and deadlock prevention

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  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)
  • Bus Control (AREA)
  • Information Transfer Systems (AREA)
  • Small-Scale Networks (AREA)
  • Mobile Radio Communication Systems (AREA)
JP2014553538A 2012-01-23 2013-01-23 バスデッドロックを回避するためのトランザクション順序付け Pending JP2015508193A (ja)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US201261589582P 2012-01-23 2012-01-23
US61/589,582 2012-01-23
US13/669,629 2012-11-06
US13/669,629 US20130191572A1 (en) 2012-01-23 2012-11-06 Transaction ordering to avoid bus deadlocks
PCT/US2013/022785 WO2013112612A1 (en) 2012-01-23 2013-01-23 Transaction ordering to avoid bus deadlocks

Publications (2)

Publication Number Publication Date
JP2015508193A true JP2015508193A (ja) 2015-03-16
JP2015508193A5 JP2015508193A5 (enExample) 2016-02-18

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JP2014553538A Pending JP2015508193A (ja) 2012-01-23 2013-01-23 バスデッドロックを回避するためのトランザクション順序付け

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Country Link
US (1) US20130191572A1 (enExample)
EP (2) EP2899642A1 (enExample)
JP (1) JP2015508193A (enExample)
KR (1) KR20140125391A (enExample)
CN (1) CN104067250A (enExample)
TW (1) TWI489288B (enExample)
WO (1) WO2013112612A1 (enExample)

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US9294354B2 (en) * 2013-10-24 2016-03-22 Netspeed Systems Using multiple traffic profiles to design a network on chip
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US9473415B2 (en) 2014-02-20 2016-10-18 Netspeed Systems QoS in a system with end-to-end flow control and QoS aware buffer allocation
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US9602464B2 (en) * 2014-12-12 2017-03-21 Intel Corporation Apparatus, system and method for allocating identifiers to components of a control system
US9660942B2 (en) 2015-02-03 2017-05-23 Netspeed Systems Automatic buffer sizing for optimal network-on-chip design
US9444702B1 (en) 2015-02-06 2016-09-13 Netspeed Systems System and method for visualization of NoC performance based on simulation output
US9568970B1 (en) 2015-02-12 2017-02-14 Netspeed Systems, Inc. Hardware and software enabled implementation of power profile management instructions in system on chip
US9928204B2 (en) 2015-02-12 2018-03-27 Netspeed Systems, Inc. Transaction expansion for NoC simulation and NoC design
US10050843B2 (en) 2015-02-18 2018-08-14 Netspeed Systems Generation of network-on-chip layout based on user specified topological constraints
US10348563B2 (en) 2015-02-18 2019-07-09 Netspeed Systems, Inc. System-on-chip (SoC) optimization through transformation and generation of a network-on-chip (NoC) topology
US9825809B2 (en) 2015-05-29 2017-11-21 Netspeed Systems Dynamically configuring store-and-forward channels and cut-through channels in a network-on-chip
US9864728B2 (en) 2015-05-29 2018-01-09 Netspeed Systems, Inc. Automatic generation of physically aware aggregation/distribution networks
US10218580B2 (en) 2015-06-18 2019-02-26 Netspeed Systems Generating physically aware network-on-chip design from a physical system-on-chip specification
US10025741B2 (en) * 2016-01-13 2018-07-17 Samsung Electronics Co., Ltd. System-on-chip, mobile terminal, and method for operating the system-on-chip
US10452124B2 (en) 2016-09-12 2019-10-22 Netspeed Systems, Inc. Systems and methods for facilitating low power on a network-on-chip
KR20180062807A (ko) 2016-12-01 2018-06-11 삼성전자주식회사 시스템 인터커넥트 및 이를 포함하는 시스템 온 칩
US20180159786A1 (en) 2016-12-02 2018-06-07 Netspeed Systems, Inc. Interface virtualization and fast path for network on chip
US10313269B2 (en) 2016-12-26 2019-06-04 Netspeed Systems, Inc. System and method for network on chip construction through machine learning
US10063496B2 (en) 2017-01-10 2018-08-28 Netspeed Systems Inc. Buffer sizing of a NoC through machine learning
US10084725B2 (en) 2017-01-11 2018-09-25 Netspeed Systems, Inc. Extracting features from a NoC for machine learning construction
US10469337B2 (en) 2017-02-01 2019-11-05 Netspeed Systems, Inc. Cost management against requirements for the generation of a NoC
US10298485B2 (en) 2017-02-06 2019-05-21 Netspeed Systems, Inc. Systems and methods for NoC construction
US20190020586A1 (en) * 2017-07-14 2019-01-17 Qualcomm Incorporated Selective insertion of a deadlock recovery buffer in a bus interconnect for deadlock recovery
US11144457B2 (en) 2018-02-22 2021-10-12 Netspeed Systems, Inc. Enhanced page locality in network-on-chip (NoC) architectures
US10547514B2 (en) 2018-02-22 2020-01-28 Netspeed Systems, Inc. Automatic crossbar generation and router connections for network-on-chip (NOC) topology generation
US10896476B2 (en) 2018-02-22 2021-01-19 Netspeed Systems, Inc. Repository of integration description of hardware intellectual property for NoC construction and SoC integration
US10983910B2 (en) 2018-02-22 2021-04-20 Netspeed Systems, Inc. Bandwidth weighting mechanism based network-on-chip (NoC) configuration
US11176302B2 (en) 2018-02-23 2021-11-16 Netspeed Systems, Inc. System on chip (SoC) builder
US11023377B2 (en) 2018-02-23 2021-06-01 Netspeed Systems, Inc. Application mapping on hardened network-on-chip (NoC) of field-programmable gate array (FPGA)
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JPH09146878A (ja) * 1995-11-02 1997-06-06 Internatl Business Mach Corp <Ibm> データ処理システム及びデータ処理方法

Also Published As

Publication number Publication date
EP2807569A1 (en) 2014-12-03
TW201346575A (zh) 2013-11-16
TWI489288B (zh) 2015-06-21
US20130191572A1 (en) 2013-07-25
EP2899642A1 (en) 2015-07-29
WO2013112612A1 (en) 2013-08-01
CN104067250A (zh) 2014-09-24
KR20140125391A (ko) 2014-10-28
EP2807569B1 (en) 2017-09-13

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