JP2015225390A - Effect application device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an effect application device capable of performing a satisfactory clear operation by reducing the number of times of program transfer, and shortening a memory clear time.SOLUTION: When a new program is transferred, the memory clear command of an external memory 20 is transmitted to an interface memory 14 so that the memory clear of the external memory 20 can be executed, and that a new program can be transferred to a program memory 10. After the memory clear of the external memory 20 is executed, a command corresponding to the new program is transferred only to the interface memory 14 so that an arithmetic part 12 can be allowed to execute processing following the new program.

Description

  The present invention relates to an effect imparting device including a digital signal processor (DSP) used in an electronic musical instrument, a sound field control device, and the like, which can easily clear an external memory.

  FIG. 8 is a block diagram schematically showing an effect applying device configured by a DSP 1 that applies an acoustic effect (effect) to a musical sound of a conventional electronic musical instrument disclosed in Patent Document 1 below.

  In the figure, a musical sound signal output from the musical sound generating device 200 is input to a DSP (digital signal processor) 1. On the other hand, the DSP 1 is connected to an external memory (delay memory) 20 and is also connected to the CPU 22 via the system bus 100. The DSP 1 performs arithmetic processing inside the DSP 1 in addition to the coefficient memory 16 for storing coefficients. A program memory 10 that can be changed to this program is also incorporated.

  The electronic musical instrument configured as described above generally operates as follows. The tone signal output from the tone generation device 200 is input to the DSP 1 where various effects are applied. At that time, the DSP 1 stores various effect programs transmitted from the CPU 22 and the coefficients used therein in the program memory 10 and the coefficient memory 16, and performs arithmetic processing on the tone signal based on them. Then, a musical sound signal to which an acoustic effect is given is generated. In particular, when a reverberation effect is applied, an external memory 20 (delay memory) is connected to the outside of the DSP 1, and the result of the arithmetic processing in the DSP 1 is temporarily stored therein using the external memory 20. In other words, the musical sound signals output with a delay by the arithmetic processing are processed one after another, and a reverberation effect is given. Thereafter, the signal is input to the D / A converter 202 and converted into an analog signal. The analog signal is output from a sound system 204 (such as an amplifier or a speaker).

These acoustic effects include various reverberation effects. In order to deal with these effects, various effects programs and coefficients used therefor are sent from the CPU 22 to the program memory 10 and the coefficient memory 16 at a certain timing. Replacement is performed.
JP 2002-358080 A

  When the DSP 1 replaces and processes a plurality of programs, it is necessary to clear the external memory 20 before executing a new program.

  As a method for performing such memory clear, there are 1) a method for transferring and executing a clear-only program, and 2) a method for executing a clear operation by temporarily changing a coefficient of a normal program.

  However, in the case of 1), there is a problem that the number of program transfers increases because another program is transferred and executed before transferring the program to be originally executed. In the case of 2), since it is not a clear-only program, there is a problem that it takes time to complete the clear.

  The present invention has been devised in view of such circumstances, and it is an object of the present invention to provide an effect imparting device that can perform a clear operation with a small number of program transfers and a short memory clear time.

The configuration of the effect applying device according to the present invention is as follows.
A program memory for storing a processing program;
An arithmetic unit that performs an input signal effect applying process according to a processing program stored in the program memory;
An external memory capable of data input / output and temporary storage by the arithmetic unit;
At least an interface memory capable of controlling access to the external memory by an external command,
At the time of new program transfer, a command for memory clear operation is set from the outside to the interface memory, the interface memory executes memory clear of the external memory according to this command, After the memory clear is completed, a command corresponding to the new program is written only in the interface memory, and the interface memory has a basic feature that allows the arithmetic unit to execute processing according to the new program in accordance with this command. .

  According to the above configuration, the memory clear of the external memory is executed by sending a command to clear the memory of the external memory to the interface memory, and the next new program is transferred to the program memory. Then, after clearing the memory of the external memory, a command corresponding to the new program is transferred only to the interface memory, so that the interface memory causes the arithmetic unit to execute processing according to the new program according to the command. Is possible. Therefore, it is possible to perform a clear operation with a small number of program transfers and a short time for clearing the external memory.

  According to the above configuration of the present invention, the memory clear command of the external memory is executed by sending the memory clear command of the external memory to the interface memory, the next new program is transferred to the program memory, and the memory of the external memory After clearing, since the command corresponding to the new program is transferred only to the interface memory, the interface memory can cause the arithmetic unit to execute processing according to the new program according to the command. It is possible to obtain an excellent effect that a good clear operation can be performed with a small number of program transfers and a short time for clearing the external memory.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  FIG. 1 is a schematic diagram showing the configuration of an embodiment of the present invention that applies an arbitrary acoustic effect (effect) to a musical sound, called an effector.

  As shown in the figure, this configuration is centered on the DSP 1, a program memory 10 that stores a processing program, and an arithmetic unit 12 that performs an input signal effect applying process according to the processing program stored in the program memory 10. The external memory 20 used as a delay memory outside the DSP 1 and capable of data input / output / temporary storage by the arithmetic unit 12 (directly connected to an interface memory 14 described later), and the above-mentioned by an external command The external memory 20 has an interface memory 14 capable of controlling access, and in addition, a coefficient memory 16 for storing coefficients used in various effect programs in the arithmetic unit 12 in the DSP 1. And a data memory 18 for storing data necessary for processing in the arithmetic unit 12. Rutotomoni located at DSP1 outside, and at least a CPU22 which are connected to DSP1 via the system bus (not shown).

  FIG. 2 is a configuration diagram showing a basic configuration of the DSP 1. Here, the program memory 10 is not connected anywhere, but controls the overall operation. In accordance with the program stored in the program memory 10 and various coefficients stored in the coefficient memory 16, the arithmetic unit 12 of the DSP 1 forms a circuit configuration as shown in FIG.

  In the configuration shown in the figure, a data bus (D_Bus) 100d and a coefficient bus (C_Bus) 100c are provided in the DSP 1, and an audio I / O (102) is connected to the data bus (D_Bus) 100d. ), Data memory 20, external memory I / O (104), multiplier 106 and barrel shifter 108, adder 120 and accumulator 122, coefficient bus 18 (C_Bus), coefficient memory 18, multiplier 106 and barrel shifter 108, the adder 120 and the accumulator 122 are connected to each other.

  The musical tone signal (In_reg) input from the audio I / O (102) is input to the multiplier 106 as D_in, and the predetermined coefficient C (n) extracted from the coefficient memory 18 is also input to the multiplier 106 by C_in. Are multiplied by each other, shifted by a predetermined number of bits (Shift_val) by the barrel shifter 108, and added to the value of the accumulator 122 by the next adder 120.

  FIG. 3 shows an equivalent circuit configuration of the delay circuit. As shown in the figure, the musical tone signal (In_reg) input from the audio I / O (102) is multiplied by the coefficient C (c_in) read from the coefficient memory 18 by the multiplier 106, and the multiplication value is obtained. Passes through the barrel shifter 108 and is stored in the accumulator 122 as A_reg.

  Data T (r_dat2) out of the data T (r_dat1) and T (r_dat2) read from the external memory 20 is multiplied by the coefficient C (c_fb) from the coefficient memory 18 as the input D_in by the multiplier 106. It is added to A_reg already stored in the accumulator 122 by the adder 120, and it is written to the external memory 20 as data T (w_dat) to be written to the external memory 20 via the interface memory 14. .

  Data T (r_dat1) read from the external memory 20 is multiplied by D_in, and coefficient C (c_05) (its value is 0.5) read from the coefficient memory 18 is multiplied by the multiplier 106 as C_in. The multiplication value is shifted (* 2) by the barrel shifter 108, stored in the accumulator 122 (A_reg), and the value A_reg of the accumulator 122 is output from the audio I / O (102) as the right output Out_R.

  On the other hand, the data T (r_dat2) read again from the external memory 20 via the interface memory 14 is D_in, and the coefficient C (c_05) (its value is 0.5) read from the coefficient memory 18 is C_in. Multiplyed by the multiplier 106, the multiplied value is shifted (* 2) by the barrel shifter 108 and stored in the accumulator 122 (A_reg). The value A_reg of the accumulator 122 is output from the audio I / O (102) to the left output. Output as Out_L.

  In this way, a delay circuit is realized by repeatedly processing a part of musical sound signals via the delay memory.

  FIG. 4 is a schematic explanatory diagram showing the state of data access to the external memory 20 by the interface memory 14 used in the configuration of the present invention. This figure shows the state of the interface memory 14 during the normal operation of the delay of FIG. At this time, the area that can be used as an effect is 0x00 to 0x07, and 0x06 and 0x07 are not used in the delay.

  The first address (0 × 00) of the interface memory 14 has a write command (w) to the external memory 20 and the write destination address (w_adr) of the external memory 20, and the next address (0 × 01) There is data content (w_dat) to be written. According to this, data (w_dat) is written to the address (w_dar) of the external memory 20.

  Thereafter, the address (0 × 02) of the interface memory 14 includes the read instruction (R) to the external memory 20 and the read destination address (r_adr1) of the external memory 20, and the next address (0 × 03) A storage area that should be read from the address is provided, and in accordance with the storage area, the state in which the data (r_dat1) is read from the read destination address (r_adr1) of the external memory 20 is shown.

  Similarly, the address (0 × 04) of the interface memory 14 includes a read command (R) to the external memory 20 and a read destination address (r_adr2) of the external memory 20, and the next address (0 × 05). A storage area that should be read from the address is provided, and a state in which data (r_dat2) is read from the read destination address (r_adr2) of the external memory 20 is shown in accordance with the storage area. Yes.

  FIG. 5 shows a state when data is cleared to the external memory 20 by the interface memory 14. In particular, this figure shows the state of the interface memory 14 for clearing the contents of the external memory 20 when switching to the delay of FIG.

  The first address (0 × 00) of the interface memory 14 has a write command (w) to the external memory 20 and a write destination address (w_adr_clear1) of the external memory 20, and the next address (0 × 01) There is a content of data to write (0; memory clear). According to this, data (0) is written to the address (w_adr_clear1) of the external memory 20, and the memory is cleared.

  Thereafter, the operation of the interface memory 14 repeats the above state until the necessary range of the external memory 20 is reached.

  Since four write operations including addresses 0x06 and 0x07 that are not used in the normal state shown in FIG. 4 can be performed on the external memory 20, the external memory 20 can be cleared at high speed.

  That is, in order to clear the external memory 20 in the normal state shown in FIG. 4, the time waiting is four times that in FIG. 5 with the coefficient values C (c_in) and C (c_fb) in FIG. 3 set to zero. There is a need to.

  FIG. 6 is a flowchart showing a processing flow of effect change processing of the effector.

  When the effect change process is executed by the CPU 22, the effect program is transferred to the program memory 10 according to the command (step S100).

  Next, the effect coefficient is transferred to the coefficient memory 16 in accordance with a command from the CPU 22 (step S102).

  Thereafter, rewriting of the interface memory 14 by the program is prohibited (step S104). The prohibition of rewriting is realized by setting a rewriting prohibition flag provided in the interface memory or temporarily changing the coefficient (c_gain_in is set to zero in the delay circuit of FIG. 3).

  Then, the clearing address and data are transferred to the interface memory 14 (step S106).

  It is checked whether or not a predetermined time has passed (step S108). If it has not passed (step S108; N), the above check is repeated until the time has passed.

  On the other hand, when the predetermined time has elapsed (step S108; Y), the effect address and data are transferred to the interface memory 14 (step S110), and the rewrite prohibition of the interface memory 14 by the program is released (step S112).

The following seven-step program is for realizing the delay processing of FIG. 3, and such a program is stored in the program memory 10.
step1 A_reg = C (c_in) * In_reg
step2 A_reg = C (c_fb) * T (r_dat2) + A_reg
step3 T (w_dat) = A_reg
step4 A_reg = C (c_05) * T (r_dat1) * 2
step5 Out_R = A_reg
step6 A_reg = C (c_05) * T (r_dat2) * 2
step7 Out_L = A_reg
Note that 0.5 is stored in C (c_05) of step 4 and step 6, and * 2 is realized by the shift of the barrel shifter 108.

  FIG. 7 is an explanatory diagram showing the state of each functional block in FIG. 2 when the above program is executed. In the figure, C_src and D_src indicate where the signal flows from the respective buses, and C_Dst and D_Dst indicate where the bus signals flow (always flows to the multiplier 106).

  The above program will be described with reference to FIG.

  In step 1, data C (c_in) at the address c_in of the coefficient memory 16 flows in C_Bus, and data in the input register In_reg of the audio I / O (102) flows in D_Bus. Each bus is connected to a multiplier 106 and is input to C_in and D_in of the multiplier 106.

  The multiplication result is input to A_in of the adder 120 via the barrel shifter 108 in which the shift amount (Shift_val) is set to zero. Zero is selected for B_in of the adder 120.

  As a result, C_in_In_reg that is the output of the multiplier 106 is stored in the A_reg that is the accumulator 122.

  Hereinafter, similarly, each function operates in accordance with the contents of the program up to step 7, thereby realizing a delay.

  According to the configuration of this embodiment described above in detail, by sending a memory clear command of the external memory 20 to the interface memory 14, the memory clear of the external memory 20 is executed, and a new program is transferred to the program memory 10. . Then, after the memory of the external memory 20 is cleared, a command corresponding to the new program is transferred only to the interface memory 14, and the interface memory 14 performs processing according to the new program to the arithmetic unit 12 according to the command. Can be executed. Therefore, a clear-only program is not transferred as in the prior art, and the number of program transfers is reduced, and the clearing time of the external memory 20 is shortened, so that a good clearing operation can be performed.

  It should be noted that the effect imparting device of the present invention is not limited to the illustrated examples described above, and it is needless to say that various modifications can be made without departing from the scope of the present invention.

  The effect imparting device of the present invention is not limited to the configuration of the effector, and has a wide range of use such as an electronic musical instrument.

It is the schematic which shows the structure of the effector which is one Example structure of this invention. It is a block diagram which shows the basic composition of DSP1. It is a functional block diagram which shows the equivalent circuit of the delay circuit comprised by the above DSP1. It is a schematic explanatory drawing which shows the state of the access of the data with respect to external memory by the interface memory used in this invention structure. It is a schematic explanatory drawing which shows the state when data clear is implemented with respect to the external memory by the interface memory. It is a flowchart which shows the processing flow of the effect change process of an effector. It is explanatory drawing which showed what kind of state each functional block of FIG. 2 will be when the program used by the structure of a present Example is performed. It is the block diagram which showed schematically the conventional effect provision apparatus comprised with DSP.

1 DSP
DESCRIPTION OF SYMBOLS 10 Program memory 12 Operation part 14 Interface memory 16 Coefficient memory 18 Data memory 20 External memory 22 CPU
100 System bus 100d Data bus 100c Coefficient bus 102 Audio I / O
104 External memory I / O
106 multiplier 108 barrel shifter 120 adder 122 accumulator 200 musical tone generator 202 D / A converter 204 sound system

Claims (1)

A program memory for storing a processing program;
An arithmetic unit that performs an input signal effect applying process according to a processing program stored in the program memory;
An external memory capable of data input / output and temporary storage by the arithmetic unit;
At least an interface memory capable of controlling access to the external memory by an external command,
At the time of new program transfer, a command for memory clear operation is set from the outside to the interface memory, the interface memory executes memory clear of the external memory according to this command, the new program is transferred to the program memory, After the memory clear is completed, a command corresponding to the new program is written only in the interface memory, and the interface memory causes the arithmetic unit to execute processing according to the new program according to the command. .

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