JP2011118501A - Data transfer system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve the processing efficiency in relation to a read command in a data transfer system having a plurality of control masters for one memory controller. <P>SOLUTION: The data transfer system performs data read processing among the plurality of control masters and a memory connected via the memory controller. The memory controller includes: a route selector which stores, upon receiving the read command, the identifier of the control master regarding the read command in FIFO format; and a read data buffer which stores the read data read from the memory in FIFO format. The control master reads the read data from the read data buffer if the first stored identifier is the one of itself among the identifiers stored in the route selector and the read data is stored in the read data buffer. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a data transfer system that performs data read processing / data write processing between a control master and a memory connected via a memory controller, and in particular, a plurality of control masters are provided for one memory controller. The present invention relates to data read processing in a given data transfer system.

  As shown in FIG. 7, a data transfer system that reads / writes data between a control master 700 and a DRAM 600 connected via a memory controller 500 is widely used. In such a data transfer system, the memory controller 500 receives a read command / write command from the control master 700 and accesses the DRAM 600.

  FIG. 8 shows parameters of a write command and a read command sent from the control master 700 to the memory controller 500. As shown in the figure, when a write command is sent, a W / R identifier indicating a write, a write address indicating a write address, write data as write data, and a part of the write data are masked. Specify the data mask to be used as a parameter. When a read command is sent, a W / R identifier indicating read and a read address indicating a read address are specified as parameters.

  As shown in FIG. 7, the memory controller 500 includes a memory interface 510 that performs access processing to the DRAM 600, a command buffer 520 that stores commands sent from the control master 700, and read data that stores read data read from the DRAM 600. And a buffer 530.

  When a read command is sent from the control master 700, the memory controller 500 reads the data from the designated address of the DRAM 600, stores it as read data in the read data buffer 530, and the read data is sent to the control master 700. Notify that reading is possible.

  Upon receiving a notification from the memory controller 500 that the read data can be read, the control master 700 that has sent the read command acquires the read data from the read data buffer 530.

  In general, in the data transfer system, the control master 700 and the memory controller 500 are configured in a one-to-one correspondence as shown in FIG. In addition, since data reading from the DRAM 600 is performed in the order of the read commands, even when the control master 700 continuously sends read commands to the control master 700, the read data buffer is read according to the notification that the read data can be read. By sequentially acquiring the read data from 530, the read data can be acquired in the order corresponding to the read command sent.

JP 2003-122627 A

  The data transfer system can be applied to various processing apparatuses, but particularly when applied to a semiconductor test apparatus or the like, the processing amount per unit time becomes very important. Therefore, it is conceivable to provide a plurality of control masters 700 for one memory controller 500 as shown in FIG. In the example of this figure, an example is shown in which four control masters 700, ie, control master (1) 700a to control master (4) 700d, are provided.

  In such a configuration, when the memory controller 500 continuously receives write commands from different control masters 700, there is no problem if the write commands are processed in the order stored in the command buffer 520.

  However, when read commands are continuously received from different control masters 700, it is determined which control master 700 the read data read from the DRAM 600 and stored in the command buffer 520 corresponds to. The control master 700 cannot determine.

  For this reason, if the conventional technique is applied as it is, the number of read commands that can be processed at the same time is limited to one, and other read commands are waited. Therefore, the effect of providing a plurality of control masters 700 is sufficiently exerted. Can not.

  Therefore, an object of the present invention is to improve the processing efficiency for a read command in a data transfer system in which a plurality of control masters are provided for one memory controller.

  In order to solve the above problems, a data transfer system of the present invention is a data transfer system that performs data read processing between a plurality of control masters and a memory connected via a memory controller, and the memory controller includes: When a read command is received from any one of the control masters, a root selector that stores the identifier of the control master related to the read command in FIFO format, and a read that stores read data read from the memory according to the read command in FIFO format A data buffer, wherein the control master has an identifier stored first among the identifiers stored in the route selector, and the read data is stored in the read data buffer. If Serial to from the read data buffer, characterized in that the read data is read.

  In the data transfer system of the present invention, the order of read commands received from the control master corresponds to the order of read data stored in the read data buffer. Further, the order of the identifiers of the control masters stored in the route selector corresponds to the order of the control masters that sent the read commands stored in the command buffer. Therefore, the read data read from the read data buffer is read data related to the read command from the control master indicated by the identifier stored first among the identifiers stored in the route selector.

  Therefore, a plurality of read commands from each control master can be received and processed in order. For this reason, the processing efficiency for the read command is improved in the data transfer system.

  Here, the root selector stores the identifier of the control master in the FIFO format, and therefore, when read data is read from the read data buffer, the identifier stored first is erased.

  According to the present invention, it is possible to improve the processing efficiency for a read command in a data transfer system in which a plurality of control masters are provided for one memory controller.

It is a block diagram which shows the structure of the data transfer system which concerns on this embodiment. It is a flowchart explaining the update process of a data validity flag. It is a figure which shows the structure of a route selector. It is a flowchart explaining the update process of the route selector of a memory controller. 5 is a flowchart for explaining read data read processing of each control master 300. It is a timing chart explaining the example of a specific process of this embodiment. It is a block diagram which shows the structure of the conventional data transfer system. It is a figure explaining the parameter of a write command and a read command. It is a block diagram which shows the structure at the time of providing the some control master with respect to one memory controller.

  Embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing the configuration of the data transfer system according to this embodiment. As shown in the figure, the data transfer system 10 includes a memory controller 100, a DRAM 200, and a plurality of control masters 300. The data transfer system 10 includes a plurality of control masters 300 so that parallel processing can be performed. In the example of this figure, an example is shown in which four control masters 300 of control master (1) 300a to control master (4) 300d are provided, but the number of control masters 300 is not limited to four, and the data transfer system The number can be set according to the scale of 10.

  In this embodiment, each control master 300 operates independently and reads / writes data to / from the DRAM 200 via the memory controller 100. The memory controller 100 receives a read command / write command from each control master 300 and accesses the DRAM 100 according to the command.

  The memory controller 100 stores a memory interface 110 that performs access processing to the DRAM 200, a command buffer 120 that stores commands sent from the respective control masters 300 in a FIFO (First In First Out) format, and read data read from the DRAM 200. The read data buffer 130 and the route selector 140 are provided.

  The read data buffer 130 includes a data valid flag 131 that indicates whether there is read data that has not been read by the control master 300 in the read data buffer 130.

  In the present embodiment, when the data valid flag 131 is 1 (ON), it indicates that there is read data that has not been read by the control master 300, and when the data valid flag 131 is 0 (OFF), the control master It is assumed that there is no read data that has not been read by 300, that is, the read data buffer 130 is empty.

  Specifically, the read data buffer 130 updates the data valid flag 131 according to the flowchart shown in FIG. As shown in the figure, it is determined whether there is read data that has not been read in the read data buffer 130 (S101). If there is read data (S101: Yes), the data valid flag 131 is turned on. (S102). On the other hand, when there is no read data in the read data buffer 130 (S101: No), the data valid flag 131 is turned OFF (S103). The above determination is repeated until the data transfer process ends (S104: Yes).

  When the memory controller 100 receives a read command from any of the control masters 300, the route selector 140 is a buffer that stores information indicating the read command from which control master 300 in a FIFO format. It can be set as a structure as shown in FIG.

  In the example of this figure, the area | region which stores the identifier of the control master 300 is provided in the depth of 8 steps | paragraphs 0-7. However, the depth of the route selector 140 is not limited to 8, and can correspond to the scale of the data transfer system.

  Here, the deepest storage area in the route selector 140, that is, an area for storing an identifier stored first and extracted next is referred to as a current route 141.

  The update process of the route selector 140 of the memory controller 100 will be described with reference to the flowchart of FIG. As shown in this figure, when the memory controller 100 receives a read command from any of the control masters 300 (S201: Yes), the identifier of the control master 300 is added to the route selector 140 in the FIFO format (S202). For this reason, the identifiers of the control master 300 are stored in the route selector 140 in the order in which the read commands are received.

  Further, when read data is read from the read data buffer 130 by any of the control masters 300 (S203: Yes), the memory controller 100 updates the route selector 140 (S204). That is, the identifier stored in the current route 141 is discarded, and the depth of the identifier stored in the remaining storage area is shifted to the storage area one level deeper. As a result, the current route 141 is also updated. The above processing is repeated until the data transfer processing ends (S205: Yes).

  In the present embodiment, the order of read commands stored in the command buffer 120 corresponds to the order of read data stored in the read data buffer 130. Further, the order of identifiers of the control master 300 stored in the route selector 140 corresponds to the order of the control master 300 that has sent the read command stored in the command buffer 120. For this reason, the read data read from the read data buffer 130 is read data related to the read command from the control master 300 indicated by the identifier stored in the current route 141.

  Next, read data read processing of each control master 300 will be described with reference to the flowchart of FIG.

  Each control master 300 refers to the current route 141 of the route selector 140 and determines whether or not the current route 141 indicates itself (S301). This may be such that the control master 300 that sent the read command refers to the current route 141 periodically / non-periodically, or the route selector 140 notifies the control master 300 indicated by the current route 141. May be.

  When the current route 141 indicates itself, it means that the processing of the preceding read command has been completed, and the read data read from the read data buffer 130 next corresponds to the read command of itself. . However, it is not known whether the read data has already been read from the DRAM 200 and stored in the read data buffer 130.

  Therefore, when the current route 141 indicates itself (S301: Yes), it is determined whether or not the data valid flag 131 is ON with reference to the data valid flag 131 of the read data buffer 130 (S302). ).

  If the data valid flag 131 is OFF (S302: No), it means that the data reading from the DRAM 200 has not been completed yet, so the process waits until the data valid flag 131 is turned ON.

  If the data valid flag 131 is ON (S302: Yes), it means that the read data related to its own read command can be read (S303), so that when the control master 300 is ready to read, the read data buffer Read data is read from 130 (S304). As a result, the read data related to the read command can be acquired without being mistaken for the read data of the other control master 300.

  Next, a specific processing example of the data transfer system 10 in this embodiment will be described with reference to the timing chart of FIG. In this example, similarly to the above, the depth of the route selector 140 is 8 and the number of the control masters 300 is 4.

  It is assumed that the route selector 140 is empty and the data valid flag 131 is 0 (OFF) at the initial state t1.

  First, it is assumed that a read command R1 is sent from the control master (1) 300a at t2. Since it is a read command, the read command R1 is stored in the command buffer 120, and the identifier C1 of the control master (1) 300a that sent the read command R1 is stored in the route selector 140. Since it is stored first in the route selector 140, C1 becomes the current route 141.

  Therefore, the control master (1) 300a can determine that the next read data read from the read data buffer 130 corresponds to its own read command. However, since the data valid flag 131 is OFF (0) and the read data has not been prepared yet, the data is not read.

  Assume that a write command W1 is sent from the control master (1) 300a at t3. Since it is a write command, the write command W 1 is only stored in the command buffer 120 and not stored in the route selector 140.

  Assume that a read command R2 is sent from the control master (2) 300b at t4. Since it is a read command, the read command R2 is stored in the command buffer 120, and the identifier C2 of the control master (2) 300b that sent the read command R2 is stored in the route selector 140.

  Assume that a write command W2 is sent from the control master (2) 300b at t5. Since it is a write command, the write command W2 is only stored in the command buffer 120 and not stored in the route selector 140.

  At t6, the read command R3 is sent from the control master (3) 300c. At t7, the write command W3 is sent from the control master (3) 300c. At t8, the read command R4 is sent from the control master (4) 300d. Is sent, and at t9, the write command W4 is sent from the control master (4) 300d. As a result, each command is stored in the command buffer 120, and the identifier C3 of the control master (3) 300c that sent the read command R3 and the identifier C4 of the control master (4) 300d that sent the read command R4 are Stored in the route selector 140.

  Assume that the read data RD1 corresponding to the read command R1 at t2 is read from the DRAM 200 and stored in the read data buffer 130 at t9. As a result, the data valid flag 131 is turned ON (1), and the control master (1) 300a can know that the read data has been prepared. Therefore, the control master (1) 300a (the lower CM1 in the figure) reads RD1 from the read data buffer 130.

  When RD1 is read from the read data buffer 130, the read data buffer 130 becomes empty, and the data valid flag 131 is turned OFF (0). Further, the route selector 140 is updated, and the current route 141 is updated from C1 to C2.

  Thereby, the control master (2) 300b can determine that the read data read from the read data buffer 130 next corresponds to its own read command. However, since the data valid flag 131 is OFF (0) and the read data has not been prepared yet, the data is not read.

  Thereafter, it is assumed that a read command R1 is sent from the control master (1) 300a at t10, t11, t12, and t13. As a result, each command is stored in the command buffer 120, and the identifier C1 of the control master (1) 300a is stored in the route selector 140 four times in succession.

  During this time, it is assumed that the read data RD2 corresponding to the read command R2 at t4 is read from the DRAM 200 and stored in the read data buffer 130 at t12. As a result, the data valid flag 131 is turned ON (1), and the control master (2) 300b can know that the read data has been prepared. However, here, because of the processing of the control master (2) 300b, the data is not read immediately but is read at t14.

  For this reason, even if the read data RD3 corresponding to the read command R3 at t6 is read from the DRAM 200 and stored in the read data buffer 130 at t13, the current route 141 indicates C2, so the control master ( 3) 300c cannot read the read data RD3. That is, the reading order of read data is maintained.

  Similarly, at t14, even if the read data RD4 corresponding to the read command R4 at t8 is read from the DRAM 200 and stored in the read data buffer 130, the control master (4) 300d reads the read data RD4. I can't. That is, the reading order of read data is maintained.

  When the control master (2) 300b (CM2) reads the read data RD2 at t14, the current route 141 is updated from C2 to C3, so that the control master (3) 300c (CM3) is read from the read data buffer 130. RD3 can be read.

  Thereby, since the current route 141 is updated from C3 to C4, the control master (4) 300d can know that the read data is prepared. During this time, since the read data continues to exist in the read data buffer 130, the data valid flag 131 is kept in the ON (1) state.

  Thereafter, it is assumed that a write command W1 is sent from the control master (1) 300a at t14 and t15, and a read command R2 is sent from the control master (2) 300a at t16. As a result, each command is stored in the command buffer 120, and the identifier C2 of the control master (2) 300b that sent the read command R2 is stored in the route selector 140.

  Through the processing as described above, the data transfer system 10 can receive a plurality of read commands from each control master 300 and process them in order, thereby improving the processing efficiency for the read commands.

  For this reason, the data transfer system 10 of the present embodiment is particularly effective when applied to an apparatus in which read / write processing such as Read modify write is frequently mixed. More specifically, this is effective when counting FAIL Data in a memory inspection device.

  Note that the storage area of the route selector 140 is almost full at time t13 in FIG. In such a case, in order to prevent the buffer from overflowing, an all-full signal can be sent from the memory controller 100 to each control master 300 to wait for a read command to be issued. Even when the command buffer 120 and the read data buffer 130 are almost full, an all-full signal may be sent to each control master 300 in a similar manner to wait for the corresponding processing.

DESCRIPTION OF SYMBOLS 10 ... Data transfer system, 100 ... Memory controller, 110 ... Memory interface, 120 ... Command buffer, 130 ... Read data buffer, 131 ... Data valid flag, 140 ... Route selector, 141 ... Current route, 200 ... DRAM, 300 ... Control Master, 500 ... Memory controller, 510 ... Memory interface, 520 ... Command buffer, 530 ... Read data buffer, 600 ... DRAM, 700 ... Control master

Claims (2)

A data transfer system for performing data read processing between a plurality of control masters and memories connected via a memory controller,
The memory controller is
When a read command is received from any of the control masters, a route selector that stores the identifier of the control master related to the read command in a FIFO format;
A read data buffer for storing read data read from the memory according to the read command in a FIFO format;
The control master is
Among the identifiers stored in the route selector, when the identifier stored first is its own identifier and read data is stored in the read data buffer, read data is read from the read data buffer. A data transfer system characterized by reading.   The data transfer system according to claim 1, wherein when the read data is read from the read data buffer, the route selector erases the identifier stored first.