JP2015201505A - semiconductor device - Google Patents
semiconductor device Download PDFInfo
- Publication number
- JP2015201505A JP2015201505A JP2014078412A JP2014078412A JP2015201505A JP 2015201505 A JP2015201505 A JP 2015201505A JP 2014078412 A JP2014078412 A JP 2014078412A JP 2014078412 A JP2014078412 A JP 2014078412A JP 2015201505 A JP2015201505 A JP 2015201505A
- Authority
- JP
- Japan
- Prior art keywords
- electrode terminal
- semiconductor device
- circuit board
- semiconductor
- width
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
- H01L2924/13055—Insulated gate bipolar transistor [IGBT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Abstract
Description
本発明は半導体装置に関し、特に、回路パターンと電極端子が接合された構成を有する半導体装置に関する。 The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a configuration in which a circuit pattern and an electrode terminal are joined.
電力用半導体装置では、電極端子は絶縁基板に形成された金属製の回路パターンと接合されている。回路パターンと電極端子との接合部分には実使用時に熱的ストレスや機械的ストレスにより歪みが発生し、クラックが生じる。その結果、接合部分の接触抵抗が増大して、機械的特性が低下し、最悪の場合には電力用半導体装置は接合部分において破断に至る。したがって、接合部分の歪みは製品の寿命を左右する重要な事項である。 In the power semiconductor device, the electrode terminal is bonded to a metal circuit pattern formed on the insulating substrate. In the actual use, the joint portion between the circuit pattern and the electrode terminal is distorted by thermal stress or mechanical stress, and a crack is generated. As a result, the contact resistance of the joint portion increases, the mechanical characteristics deteriorate, and in the worst case, the power semiconductor device breaks at the joint portion. Therefore, the distortion of the joining portion is an important matter that affects the life of the product.
電極端子と回路パターンとの接合部分に生じる歪みを解消するために、各種の電力用半導体装置が提案されてきた。例えば、電極（回路パターン）に接続される接続端子に板厚方向に湾曲部を形成して接続端子を伸縮可能に構成した電力用半導体装置が提案されている（例えば特許文献１）。また、接続端子にスリット状の湾曲部を形成して低応力化する構成とした電力用半導体装置が提案されている（例えば特許文献２）。また、電極端子を接合する回路パターンに可塑性多孔質金属層を挿入して応力を低減する構造を提案したものがある（例えば特許文献３）。 Various types of power semiconductor devices have been proposed in order to eliminate the distortion generated at the junction between the electrode terminal and the circuit pattern. For example, a power semiconductor device has been proposed in which a connection portion connected to an electrode (circuit pattern) is formed with a curved portion in the thickness direction so that the connection terminal can be expanded and contracted (for example, Patent Document 1). In addition, a power semiconductor device has been proposed in which a slit-like curved portion is formed in a connection terminal to reduce stress (for example, Patent Document 2). In addition, there has been proposed a structure for reducing stress by inserting a plastic porous metal layer into a circuit pattern for joining electrode terminals (for example, Patent Document 3).
産業機器の小型化と大電力化の要求に伴い、電力用半導体装置には高出力密度と高信頼性が求められているため、電力用半導体装置は、動作時にさらなる温度上昇に晒されことになる。そこで、電極端子と回路パターンとの接合部分における熱ストレスや機械的ストレスによる歪みの発生を確実に抑制し、高い信頼性と長寿命化を達成することが強く要望されている。 Due to demands for miniaturization of industrial equipment and higher power consumption, power semiconductor devices are required to have high output density and high reliability, so power semiconductor devices are subject to further temperature rise during operation. Become. Therefore, there is a strong demand to reliably suppress the occurrence of distortion due to thermal stress or mechanical stress at the joint between the electrode terminal and the circuit pattern, and to achieve high reliability and long life.
しかしながら、特許文献１に開示のように、回路パターンと電極端子との接合部の破断を防止するために電極端子に湾曲部を形成して応力緩和を図る構成では、電極端子が水平方向に長くなり、半導体装置の小型化には不都合である。また配線長も長くなり、電極端子のジュール発熱のため接合部が過度に昇温する。 However, as disclosed in Patent Document 1, in the configuration in which a curved portion is formed in the electrode terminal to reduce stress in order to prevent breakage of the joint between the circuit pattern and the electrode terminal, the electrode terminal is long in the horizontal direction. This is inconvenient for downsizing of the semiconductor device. In addition, the wiring length becomes longer, and the temperature of the joint portion is excessively increased due to Joule heat generation of the electrode terminals.
また、特許文献２に開示の構成では、電極端子が高さ方向に長くなることで装置の小型化に不都合である。さらには、スリット状部位の電流密度が大きくなることで同様に接合部が昇温する。一方、特許文献３に開示の構成では、熱伝導率の小さな部材を挿入することによる温度上昇を回避するため、大きな接合部寸法を必要とする。この構造も、装置の小型化には不都合である。 In the configuration disclosed in Patent Document 2, the electrode terminals are elongated in the height direction, which is inconvenient for downsizing of the apparatus. Further, the temperature of the joint is similarly raised by increasing the current density of the slit-like portion. On the other hand, the configuration disclosed in Patent Document 3 requires a large joint size in order to avoid a temperature rise due to insertion of a member having low thermal conductivity. This structure is also inconvenient for downsizing of the apparatus.
本発明は、以上のような課題を鑑みてなされたもので、装置の小型化を損なうことなく、電極端子と回路パターンとの取り付け部における熱ストレスや機械的ストレスによる歪みを低減することを目的とする。 The present invention has been made in view of the above problems, and an object thereof is to reduce distortion due to thermal stress or mechanical stress in an attachment portion between an electrode terminal and a circuit pattern without impairing downsizing of the apparatus. And
本発明の半導体装置は、金属製のベース板と、ベース板に接合材で接合されている絶縁回路基板と、絶縁回路基板に接合材で接合されている半導体チップと、接合部と立ち上がり部を有し、絶縁回路基板に接合部で直接接合されている電極端子と、絶縁回路基板と半導体チップと電極端子とを封止する封止樹脂体とを備え、電極端子は、接合部の幅が立ち上がり部の幅よりも大きいことを特徴とするものである。 A semiconductor device of the present invention includes a metal base plate, an insulating circuit substrate bonded to the base plate with a bonding material, a semiconductor chip bonded to the insulating circuit substrate with a bonding material, a bonding portion, and a rising portion. And an electrode terminal that is directly bonded to the insulated circuit board at the joint, and a sealing resin body that seals the insulated circuit board, the semiconductor chip, and the electrode terminal. It is characterized by being larger than the width of the rising portion.
本発明によれば、電極端子と回路パターンとの取り付け部における熱ストレスや機械的ストレスにより生じる歪みが低減する。その結果、信頼性が高く寿命の長い電力用半導体装置を提供することが可能になる。 According to the present invention, distortion caused by thermal stress or mechanical stress in the attachment portion between the electrode terminal and the circuit pattern is reduced. As a result, it is possible to provide a power semiconductor device with high reliability and long life.
本発明の実施の形態に係る半導体装置について、図を参照しながら以下に説明する。なお、各図において、同一または同様の構成部分については同じ符号を付している。各図間の図示では、対応する各構成部のサイズや縮尺はそれぞれ独立している。例えば構成の一部を変更した断面図の間で、変更されていない同一構成部分を図示する際に、同一構成部分のサイズや縮尺が異なっている場合もある。また、半導体装置の構成は、実際にはさらに複数の部材を備えているが、説明を簡単にするため、説明に必要な部分のみを記載し、他の部分については省略している。 A semiconductor device according to an embodiment of the present invention will be described below with reference to the drawings. In each figure, the same or similar components are denoted by the same reference numerals. In the drawings between the drawings, the sizes and scales of the corresponding components are independent of each other. For example, when the same components that are not changed are illustrated in cross-sectional views in which a part of the configuration is changed, the sizes and scales of the same components may be different. In addition, the configuration of the semiconductor device actually includes a plurality of members. However, for the sake of simplicity, only the portions necessary for the description are shown and the other portions are omitted.
実施の形態１．
以下、添付の図面を参照して本発明の実施の形態について説明する。ここでは単数の半導体チップを有する半導体パワーモジュールの場合を例示して説明している。本発明は、これに限定されるものではなく、例えば、複数の半導体チップを１つのパッケージに搭載した複合半導体装置を用いた場合にも適用可能である。図１は本発明の実施の形態に係る半導体パワーモジュールの断面構造を示している。半導体装置１００において、Ｃｕ等から成る金属製のベース板１の上面には、絶縁回路基板２が導電性接合材５によって接合されている。半導体チップ３は絶縁回路基板２の上に導電性接合材５で固着接合されている。導電性接合材５は、Ｓｎ−Ｐｂ系、Ｐｂ−Ｉｎ系、Ａｇ−Ｓｎ系等の半田材を使用する。
Embodiment 1 FIG.
Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. Here, the case of a semiconductor power module having a single semiconductor chip is described as an example. The present invention is not limited to this. For example, the present invention can also be applied to a case where a composite semiconductor device in which a plurality of semiconductor chips are mounted in one package is used. FIG. 1 shows a cross-sectional structure of a semiconductor power module according to an embodiment of the present invention. In the semiconductor device 100, an insulating circuit substrate 2 is bonded to the upper surface of a metal base plate 1 made of Cu or the like by a conductive bonding material 5. The semiconductor chip 3 is fixedly bonded to the insulating circuit substrate 2 with a conductive bonding material 5. As the conductive bonding material 5, a solder material such as Sn—Pb, Pb—In, or Ag—Sn is used.
半導体チップ（または半導体素子）３は、電力用電界効果トランジスタ（パワーＭＯＳＦＥＴ：Power Metal-Oxide-Semiconductor Field-Effect Transistor）、絶縁ゲートバイポーラトランジスタ（ＩＧＢＴ：Insulated Gate Bipolar Transistor）などで構成されている。樹脂ケース７はベース板１の上に設けられている。電極端子４はその一端部が絶縁回路基板２の上面部所定箇所に固着接合されるとともに、他端部が樹脂ケース７に固定されている。樹脂ケース７の内側にはシリコン樹脂ゲルなどからなる封止樹脂体６が充填され、半導体チップ３を保護している。電極端子４と絶縁回路基板２との接合は、半田等の導電性接合材５を介して行ってもよいが、超音波接合のように両者を直接接合してもよい。 The semiconductor chip (or semiconductor element) 3 includes a power field effect transistor (power MOSFET), an insulated gate bipolar transistor (IGBT), and the like. The resin case 7 is provided on the base plate 1. One end of the electrode terminal 4 is fixedly bonded to a predetermined position on the upper surface of the insulating circuit board 2, and the other end is fixed to the resin case 7. A sealing resin body 6 made of silicon resin gel or the like is filled inside the resin case 7 to protect the semiconductor chip 3. The electrode terminal 4 and the insulated circuit board 2 may be joined via a conductive joining material 5 such as solder, or may be joined directly like ultrasonic joining.
半導体チップ３の材質に関しては、Ｓｉのみならず、ＳｉＣまたはＧａＮ等のような所謂ワイドバンドギャップ半導体、あるいはそれらの混載等が可能であり、特に制約はない。ここで、ワイドバンドギャップ半導体とは、一般に、およそ２ｅＶ以上の禁制帯幅をもつ半導体を指す。具体的には、ＧａＮに代表される３族窒化物、ＺｎＯに代表される２族窒化物、ＺｎＳｅに代表される２族カルコゲナイドおよびＳｉＣ等が知られている。特に、Ｓｉチップに比べ大電流密度で使用可能なＳｉＣチップを搭載して装置全体を小型化する場合には、熱応力に対して信頼性が高く、同時に小型化を可能とする本発明が好適である。 With respect to the material of the semiconductor chip 3, not only Si but also a so-called wide band gap semiconductor such as SiC or GaN, or mixed mounting of them can be used, and there is no particular limitation. Here, the wide band gap semiconductor generally refers to a semiconductor having a forbidden band width of about 2 eV or more. Specifically, a Group 3 nitride represented by GaN, a Group 2 nitride represented by ZnO, a Group 2 chalcogenide represented by ZnSe, SiC, and the like are known. In particular, when a SiC chip that can be used at a larger current density than that of a Si chip is mounted to reduce the size of the entire apparatus, the present invention that is highly reliable against thermal stress and can be reduced at the same time is preferable. It is.
図２は、絶縁回路基板２の基本構造を示す拡大図である。絶縁回路基板２の表面２ｄは図で上面側に該当し、絶縁回路基板２の裏面２ｅは図で下面側に該当する。板状の絶縁基板２ａの表面２ｄには表面側導体層となる表側回路パターン２ｂが固着形成されている。同様に、板状の絶縁基板２ａの裏面２ｅには裏面側導体層となる裏側回路パターン２ｃが固着形成されている。表側回路パターン２ｂおよび裏側回路パターン２ｃは例えばＣｕ又はＡｌにより形成されている。絶縁基板２ａはアルミナ（Ａｌ２Ｏ３）、窒化アルミニウム（ＡｌＮ）又は窒化ケイ素（Ｓｉ３Ｎ４）などのセラミック基板により構成する。表側回路パターン２ｂおよび裏側回路パターン２ｃと絶縁基板２ａとの接合には、Ａｌ−Ｓｉ、Ａｇ−Ｃｕ、Ａｇ−Ｃｕ−Ｔｉ等をろう材として公知の活性金属接合法や直接接合法を適用することができる。 FIG. 2 is an enlarged view showing the basic structure of the insulated circuit board 2. The front surface 2d of the insulated circuit board 2 corresponds to the upper surface side in the figure, and the rear surface 2e of the insulated circuit board 2 corresponds to the lower surface side in the figure. A front-side circuit pattern 2b serving as a surface-side conductor layer is fixedly formed on the surface 2d of the plate-like insulating substrate 2a. Similarly, a back side circuit pattern 2c serving as a back side conductor layer is fixedly formed on the back side 2e of the plate-like insulating substrate 2a. The front side circuit pattern 2b and the back side circuit pattern 2c are made of, for example, Cu or Al. The insulating substrate 2a is made of a ceramic substrate such as alumina (Al 2 O 3 ), aluminum nitride (AlN), or silicon nitride (Si 3 N 4 ). For joining the front side circuit pattern 2b and the back side circuit pattern 2c to the insulating substrate 2a, a known active metal joining method or a direct joining method using Al—Si, Ag—Cu, Ag—Cu—Ti or the like as a brazing material is applied. be able to.
図３は、電極端子４と表側回路パターン２ｂとの取り付け部の基本構造を示す要部拡大斜視図である。電極端子４は、例えばＣｕ板のプレス成形又はエッチング加工により形成する。Ｃｕ板は、通常Ｎｉメッキを施し、Ａｌ板で代用することも可能である。電極端子４は横断面形状がＬ字状梁構造であり、立ち上がり部４ａと接合部４ｂを有する。本実施の形態では立ち上がり部４ａは本体４ｈの幅が一定である。接合部４ｂは、超音波接合により絶縁回路基板２の表側回路パターン２ｂに固着されている。本実施の形態では、接合部４ｂの幅（寸法Ｂ）が立ち上がり部４ａの幅（寸法Ａ）よりも大きい。 FIG. 3 is an enlarged perspective view of a main part showing a basic structure of a mounting portion between the electrode terminal 4 and the front side circuit pattern 2b. The electrode terminal 4 is formed, for example, by press molding or etching of a Cu plate. The Cu plate is usually plated with Ni, and an Al plate can be substituted. The electrode terminal 4 has an L-shaped beam structure in cross section, and has a rising portion 4a and a joint portion 4b. In the present embodiment, the rising portion 4a has a constant width of the main body 4h. The joint 4b is fixed to the front circuit pattern 2b of the insulating circuit board 2 by ultrasonic joining. In the present embodiment, the width (dimension B) of the joint portion 4b is larger than the width (dimension A) of the rising portion 4a.
次に、電極端子４が曲げモーメントを受けるときに取り付け部に生じる最大応力を有限要素法解析により調べた結果を説明する。計算にあたり、仮定した電極端子の模式構造を図４に示す。同図に示す電極端子モデルを用いて有限要素法により取り付け部に生じる応力を計算した。図中の白抜き三角印（△）は、固着接合した超音波接合部を模擬して底面に設定した拘束条件を示している。同じく回転矢印は電極端子に加わる曲げモーメントを模式的に示している。電極端子４が曲げモーメントを受けると接合部４ｂには引き剥がす方向の応力が発生する。そのとき発生する接合面内の最大値を接合部最大応力として種々の寸法について計算した。 Next, the result of examining the maximum stress generated in the mounting portion when the electrode terminal 4 receives a bending moment by finite element analysis will be described. FIG. 4 shows a schematic structure of electrode terminals assumed for the calculation. Using the electrode terminal model shown in the figure, the stress generated in the attachment portion was calculated by the finite element method. A white triangle mark (Δ) in the figure represents a constraint condition set on the bottom surface by simulating an ultrasonic bonded portion that is firmly bonded. Similarly, the rotation arrow schematically shows the bending moment applied to the electrode terminal. When the electrode terminal 4 receives a bending moment, a stress in the peeling direction is generated at the joint 4b. The maximum value in the joint surface generated at that time was calculated as the joint maximum stress for various dimensions.
図５は、（寸法Ｂ／寸法Ａ）に対して接合部に発生する最大応力を規格化して示した特性図である。ここで寸法Ｂと寸法Ａは接合部４ｂの幅と立ち上がり部４ａの幅をそれぞれ表している（図４参照）。規格化は、（寸法Ｂ／寸法Ａ）が１のときに発生する接合部最大応力で除すことで行った。この図から、（寸法Ｂ／寸法Ａ）を１．２に以上にすることで、立ち上がり部４ａの幅と接合部４ｂの幅とが同じときに比べて最大応力は約２／３に低減することが分かる。 FIG. 5 is a characteristic diagram showing a standardized maximum stress generated in the joint with respect to (dimension B / dimension A). Here, the dimension B and the dimension A represent the width of the joint portion 4b and the width of the rising portion 4a, respectively (see FIG. 4). The normalization was performed by dividing by the maximum joint stress generated when (dimension B / dimension A) was 1. From this figure, by setting (dimension B / dimension A) to 1.2 or more, the maximum stress is reduced to about 2/3 compared to when the width of the rising portion 4a and the width of the joint portion 4b are the same. I understand that.
本発明の実施の形態によれば、熱変形により電極端子と回路パターンとの接合部に生じる応力は確実に低減する。同時に、電極端子の高さや断面形状を大きく変更することなく低応力化が実現できるため、装置の小型化の特性を損なうことが無い。なお、電極端子４と表側回路パターン２ｂは、接合材を用いずに超音波接合により直接接合しているため、接合部における熱伝導が良好であり、接合部の温度上昇も小さい。接合面積を小さくすることができるうえに、接合部の強度が半田などの接合材の融点により上限を迎えることが無い。また、半田等を例とする導電性接合材５を介して電極端子４と回路パターンを接合すれば、接合部がより強固になり、信頼性の高い半導体パワーモジュールを得ることができる。 According to the embodiment of the present invention, the stress generated at the joint between the electrode terminal and the circuit pattern due to thermal deformation is reliably reduced. At the same time, the stress reduction can be realized without greatly changing the height and cross-sectional shape of the electrode terminal, so that the downsizing characteristics of the apparatus are not impaired. In addition, since the electrode terminal 4 and the front side circuit pattern 2b are directly bonded by ultrasonic bonding without using a bonding material, the heat conduction at the bonded portion is good and the temperature rise at the bonded portion is small. The bonding area can be reduced, and the strength of the bonding portion does not reach the upper limit due to the melting point of the bonding material such as solder. Further, if the electrode terminal 4 and the circuit pattern are bonded via the conductive bonding material 5 such as solder, the bonded portion becomes stronger and a highly reliable semiconductor power module can be obtained.
上記したように、立ち上がり部の幅に対して接合部の幅を１．２倍以上にすることで最大応力は約２／３に低減できることが明らかになった。この理由として、回路パターンと電極端子との取り付け部の端部は応力集中を生じやすい形状であることが考えられる。立ち上がり部の幅と接合部の幅とが等しい形状の場合には曲げ応力が直接この端部に作用することで高い応力が生じる。本発明は、接合部の幅を広げて、応力集中部に曲げ応力が直接作用することを回避することで上述の効果を得ているものである。 As described above, it has been clarified that the maximum stress can be reduced to about 2/3 by making the width of the joint portion 1.2 times or more than the width of the rising portion. As a reason for this, it is conceivable that the end portion of the attachment portion between the circuit pattern and the electrode terminal has a shape that easily causes stress concentration. In the case where the width of the rising portion is equal to the width of the joint portion, a high stress is generated by bending stress acting directly on the end portion. The present invention achieves the above-described effect by expanding the width of the joint and avoiding the bending stress directly acting on the stress concentration portion.
実施の形態２．
図６は、実施の形態２に係る半導体装置の電極端子と回路パターンとの取り付け部の基本構造を示す要部拡大斜視図である。本実施の形態では、立ち上がり部４ａは本体４ｈの幅（寸法Ａ）と付け根４ｃの幅（寸法Ｃ）が異なる。図示されているように、接合部４ｂの幅（寸法Ｂ）は、立ち上がり部４ａの本体４ｈの幅（寸法Ａ）よりも大きいことに加え、本体４ｈの幅（寸法Ａ）が付け根４ｃの幅（寸法Ｃ）よりも広いことを特徴とする。本実施の形態におけるその他の構成は、実施の形態１に関わる半導体装置と実質的に同じである。
Embodiment 2. FIG.
FIG. 6 is an enlarged perspective view of a main part showing a basic structure of a mounting portion between the electrode terminal and the circuit pattern of the semiconductor device according to the second embodiment. In the present embodiment, the rising portion 4a is different in the width (dimension A) of the main body 4h and the width (dimension C) of the base 4c. As shown in the drawing, the width (dimension B) of the joint 4b is larger than the width (dimension A) of the main body 4h of the rising portion 4a, and the width (dimension A) of the main body 4h is the width of the base 4c. It is characterized by being wider than (dimension C). Other configurations in the present embodiment are substantially the same as those of the semiconductor device according to the first embodiment.
本実施の形態によれば、実施の形態１で説明した効果と同じ理由により、電極端子と回路パターンとの取り付け部に生じる応力が確実に低減する。さらには、電流密度が増大した場合にも電極端子の導体抵抗を小さくすることが容易に達成できるため、装置の小型化の特性を損なうことなく同時に信頼性を向上できる。 According to the present embodiment, for the same reason as the effect described in the first embodiment, the stress generated in the attachment portion between the electrode terminal and the circuit pattern is reliably reduced. Furthermore, since the conductor resistance of the electrode terminal can be easily reduced even when the current density is increased, the reliability can be improved at the same time without impairing the downsizing characteristics of the apparatus.
実施の形態３．
図７は、実施の形態３に係る半導体装置の電極端子と回路パターンとの取り付け部の基本構造を示す要部拡大斜視図である。平面状の立ち上がり部４ａに対して、その両面側に電極端子の接合部４ｂの切り起こし部４ｄが形成されている構成である。接合部４ｂの切り起こし部４ｄの存在により、接合部４ｂが立ち上がり部４ａの後ろ側まで延在している。立ち上がり部４ａの平面に対して立ち上がり部４ａよりも広い幅で接合される側を前側とすると、立ち上がり部４ａの付け根部分から後ろ側に切り起こし部４ｄが伸びて下地に接合している。接合部４ｂの切り起こし部４ｄの存在によって、立ち上がり部４ａの付け根部分の前後に接合部ができることになり、接合の強度をより高めることができる。切り起こし部４ｄは、切り起こし加工などで、電極端子４から接合部４ｂと同時に形成することができる。
Embodiment 3 FIG.
FIG. 7 is an enlarged perspective view of a main part showing a basic structure of a mounting portion between the electrode terminal and the circuit pattern of the semiconductor device according to the third embodiment. With respect to the flat rising portion 4a, the cut-and-raised portion 4d of the joint portion 4b of the electrode terminal is formed on both sides thereof. Due to the presence of the cut-and-raised portion 4d of the joint portion 4b, the joint portion 4b extends to the rear side of the rising portion 4a. Assuming that the side bonded to the plane of the rising portion 4a with a width wider than that of the rising portion 4a is the front side, the raised portion 4d extends from the base portion of the rising portion 4a to the rear side and is bonded to the base. The presence of the cut-and-raised portion 4d of the joint portion 4b allows a joint portion to be formed before and after the root portion of the rising portion 4a, thereby further increasing the strength of the joint. The cut-and-raised portion 4d can be formed simultaneously with the joint portion 4b from the electrode terminal 4 by cutting and raising processing or the like.
実施の形態４．
図８は、実施の形態４に係る半導体装置の電極端子と回路パターンとの取り付け部の基本構造を示す要部拡大斜視図である。本実施の形態では、立ち上がり部４ａの付け根４ｃが接合部４ｂから本体４ｈに向かって次第に狭まっていることを特徴とする。すなわち、電極端子の接合部４ｂの幅（寸法Ｂ）が、立ち上がり部４ａの幅（寸法Ａ）よりも大きいことに加え、立ち上がり部４ａは接合部４ｂから本体４ｈにかけて付け根４ｃにテーパー状部４ｅを有する。本実施の形態におけるその他の構成は、実施の形態１の半導体装置と実質的に同じである。
Embodiment 4 FIG.
FIG. 8 is an enlarged perspective view of a main part showing a basic structure of a mounting portion between the electrode terminal and the circuit pattern of the semiconductor device according to the fourth embodiment. The present embodiment is characterized in that the base 4c of the rising portion 4a is gradually narrowed from the joint 4b toward the main body 4h. That is, in addition to the width (dimension B) of the joint 4b of the electrode terminal being larger than the width (dimension A) of the rising portion 4a, the rising portion 4a extends from the joining portion 4b to the main body 4h to the base 4c with the tapered portion 4e. Have Other configurations in the present embodiment are substantially the same as those of the semiconductor device of the first embodiment.
本発明における応力低減の効果は電極端子を接合した取り付け部の応力集中を回避するところにある。本観点から、テーパー形状を有して応力集中を抑制することで、いっそう効果的に応力を低減することが可能である。また実施の形態１と同様に、同時に電極端子の高さや断面形状を大きく変更することなく低応力化が実現できるため、装置の小型化の特性を損なうことが無い。 The effect of reducing the stress in the present invention is to avoid stress concentration at the mounting portion where the electrode terminals are joined. From this viewpoint, it is possible to reduce the stress more effectively by suppressing the stress concentration by having a tapered shape. In addition, as in the first embodiment, the stress can be reduced without greatly changing the height and cross-sectional shape of the electrode terminal at the same time, so that the characteristics of downsizing the device are not impaired.
実施の形態５．
図９は、実施の形態５に係る半導体装置の電極端子と回路パターンとの取り付け部の基本構造を示す要部拡大斜視図である。接合部４ｂの切り起こし部４ｄの存在により、接合部４ｂは立ち上がり部４ａの後ろ側まで延在している。さらに、寸法Ｂ（接合部４ｂの幅）が、寸法Ａ（立ち上がり部の本体４ｈの幅）よりも大きいことに加え、寸法Ａ（立ち上がり部の本体４ｈの幅）が寸法Ｃ（立ち上がり部の付け根４ｃの幅）よりも広くなっている。切り起こし部４ｄの幅を大きく取ることが出来るので、接合の強度を高めることができる。切り起こし部４ｄは付け根４ｃを本体４ｈよりも狭く形成することによって自動的に形成される。切り起こし部４ｄの奥行きと付け根４ｃの高さを一致させることが好ましい。
Embodiment 5 FIG.
FIG. 9 is an enlarged perspective view of a main part showing a basic structure of a mounting portion between the electrode terminal and the circuit pattern of the semiconductor device according to the fifth embodiment. Due to the presence of the cut-and-raised portion 4d of the joint portion 4b, the joint portion 4b extends to the rear side of the rising portion 4a. Furthermore, in addition to the dimension B (width of the joint portion 4b) being larger than the dimension A (width of the main body 4h of the rising portion), the dimension A (width of the main body 4h of the rising portion) is dimension C (root of the rising portion). 4c)). Since the width of the cut-and-raised portion 4d can be increased, the bonding strength can be increased. The cut-and-raised portion 4d is automatically formed by forming the base 4c narrower than the main body 4h. It is preferable that the depth of the cut-and-raised portion 4d and the height of the base 4c are matched.
なお、本発明は、その発明の範囲内において、実施の形態を自由に組み合わせたり、各実施の形態を適宜、変形、省略することが可能である。 It should be noted that the present invention can be freely combined with each other within the scope of the invention, and each embodiment can be appropriately modified or omitted.
１ ベース板、２ 絶縁回路基板、２ａ 絶縁基板、２ｂ 表側回路パターン、２ｃ 裏側回路パターン、２ｄ 表面、２ｅ 裏面、３ 半導体チップ、４ 電極端子、４ａ 立ち上がり部、４ｂ 接合部、４ｃ 付け根、４ｄ 切り起こし部、４ｅ テーパー状部、４ｈ 本体、５ 導電性接合材、６ 封止樹脂体、７ 樹脂ケース、１００ 半導体装置、Ａ 寸法、Ｂ 寸法、Ｃ 寸法 1 Base plate, 2 Insulated circuit board, 2a Insulated board, 2b Front side circuit pattern, 2c Back side circuit pattern, 2d Surface, 2e Back surface, 3 Semiconductor chip, 4 Electrode terminal, 4a Rising part, 4b Joint part, 4c Base, 4d Cutting Raised part, 4e tapered part, 4h body, 5 conductive bonding material, 6 sealing resin body, 7 resin case, 100 semiconductor device, A dimension, B dimension, C dimension
Claims (6)
前記ベース板に接合材で接合されている絶縁回路基板と、
前記絶縁回路基板に接合材で接合されている半導体チップと、
接合部と立ち上がり部を有し、前記絶縁回路基板に前記接合部で直接接合されている電極端子と、
前記絶縁回路基板と前記半導体チップと前記電極端子とを封止する封止樹脂体とを備え、前記電極端子は、前記接合部の幅が前記立ち上がり部の幅よりも大きいことを特徴とする半導体装置。 A metal base plate,
An insulated circuit board bonded to the base plate with a bonding material;
A semiconductor chip bonded to the insulating circuit board with a bonding material;
An electrode terminal having a bonding portion and a rising portion, and being directly bonded to the insulating circuit board at the bonding portion;
A semiconductor comprising: a sealing resin body that seals the insulating circuit substrate, the semiconductor chip, and the electrode terminal, wherein the electrode terminal has a width of the joint portion larger than a width of the rising portion. apparatus.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2014078412A JP2015201505A (en) | 2014-04-07 | 2014-04-07 | semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2014078412A JP2015201505A (en) | 2014-04-07 | 2014-04-07 | semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2015201505A true JP2015201505A (en) | 2015-11-12 |
Family
ID=54552532
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2014078412A Pending JP2015201505A (en) | 2014-04-07 | 2014-04-07 | semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2015201505A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107818963A (en) * | 2016-09-14 | 2018-03-20 | 富士电机株式会社 | The manufacture method of semiconductor device and semiconductor device |
| WO2020213214A1 (en) * | 2019-04-19 | 2020-10-22 | 株式会社三社電機製作所 | External terminal for semiconductor module |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003115337A (en) * | 2001-07-31 | 2003-04-18 | Rohm Co Ltd | Terminal plate, circuit board provided with this terminal plate, and connecting method of this terminal plate |
| JP2004193405A (en) * | 2002-12-12 | 2004-07-08 | Mitsubishi Electric Corp | Semiconductor power module |
| JP2006236896A (en) * | 2005-02-28 | 2006-09-07 | Fenwall Controls Of Japan Ltd | Connection terminal and electric heater equipped with it |
| JP2006278913A (en) * | 2005-03-30 | 2006-10-12 | Toyota Motor Corp | Circuit device and manufacturing method therefor |
| JP2013065836A (en) * | 2011-08-31 | 2013-04-11 | Mitsubishi Electric Corp | Electrode member and power semiconductor device using the same |
-
2014
- 2014-04-07 JP JP2014078412A patent/JP2015201505A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003115337A (en) * | 2001-07-31 | 2003-04-18 | Rohm Co Ltd | Terminal plate, circuit board provided with this terminal plate, and connecting method of this terminal plate |
| JP2004193405A (en) * | 2002-12-12 | 2004-07-08 | Mitsubishi Electric Corp | Semiconductor power module |
| JP2006236896A (en) * | 2005-02-28 | 2006-09-07 | Fenwall Controls Of Japan Ltd | Connection terminal and electric heater equipped with it |
| JP2006278913A (en) * | 2005-03-30 | 2006-10-12 | Toyota Motor Corp | Circuit device and manufacturing method therefor |
| JP2013065836A (en) * | 2011-08-31 | 2013-04-11 | Mitsubishi Electric Corp | Electrode member and power semiconductor device using the same |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107818963A (en) * | 2016-09-14 | 2018-03-20 | 富士电机株式会社 | The manufacture method of semiconductor device and semiconductor device |
| JP2018046164A (en) * | 2016-09-14 | 2018-03-22 | 富士電機株式会社 | Semiconductor device and semiconductor device manufacturing method |
| CN107818963B (en) * | 2016-09-14 | 2023-08-29 | 富士电机株式会社 | Semiconductor device and method for manufacturing semiconductor device |
| WO2020213214A1 (en) * | 2019-04-19 | 2020-10-22 | 株式会社三社電機製作所 | External terminal for semiconductor module |
| JP2020178060A (en) * | 2019-04-19 | 2020-10-29 | 株式会社三社電機製作所 | External terminal for semiconductor module |
| JP7244339B2 (en) | 2019-04-19 | 2023-03-22 | 株式会社三社電機製作所 | External terminals for semiconductor modules |
| US11791244B2 (en) | 2019-04-19 | 2023-10-17 | Sansha Electric Manufacturing Co., Ltd. | Semiconductor-module external terminal |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| WO2013118478A1 (en) | Semiconductor device | |
| US9536803B2 (en) | Integrated power module with improved isolation and thermal conductivity | |
| JP2016018866A (en) | Power module | |
| JP6305176B2 (en) | Semiconductor device and manufacturing method | |
| JP2019186326A (en) | Semiconductor device and manufacturing method of the same | |
| JP2015090965A (en) | Semiconductor device | |
| JP2005116702A (en) | Power semiconductor module | |
| JP5916651B2 (en) | Method for manufacturing power semiconductor device | |
| JPWO2018061711A1 (en) | Semiconductor device and manufacturing method | |
| JP4614107B2 (en) | Semiconductor device | |
| JP6139329B2 (en) | Ceramic circuit board and electronic device | |
| JP4124040B2 (en) | Semiconductor device | |
| JP2015201505A (en) | semiconductor device | |
| JP6129090B2 (en) | Power module and method for manufacturing power module | |
| JP2006196765A (en) | Semiconductor device | |
| JP2017073406A (en) | Electrode lead and semiconductor device | |
| JP5083294B2 (en) | Power semiconductor device | |
| JP2008103558A (en) | Semiconductor power module | |
| US11101199B2 (en) | Power semiconductor device | |
| US10600765B2 (en) | Semiconductor device and method for producing the same | |
| JPWO2020149225A1 (en) | Semiconductor device | |
| WO2018029801A1 (en) | Semiconductor device | |
| JP2007042738A (en) | Semiconductor device | |
| CN218769501U (en) | Power semiconductor device | |
| US11646250B2 (en) | Semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20161024 |
|
| A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20170609 |
|
| A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20170725 |
|
| A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 20180306 |