JP2015186381A - switching power supply - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a switching power supply capable of easily suppressing the fluctuation of an output current limit value according to the increase or decrease of an input voltage.SOLUTION: The switching power supply includes: a first correction resistor 50 inserted between one end of a detection resistor 26a and a first input terminal 34(1) of a comparator 34; a timer capacitor 52; and a charging resistor 54 for supplying to the timer capacitor 52 a charge current which fluctuates according to an input voltage Vi; a discharge circuit 56 for resetting the timer capacitor 52 in an OFF period of a main switching element 20 and for enabling charging at timing when ON is started; an NPN transistor 58b having the base terminal connected to the timer capacitor 52; and a second correction resistor 60 disposed between the emitter terminal of the NPN transistor 58b and the first input terminal 34(1). In the ON period of the main switching element 20, a correction voltage of a saw tooth wave shape is generated at both ends of the first correction resistor 50, due to the correction current output from the NPN transistor 58b.

Description

  The present invention relates to a switching power supply device that detects a switching current and performs pulse-by-pulse overcurrent protection.

  The switching power supply device is generally provided with an overcurrent protection circuit that limits an output current to a certain level or less in order to prevent an excessive current from flowing into a load that has failed during energization. In particular, pulse-by-pulse overcurrent protection observes the switching current flowing through the main switching element for each pulse, limits the peak value of each pulse, and has features such as excellent high-speed response. Have been widely used.

  For example, the conventional switching power supply device 10 shown in FIG. 5A is a single-ended forward type power supply device that performs pulse-by-pulse overcurrent protection. A series circuit of the primary winding 18a of the transformer 18 and the main switching element 20 is provided between the input line 14 to which the input power supply 12 is connected and the ground line 16, and the primary switching element 20 is turned on and off, whereby the primary A voltage obtained by intermittently inputting the input voltage Vi is applied to the winding 18a. A rectifying / smoothing circuit 22 is connected to the secondary winding 18 b of the transformer 18 to rectify and smooth the voltage generated in the secondary winding 18 b, and supply a DC output voltage Vo and an output current Io to the load 24.

  A detection resistor 26 a that is a current detection circuit 26 is inserted between the main switching element 20 and the ground line 16. A positive voltage drop occurs when the switching current Id of the main switching element 20 flows through the detection resistor 26a, and the voltage drop is output as the current detection voltage V26. As shown in FIG. 5C, the current detection circuit 26 converts the switching current Id to a small value by using the current transformer 26b to reduce the loss of the detection resistor 26a, and flows it to the detection resistor 26a through the diode 26c. The current detection voltage V26 may be generated in a form.

  The main switching element 20 is an N-channel MOS FET here, and is driven by a drive pulse Vg32 output from the control circuit 28. The main switching element 20 is turned on when the drive pulse Vg32 is at a high level and turned off when the drive pulse Vg32 is at a low level.

  The control circuit 28 is provided with an error amplification circuit 30 and a drive pulse generation circuit 32. The error amplification circuit 30 generates an error amplification voltage V30 obtained by amplifying the difference between the output voltage Vo and the target value Vo1, and outputs the error amplification voltage V30 to the drive pulse generation circuit 32. The drive pulse generation circuit 32 performs voltage mode pulse width modulation using a predetermined reference triangular wave and the error amplification voltage V30. Then, the high level and low level times of the drive pulse Vg32 are determined so that the output voltage Vo approaches the target value Vo1, and the on time and off time of the main switching element 20 are controlled.

  Further, the control circuit 28 is provided with a comparator 34 for overcurrent protection. In the comparator 34, the output terminal of the detection resistor 26a is connected to the first input terminal 34 (1), the first reference voltage Vr1 is set to the second input terminal 34 (2), and the first input terminal 34 (1). When the voltage V34 (1) exceeds the first reference voltage Vr1, the output of the comparator 34 is inverted. Here, the voltage V34 (1) is the current detection voltage V26. When the output of the comparator 34 is inverted, the drive pulse generation circuit 32 inverts the drive pulse Vg32 to a low level regardless of the error amplification voltage V30. As a result, the on-time of the main switching element 20 is forcibly shortened, the output voltage Vo is reduced, and the output current Io is also limited.

  A conventional switching power supply 36 shown in FIG. 5B is a flyback power supply that performs pulse-by-pulse overcurrent protection. The difference from the switching power supply device 10 described above is that a rectifying / smoothing circuit 38 is provided instead of the rectifying / smoothing circuit 22, and the other configurations are the same and are denoted by the same reference numerals.

  FIG. 7 of Patent Document 1 shows a single-ended-forward power supply device that performs pulse-by-pulse overcurrent protection, and a switching power supply device that performs current-mode pulse width modulation (hereinafter, referred to as “power supply mode”). (Referred to as switching power supply device of Patent Document 1). The configuration of the switching power supply device will be described in comparison with the switching power supply device 10 described above. An error signal (error amplified voltage) output from an error amplification circuit (not shown) is a non-inverting input terminal (second input terminal) of the comparator. The comparator performs pulse width modulation using the error signal and the voltage input to the inverting input terminal (first input terminal). The output terminal of the current detection resistor inserted between the main switching element and the ground line is connected to the inverting input terminal of the comparator, and the first reference voltage Vr1 for overcurrent protection is connected to the inverting input terminal. Zener diode (the Zener voltage is Vr1). Therefore, similarly to the switching power supply device 10 described above, when the voltage at the inverting input terminal exceeds the first reference voltage Vr1, the on-time of the main switching element is shortened, the output voltage is reduced, and the output current is limited.

  What is characteristic here is that a slope correction circuit is provided between the inverting input terminal of the comparator and the output terminal of the current detection resistor. The slope correction circuit has a resistor (hereinafter referred to as a first resistor) inserted between the output terminal of the current detection resistor and the inverting input terminal of the comparator, and a timer capacitor having one end connected to the ground line. doing. It also has a charging resistor that supplies a constant charging current toward the other end of the timer capacitor, and a switch that resets the voltage of the timer capacitor immediately before the start of one switching cycle (immediately before the main switching element is turned on). ing. Further, an emitter follower circuit having an NPN transistor whose base terminal is connected to the other end of the timer capacitor, and a resistor (hereinafter referred to as a second resistor) connected between the emitter terminal of the NPN transistor and the inverting input terminal of the comparator. And). With this configuration, the correction current output from the emitter follower circuit through the second resistor flows through the first resistor during the period from the start of one switching cycle to just before the next cycle starts, and sawtooth-like current is generated at both ends of the first resistor. A correction voltage is generated. Therefore, a voltage obtained by adding this correction voltage to the current detection voltage generated in the current detection resistor is input to the inverting input terminal of the comparator.

  In current mode control, it is known that when the main switching element's on-time ratio exceeds 50%, a current oscillation phenomenon occurs in which the main switching element's on-time and off-time change for each switching cycle. The slope correction circuit is provided to prevent a current oscillation phenomenon. In the case of this slope correction circuit, the slope of the sawtooth correction voltage is constant regardless of the input voltage.

JP 2012-157191 A

  As shown in FIG. 6, in the conventional switching power supply devices 10 and 36 and the switching power supply device disclosed in Patent Document 1, the limit value Io2 (H) of the output current Io when the input voltage Vi is high has a low input voltage Vi. When the input voltage Vi is high, there is a problem in that sufficient overcurrent protection cannot be performed when the input voltage Vi is high. The cause of this problem can be roughly explained by considering the following two factors. The first factor is “how does the correlation between the output current Io and the peak value Ip of the switching current Id change depending on the level of the input voltage Vi”. The second factor is “how the influence of the delay time of the overcurrent protection comparator changes depending on the level of the input voltage Vi”. Hereinafter, the first and second factors will be considered for each switching power supply device.

  First, the single-ended forward type switching power supply 10 will be considered. Here, it is assumed that the switching power supply device 10 performs the inductor current continuous mode operation in which the switching frequency (one cycle = Tsw) is constant and the current of the smoothing inductor 22a of the rectifying and smoothing circuit 22 is continuous. Further, it is assumed that the exciting inductance of the transformer 18 is sufficiently large and the forward voltage of the two diodes included in the rectifying and smoothing circuit 22 is sufficiently small.

  The first factor is the operation waveform (FIG. 7 (a)) at the operating point P1 (L) where the input voltage Vi is low and the output current Io is Io1 (<Io2 (L), Io2 (H)). This can be considered by comparing the operation waveform (FIG. 7B) of the operating point P1 (H) where the voltage Vi is high and the output current Io is the same Io1. FIG. 7A shows the waveform of the switching current Id (L) flowing through the main switching element 20 and the waveform of the current If (L) flowing through the commutation side diode 22b of the rectifying and smoothing circuit 22 overwritten. In consideration of the turns ratio of the windings 18a and 18b of the transformer, the scale of the vertical axis is adjusted so that the peak values of the transformers coincide with the peak value Ip (L) of the switching current Id (L). Ir1 is a current value obtained by dividing the first reference voltage Vr1 of the comparator 34 by the resistance value of the detection resistor 26a. The same applies to FIG. 7B.

  When the output current Io = Io1, the peak value Ip of the switching current Id is at a level obtained by adding 1/2 of the component ΔId that causes the switching current Id to rise to the right. The operating points P1 (L) and P2 (H) are both turned on and off so that the output voltage Vo becomes the target value Vo1, the rising components ΔId (L) and ΔId (H) are equal to each other, and the peak value Ip Since (L) and Ip (H) are also equal to each other, the correlation between the output current Io and the peak value Ip is uniform regardless of the level of the input voltage Vi. Therefore, in the case of the switching power supply device 10, the first factor does not cause the problem that “the higher the input voltage Vi, the larger the limit value Io2 of the output current Io”.

  The second factor is the operation waveform (FIG. 8A) at the operating point P2 (L) where the input voltage Vi is low and the output current Io is Io2 (L), and the output current Io is high when the input voltage Vi is high. This can be considered by comparing the operation waveform of the operating point P2 (H) that is Io2 (H) (FIG. 8B).

  When the switching current Id rises to the right and reaches the current value Ir1, the main switching element 20 is turned off when the operation delay time td1 of the comparator 34 or the like has elapsed. Therefore, the switching current Id continues to rise during the time td1. The operating point P2 (L) has a small slope at which the drain current Id (L) rises because the input voltage Vi is low, so the drain current Id (L) rises to a value Ip (L) that slightly exceeds the current value Ir1. Then, the limit value Io2 (L) of the output current Io is determined. On the other hand, the operating point P2 (H) has a large slope at which the drain current Id (H) rises due to the high input voltage Vi, so the drain current Id (H) greatly exceeds the current value Ir1 during the same time td. It rises to the value Ip (H). As a result, the limit value Io2 (H) of the output current Io is larger than the limit value Io2 (L). Therefore, in the case of the switching power supply device 10, the second factor causes the problem that “the higher the input voltage Vi, the larger the limit value Io2 of the output current Io”.

  Next, the case of the flyback type switching power supply 36 will be considered. The flyback type also has a plurality of types of operation, for example, a case where the transformer current discontinuous mode operation is performed with a constant switching period Tsw (first case), and a transformer current critical mode operation is performed when the switching period Tsw varies. There are a case (second case), a case (third case) in which the switching period Tsw varies and a quasi-resonant mode operation is performed. Hereinafter, these three representative cases will be described in order.

  First, a case (first case) in which the switching power supply 36 performs a transformer current discontinuous mode operation with a constant switching period Tsw will be described.

  The first factor is the operating waveform (FIG. 9A) of the operating point P1 (L) where the input voltage Vi is low and the output current Io is Io1 (<Io2 (L), Io2 (H)), and the input. This can be considered by comparing the operation waveform (FIG. 9B) of the operating point P1 (H) where the voltage Vi is high and the output current Io is the same Io1. FIG. 9A shows the waveform of the switching current Id (L) flowing through the main switching element 20 and the waveform of the current If (L) flowing through the rectifier diode 38a of the rectifying / smoothing circuit 38. In consideration of the turns ratio of the windings 18a and 18b, the scale of the vertical axis is adjusted so that the peak values of the windings coincide with the peak value Ip (L) of the switching current Id (L). Ir1 is a current value obtained by dividing the first reference voltage Vr1 of the comparator 34 by the resistance value of the detection resistor 26a. The same applies to FIG. 9B and FIGS.

  When the output current Io = Io1, a reverse sawtooth current If flows during the time tf when the rectifier diode 38a is conducted, so that the “area of the reverse sawtooth portion” and “product of Io1 and Tsw” are equal. In addition, the peak value of the current If and the peak value Ip of the switching current Id are determined. At both operating points P1 (L) and P2 (H), the main switching element 20 is turned on / off so that the output voltage Vo becomes the target value Vo1, and the slopes of the current If (L) and If (H) descending from each other are mutually reduced. Since the times tf (L) and tf (H) are also equal to each other, the correlation between the output current Io and the peak value Ip is uniform regardless of the level of the input voltage Vi. Therefore, when the operation mode of the switching power supply 36 is the first case, the first factor does not cause the problem that “the higher the input voltage Vi, the larger the limit value Io2 of the output current Io”.

  The second factor is the operating waveform (FIG. 10A) of the operating point P2 (L) where the input voltage Vi is low and the output current Io is Io2 (L), and the output current Io is high when the input voltage Vi is high. This can be considered by comparing the operation waveform of the operation point P2 (H) that is Io2 (H) (FIG. 10B).

  When the switching current Id rises to the right and reaches the current value Ir1, the main switching element 20 is turned off when the operation delay time td1 of the comparator 34 or the like has elapsed. Therefore, the switching current Id continues to rise during the time td1. The operating point P2 (L) has a small slope at which the drain current Id (L) rises because the input voltage Vi is low, so the drain current Id (L) rises to a value Ip (L) that slightly exceeds the current value Ir1. The limit value Io2 (L) of the output current Io is determined. On the other hand, since the operating point P1 (H) has a large slope at which the drain voltage Id (H) rises due to the high input voltage Vi, the drain current Id (L) greatly exceeds the current value Ir1 during the same time td. It rises to the value Ip (H). As a result, the limit value Io2 (H) of the output current Io is larger than the limit value Io2 (L). Therefore, when the operation mode of the switching power supply 36 is the first case, the second factor causes the problem that “the higher the input voltage Vi, the larger the limit value Io2 of the output current Io”.

  Next, a case (second case) in which the switching cycle Tsw varies and the transformer current critical mode operation is performed in the switching power supply 36 will be described.

  The first factor is the operation waveform (FIG. 11 (a)) at the operating point P1 (L) where the input voltage Vi is low and the output current Io is Io1 (<Io2 (L), Io2 (H)), and the input. This can be considered by comparing the operation waveform (FIG. 12B) of the operation point P1 (H) where the voltage Vi is high and the output current Io is the same Io1.

  When the output current Io = Io1, a reverse sawtooth current If flows during the time tf when the rectifier diode 38a is conducted, so that the “area of the reverse sawtooth portion” and “product of Io1 and Tsw” are equal. In addition, the peak value of the current If and the peak value Ip of the switching current Id are determined. At both operating points P1 (L) and P2 (H), the main switching element 20 is turned on / off so that the output voltage Vo becomes the target value Vo1, and the slopes of the current If (L) and If (H) descending from each other are mutually reduced. Although the time tf (L) and tf (H) are equal to each other, the switching period Tsw (H) of the operating point P1 (H) is changed to the switching of the operating point P1 (L) in order to perform the transformer current critical mode operation. It becomes shorter than the cycle Tsw (L). As a result, even if the output current Io is the same at Io1, the peak value Ip (H) at the operating point P1 (H) is lower than the peak value Ip (L) at the operating point P1 (L). Therefore, when the operation mode of the switching power supply 36 is the second case, the first factor causes a problem that “the higher the input voltage Vi, the larger the limit value Io2 of the output current Io”.

  The second factor is the operation waveform (FIG. 12 (a)) at the operating point P2 (L) where the input voltage Vi is low and the output current Io is Io2 (L), and the output current Io is high when the input voltage Vi is high. This can be considered by comparing the operation waveform of the operating point P2 (H) that is Io2 (H) (FIG. 12B).

  When the switching current Id rises to the right and reaches the current value Ir1, the main switching element 20 is turned off when the operation delay time td1 of the comparator 34 or the like has elapsed. Therefore, the switching current Id continues to rise during the time td1. The operating point P2 (L) has a small slope at which the drain current Id (L) rises because the input voltage Vi is low, so the drain current Id (L) rises to a value Ip (L) that slightly exceeds the current value Ir1. The limit value Io2 (L) of the output current Io is determined. On the other hand, since the operating point P1 (H) has a large slope at which the drain voltage Id (H) rises due to the high input voltage Vi, the drain current Id (L) greatly exceeds the current value Ir1 during the same time td. It rises to the value Ip (H). As a result, the limit value Io2 (H) of the output current Io is larger than the limit value Io2 (L). Therefore, even when the operation form of the switching power supply 36 is the second case, the second factor causes the problem that “the higher the input voltage Vi, the larger the upper limit value Io2 of the output current Io”.

  Next, in the switching power supply 36, a case (third case) in which the switching cycle Tsw varies and the pseudo resonance mode operation is performed will be described. The operation in the quasi-resonant mode is similar to the transformer current critical mode described above, except that the voltage across the main switching element 20 decreases to near zero after the rectifier diode 38a is turned off. Since the main switching element 20 is turned on after waiting, a time td2 (approximately constant) in which both the currents Id and if do not flow occurs. Therefore, the switching period Tsw in the quasi-resonant mode is a period obtained by adding the time td2 to the switching period Tsw in the transformer current critical mode.

  The first factor is the operation waveform (FIG. 13 (a)) at the operating point P1 (L) where the input voltage Vi is low and the output current Io is Io1 (<Io2 (L), Io2 (H)), and the input. It can be considered by comparing with the operation waveform (FIG. 13B) of the operating point P1 (H) where the voltage Vi is high and the output current Io is the same Io1, and the content to be considered is the second case described above. It is the same. Therefore, even when the operation mode of the switching power supply 36 is the third case, the first factor causes a problem that “the higher the input voltage Vi, the larger the limit value Io2 of the output current Io”.

  The second factor is the operation waveform (FIG. 14 (a)) at the operating point P2 (L) where the input voltage Vi is low and the output current Io is Io2 (L), and the output current Io is high when the input voltage Vi is high. This can be considered by comparing the operation waveform of the operation point P2 (H) that is Io2 (H) (FIG. 14B), and the contents to be considered are the same as those in the second case described above. Therefore, even when the operation mode of the switching power supply 36 is the third case, the second factor causes the problem that “the higher the input voltage Vi, the larger the upper limit value Io2 of the output current Io”.

  Next, the switching power supply device of Patent Document 1 will be considered. The switching power supply device of Patent Document 1 is a single-ended forward type with a constant switching cycle Tsw, and when performing a so-called inductor current continuous mode operation, the contents considered for the first and second factors are described above. It is the same as the switching power supply device 10. In addition, since this switching power supply device has the slope correction circuit, a third factor is newly generated. The third factor is “how does the correction voltage added to the current detection voltage change depending on the level of the input voltage Vi”.

  The third factor is the operation waveform (FIG. 15 (a)) of the operating point P1 (L) where the input voltage Vi is low and the output current Io is Io1 (<Io2 (L), Io2 (H)) and the input. This can be considered by comparing the operation waveform (FIG. 15B) of the operating point P1 (H) where the voltage Vi is high and the output current Io is the same Io1. FIG. 15A shows the waveform of the voltage input to the inverting input terminal of the comparator, the waveform of the current detection voltage Vd (L) output from the current detection resistor and the sawtooth correction generated in the first resistor. This is a combination of the waveform of the voltage Vb. ta (L) is a time during which the switching current Id (L) flows. The waveform of the current detection voltage Vd (L) becomes the waveform of the switching current Id (L) when divided by the resistance value of the current detection resistor. Vba (L) is the value of the correction voltage Vb when the time ta (L) ends. The same applies to FIG.

  The waveform of the sawtooth correction voltage Vb rises with a constant slope regardless of the level of the input voltage Vi. Since both the operating points P1 (L) and P2 (H) are turned on and off so that the output voltage Vo becomes the target value Vo1, the time ta (H) of the operating point P2 (H) is the operating point P2. The time ta (L) of (L) is longer, and the voltage value Vba (H) becomes smaller than Vba (L). As a result, although the output current Io is the same Io1, the difference between the peak value of the voltage at the inverting input terminal of the comparator and the first reference voltage Vr1 is larger at the operating point P1 (H). Therefore, in the switching power supply device circuit of Patent Document 1, the third factor causes the problem that “the higher the input voltage Vi, the larger the limit value Io2 of the output current Io”.

  The problems and causes of overcurrent protection of the five types of switching power supply devices have been described above. The contents are summarized as shown in Table 1.

The present invention has been made in view of the above-described background art, and an object of the present invention is to provide a switching power supply device that can easily suppress fluctuations in the limit value of the output current with respect to the level of the input voltage.

The present invention includes an input line and a ground line to which an input voltage is applied, a series circuit of a primary winding of a transformer and a main switching element connected between the input line and the ground line, A rectifying / smoothing circuit connected to a secondary winding, rectifying and smoothing a voltage generated in the secondary winding, and supplying an output voltage and an output current to a load, and inserted in a position in series with the main switching element, A current detection circuit that generates a positive current detection voltage by voltage-converting the switching current flowing through the main switching element and outputs it from the other end of the detection resistor connected to the ground line, and on / off the main switching element A control circuit for generating a drive pulse for controlling the on-time and off-time of the main switching element based on the output voltage. The control circuit has a comparator, and the comparator has a first input terminal connected to the output terminal of the detection resistor, a second input terminal set with a first reference voltage, and the first input terminal When the voltage at the input terminal exceeds the first reference voltage, the output of the comparator is inverted to invert the logic of the drive pulse, and the switching power supply device turns off the main switching element regardless of the output voltage. There,
A first correction resistor inserted between the other end of the detection resistor and the first input terminal of the comparator, a timer capacitor having one end connected to the ground line, and toward the other end of the timer capacitor A charging circuit that supplies a charging current that increases or decreases according to the level of the input voltage, and resets the voltage of the timer capacitor during an off period of the main switching element, and then the timer capacitor can be charged at the timing when the on starts. A discharge circuit, an emitter follower circuit having an NPN transistor whose base terminal is connected to the other end of the timer capacitor, an emitter terminal of the NPN transistor which is an output terminal of the emitter follower circuit, and the comparator A second correction resistor connected between the first input terminal and
While the main switching element is on, a correction current output from the emitter follower circuit through the second correction resistor flows through the first correction resistor, so that both ends of the first correction resistor correspond to the level of the input voltage. This is a switching power supply device that generates a sawtooth correction voltage whose inclination changes.

  The discharge circuit is a series circuit of a discharge resistor and a discharge diode connected between the other end of the timer capacitor and the output of the control circuit, and a cathode terminal of the discharge diode is arranged on the control circuit side. The main switching element is preferably turned on when the drive pulse output from the control circuit is at a high level and turned off when the drive pulse is at a low level.

  The control circuit generates a drive pulse generation circuit that generates the drive pulse, and an error amplification voltage obtained by amplifying a difference between the output voltage and a target value thereof, toward the second input terminal of the comparator. An error amplification circuit for outputting, and when the error amplification voltage is lower than the first reference voltage, the comparator is configured to output the error amplification voltage input to the second input terminal and the first input terminal. Current mode pulse width modulation may be performed using a voltage, and the drive pulse generation circuit may generate the drive pulse based on the modulation result.

  When the on-time ratio of the main switching element exceeds 50%, the on-time and the off-time of the main switching element are changed every switching period by the sawtooth correction voltage generated at both ends of the first correction resistor. It may be configured to prevent a changing current oscillation phenomenon.

  The error amplification circuit outputs the error amplification voltage to a drive pulse generation circuit, and the drive pulse generation circuit is set with a second reference voltage lower than the first reference voltage, and the drive pulse generation circuit When the error amplification voltage becomes lower than the second reference voltage, a burst mode operation in which a period for outputting the driving pulse and a period for stopping the driving pulse are alternately performed may be performed.

  The switching power supply device of the present invention is provided with an input correction circuit that generates a sawtooth correction voltage whose slope changes according to the level of the input voltage, and adds the correction voltage to the current detection voltage that detects the switching current. Thus, it is possible to suppress fluctuation of the limit value of the output current with respect to the input voltage. Further, the input correction circuit has a simple configuration and can easily adjust the correction amount (adjustment of the ratio of the correction voltage to the current detection voltage).

It is a circuit diagram showing one embodiment of a switching power supply device of the present invention. 2 is a graph (a) representing the error amplification voltage-output current characteristics of this embodiment, and a graph (b) representing the output voltage-output current characteristics. They are an operation waveform (a) at the operation point P1 (L) and an operation waveform (b) at the operation point P1 (H) of this embodiment. They are an operation waveform (a) at the operation point P1 (H) and an operation waveform (b) at the operation point P0 (H) of this embodiment. A circuit diagram (a) showing a conventional single-ended forward type switching power supply device, a circuit diagram (b) showing a conventional flyback type switching power supply device, and a circuit diagram (c) showing another example of a current detection circuit It is. It is the graph showing the output voltage-output current characteristic of the conventional switching power supply device. 6 is an operation waveform (a) at an operation point P1 (L) and an operation waveform (b) at an operation point P1 (H) of the switching power supply device shown in FIG. 6 is an operation waveform (a) at an operation point P2 (L) and an operation waveform (b) at an operation point P2 (H) of the switching power supply device shown in FIG. FIG. 6 is an operation waveform (a) at an operation point P1 (L) and an operation waveform (b) at an operation point P1 (H) of the switching power supply device (first case) shown in FIG. FIG. 6 is an operation waveform (a) at an operation point P2 (L) and an operation waveform (b) at an operation point P2 (H) of the switching power supply device (first case) shown in FIG. FIG. 6 is an operation waveform (a) at an operation point P1 (L) and an operation waveform (b) at an operation point P1 (H) of the switching power supply device (second case) shown in FIG. FIG. 6 is an operation waveform (a) at an operation point P2 (L) and an operation waveform (b) at an operation point P2 (H) of the switching power supply device (second case) shown in FIG. FIG. 6 is an operation waveform (a) at an operation point P1 (L) and an operation waveform (b) at an operation point P1 (H) of the switching power supply device (third case) shown in FIG. FIG. 6 is an operation waveform (a) at an operation point P2 (L) and an operation waveform (b) at an operation point P2 (H) of the switching power supply device (third case) shown in FIG. They are the operating waveform (a) at the operating point P1 (L) and the operating waveform (b) at the operating point P1 (H) of the switching power supply device of Patent Document 1 having the slope correction circuit.

  Hereinafter, an embodiment of a switching power supply device of the present invention will be described with reference to FIGS. Here, the same components as those of the conventional switching power supply devices 10 and 36 will be described with the same reference numerals. As shown in FIG. 1, the switching power supply 40 of this embodiment is a flyback type power supply that performs pulse-by-pulse overcurrent protection, performs current mode pulse width modulation, and performs switching. The pseudo resonance mode operation is performed by changing the frequency Tsw.

  A series circuit of the primary winding 18a of the transformer 18 and the main switching element 20 is provided between the input line 14 to which the input power supply 12 is connected and the ground line 16, and the primary switching element 20 is turned on and off, whereby the primary A voltage obtained by intermittently inputting the input voltage Vi is applied to the winding 18a. A rectifying / smoothing circuit 38 is connected to the secondary winding 18 b of the transformer 18 to rectify and smooth the voltage generated in the secondary winding 18 b, and supply a DC output voltage Vo and an output current Io to the load 24. Further, the transformer 18 is provided with an auxiliary winding 18c, and one end with a polarity dot is connected to the ground line 16.

  A detection resistor 26 a that is a current detection circuit 26 is inserted between the main switching element 20 and the ground line 16. A positive voltage drop occurs when the switching current Id of the main switching element 20 flows in the detection resistor 26a, and the voltage drop is output as the current detection voltage Vd.

  The main switching element 20 is an N-channel MOS FET here, and is driven by a drive pulse Vg44 output from the control circuit 42. The main switching element 20 is turned on when the drive pulse Vg44 is at a high level and turned off when the drive pulse Vg44 is at a low level.

  The control circuit 42 includes an error amplifier circuit 30, a comparator 34, and a drive pulse generation circuit 44. The error amplification circuit 30 generates an error amplification voltage V30 obtained by amplifying the difference between the output voltage Vo and the target value Vo1, and outputs the error amplification voltage V30 to the drive pulse generation circuit 44 and the comparator 34.

  The comparator 34 has first and second input terminals 34 (1) and 34 (2). The first input terminal 34 (1) is connected to the output terminal of the current detection circuit 26, and the second input terminal 34. (2) is connected to the output terminal of the error amplifier circuit 30. A Zener diode 46 is connected to the second input terminal 34 (2), and the first reference voltage Vr1 is set by the Zener voltage Vr1.

  When the error amplification voltage V30 is lower than the first reference voltage Vr1, the comparator 34 uses the error amplification voltage V30 and the voltage V34 (1) of the first input terminal 34 (1) to perform current mode pulse width modulation. . Then, the drive pulse generation circuit 44 generates a drive pulse Vg44 that brings the output voltage Vo close to the target value Vo1 based on the modulation output of the comparator 34. On the other hand, when the error amplification voltage V30 exceeds the first reference voltage Vr1, the comparator 34 outputs every time the voltage V34 (1) reaches the first reference voltage Vr1 set at the second input terminal 34 (2). The drive pulse generation circuit 44 receives the output inversion of the comparator 34 and inverts the drive pulse Vg44 to a low level. As a result, the on-time of the main switching element 20 is forcibly shortened, the output voltage Vo is reduced, and the output current Io is also limited.

  Further, the drive pulse generation circuit 44 observes the voltage of the auxiliary winding 18c in order to realize the quasi-resonant mode operation. Specifically, after the rectifier diode 38a becomes non-conductive, it is detected by observing the voltage Vs of the auxiliary winding 18a that the voltage across the main switching element 20 has dropped to near zero. The timing at which 20 turns on is determined.

  Further, when the second reference voltage Vr2 lower than the first reference voltage Vr1 is set in the drive pulse generation circuit 44 and the error amplification voltage V30 becomes lower than the second reference voltage Vr2, the drive pulse Vg44 is output and stopped. The burst mode operation is repeated alternately with the period to be performed. Since the control circuit 42 is configured so that the comparator 34 performs pulse width modulation of the current mode method, as shown in the graph of FIG. 2A, the error amplification voltage V30 decreases as the output current Io decreases. Therefore, when the error amplification voltage V30 becomes equal to or lower than the second reference voltage Vr2, the drive pulse generation circuit 44 determines that the output current Io has decreased below a certain level (for example, the load 24 has stopped operating and has entered a standby state). Determine and perform burst mode operation. When the burst mode operation is performed, useless power consumption such as switching loss generated in the main switching element 20 is suppressed, and energy saving of the power supply device can be achieved.

  In addition to the above configuration, the control circuit 42 is provided with an input correction circuit 48 for correcting the limit value Io2 of the output current Io according to the level of the input voltage Vi. As shown in FIG. 1, the input correction circuit 48 includes a first correction resistor 50, a timer capacitor 52, a charging resistor 54 that is a charging circuit, a discharging circuit 56, an emitter follower circuit 58, and a second correction resistor 60. Yes. The first correction resistor 50 is a resistor inserted between one end of the detection resistor 26a on the main switching element 20 side and the first input terminal 34 (1) of the comparator 34, and is sufficiently larger than the detection resistor 26a. Is set to a value. The timer capacitor 52 is a capacitor having a relatively small capacity and having one end connected to the ground line 16. The charging resistor 54 is a resistor connected between the input line 14 and the other end of the timer capacitor 52 and serves to supply a charging current that increases or decreases to the timer capacitor 52 according to the level of the input voltage Vi. The discharge circuit 56 is composed of a series circuit of a discharge resistor 56a and a discharge diode 56b having a small resistance value, and is connected between the other end of the timer capacitor 52 and the output end of the drive pulse generating circuit 44, and is the cathode of the discharge diode 56b. The terminals are arranged on the drive pulse generation circuit 44 side. The discharge circuit 56 functions to reset the voltage V52 of the timer capacitor 52 during the OFF period of the main switching element 20, and then to charge the timer capacitor at the timing when ON is started. The emitter follower circuit 58 has an auxiliary power supply circuit 58a for generating a DC voltage Vcc by peak-holding the voltage Vs of the auxiliary winding 18c, a base terminal connected to the other end of the timer capacitor 52, and a collector terminal connected to the auxiliary power supply circuit 58a. And an NPN transistor 58b connected to the output of No. 5 and outputs the voltage V52 from the emitter terminal to a low impedance. The second correction resistor 60 is connected between the emitter terminal of the NPN transistor 58 b which is the output of the emitter follower circuit 58 and the first input terminal 34 (1) of the comparator 34, and the correction current output from the emitter follower circuit 58. It works to adjust the size of Ib.

  The input correction circuit 48 operates as follows. During a period in which the drive pulse Vg44 is at a high level (a period in which the main switching element 20 is on), the discharge circuit 56 is turned off, the timer capacitor 52 is charged by the charging resistor 54, and the voltage V52 is inclined according to the level of the input voltage Vi. To rise. When the drive pulse Vg44 turns to low level (when the main switching element 20 turns off), the discharge circuit 56 becomes conductive, the voltage V52 is instantaneously reset through the discharge resistor 56a, and the voltage V52 becomes the forward voltage of the discharge diode 56b. Retained. Therefore, the voltage V52 has a sawtooth waveform that rises to the right with the forward voltage of the discharge diode 56b as an initial value.

  The output voltage of the emitter follower circuit 58 is a voltage obtained by subtracting the base-emitter saturation voltage of the NPN transistor 58b from the voltage V52, and the influence of the forward voltage of the discharge diode 56b is cancelled. Therefore, this discharge circuit 56 has an advantage that the base-emitter saturation voltage of the NPN transistor 58b is temperature-compensated by the forward voltage of the discharge diode 56b.

  The correction current Ib output from the emitter follower circuit 58 through the second correction resistor 60 flows to the first correction resistor 50 and the detection resistor 26a. The correction current Ib has a waveform similar to that of the output voltage of the emitter follower circuit 58, and a sawtooth correction voltage Vb whose slope changes according to the level of the input voltage Vi is generated at both ends of the first correction resistor 50.

  The input correction circuit 48 also functions to prevent a current oscillation phenomenon, similar to the slope correction circuit included in the switching power supply device of Patent Document 1. The current oscillation phenomenon is more likely to occur as the input voltage Vi is lower (when the slope of the switching current Id is smaller). Therefore, the input voltage correction circuit 48 is designed so that the slope of the correction voltage Vb is equal to or greater than a certain value even when the input voltage Vi is low, in order to reliably prevent the current oscillation phenomenon. When it is clear that the current oscillation phenomenon does not occur, it is not necessary to consider this at the time of designing (for example, when the ON ratio of the main switching element 20 does not exceed 50%).

  Next, the relationship between the input voltage Vi and the limit value Io2 of the output current Io will be described. In the case of the switching power supply 40, as shown in FIG. 2 (b), the limit value Io2 (H) when the input voltage Vi is high is set to the same value as the limit value Io (L) when the input voltage Vi is low. can do.

  Since the switching power supply 40 is a flyback type power supply operating in a quasi-resonant mode, the first factor is “depending on the input voltage Vi, the correlation between the output current Io and the peak value Ip of the switching current Id. And two factors, the second factor is "how the influence of the delay time of the comparator for overcurrent protection changes depending on the level of the input voltage Vi" However, this may cause a problem that “the higher the input voltage Vi, the larger the limit value Io2 of the output current Io”. This is as described with reference to FIGS. 13 and 14.

  However, in the case of the switching power supply device 40, the first factor and the second factor are canceled by the action of the unique correction voltage Vb output from the input correction circuit 48. First, the operating waveform (FIG. 3A) of the operating point P1 (L) where the input voltage Vi is low and the output current Io is Io1 (<Io2 (L), Io2 (H)) and the input voltage Vi is high. Then, the operation waveform (FIG. 3B) at the operation point P1 (H) where the output current Io is the same Io1 is compared. 3A shows the waveform of the voltage V34 (1) at the first input terminal 34 of the comparator 34. The waveform of the current detection voltage Vd (L) output from the detection resistor 26a and the first correction are shown in FIG. This is a combination of the waveform of the correction voltage Vb (L) generated in the resistor 50. ta (L) is a time during which the switching current Id (L) flows. The waveform of the current detection voltage Vd (L) becomes the waveform of the switching current Id (L) when divided by the resistance value of the detection resistor 26a. Vba (L) is the value of the correction voltage Vb when the time ta (L) ends. The same applies to FIG.

  As can be seen from FIGS. 3A and 3B, the correction voltage Vb generated by the input correction circuit 48 changes in slope according to the level of the input voltage Vi, and the voltage value Vba (H) is changed to the voltage value Vba (H Moderately higher than L). As a result, although the output current Io is the same Io1, the difference between the peak value of the voltage V34 (1) and the first reference voltage Vr1 is smaller at the operating point P1 (H). Therefore, the change in the slope of the correction voltage Vb works in a direction to cancel the first factor and the second factor, and the problem that “the higher the input voltage Vi, the larger the limit value Io2 of the output current Io” is solved.

  Further, since the switching power supply device 40 has the input correction circuit 48, the third factor is “how the correction voltage Vb added to the current detection voltage Vd varies depending on the level of the input voltage Vi. You should also consider the point of “do you?” However, in the case of the switching power supply device 40, the voltage value Vba (H) is higher than the voltage value Vba (L), unlike the switching power supply disclosed in Patent Document 1 described with reference to FIG. Therefore, the third factor does not cause the problem that “the higher the input voltage Vi, the larger the limit value Io2 of the output current Io”.

  Next, the relationship between the operation of the input correction circuit 48 and the burst mode operation performed by the drive pulse generation circuit 44 will be described. As described above, the comparator 34 of the switching power supply device 40 performs current mode pulse width modulation using the error amplification voltage V30 and the voltage V34 (1) of the first input terminal 34 (1). The error amplification voltage V30 becomes substantially equal to the peak value of the voltage V34 (1). Therefore, when the output current Io decreases, the voltage V34 (1) and the error amplification voltage V30 decrease, and when the error amplification voltage V30 becomes equal to or lower than the second reference voltage Vr1, a burst mode operation for suppressing power consumption is started.

  Here, the operating waveform (FIG. 4A) of the operating point P1 (H) where the input voltage Vi is high and the output current Io is Io1, and the operating point P0 where the input voltage Vi is high and the output current Io is very small. The operation waveform (H) (FIG. 4B) is compared. FIG. 4A shows the waveform of the voltage V34 (1) at the first input terminal 34 (1) of the comparator 34. The waveform of the current detection voltage Vd (H) output from the detection resistor 26a and the first correction are shown in FIG. The waveform of the correction voltage Vb (H) generated in the resistor 50 is combined. The same applies to FIG.

  As can be seen from FIGS. 4A and 4B, the drive pulse generation circuit 44 appropriately performs the burst mode operation at light load although the voltage V34 (1) includes the component of the correction voltage Vb. be able to. This is due to the fact that the correction voltage Vb has a sawtooth waveform that rises to the right.

  As a comparative example, the correction voltage Vb is a DC voltage, the value when the input voltage Vi is low is Vba (L), the value Vba (H) when high, and the magnitude relationship between these and the second reference voltage Vr2, Consider the case where Vba (H)> Vr2> Vba (L). In this case, when the input voltage Vi is low, when the output current Io becomes zero, the error amplification voltage V30 drops to almost Vba (L) and becomes lower than the second reference voltage Vr2, so that a burst mode operation can be performed. On the other hand, when the input voltage Vi is high, when the output current Io becomes zero, the error amplification voltage V30 decreases only to approximately Vba (H) and is maintained at a value higher than the second reference voltage Vr2, so that the burst mode operation is performed. I can't do it.

  As described above, the switching power supply 40 appropriately performs the burst mode operation when the output current Io is small, regardless of the level of the input voltage Vi, because the correction voltage Vb has a sawtooth waveform rising upward. Can be done.

As described above, the switching power supply device 40 is provided with the input correction circuit 48 that generates the sawtooth correction voltage Vb whose slope changes according to the level of the input voltage Vi, and the current detection voltage that detects the switching current Id. By adding the correction voltage Vb to Vd, it is possible to prevent the limit value Io2 of the output current Io from fluctuating with respect to the input voltage Vi. Further, the input correction circuit 48 has a simple configuration and can easily adjust the correction amount (adjustment of the ratio of the correction voltage Vd to the current detection voltage Vd). In addition, since the correction voltage Vb has a sawtooth waveform, the effect of preventing the current oscillation phenomenon and the effect of appropriately performing the burst mode operation at a light load can be obtained.
The switching power supply device of the present invention is not limited to the above embodiment. For example, the charging circuit of the input correction circuit may be any circuit that can supply a charging current that increases or decreases depending on the level of the input voltage toward the timer capacitor, and one end of the charging resistor 54 is not connected to the input line 14. Alternatively, it may be connected to another circuit portion whose potential changes depending on the level of the input voltage. Instead of the charging resistor 54, a voltage-current conversion circuit that converts the input voltage into a current signal and outputs the current signal may be used.

  The discharge circuit of the input correction circuit is not limited to the configuration of the discharge circuit 56 described above. For example, just like the switching power supply device of Patent Document 1, just before one switching cycle starts (just before the main switching element is turned on). Alternatively, the switch may be configured to reset the voltage of the timer capacitor.

  The current detection circuit may have a configuration in which a detection resistor 26a is inserted between the main switching element 20 and the ground line 16 as shown in FIG. 1, or a current transformer 26b or the like is used as shown in FIG. 4 (c). You may make it the structure which was.

  The switching power supply device 40 has a configuration in which the comparator 34 performs pulse width modulation of the current mode method, and the drive pulse generation circuit 44 performs the burst mode operation using this, but the function of the burst mode operation is necessary. It can be omitted accordingly. Further, the current mode method may be changed to the voltage mode method. In any case, similar to the above, it is possible to obtain an excellent effect such as suppression of fluctuations in the limit value Io2 of the output current Io with respect to the input voltage Vi.

  Further, the switching power supply device 40 corresponds to “a flyback power supply device in which the switching frequency fluctuates and operates in a quasi-resonant mode” in Table 1, and includes an input correction circuit having a novel configuration as described above. As a result, the influence of the first and second factors can be counteracted, and the adverse effect of the third factor does not occur. This new input correction circuit can also be applied to other circuit systems exemplified in Table 1, and the same operational effects can be obtained. For example, when applied to a “flyback type power supply device in which the switching frequency varies and the transformer current critical mode operation is performed”, the influence of the first and second factors can be canceled out. In the case of “single-end flyback type power supply device with constant switching frequency and continuous inductor current mode operation” and “flyback type power supply device with constant switching frequency and transformer current discontinuous mode operation” The influence of two factors can be counteracted. In addition, the present invention can be applied to various bridge type and push-pull type power supply devices. In the case of canceling two of the first and second factors, it is preferable to increase the correction amount (the ratio of the correction voltage to the current detection voltage) compared to the case of canceling only the second factor. Adjustment of the correction amount can be easily performed by changing the resistance values of the first and second correction resistors of the input correction circuit, the capacitance value of the timer capacitor, the magnitude of the charging current of the charging circuit, and the like.

10, 36, 40 Switching power supply device 14 Input line 16 Ground line 18 Transformer 18a Input winding 18b Output winding 20 Main switching element 22, 38 Rectification smoothing circuit 26 Current detection circuit 26a Detection resistance 28, 42 Control circuit 30 Error amplification circuit 32, 44 Drive pulse generation circuit 34 Comparator 34 (1) First input terminal 34 (2) Second input terminal 48 Input correction circuit 50 First correction resistor 52 Timer capacitor 54 Charging resistor (charging circuit)
56 discharge circuit 56a discharge resistor 56b discharge diode 58 emitter follower circuit 58b NPN transistor 60 second correction resistor
Ib correction current
Id switching current
Io output current
Io2 limit value
V30 Error amplification voltage
V34 (1) Voltage of the first input terminal
Vb correction voltage
Vd Current detection voltage
Vg44 drive pulse
Vi input voltage
Vo output voltage
Vo1 output voltage target value
Vr1 first reference voltage
Vr2 Second reference voltage

Claims (5)

An input line to which an input voltage is applied, a ground line, a series circuit of a primary winding of the transformer and a main switching element connected between the input line and the ground line, and a secondary winding of the transformer A rectifying / smoothing circuit that rectifies and smoothes a voltage generated in the secondary winding and supplies an output voltage and an output current to a load; and is inserted in a position in series with the main switching element; A current detection circuit that generates a positive current detection voltage by voltage-converting the flowing switching current and outputs one end from the other end of the detection resistor connected to the ground line, and a drive for turning on and off the main switching element A control circuit that generates a pulse and controls an on time and an off time of the main switching element based on the output voltage.
The control circuit includes a comparator, and the comparator has a first input terminal connected to an output terminal of the detection resistor, a second input terminal set with a first reference voltage, and a voltage at the first input terminal. When the voltage exceeds the first reference voltage, the output of the comparator is inverted to invert the logic of the driving pulse, and the switching power supply device that turns off the main switching element regardless of the output voltage,
A first correction resistor inserted between the other end of the detection resistor and the first input terminal of the comparator, a timer capacitor having one end connected to the ground line, and toward the other end of the timer capacitor A charging circuit that supplies a charging current that increases or decreases according to the level of the input voltage, and resets the voltage of the timer capacitor during an off period of the main switching element, and then the timer capacitor can be charged at the timing when the on starts. A discharge circuit, an emitter follower circuit having an NPN transistor whose base terminal is connected to the other end of the timer capacitor, an emitter terminal of the NPN transistor which is an output terminal of the emitter follower circuit, and the comparator A second correction resistor connected between the first input terminal and
While the main switching element is on, a correction current output from the emitter follower circuit through the second correction resistor flows through the first correction resistor, so that both ends of the first correction resistor correspond to the level of the input voltage. A switching power supply device characterized by generating a sawtooth correction voltage whose inclination changes. The discharge circuit is a series circuit of a discharge resistor and a discharge diode connected between the other end of the timer capacitor and the output of the control circuit, and a cathode terminal of the discharge diode is arranged on the control circuit side. ,
2. The switching power supply device according to claim 1, wherein the main switching element is turned on when the drive pulse output from the control circuit is at a high level and turned off when the drive pulse is at a low level. The control circuit generates a drive pulse generation circuit that generates the drive pulse, and an error amplification voltage obtained by amplifying a difference between the output voltage and a target value thereof, toward the second input terminal of the comparator. An error amplifier circuit for output,
When the error amplification voltage is lower than the first reference voltage, the comparator uses the error amplification voltage input to the second input terminal and the voltage of the first input terminal to generate a current mode type pulse. 3. The switching power supply device according to claim 1, wherein width modulation is performed, and the drive pulse generation circuit generates the drive pulse based on the modulation result.   When the on-time ratio of the main switching element exceeds 50%, the on-time and the off-time of the main switching element are changed every switching period by the sawtooth correction voltage generated at both ends of the first correction resistor. 4. The switching power supply device according to claim 3, wherein a changing current oscillation phenomenon is prevented. The error amplification circuit outputs the error amplification voltage to a drive pulse generation circuit,
A second reference voltage lower than the first reference voltage is set in the drive pulse generation circuit, and the drive pulse generation circuit outputs the drive pulse when the error amplification voltage becomes lower than the second reference voltage. 6. The switching power supply device according to claim 4, wherein a burst mode operation that alternately repeats a period for stopping and a period for stopping is performed.