JP2015185574A - El device, and method of manufacturing el device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an EL device capable of suppressing generation of control defects, and to provide a method of manufacturing the EL device.SOLUTION: A thin-film transistor comprises: a gate electrode layer; and two terminal electrode layers that are connected with one surface included in a semiconductor layer, and that are opposed to an end part of the gate electrode layer in a channel length direction while interposing the semiconductor layer. On the one surface, a distance between the terminal electrode layers in the channel length direction is a channel length, and a length of the gate electrode layer in the channel length direction is a gate electrode length. A difference between the gate electrode length and the channel length is a channel length/gate electrode length difference. A channel length/gate electrode length difference of a holding transistor T2 is larger than that of a drive transistor T1.

Description

  The technology of the present disclosure relates to an EL device including a holding transistor that holds a voltage for driving a driving transistor in a holding capacitor, and a method for manufacturing the EL device.

  An electroluminescence (EL) device includes, for example, a plurality of EL elements arranged in a matrix, and each of the plurality of EL elements is connected to different pixel circuits. Each of the plurality of pixel circuits includes, for example, a drive transistor, a storage capacitor connected between the gate and the source of the drive transistor, a storage transistor connected to both electrodes of the storage capacitor, and a selection transistor.

  The driving transistor constituting the pixel circuit is connected to the power supply driver through the power supply line, and a drive current corresponding to the holding voltage of the storage capacitor is passed from the power supply line to the EL element. The selection transistor constituting the pixel circuit is connected to one of the two electrodes of the holding capacitor and the data line, and the holding transistor constituting the pixel circuit is connected to the other of the two electrodes of the holding capacitor and the power line. Yes. The holding transistor and the selection transistor selected by the selection driver hold the voltage corresponding to the difference between the light emission level of the power supply line and the gradation level of the data line in the holding capacitor (for example, Patent Document 1 and , See Patent Document 2).

JP 2003-195810 A JP 2012-73498 A

By the way, a thin film transistor such as a holding transistor may have a defect in a channel, and the defect included in the channel is one factor that causes an off-state thin film transistor to flow an off current. Then, when the off-current flows in the holding transistor that connects the power supply line and the holding capacitor, the current value of the current flowing in the driving transistor is different from the current value based on the gradation data. As a result, control defects such as a bright spot defect in the black display of the EL element and a dark spot defect in the white display of the EL element occur.
An object of the technology of the present disclosure is to provide an EL device capable of suppressing the occurrence of a control defect and a method for manufacturing the EL device.

  In one embodiment of the EL device according to the present disclosure, a holding transistor and a power supply line are connected to hold a voltage in the holding capacitor, and a current corresponding to the voltage held in the holding capacitor is supplied to the EL element. A plurality of thin film transistors including a driving transistor. The thin film transistor includes a gate electrode layer and two terminal electrode layers connected to one surface of the semiconductor layer, each of the two terminal electrode layers sandwiching an end portion of the gate electrode layer and the semiconductor layer Are facing each other. The distance between the two terminal electrode layers is the channel length. The length of the gate electrode layer along the channel length direction is the gate electrode length, and the difference between the gate electrode length and the channel length is the channel length / gate electrode length difference. The channel length / gate electrode length difference of the holding transistor is larger than the channel length / gate electrode length difference of the driving transistor.

  In one embodiment of a method for manufacturing an EL device according to the present disclosure, a holding transistor that connects a holding capacitor and a power supply line to hold a voltage in the holding capacitor, and a current corresponding to the voltage held in the holding capacitor is EL. The step of forming the thin film transistor, which is a manufacturing method of an EL device including a plurality of thin film transistors including a driving transistor that flows through the element, includes a step of forming a gate electrode layer on a substrate, and a gate insulation of the gate electrode layer A step of covering the gate insulating layer with a semiconductor layer, a step of forming two ohmic contact layers and two terminal electrode layers on the semiconductor layer, the gate electrode in the channel length direction Forming the ohmic contact layer and the terminal electrode layer in this order at a position facing the end of the layer. . A distance between the terminal electrode layers along the channel length direction on the one surface is a channel length, a length of the gate electrode layer along the channel length direction is a gate electrode length, and the gate electrode length The difference from the channel length is the channel length / gate electrode length difference. In the step of forming the terminal electrode layer, the difference between the channel length / gate electrode length of the holding transistor is made larger than the channel length / gate electrode length difference of the driving transistor.

  According to the aspect of the technology of the present disclosure, the channel length / gate electrode length difference of the holding transistor is larger than the channel length / gate electrode length difference of the driving transistor, so that the off-current of the holding transistor is suppressed more than that of the driving transistor. As a result, control defects such as a bright spot defect in the black display of the EL element and a dark spot defect in the white display of the EL element can be suppressed as compared with an EL device including a holding transistor having the same configuration as the drive transistor.

  In another aspect of the EL device according to the present disclosure, the thin film transistor further includes a stopper layer connected to the one surface and positioned between the two terminal electrode layers, and defining the channel length between the two terminal electrode layers. It is preferable.

  According to another aspect of the EL device of the present disclosure, the distance between the two terminal electrode layers is determined by the stopper layer that is one layer structure. As a result, the channel length is determined by the stopper layer, and the gate electrode length is determined by the gate electrode layer. Therefore, the channel length in the thin film transistor and the channel length / gate electrode length difference in the thin film transistor are set by one layer structure for each, so that the setting is easy.

  In another aspect of the EL device according to the present disclosure, the two electrode terminal layers include a source electrode layer and a drain electrode layer, and are close to the source electrode layer in both ends of the stopper layer in the channel length direction. The end is a first stopper end, and the end close to the drain electrode layer is a second stopper end. Of the both ends of the gate electrode layer in the channel length direction, an end close to the source electrode layer is a first electrode end, and an end close to the drain electrode layer is a second electrode end. A distance along the channel length direction between the first stopper end and the first electrode end is a source side channel length / gate electrode length difference. A distance along the channel length direction between the second stopper end and the second electrode end is a drain side channel length / gate electrode length difference. In the driving transistor, the stopper layer is an upper layer than the gate electrode layer, and the source side channel length / gate electrode length difference and the drain side channel length / gate electrode length difference are equal to each other.

  According to another aspect of the EL device of the present disclosure, the source-side channel length / gate electrode length difference and the drain-side channel length / gate electrode length difference are equal to each other in the driving transistor. It is possible to use a self-alignment technique. That is, it is possible to form the gate electrode layer before the stopper layer and to expose the resist mask used for patterning the stopper layer using the gate electrode layer as a mask.

  In another aspect of the EL device according to the present disclosure, of the two electrodes of the storage capacitor, the electrode connected to the storage transistor is the first electrode, and the electrode different from the first electrode is the second electrode. . The plurality of thin film transistors include a selection transistor that connects a data line and the second electrode and applies a grayscale voltage in the data line to the second electrode, and the channel length / gate electrode length of the holding transistor The difference is larger than the channel length / gate electrode length difference of the selection transistor.

  According to another aspect of the EL device of the present disclosure, since the channel length / gate electrode length difference of the holding transistor is larger than the channel length / gate electrode length difference of the selection transistor, the off-current of the holding transistor is suppressed more than the selection transistor. It is done. As a result, control defects such as a bright spot defect in the black display of the EL element and a dark spot defect in the white display of the EL element can be suppressed as compared with an EL device including a holding transistor having the same configuration as the selection transistor.

  In another aspect of the EL device according to the present disclosure, of the two electrodes of the storage capacitor, the electrode connected to the storage transistor is the first electrode, and the electrode different from the first electrode is the second electrode. . The plurality of thin film transistors include a selection transistor that connects a data line and the second electrode and applies a grayscale voltage in the data line to the second electrode, wherein the stopper layer includes the gate It is an upper layer than the electrode layer, and the source side channel length / gate electrode length difference and the drain side channel length / gate electrode length difference are equal to each other.

  According to another aspect of the EL device of the present disclosure, the source-side channel length / gate electrode length difference and the drain-side channel length / gate electrode length difference in the selection transistor are equal to each other. It is possible to use a self-alignment technique. That is, it is possible for both the selection transistor and the drive transistor to form the gate electrode layer before the stopper layer and to expose the resist mask used for patterning the stopper layer using the gate electrode layer as a mask. is there.

  In another aspect of the EL device according to the present disclosure, a first selection line to which a first selection signal that changes between a first selection level and a first non-selection level is input, a second selection level, and a second non-selection level. A second selection line to which a second selection signal to be changed is input. The gate electrode layer included in the holding transistor is connected to the first selection line, and the gate electrode layer included in the selection transistor is connected to the second selection line.

  According to another aspect of the EL device of the present disclosure, the holding transistor and the selection transistor transition between an on state and an off state in response to input of different selection signals. Therefore, the first non-selection level input to the holding transistor and the second non-selection level input to the selection transistor can be set to different levels. As a result, it is possible to set the first non-selection level input to the holding transistor to a level specialized for suppressing the off-current in the holding transistor.

  In another aspect of the EL device according to the present disclosure, the EL device further includes a selection driver that changes the selection signal between a selection level and a non-selection level. The holding transistor has a gate to which the selection signal is input, and electrically writes the voltage to the holding capacitor by electrically connecting the holding capacitor and the power supply line by inputting the selection level. The selection driver sets the selection signal to the selection level in the writing operation, and sets the selection signal to the non-selection level in the light emission operation. In the selection driver, the voltage at which the on-current rises is the first level, the voltage at which the off-current rises is the second level, and the non-selection level is set to the first level. And between the second level and the second level.

  According to another aspect of the EL device of the present disclosure, since the non-selection level is positioned between the first level and the second level, it is possible to suppress the off current of the holding transistor from flowing in the light emitting operation.

  In another aspect of the method for manufacturing an EL device according to the present disclosure, the step of forming the thin film transistor includes a step of laminating a stopper film on the semiconductor layer before forming the terminal electrode layer, Forming a resist film, forming a resist mask in a portion facing the gate electrode layer by exposure and development of the resist film, and forming a stopper layer by etching the stopper film using the resist mask; And a process. In the step of forming the terminal electrode layer, an ohmic contact thin film and a terminal metal film covering the stopper layer are formed in this order on the semiconductor layer, and the terminal metal film and the ohmic contact thin film are formed on the semiconductor layer. Etching the terminal metal film and the ohmic contact thin film so as to be divided on the stopper layer. In the step of forming the resist mask, the resist mask for determining the channel length of the driving transistor is formed by exposure from the back side of the substrate using the gate electrode layer as a mask, and the holding The resist mask for forming a transistor is preferably formed by exposure from the surface side of the substrate.

  According to another aspect of the EL device manufacturing method of the present disclosure, the driving transistor is a thin film transistor having a relatively small channel length / gate electrode length difference, and the channel length of the driving transistor masks the gate electrode layer. Determined through exposure. Therefore, although the channel length / gate electrode length difference determined by the two terminal electrode layers and the gate electrode layer is relatively small, it is possible to ensure the accuracy.

  On the other hand, the holding transistor is a thin film transistor having a relatively large channel length / gate electrode length difference, and is formed through exposure in which exposure light is not easily irradiated to the semiconductor layer between the gate electrode layer and the stopper layer. Therefore, in the holding transistor, generation of defects due to exposure is suppressed, and consequently, off current is further suppressed.

  According to the EL device and the EL device manufacturing method according to the technique of the present disclosure, control defects are suppressed.

It is a block diagram which shows the structure of EL device in one Embodiment of EL device in the technique of this indication, Comprising: It is a figure shown in the state which planarly viewed the EL panel. It is an electric circuit diagram which shows an example of the electrical constitution which the pixel in one Embodiment has. It is a timing chart which shows an example of the operation transition of the pixel in one embodiment. FIG. 3 is a circuit diagram showing a pixel circuit according to an embodiment together with potentials of nodes, and is a diagram showing a state during a writing operation in black display. It is a circuit diagram which shows the pixel circuit in one Embodiment with the electric potential of each node, Comprising: It is a figure which shows the state at the time of the light emission operation | movement in black display. FIG. 3 is a circuit diagram showing a pixel circuit according to an embodiment together with potentials of nodes, and is a diagram showing a state during a writing operation in white display. It is a circuit diagram which shows the pixel circuit in one Embodiment with the electric potential of each node, Comprising: It is a figure which shows the state at the time of the light emission operation | movement in white display. 4 is a timing chart showing an example of an operation flow in an i-th row pixel and an operation flow in an (i + 1) -th row pixel of the EL device according to the embodiment. 4 is a time chart illustrating an example of an operation flow in an upper pixel group and an operation flow in a lower pixel group included in an EL device according to an embodiment. It is a characteristic view which shows the characteristic line of the drive transistor in one Embodiment, Comprising: It is a figure which shows a characteristic line when a drive transistor is diode-connected. It is a graph which shows the load line of the EL element in one Embodiment. It is a characteristic view which shows the characteristic line of the drive transistor in one Embodiment, Comprising: It is a figure which shows a characteristic line when the diode connection of a drive transistor is cancelled | released. FIG. 4 is a characteristic diagram illustrating a characteristic line of a driving transistor according to an embodiment, and illustrates a load line of an EL element together with a characteristic line of the driving transistor in association with a difference between a light emission voltage and a reference voltage. FIG. 4 is a characteristic diagram illustrating a characteristic line of a driving transistor according to an embodiment, and illustrates a load line of an EL element together with a characteristic line of the driving transistor in association with a difference between a light emission voltage and a reference voltage. It is a top view which shows arrangement | positioning of the drive transistor, holding | maintenance transistor, and selection transistor in one Embodiment based on the planar structure of a pixel. It is a top view which shows the planar structure of the drive transistor in one Embodiment. It is sectional drawing which shows the cross-section of the drive transistor in one Embodiment. It is a top view which shows the planar structure of the holding transistor in one Embodiment. It is sectional drawing which shows the cross-section of the holding transistor in one Embodiment. It is a figure explaining the manufacturing method of the EL apparatus in one Embodiment, (a) (b) is process sectional drawing which shows the patterning process of the etching stopper layer which a holding transistor has. It is a figure explaining the manufacturing method of the EL apparatus in one Embodiment, (a) (b) is process sectional drawing which shows the patterning process of the etching stopper layer which a drive transistor has. 4 is a graph showing a relationship between a gate-source voltage and an on-current of a thin film transistor and a relationship between a gate-source voltage and an off-current in an embodiment. It is a graph which shows the relationship between the gate-drain voltage and off-state current of the selection transistor in one Embodiment. It is an electric circuit diagram which shows an example of the electrical constitution which the pixel in 2nd Embodiment has. FIG. 10 is a circuit diagram showing a pixel circuit according to a second embodiment together with potentials of nodes, and is a diagram showing a state during a writing operation in black display. It is a circuit diagram which shows the pixel circuit in 2nd Embodiment with the electric potential of each node, Comprising: It is a figure which shows the state at the time of the light emission operation | movement in black display. FIG. 6 is a circuit diagram showing a pixel circuit according to a second embodiment together with potentials of nodes, and is a diagram showing a state during a writing operation in white display. It is a circuit diagram which shows the pixel circuit in 2nd Embodiment with the electric potential of each node, Comprising: It is a figure which shows the state at the time of the light emission operation | movement in white display.

[First Embodiment]
With reference to FIG. 1 to FIG. 23, an EL device and a method for manufacturing the EL device according to an embodiment embodying the technique of the present disclosure will be described.

[EL device 100]
An example of the configuration of the EL device will be described with reference to FIG.
As shown in FIG. 1, the EL device 100 includes a display signal generation unit 110, a system controller 120, a selection driver 130, a data driver 140, a power supply driver 150, and an EL panel 160.

  The display signal generation unit 110 accepts the video signal SIG from the outside of the EL device 100, extracts the gradation voltage component included in the video signal SIG from the video signal SIG, and the gradation voltage component is a digital signal as gradation data D1. Convert to Then, the display signal generation unit 110 sequentially outputs the gradation data D1 for each row of the EL panel 160 to the data driver 140. The display signal generation unit 110 extracts or generates a timing signal SCLK such as a system clock for displaying an image based on the gradation data D1 on the EL panel 160, and outputs the timing signal SCLK to the system controller 120. When the video signal SIG includes a timing signal component that defines the display timing of an image, such as a composite video signal such as a television broadcast signal, for example, the display signal generation unit 110 has a function of extracting a gradation voltage component. In addition, the timing signal component is extracted and output to the system controller 120.

  The system controller 120 generates a selection control signal SCON1 for controlling the driving of the selection driver 130 based on the timing signal SCLK output from the display signal generation unit 110, and outputs the selection control signal SCON1 to the selection driver 130. To do. Based on the timing signal SCLK output from the display signal generation unit 110, the system controller 120 generates a data control signal SCON2 for controlling the driving of the data driver 140, and outputs the data control signal SCON2 to the data driver 140. To do. Based on the timing signal SCLK output from the display signal generation unit 110, the system controller 120 generates a power control signal SCON3 for controlling driving of the power driver 150, and outputs the power control signal SCON3 to the power driver 150. To do.

  The EL panel 160 includes a plurality of selection lines Ls extending along the row direction that is one direction, a plurality of power supply lines Lv that also extend along the row direction, and a column direction that is a direction orthogonal to the row direction. And a plurality of extending data lines Ld. In a plan view, the pixel PIX is located in the vicinity of a portion where each of the plurality of selection lines Ls and each of the plurality of data lines Ld intersect. The pixels PIX are located in a matrix composed of n rows × m columns (n and m are arbitrary positive integers).

  Each of the plurality of selection lines Ls is electrically connected to the selection driver 130, and the plurality of pixels PIX located in a matrix are connected to one selection line Ls for each row of pixels PIX.

  Each of the plurality of data lines Ld is electrically connected to the data driver 140, and the plurality of pixels PIX located in a matrix are connected to one data line Ld for each column of pixels PIX.

  The plurality of pixels PIX located in a matrix form includes an upper pixel group composed of a plurality of pixels PIX located in the upper half in the vertical direction in FIG. 1 and a plurality of pixels located in the lower half in the vertical direction in FIG. It is divided into a lower pixel group consisting of PIX. Among the plurality of pixels PIX constituting the upper pixel group, the pixels PIX for one row are connected to one power supply line Lv, and the plurality of power supply lines Lv connected to the plurality of pixels PIX constituting the upper pixel group are power drivers. 150 is commonly connected. Also in the plurality of pixels PIX constituting the lower pixel group, the pixels PIX for one row are connected to one power supply line Lv, and the plurality of power supply lines Lv connected to the plurality of pixels PIX constituting the lower pixel group are This is also commonly connected to the power supply driver 150.

  The selection driver 130 includes, for example, a shift register that sequentially outputs a shift signal corresponding to each of the plurality of selection lines Ls for each row based on a selection control signal SCON1 output from the system controller 120. In addition, the selection driver 130 includes an output buffer that outputs the selection signal Vsel obtained by converting the shift signal to the selection level H to the selection line Ls of the row corresponding to the shift signal.

  The selection driver 130 sequentially outputs the selection signal Vsel set to the selection level H to each of the plurality of selection lines Ls based on the selection control signal SCON1 output from the system controller 120, and each of the plurality of pixels PIX. Is selected for each row. For example, the selection driver 130 outputs the selection signal Vsel set to the selection level H to the selection line Ls in the specific row in the writing operation of the pixel PIX located in the specific row. Then, the selection driver 130 sequentially outputs the selection signal Vsel set to the selection level H to each row, and sequentially sets each of the plurality of pixels PIX to the selected state for each row.

  The data driver 140 includes, for example, a shift register that sequentially fetches the gradation data for each pixel PIX output from the display signal generation unit 110 one row at a time based on the data control signal SCON2 output from the system controller 120. Yes. Further, the data driver 140 includes a data latch unit that holds each row of gradation data fetched into the shift register in association with different columns. In addition, the data driver 140 generates a gradation level Vdata that is a potential corresponding to the gradation data for each column held in the data latch unit, and outputs a signal set to the gradation level Vdata to the column corresponding to the gradation level Vdata. An output circuit for outputting to the data line Ld is provided.

  The data driver 140 sequentially holds the gradation data for each pixel PIX output from the display signal generation unit 110 for each row. Then, the data driver 140 generates a gradation level Vdata for each column that is a potential corresponding to the gradation data, and simultaneously outputs a signal set to the gradation level Vdata to the data line Ld of each column. .

  The power driver 150 includes a timing generator that generates timing signals corresponding to each of the two pixel groups based on, for example, the power control signal SCON3 output from the system controller 120. The power supply driver 150 converts the timing signal generated by the timing generator into a predetermined voltage level based on the power supply control signal SCON3 output from the system controller 120, and supplies it to the power supply lines Lv of the two pixel groups. An output buffer for outputting the power supply signal Vcc is provided.

  Based on the power supply control signal SCON3 output from the system controller 120, the power supply driver 150 is configured to write each of the plurality of power supply lines Lv connected to the specific pixel group in the writing operation of the pixel PIX configuring the specific pixel group. Write level Vccw is set to the potential. For example, the power supply driver 150 sets the write level Vccw to the potential of each of the plurality of power supply lines Lv connected to the upper pixel group in the write operation of the pixels PIX constituting the upper pixel group. On the other hand, in the light emission operation of the pixel PIX constituting the specific pixel group, the power supply driver 150 has a light emission level Vcss different from the write level Vccw at each potential of the plurality of power supply lines Lv connected to the specific pixel group. Set. For example, the power supply driver 150 sets the light emission level Vcss to the potential of each of the plurality of power supply lines Lv connected to the upper pixel group in the light emission operation of the pixels PIX constituting the upper pixel group.

[Configuration and Operation of Pixel PIX]
An example of the configuration and operation of the pixel PIX will be described with reference to FIG. 2 and FIG.
As shown in FIG. 2, each of the plurality of pixels PIX includes an EL element OEL that is a current-driven light emitting element, and a pixel circuit DC for driving the EL element OEL. The pixel circuit DC includes a drive transistor T1, a holding transistor T2, a selection transistor T3, and a holding capacitor Cs.

  The drive transistor T1 is an n-channel transistor, and the gate of the drive transistor T1 is electrically connected to the node N1. The source of the driving transistor T1 is electrically connected to the anode of the EL element OEL through the node N2, and the drain of the driving transistor T1 is electrically connected to the power supply line Lv through the node N3. The drive transistor T1 has a function of causing a drive current corresponding to the voltage between the gate and the source of the drive transistor T1 to flow to the EL element OEL.

  The anode of the EL element OEL is electrically connected to the node N2 in the pixel circuit DC, and a reference level Vss such as a ground level is set as the cathode potential of the EL element OEL.

  Of the two electrodes of the storage capacitor Cs, the first electrode is electrically connected to the node N1, and among the two electrodes of the storage capacitor Cs, the second electrode is electrically connected to the node N2. The storage capacitor Cs may be a parasitic capacitor formed between the gate of the driving transistor T1 and the source of the driving transistor T1, or may be a capacitive element provided separately between the node N1 and the node N2. Or a combination thereof. The holding capacitor Cs has a function of holding the voltage between the gate and the source of the driving transistor T1.

  The holding transistor T2 is an n-channel transistor, and the gate of the holding transistor T2 is electrically connected to the selection line Ls through the node N4. The drain of the holding transistor T2 is electrically connected to the power supply line Lv through the node N3, and the source of the holding transistor T2 is electrically connected to the node N1. The holding transistor T2 has a function of selecting whether or not the drive transistor T1 is diode-connected based on the level of the selection signal Vsel input to the selection line Ls.

  The selection transistor T3 is an n-channel transistor, and the gate of the selection transistor T3 is electrically connected to the selection line Ls. The source of the selection transistor T3 is electrically connected to the data line Ld, and the drain of the selection transistor T3 is electrically connected to the node N2. The selection transistor T3 has a function of holding a voltage corresponding to the gradation level Vdata in the holding capacitor Cs in cooperation with the driving transistor T1 and the holding transistor T2.

  As shown in FIG. 3, the operation of the pixel PIX includes a writing operation, a holding operation, and a light emitting operation, and the pixel PIX sequentially repeats the writing operation, the holding operation, and the light emitting operation.

  In the writing operation in the pixel PIX, the selection driver 130 sets the selection signal Vsel to the selection level H, and the holding transistor T2 and the selection transistor T3 are turned on. In the writing operation in the pixel PIX, the power supply driver 150 sets the power supply signal Vcc to the write level Vccw, and the holding transistor T2 and the selection transistor T3 apply a voltage corresponding to the gradation level Vdata to the holding capacitor Cs. Write to.

  In the holding operation in the pixel PIX, the selection driver 130 changes the selection signal Vsel from the selection level H to the non-selection level L, and the holding transistor T2 and the selection transistor T3 transition from the on state to the off state. In the holding operation in the pixel PIX, the power driver 150 keeps the power signal Vcc at the writing level Vccw, and the holding transistor T2 and the selection transistor T3 hold the voltage at the writing operation in the holding capacitor Cs.

  In the light emission operation in the pixel PIX, the selection driver 130 maintains the selection signal Vsel at the non-selection level L, and the holding transistor T2 and the selection transistor T3 hold the off state. In the light emission operation in the pixel PIX, the power supply driver 150 changes the power supply signal Vcc from the write level Vccw to the light emission level Vcss, and the drive transistor T1 generates a drive current corresponding to the voltage held in the storage capacitor Cs by the EL element. Flow in OEL.

[Bright spot defect in black display]
With reference to FIGS. 4 and 5, an example of the potential of each terminal during the black display write operation, an example of the potential of each terminal during the black display light emission operation, and the bright spot defect in the black display Will be explained.

  As shown in FIG. 4, in the writing operation in the black display, the selection driver 130 uses the selection signal Vsel set to 15 V, which is an example of the selection level H, as the gate of the holding transistor T2 and the gate of the selection transistor T3. To enter. Then, the selection driver 130 causes the holding transistor T2 and the selection transistor T3 to transition to the on state. As a result, the gate of the driving transistor T1 and the drain of the driving transistor T1 become conductive, the driving transistor T1 is diode-connected, and the source of the driving transistor T1 is connected to the data line Ld.

  The power supply driver 150 is an example of the write level Vccw and sets 0V equal to the reference level Vss to the potential of the power supply line Lv, and the data driver 140 is an example of the gray level Vdata for black display. 0V equal to the level Vss is set to the potential of the data line Ld. As a result, the source potential of the drive transistor T1 is set to 0V, and the gate potential of the drive transistor T1 is set equal to the potential of the drain of the drive transistor T1. Since the drain-source voltage Vds of the driving transistor T1 is 0 V, the drain-source current Ids does not flow. At this time, since the drive transistor T1 is diode-connected, the drain-source voltage Vds of the drive transistor T1 is equal to the gate-source voltage Vgs, and 0V is written to the storage capacitor Cs as the gate-source voltage Vgs. It is.

  In the holding operation in black display, the selection driver 130 inputs the selection signal Vsel set to −14V, which is an example of the non-selection level L, to the gate of the holding transistor T2 and the gate of the selection transistor T3. Then, the selection driver 130 causes the holding transistor T2 and the selection transistor T3 to transition to the off state. As a result, the gate of the drive transistor T1 and the drain of the drive transistor T1 become non-conductive, and the diode connection in the drive transistor T1 is released. In addition, the source of the drive transistor T1 and the data line Ld are not conductive.

  As shown in FIG. 5, in the light emission operation in the black display, the selection driver 130 uses the selection signal Vsel set to −14V, which is an example of the non-selection level L, to the gate of the holding transistor T2 and the selection transistor T3. Keep typing at the gate. Then, the selection driver 130 maintains the holding transistor T2 and the selection transistor T3 in the off state.

  The power supply driver 150 sets 15V, which has a polarity opposite to the non-selection level L and is higher than the reference level Vss, to the potential of the power supply line Lv as an example of the light emission level Vcss. The data driver 140 continues to set 0V equal to the reference level Vss as the potential of the data line Ld as an example of the black display gradation level Vdata. As a result, although the drain potential of the drive transistor T1 is set to a level higher than that of the source of the drive transistor T1, the gate-source voltage Vgs held in the holding capacitor Cs is 0 V. The drain-source current Ids does not flow between the drain and the source, and the EL element OEL does not emit light.

  On the other hand, in such a black display light emission operation, a large reverse bias of −29 V corresponding to the difference between the non-selection level L and the light emission level Vcss is applied between the gate of the holding transistor T2 and the node N3. . Therefore, if the leakage current caused by the gate-drain voltage Vgd of the holding transistor T2 flows to the holding transistor T2, the potential of the node N1 rises toward the potential of the node N3, and the gate of the driving transistor T1 The source-to-source voltage Vgs increases from 0V. As a result, a bright spot defect occurs in the light emission operation for black display.

[Dark spot defect in white display]
Referring to FIGS. 6 and 7, an example of a level that is a potential of each terminal during a white display write operation, an example of a level that is a potential of each terminal during a light emission operation of white display, The dark spot defect in the display will be described.

  As shown in FIG. 6, in the writing operation in white display, the selection driver 130 uses the selection signal Vsel set to 15 V, which is an example of the selection level H, as the gate of the holding transistor T2 and the gate of the selection transistor T3. To enter. Then, the selection driver 130 changes the holding transistor T2 to the on state. As a result, the gate of the driving transistor T1 and the drain of the driving transistor T1 become conductive, the driving transistor T1 is diode-connected, and the source of the driving transistor T1 is connected to the data line Ld.

  The power supply driver 150 is an example of the write level Vccw and sets 0V equal to the reference level Vss to the potential of the power supply line Lv. The data driver 140 is an example of the gray level Vdata for white display, -12V, which is a level lower than the level Vss, is set to the potential of the data line Ld. As a result, the source potential of the drive transistor T1 is set to −10V, and the gate potential of the drive transistor T1 is set equal to the potential of the drain of the drive transistor T1. Since the drain-source voltage Vds of the driving transistor T1 is 10 V, a drain-source current Ids corresponding to the drain-source voltage Vds flows. At this time, since the drive transistor T1 is diode-connected, the drain-source voltage Vds of the drive transistor T1 is equal to the gate-source voltage Vgs, and 10V is written to the storage capacitor Cs as the gate-source voltage Vgs. It is.

  At this time, the data driver 140 sets the gradation level Vdata to −12 V so that the potential of the node N2 that is the anode of the EL element OEL is lower than the reference level Vss that is the potential of the cathode of the EL element OEL. It is set to. Then, the data driver 140 sets a reverse bias between both electrodes of the EL element OEL, and suppresses the drain-source current Ids from flowing through the EL element OEL.

  In the holding operation in the white display, the selection driver 130 inputs the selection signal Vsel set to −14V, which is an example of the non-selection level L, to the gate of the holding transistor T2 and the gate of the selection transistor T3. Then, the selection driver 130 causes the holding transistor T2 and the selection transistor T3 to transition to the off state. As a result, the gate of the drive transistor T1 and the drain of the drive transistor T1 become non-conductive, and the diode connection in the drive transistor T1 is released. In addition, the source of the drive transistor T1 and the data line Ld are not conductive.

  As shown in FIG. 7, in the light emission operation in the white display, the selection driver 130 uses the selection signal Vsel set to −14 V, which is an example of the non-selection level L, to the gate of the holding transistor T2 and the selection transistor T3. Keep typing at the gate. Then, the selection driver 130 maintains the holding transistor T2 and the selection transistor T3 in the off state.

  The power supply driver 150 sets 15V, which has a polarity opposite to the non-selection level L and is higher than the reference level Vss, to the potential of the power supply line Lv as an example of the light emission level Vcss. The data driver 140 is an example of the gradation level Vdata, and continues to set −12V, which is lower than the reference level Vss, to the potential of the data line Ld. As a result, the drain-source current corresponding to 10 V which is the gate-source voltage Vgs held in the storage capacitor Cs is set such that the drain potential of the drive transistor T1 is set to a level higher than the source of the drive transistor T1. Ids flows between the drain and source of the drive transistor T1, and the EL element OEL emits light.

  On the other hand, in such white display light emitting operation, a large reverse bias of 31 V corresponding to the difference between the non-selection level L and the level of the node N1 is applied between the gate of the holding transistor T2 and the node N1. Yes. Therefore, if a leakage current caused by the gate-drain voltage Vgd of the holding transistor T2 flows to the holding transistor T2, the potential of the node N1 falls toward the potential of the node N3, and the gate-source of the driving transistor T1 The voltage Vgs falls from the holding voltage. As a result, a dark spot defect occurs in the white display light emitting operation.

[Operation of EL device]
An example of the operation of the EL device will be described with reference to FIG. FIG. 8 is a timing chart showing an example of a driving mode in a plurality of pixels located in a specific row. In FIG. 8, for convenience of describing the operation of the EL device, among a plurality of pixels PIX located in a matrix, i rows and j columns and (i + 1) rows and j columns (i is 1 ≦ 1) included in the same pixel group. 4 is a timing chart when a pixel PIX having a positive integer satisfying i ≦ n and j is a positive integer satisfying 1 ≦ j ≦ m is emitted with luminance gradation based on gradation data.

  As shown in FIG. 8, the driving cycle Tcyc of the pixel PIX for each row includes a writing operation period Twrt in which a writing operation is performed, a holding operation period Thld in which a holding operation is performed, and light emission. The light emission operation period Tem, which is a period during which the operation is performed, is configured.

[Write operation period Twrt]
In the write operation period Twrt, the power supply driver 150 writes to a plurality of power supply lines Lv connected to all the pixels PIX with respect to the pixel group including the pixels PIX in the i rows and j columns and the (i + 1) rows and j columns. Level Vccw is set.

  In the write operation period Twrt, the selection driver 130 inputs the selection signal Vsel set to the selection level H to the selection line Ls in the i-th row. As a result, in the pixel PIX in the i-th row, the holding transistor T2 and the selection transistor T3 are turned on, and the driving transistor T1 is set in a diode connection state. Then, the drain potential of the drive transistor T1 and the gate potential of the drive transistor T1 are set to the write level Vccw, and the source of the drive transistor T1 is electrically connected to the data line Ld. That is, one of the electrodes of the storage capacitor Cs is set to a level corresponding to the write level Vccw, and the other electrode is electrically connected to the data line Ld.

  In the write operation period Twrt, the data driver 140 sets the gradation level Vdata corresponding to the i-th gradation data to each data line Ld. As a result, a voltage corresponding to the difference between the gradation level Vdata and the write level Vccw is written as the gate-source voltage Vgs of the drive transistor T1.

[Holding operation period Thld]
In the write operation period Twrt, the power supply driver 150 writes to a plurality of power supply lines Lv connected to all the pixels PIX with respect to the pixel group including the pixels PIX in the i rows and j columns and the (i + 1) rows and j columns. Continue to set the embedded level Vccw.

  In the holding operation period Thld, the selection driver 130 inputs the selection signal Vsel set to the non-selection level L to the selection line Ls in the i-th row. As a result, in the pixel PIX in the i-th row, the holding transistor T2 and the selection transistor T3 are turned off, and the driving transistor T1 is released from the diode connection state. Then, the setting of the gradation level Vdata for the source of the driving transistor T1 is canceled, and the gate-source voltage Vgs of the driving transistor T1 is held in the holding capacitor Cs.

[Light emitting operation period Tem]
In the light emission operation period Tem, the power supply driver 150 emits light to a plurality of power supply lines Lv connected to all the pixels PIX with respect to a pixel group including the pixels PIX in i rows and j columns and (i + 1) rows and j columns. Set Vcss. At this time, a voltage corresponding to the holding voltage written in the holding capacitor Cs is applied to the anode of the EL element OEL, while the reference level Vss is continuously set to the cathode of the EL element OEL. As a result, in the pixel PIX in which the holding voltage of the holding capacitor Cs exceeds 0 V, the both electrodes of the EL element OEL are set to the forward bias, and the driving current Iel according to the gate-source voltage Vgs of the driving transistor T1, that is, A drive current Iel corresponding to the gradation data flows through the EL element. Such a light emission operation is continuously executed until the start of the next drive cycle Tcyc.

  FIG. 9 is a time chart showing a flow in the upper pixel group and a flow in the lower pixel group of three operations including a writing operation, a holding operation, and a light emitting operation. For convenience of explaining the relationship between the operation of the upper pixel group and the operation of the lower pixel group, the upper pixel group is composed of the pixels PIX from the first row to the sixth row, and the lower pixel group is from the seventh row. An example including pixels PIX up to the 12th row is shown.

  As shown in FIG. 9, the pixels PIX from the first row of pixels PIX to the sixth row sequentially execute the writing operation from the first row of pixels PIX every writing operation period Twrt, and the writing operation is finished. The holding operation is sequentially started from the pixels PIX. When the pixels PIX in the seventh row finish the writing operation, all the pixels PIX in the upper pixel group start the light emitting operation all at once.

  Further, when the pixel PIX in the sixth row finishes the writing operation, the pixel PIX from the pixel PIX in the seventh row sequentially writes from the pixel PIX in the seventh row every writing operation period Twrt. The operation is executed, and the holding operation is sequentially started from the pixel PIX that has completed the writing operation. At this time, the pixels PIX from the 8th row to the 12th row are set according to the setting of the write level Vccw from the time when the pixel PIX of the upper pixel group starts the light emission operation to the time when the write operation starts. Perform a non-light emitting operation. When the pixels PIX in the twelfth row finish the writing operation, all the pixels PIX in the lower pixel group start the light emitting operation all at once.

  Further, when the pixel PIX in the twelfth row finishes the writing operation, the pixels PIX from the pixel PIX in the first row to the sixth row finish the light emitting operation all at once, and the writing is performed again every writing operation period Twrt. Are sequentially executed, and the holding operation is sequentially started from the pixels PIX that have completed the writing operation. At this time, the pixels PIX from the second row to the seventh row set the write level Vccw from the time when the pixel PIX in the lower pixel group starts the light emission operation to the time when the write operation starts. Executes the non-light emission operation.

[Write level Vccw and light emission level Vcss]
The write level Vccw and the light emission level Vcss common to the drain level of the drive transistor T1 and the drain level of the holding transistor T2 will be described with reference to FIGS. First, the write level Vccw during the write operation will be described based on the characteristic line of the diode-connected drive transistor T1 and the load line of the EL element OEL. Next, the writing level Vccw during the holding operation and the light emission level Vcss during the light emitting operation will be described in order based on the characteristic line of the drive transistor T1 from which the diode connection is released.

[Characteristic line when diode is connected]
A characteristic line SPw, which is a solid line shown in FIG. 10, is a curve showing the relationship between the drain-source voltage Vds of the diode-connected driving transistor T1 and the drain-source current Ids of the diode-connected driving transistor T1. The relationship that the drive transistor T1 has in the initial state is shown. A characteristic line SPw2 which is a broken line shown in FIG. 10 is an example of a characteristic line when a change occurs in the characteristics of the drive transistor T1 according to the drive history of the drive transistor T1. A point PMw on the characteristic line SPw indicates an operating point of the drive transistor T1.

The characteristic line SPw has a threshold voltage Vth with respect to the drain-source current Ids. When the drain-source voltage Vds exceeds the threshold voltage Vth, the drain-source current increases as the drain-source voltage Vds increases. Ids increases nonlinearly. The effective voltage Veff is a voltage component that effectively causes the drain-source current Ids to flow in the drain-source voltage Vds. As shown in the following formula (1), the drain-source voltage Vds is represented by the sum of the threshold voltage Vth and the effective voltage Veff. During the write operation, the drive transistor T1 is diode-connected, and the operation point of the drive transistor T1 is a write operation point that is a point on the characteristic line SPw.
Vds = Vth + Veff (1)

  On the other hand, the threshold voltage Vth of the drive transistor T1 usually increases according to the drive history of the drive transistor T1. A characteristic line SPw2 shows an example of a characteristic line when the characteristics of the drive transistor T1 change due to the drive history of the drive transistor T1, and a threshold change amount ΔVth shows a change amount of the threshold voltage Vth due to the drive history. The characteristic line SPw2 has a shape in which the characteristic line SPw in the drive transistor T1 in the initial state is substantially translated by the threshold change amount ΔVth.

  Here, when the gradation level Vdata is the same between the driving transistor T1 having the writing operation point on the characteristic line SPw and the driving transistor T1 having the writing operation point on the characteristic line SPw2, At the write operation point on the characteristic line SPw2, the drain-source current Ids is lower than that at the write operation point on the characteristic line SPw. For example, when the gradation level Vdata at the maximum gradation is the maximum gradation level Vdata (max), the maximum gradation current Ids (max) can be obtained at the writing operation point on the characteristic line SPw. At the write operation point on the characteristic line SPw2, the drain-source current Ids becomes lower than the maximum gradation current Ids (max). Therefore, when fluctuation occurs in the characteristics of the driving transistor T1, the threshold value is higher than the drain-source voltage Vds before fluctuation so that the same drain-source current Ids flows as the drain-source current Ids before fluctuation. A drain-source voltage Vds that is higher by the change amount ΔVth is set by correcting the gradation level Vdata.

[Load line of EL element OEL]
The load line SPe, which is a solid line shown in FIG. 11, is a curve representing the relationship between the drive voltage Vel applied to the EL element OEL and the drive current Iel flowing through the EL element OEL, and the relationship that the EL element OEL has in the initial state. Indicates. A load line SPe2 that is a broken line shown in FIG. 11 is an example of a characteristic line when a change occurs in the characteristic of the EL element OEL in accordance with the driving history of the EL element OEL.

  The load line SPe has a threshold voltage Vthel with respect to the drive current Iel. When the drive voltage Vel exceeds the threshold voltage Vthel, the drive current Iel increases nonlinearly as the drive voltage Vel increases.

  On the other hand, the EL element OEL usually increases in resistance according to the driving history of the EL element OEL. The load line SPe2 indicates an example of a characteristic line when a change occurs in the characteristic of the EL element OEL due to the driving history of the EL element OEL. The increase rate of the drive current Iel with respect to the drive voltage Vel decreases in the load line SPe2 rather than in the load line SPe.

  Here, when the voltage value of the drive voltage Vel is the same between the EL element OEL having the operating point on the load line SPe and the EL element OEL having the operating point on the load line SPe2, the load line At the operating point on SPe2, the drive current Iel is lower than the operating point on the load line SPe. Therefore, when fluctuations occur in the characteristics of the EL element OEL, the drive voltage Vel higher than the drive voltage Vel before the fluctuation is the gradation level so that the same drive current Iel as the drive current Iel before the fluctuation is obtained. It is set by correcting Vdata. The increase ΔVel of the drive voltage Vel is the maximum increase ΔVel (max) at the highest gray level when the drive current Iel is the maximum value Iel (max).

[Write level Vccw during write operation]
In the write operation, the selection driver 130 connects the gate and drain of the drive transistor T1 to set the drive transistor T1 in a diode connection state. Further, the power supply driver 150 sets the drain level of the driving transistor T1 to be more positive than the source level of the driving transistor T1 in order to flow the drain-source current Ids. That is, the power supply driver 150 sets the write level Vccw so as to satisfy the following expression (2) with respect to the gradation level Vdata. Further, the data driver 140 sets the gradation level Vdata at the source of the drive transistor T1 through the conduction of the selection transistor T3.

As a result, a drain-source current Ids corresponding to the drain-source potential difference (Vccw-Vdata) flows between the drain and source of the drive transistor T1. At this time, since the drive transistor T1 is diode-connected, the drain-source voltage Vds of the drive transistor T1 is equal to the gate-source voltage Vgs, and is expressed by the following equation (3). Then, such a gate-source voltage Vgs is written in the storage capacitor Cs.
Vdata <Vccw (2)
Vds = Vgs = Vccw−Vdata (3)

Note that since the source of the drive transistor T1 and the anode of the EL element OEL are both connected to the node N2, the drain-source current Ids during the write operation does not flow to the EL element OEL. Level Vdata is set. That is, the gradation level Vdata is set to be equal to or less than the sum of the reference level Vss, which is the cathode voltage of the EL element OEL, and the threshold voltage Vthel of the EL element OEL so as to satisfy the following expression (4). Further, when the reference level Vss is the ground level (0 V), the gradation level Vdata is set so as to satisfy the following expression (5).
Vdata ≦ Vss + Vthel (4)
Vdata ≦ Vthel (5)

When the above formula (3) is substituted into the above formula (5), the following formula (6) is obtained. When the above formula (1) is substituted into the following formula (6), the following formula (7) is obtained. Further, since the following formula (7) needs to hold even when Veff = 0V, the following formula (8) is obtained by substituting Veff = 0 into the following formula (7).
From the above, the write level Vccw during the write operation is set to a level lower than the reference level Vss so as to satisfy the relationship of the following equation (8).
Vccw−Vgs ≦ Vthel (6)
Vccw ≦ Vthel + Vth + Veff (7)
Vdata <Vccw ≦ Vthel + Vth (8)

[Characteristic line when diode is disconnected]
A characteristic line SPh, which is a solid line shown in FIG. 12, is a curve showing the relationship between the drain-source voltage Vds in the driving transistor T1 and the drain-source current Ids in the driving transistor T1, and the diode connection is released. The characteristic line when the gate-source voltage Vgs is constant in the driving transistor T1 is shown. A characteristic line SPw, which is a broken line in FIG. 12, is the characteristic line SPw described in FIG. 10 and is a characteristic line when the drive transistor T1 is diode-connected. A characteristic line SPo that is a one-dot chain line in FIG. 12 is a curve including an operating point obtained by subtracting the drain-source voltage Vds at each writing operation point on the characteristic line SPw by the threshold voltage Vth.

  As shown in FIG. 12, the operating point PMh is an intersection of the characteristic line SPw of the diode-connected driving transistor T1 and the characteristic line SPh of the driving transistor T1 whose diode connection is released. The operating point Po is an intersection with the characteristic line SPh of the driving transistor T1 from which the diode connection is released, and the drain-source voltage Vds at the operating point Po is the pinch-off voltage Vpo. During the holding operation and the light emitting operation, the driving transistor T1 is disconnected from the diode connection. The operating point of the driving transistor T1 is a holding operating point that is a point on the characteristic line SPh, and a light emitting operating point. It is.

  In the characteristic line SPh, a region where the drain-source voltage Vds is 0 V to the pinch-off voltage Vpo is a linear region, and a region where the drain-source voltage Vds is equal to or higher than the pinch-off voltage Vpo is the drain-source current Ids. It is a saturation region that is almost constant. The drain-source current Ids corresponds to the drive current of the EL element OEL.

  Here, in the holding operation, the selection driver 130 releases the diode connection in the driving transistor T1, and holds the gate-source voltage Vgs of the driving transistor T1 in the writing operation in the holding capacitor Cs. At this time, in controlling the drain-source current Ids by the gate-source voltage Vgs of the driving transistor T1 in the subsequent light emitting operation, the drain-source current Ids is constant with respect to the drain-source voltage Vds. It is required to be. Therefore, during the write operation and the hold operation, the write level Vccw is a voltage that drives the drive transistor T1 in the saturation region of the drain-source current Ids.

  Next, in the light emitting operation, the selection driver 130 continues to release the diode connection in the driving transistor T1. The power supply driver 150 changes the power supply signal Vcc, which is the potential of the drain of the drive transistor T1, from the write level Vccw to the light emission level Vcss in order to flow the drain-source current Ids. As a result, the driving transistor T1 is driven in the saturation region, and a drain-source current Ids corresponding to the gate-source voltage Vgs held in the holding capacitor Cs flows between the drain and source of the driving transistor T1. Then, the drain-source current Ids is supplied to the EL element OEL, so that the EL element OEL emits light with luminance corresponding to the drain-source current Ids.

  As shown in FIG. 13, the characteristic line SPw and the characteristic line SPo are the characteristic lines described in FIG. 10, and the characteristic line SPh is the characteristic line described in FIG. Further, the load line SPe and the load line SPe2 are the load lines described in FIG. 11, and are the voltages between the drain of the drive transistor T1 and the cathode of the EL element OEL, that is, the light emission level Vcss and the reference level Vss. Is a curve corresponding to the drive voltage Vel of the EL element OEL.

  During the holding operation, the operating point of the driving transistor T1 is a holding operating point that is an intersection of the characteristic line SPw of the diode-connected driving transistor T1 and the characteristic line SPh of the driving transistor T1 that has been disconnected from the diode. On the other hand, the operating point of the drive transistor T1 during the light emitting operation changes from the holding operating point to the light emitting operating point PMe that is the intersection of the characteristic line SPh and the load line SPe.

  At the light emission operating point PMe, a voltage corresponding to the difference between the light emission level Vcss and the reference level Vss is applied between the drain of the drive transistor T1 and the cathode of the EL element OEL. The light emission operating point PMe determines a ratio of distributing a voltage corresponding to the difference between the light emission level Vcss and the reference level Vss between the drain and source of the drive transistor T1 and between the anode and cathode of the EL element OEL. That is, the light emission operating point PMe determines the drain-source voltage Vds of the driving transistor T1 and the driving voltage Vel of the EL element OEL.

  As shown in FIG. 14, the load line of the EL element OEL changes in the order of the load line SPe, the load line SPe2, and the load line SPe3 according to the driving history of the EL element OEL. That is, the load line of the EL element OEL changes in a direction in which the increase rate of the drive current Iel decreases with respect to the drive voltage Vel corresponding to the difference between the light emission level Vcss and the reference level Vss. The light emission operation point of the drive transistor T1 also changes on the characteristic line SPh of the drive transistor T1 in the order of the light emission operation point PMe, the light emission operation point PMe2, and the light emission operation point PMe3 according to the drive history of the EL element OEL.

  Here, the light emission operation point PMe and the light emission operation point PMe2 are located in the saturation region on the characteristic line SPh, while the light emission operation point PMe3 is located in the linear region on the characteristic line SPh. If the light emitting operation point is in the saturation region, the drive current Iel of the EL element OEL is substantially equal to the drain-source current Ids of the drive transistor T1 during the write operation. On the other hand, at the light emission operation point PMe3 in the linear region, the drive current Iel of the EL element OEL becomes lower than the drain-source current Ids of the drive transistor T1 during the write operation. Therefore, since the drain-source current Ids of the drive transistor T1 and the drive current Iel are substantially equal during the write operation, the light emission operation point needs to be located in the saturation region on the characteristic line SPh.

  The compensation range Vmarg is a potential difference between the operating point Po corresponding to the pinch-off voltage Vpo and the light emitting operating point PMe on the characteristic line SPh of the driving transistor T1. The compensation range Vmarg is a range in which the drain-source current Ids of the drive transistor T1 during the write operation can be maintained as the drive current Iel with respect to a change in characteristics of the EL element OEL due to the drive history of the EL element OEL. That is, the potential range that the light emission operating point can take on the saturation region is the compensation range Vmarg. The compensation range Vmarg decreases as the drain-source current Ids of the driving transistor T1 increases during the write operation, and increases as the difference between the light emission level Vcss and the reference level Vss increases.

From the above, the light emission level Vcss in the light emission operation is set so that the light emission operation point can be located in the saturation region on the characteristic line SPh and the compensation range Vmarg is sufficient. That is, when the maximum value of the drive voltage Vel applied to the EL element OEL is the maximum drive voltage Vel (max), the light emission level Vcss satisfies the following expression (9), and the reference level Vss is the ground level. When it is (0V), it is set to a level higher than the reference level Vss so as to satisfy the following expression (10).
Vccs−Vss ≧ Vpo + Vmarg + Vel (max) (9)
Vccs ≧ Vpo + Vmarg + Vel (max) (10)

[Difference in channel length / gate electrode length in transistors]
The configuration of the drive transistor T1, the holding transistor T2, and the selection transistor T3 will be described with reference to FIGS. First, the planar structure of the pixel PIX will be described with reference to FIG. Hereinafter, an example of the pixel PIX in the bottom emission type EL device in which the EL element OEL is formed on the surface of the substrate and light emission of the EL element OEL is extracted from the back surface of the substrate will be described.

  As shown in FIG. 15, an EL layer OELL constituting the EL element OEL is located in the center of the pixel PIX, and the EL layer OELL has a substantially rectangular shape in plan view. Around the EL layer OELL, a driving transistor T1, a holding transistor T2, and a selection transistor T3 are located.

  The drive transistor T1 includes a drive gate electrode layer T1g that is a gate of the drive transistor T1, a drive drain electrode layer T1d that is a drain of the drive transistor T1, and a drive source electrode layer T1s that is a source of the drive transistor T1. . The drive gate electrode layer T1g is located adjacent to each of the four sides that are the outer edges of the EL layer, and has a strip shape extending along each side. Each of the drive drain electrode layer T1d and the drive source electrode layer T1s has a strip shape extending along the extending direction of the drive gate electrode layer T1g, and overlaps a part of the drive gate electrode layer T1g in plan view. .

  In the drive transistor T1, the direction in which the drive gate electrode layer T1g extends is the channel width direction, and the direction orthogonal to the channel width direction is the channel length direction. The drive gate electrode layer T1g has a drive gate electrode length L1g in the channel length direction. The length of the drive gate electrode layer T1g in the channel width direction is the drive electrode width W1.

  The holding transistor T2 includes a holding gate electrode layer T2g that is the gate of the holding transistor T2, a holding drain electrode layer T2d that is the drain of the holding transistor T2, and a holding source electrode layer T2s that is the source of the holding transistor T2. . The holding gate electrode layer T2g is located adjacent to the right side of the four sides that are the outer edges of the EL layer OELL, and has a strip shape extending along the right side. Each of the holding drain electrode layer T2d and the holding source electrode layer T2s has a strip shape extending along the extending direction of the holding gate electrode layer T2g, and overlaps a part of the holding gate electrode layer T2g in plan view. .

  In the holding transistor T2, the extending direction of the holding gate electrode layer T2g is the channel width direction, and the direction orthogonal to the channel width direction is the channel length direction. The length of the holding gate electrode layer T2g in the channel length direction is the holding gate electrode length L2g. The length of the holding gate electrode layer T2g in the channel width direction is the holding electrode width W2.

  The selection transistor T3 includes a selection gate electrode layer T3g that is a gate of the selection transistor T3, a selection drain electrode layer T3d that is a drain of the selection transistor T3, and a selection source electrode layer T3s that is a source of the selection transistor T3. . The selection gate electrode layer T3g is located adjacent to the lower side of the four sides that are the outer edges of the EL layer OELL, and has a strip shape extending along the lower side. Each of the selection drain electrode layer T3d and the selection source electrode layer T3s has a strip shape extending along the extending direction of the selection gate electrode layer T3g, and overlaps a part of the selection gate electrode layer T3g in plan view. .

  In the select transistor T3, the direction in which the select gate electrode layer T3g extends is the channel width direction, and the direction orthogonal to the channel width direction is the channel length direction. The length of the select gate electrode layer T3g in the channel length direction is the select gate electrode length. The length of the selection gate electrode layer T3g in the channel width direction is the selection electrode width W3.

  The drive electrode width W1 is larger than the holding electrode width W2 and larger than the selection electrode width W3. Further, the selection electrode width W3 is larger than the holding electrode width W2. Since the driving transistor T1 has the largest driving electrode width W1 among the three transistors T1, T2, and T3, the driving transistor T1 is more suitable than the holding transistor T2 and the selection transistor T3 in passing the driving current Iel to the EL element OEL. ing. Since the selection transistor T3 has a selection electrode width W3 larger than the holding electrode width W2, the selection transistor T3 is more suitable than the holding transistor T2 for suppressing a voltage drop in the writing operation of the gradation level Vdata. The holding transistor T2 having the main function of holding the driving voltage in the driving transistor T1 has the smallest electrode width among the three transistors T1, T2, and T3.

  Since the holding transistor T2 has the smallest electrode width among the three transistors, the holding transistor T2 has a structure suitable for suppressing a decrease in the aperture ratio in the pixel PIX. In addition, since the driving transistor T1 has the largest electrode width among the three transistors and has a smaller gate electrode length than the holding transistor T2, this is also suitable for suppressing a decrease in the aperture ratio in the pixel PIX. Have a structure.

  With reference to FIGS. 16 to 19, the structural relationship between the gate electrode layer in each thin film transistor and an etching stopper layer which is an example of a stopper layer will be described. Since the drive transistor T1 and the select transistor T3 have the same relationship in the structural relationship between the gate electrode layer and the etching stopper layer, the structure of the drive transistor T1 will be mainly described below, and the select transistor T3. I will omit duplicate explanations. In FIGS. 16 and 18, the drain electrode layer and the source electrode layer are indicated by a two-dot chain line for convenience of explaining the structural relationship between the gate electrode layer and the etching stopper layer.

  As shown in FIG. 16, the drive gate electrode layer T1g of the drive transistor T1 has a strip shape extending along one direction in plan view. The portion where the drive gate electrode layer T1g and the drive drain electrode layer T1d overlap in plan view is intermittent along the channel width direction that is the extending direction of the drive gate electrode layer T1g. A portion where the driving gate electrode layer T1g and the driving source electrode layer T1s overlap in a plan view is also continuous along the channel width direction. The drive drain electrode layer T1d and the drive source electrode layer T1s are separated from each other in the channel length direction, and the gap between the drive drain electrode layer T1d and the drive source electrode layer T1s in the channel length direction is along the channel width direction. It is almost constant.

  A driving etching stopper layer T1BL, which is an example of a stopper layer, is positioned on the front side of the drawing with respect to the driving gate electrode layer T1g. Similarly to the drive gate electrode layer T1g, the drive etching stopper layer T1BL has a strip shape extending along the channel width direction in plan view. The drive etching stopper layer T1BL is continuous over substantially the entire drive gate electrode layer T1g in the channel width direction.

  The length of the driving etching stopper layer T1BL in the channel length direction is the driving channel length L1BL, which is shorter than the driving gate electrode length L1g. The difference between the drive gate electrode length L1g and the drive channel length L1BL is the channel length / gate electrode length difference in the drive transistor T1, and the channel length / gate electrode length difference in the drive transistor T1 is along the channel width direction. It is almost constant.

  As shown in FIG. 17, the driving gate electrode layer T <b> 1 g included in the driving transistor T <b> 1 is located on the surface of the substrate 11 in a cross-sectional view orthogonal to the channel width direction. On the upper surface of the driving gate electrode layer T1g, the gate insulating layer 12 covering the entire surface of the substrate 11 together with the driving gate electrode layer T1g is located. In the upper surface of the gate insulating layer 12, the semiconductor layer 13 is located in a region facing the drive gate electrode layer T1g and outside the region.

  Two ohmic contact layers 14 are positioned in a state of being separated from each other on the upper surface of the semiconductor layer 13, the drive drain electrode layer T 1 d is positioned on the upper surface of one ohmic contact layer 14, and the other ohmic contact layer 14 The driving source electrode layer T1s is located on the upper surface. Further, a part of the region facing the drive gate electrode layer T1g on the upper surface of the semiconductor layer 13 is sandwiched between the two ohmic contact layers 14 and sandwiched between the drive drain electrode layer T1d and the drive source electrode layer T1s. The driving etching stopper layer T1BL is located.

  The two ohmic contact layers 14 overlap each other on the upper surface of the drive etching stopper layer T1BL. The drive drain electrode layer T1d and the drive source electrode layer T1s also overlap with the upper surface of the drive etching stopper layer T1BL. Between the portion connected to the semiconductor layer 13 through the ohmic contact layer 14 in the driving drain electrode layer T1d and the portion connected to the semiconductor layer 13 through the ohmic contact layer 14 in the driving source electrode layer T1s. The distance is the length of the drive etching stopper layer T1BL along the channel length direction, that is, the drive channel length L1BL.

  Of the both ends of the drive etching stopper layer T1BL in the channel length direction, the end close to the drive source electrode layer T1s is the first stopper end, and the end close to the drive drain electrode layer T1d is the second stopper end. Of the both ends of the drive gate electrode layer T1g in the channel length direction, the end close to the drive source electrode layer T1s is the first electrode end, and the end close to the drive drain electrode layer T1d is the second electrode end. . In the driving transistor T1, the distance along the channel length direction between the first stopper end and the first electrode end is a source side channel length / gate electrode length difference L1gs. In the driving transistor T1, the distance along the channel length direction between the second stopper end and the second electrode end is a drain side channel length / gate electrode length difference L1gd.

  In the driving transistor T1, the source side channel length / gate electrode length difference L1gs is equal to the drain side channel length / gate electrode length difference L1gs, and the source side channel length / gate electrode length difference L1gs is equal to the drain side channel length / gate electrode length difference L1gs. The sum of the length difference L1gd is the channel length / gate electrode length difference of the drive transistor T1, which is the difference between the drive gate electrode length L1g and the drive channel length L1BL.

  Since the source side channel length / gate electrode length difference L1gs and the drain side channel length / gate electrode length difference L1gd are equal to each other, it is possible to use a self-alignment technique when patterning the drive etching stopper layer T1BL. That is, it is possible to form the drive gate electrode layer T1g before the drive etching stopper layer T1BL, and to expose the resist mask used for patterning the drive etching stopper layer T1BL using the drive gate electrode layer T1g as a mask. is there.

  As shown in FIG. 18, the holding gate electrode layer T2g of the holding transistor T2 has a strip shape extending along one direction in a plan view. The portion where the holding gate electrode layer T2g and the holding drain electrode layer T2d overlap in plan view is continuous along the channel width direction, which is the extending direction of the holding gate electrode layer T2g. A portion where the holding gate electrode layer T2g and the holding source electrode layer T2s overlap in a plan view is also continuous along the channel width direction. The holding drain electrode layer T2d and the holding source electrode layer T2s are separated from each other in the channel length direction, and the gap between the holding drain electrode layer T2d and the holding source electrode layer T2s in the channel length direction is along the channel width direction. It is almost constant.

  A holding etching stopper layer T2BL, which is an example of a stopper layer, is located on the front side of the drawing with respect to the holding gate electrode layer T2g. Similar to the holding gate electrode layer T2g, the holding etching stopper layer T2BL has a strip shape extending along the channel width direction in plan view. The holding etching stopper layer T2BL is located over substantially the entire holding gate electrode layer T2g in the channel width direction.

  The length of the holding etching stopper layer T2BL in the channel length direction is the holding channel length L2BL, which is shorter than the holding gate electrode length L2g. The difference between the holding gate electrode length L2g and the holding channel length L2BL is a channel length / gate electrode length difference in the holding transistor T2. The channel length / gate electrode length difference in the holding transistor T2 is substantially constant along the channel width direction, and is based on the channel length / gate electrode length difference in the drive transistor T1 and the channel length / gate electrode length difference in the selection transistor T3. Is also big.

  As shown in FIG. 19, the holding gate electrode layer T <b> 2 g included in the holding transistor T <b> 2 is located on the surface of the substrate 11 in a cross-sectional view facing the channel width direction. Similar to the drive transistor T1, the gate insulating layer 12 is located on the upper surface of the holding gate electrode layer T2g. Further, in the upper surface of the gate insulating layer 12, the semiconductor layer 13 is located in the region facing the holding gate electrode layer T2g and on the outside of the region, similarly to the driving transistor T1.

  On the upper surface of the semiconductor layer 13, the two ohmic contact layers 14 are located in a state of being separated from each other, the holding drain electrode layer T 2 d is located on the upper surface of one of the ohmic contact layers 14, and the other ohmic contact layer 14 The holding source electrode layer T2s is located on the upper surface. Further, a part of the region facing the holding gate electrode layer T2g on the upper surface of the semiconductor layer 13 is sandwiched between the two ohmic contact layers 14 and sandwiched between the holding drain electrode layer T2d and the holding source electrode layer T2s. The holding etching stopper layer T2BL is located.

  The two ohmic contact layers 14 overlap each other on the upper surface of the drive etching stopper layer T1BL. In addition, the holding drain electrode layer T2d and the holding source electrode layer T2s overlap with the upper surface of the holding etching stopper layer T2BL. The distance between the portion connected to the semiconductor layer 13 through the ohmic contact layer 14 in the holding drain electrode layer T2d and the portion connected to the semiconductor layer 13 in the holding source electrode layer T2s is the holding channel length L2BL. And it is larger than the drive channel length L1BL.

  Since the holding channel length L2BL is larger than the driving channel length L1BL and the channel length / gate electrode length difference of the holding transistor T2 is larger than the channel length / gate electrode length difference of the driving transistor T1, the holding transistor T2 Is reduced more than the driving transistor T1. Similarly, since the selection transistor T3 and the driving transistor T1 are common in the structural relationship between the gate electrode layer and the etching stopper layer, the off-state current of the holding transistor T2 is suppressed more than that of the selection transistor T3. Therefore, as compared with an EL device including a holding transistor T2 having the same configuration as the drive transistor T1 and the selection transistor T3, a bright spot defect in the EL element OEL in black display and a dark spot defect in the white display in the EL element OEL Control defects such as are suppressed.

  Of the both ends of the holding etching stopper layer T2BL in the channel length direction, the end close to the holding source electrode layer T2s is the first stopper end, and the end close to the holding drain electrode layer T2d is the second stopper end. Of the both ends of the holding gate electrode layer T2g in the channel length direction, the end close to the holding source electrode layer T2s is the first electrode end, and the end close to the holding drain electrode layer T2d is the second electrode end. . In the holding transistor T2, the distance along the channel length direction between the first stopper end and the first electrode end is a source side channel length / gate electrode length difference L2gs. In the holding transistor T2, the distance along the channel length direction between the second stopper end and the second electrode end is a drain side channel length / gate electrode length difference L2gd.

  In the holding transistor T2, the source side channel length / gate electrode length difference L2gs may be equal to the drain side channel length / gate electrode length difference L2gd or may be larger than the drain side channel length / gate electrode length difference L2gd. However, it may be smaller than the drain side channel length / gate electrode length difference L2gd. The sum of the source side channel length / gate electrode length difference L2gs and the drain side channel length / gate electrode length difference L2gd is the difference between the holding gate electrode length L2g and the holding channel length L2BL. The gate electrode length difference is larger than the channel length / gate electrode length difference of the driving transistor T1 and the channel length / gate electrode length difference of the selection transistor T3.

[Method for Manufacturing EL Device]
The manufacturing method of an EL device includes an EL panel forming process and an assembling process, and the EL panel forming process includes a transistor array forming process, an EL layer forming process, and a sealing process. In the EL panel formation step, the EL panel 160 is formed by forming pixels PIX, selection lines Ls, data lines Ld, power supply lines Lv, various pads, and the like on a substrate. In the assembly process, various drive circuits for driving the EL panel 160 such as the selection driver 130, the data driver 140, and the power supply driver 150 are connected to the EL panel 160 to assemble the EL device 100. In the configuration in which various drive circuits such as the selection driver 130, the data driver 140, and the power supply driver 150 are incorporated in the EL panel 160, various drive circuits are formed in the formation process of the EL panel 160, and the assembly process is omitted. Is done.

  In the EL panel forming step, the transistor array forming step forms the driving transistor T1, the holding transistor T2, the selection transistor T3, and the holding capacitor Cs on the substrate together with the selection line Ls, the data line Ld, the power supply line Lv, and the like. In the EL layer forming step, an EL layer OELL and an electrode layer constituting the EL element OEL are formed on the substrate on which the transistor array is formed. In the sealing step, a sealing layer for protecting the EL layer OELL is formed on the substrate on which the EL element OEL is formed.

  The transistor array formation step will be described with reference to FIGS. 20 (a) and 20 (b) and FIGS. 21 (a) and 21 (b). In the transistor array formation step, the functional layer of the drive transistor T1 is the same by patterning one functional film formed on the substrate together with the functional layer of the holding transistor T2 and the functional layer of the selection transistor T3. Formed with timing. The patterning method of the etching stopper layer is different between the driving transistor T1 and the holding transistor T2, while the patterning of the etching stopper layer is equal between the driving transistor T1 and the selection transistor T3. Therefore, in the following, a method for forming the drive transistor T1 will be mainly described, and an overlapping description in the selection transistor T3 will be omitted.

  In the transistor array formation step, a gate metal film is formed on the surface of the substrate 11, and the holding gate electrode layer T2g is formed by patterning the gate metal film. When the holding gate electrode layer T2g is formed, the gate insulating layer 12, the semiconductor layer 13, and the etching stopper film BL are stacked on the substrate 11 so that the holding gate electrode layer T2g is covered with the gate insulating layer 12. At this time, the formation of the holding transistor T2, the formation of the driving transistor T1, and the formation of the selection transistor T3 are also advanced. That is, the gate metal film formed on the surface of the substrate 11 is patterned so that the drive gate electrode layer T1g is formed together with the holding gate electrode layer T2g, and the drive gate electrode layer T1g is covered with the gate insulating layer 12. The insulating layer 12, the semiconductor layer 13, and the etching stopper film BL are stacked on the substrate 11. The same applies to the portion where the selection transistor T3 is formed.

  Next, a resist coating film RL is laminated so as to cover the entire etching stopper film BL. Subsequently, as shown in FIG. 20, surface exposure using a photomask MK is performed, and subsequently, back surface exposure is performed as shown in FIG.

  FIG. 20 is an example of surface exposure at a portion where the holding transistor T2 is formed. When the resist coating film RL is formed, a photomask MK having a closed portion Mka that covers a part of the holding gate electrode layer T2g. And exposure light is irradiated from the surface side of the substrate 11. As a result, in the resist coating film RL, the exposure light is irradiated from the surface side of the substrate 11 other than the portion sandwiched between the solid arrows in FIG. 20A, and the resist coating film RL is exposed. In addition, although back surface exposure is performed subsequently, the site | part which can be exposed by this back surface exposure is a site | part which is not exposed by surface exposure, Comprising: The inside of holding gate electrode layer T2g. Therefore, a new exposure portion does not occur in the backside exposure at the portion where the holding transistor T2 is formed.

  As a result, as shown in FIG. 20B, the resist coating film RL is developed and the patterned resist coating film RL is cured, so that the region on the holding gate electrode layer T2g is opposed to the closed portion Mka. A covering resist mask RM2 is formed.

  At this time, since the resist coating film RL is exposed using a photomask MK that is a member different from the substrate 11, the closing portion Mka of the photomask MK is based on the alignment accuracy between the substrate 11 and the photomask MK. Has a length sufficiently smaller than the holding gate electrode length L2g in the channel length direction. The closed portion Mka of the photomask MK has a width sufficiently smaller than the holding electrode width W2 also in the channel width direction. In the back exposure performed following the front exposure, the back surface exposure light is not irradiated to the portion facing the closed portion Mka in the semiconductor layer 13 facing the holding gate electrode layer T2g. Damage to the can be suppressed.

  FIG. 21 is an example of backside exposure at a portion where the driving transistor T1 and the selection transistor T3 are formed. In the front surface exposure performed before the back surface exposure, the closed portion of the photomask MK is longer than each gate electrode length in the channel length direction at the portion where the drive transistor T1 and the selection transistor T3 are formed. Largely formed. Therefore, in the subsequent backside exposure, the resist coating film RL is newly exposed using the drive gate electrode layer T1g as a mask. Similarly, the resist film is newly exposed using the gate electrode layer as a mask also at the portion where the selection transistor T3 is formed. At this time, the resist coating film RL is irradiated with exposure light other than the portion sandwiched between the solid line arrows in FIG. 21A, but some exposure light wraps inward from the end of the gate electrode layer. As a result, the newly exposed portion of the resist coating film RL actually recedes to the two-dot chain line located inside the solid line arrow.

  Then, a resist mask RM1 that covers a region facing the drive gate electrode layer T1g is formed by developing the resist coating film RL and curing the patterned resist coating film RL. As a result, the resist mask RM1 has a length slightly smaller than the drive gate electrode length L1g in the channel length direction.

  As shown in FIG. 21B, when the resist mask RM1 is formed, etching using the resist mask RM1 as a mask is performed on the etching stopper film BL to form the driving etching stopper layer T1BL. Thus, a driving etching stopper layer T1BL having a source side channel length / gate electrode length difference L1gs and a drain side channel length / gate electrode length difference L1gd in the channel length direction is formed with respect to the driving gate electrode layer T1g.

  Then, after the resist masks RM1 and RM2 are removed, an ohmic contact layer thin film and a terminal metal film are formed. By patterning the ohmic contact layer thin film and the terminal metal film, the ohmic contact layer 14 and the drive drain electrode are formed. A layer T1d and a drive source electrode layer T1s are formed. At this time, since the driving etching stopper layer T1BL is located between the driving drain electrode layer T1d and the driving source electrode layer T1s, the patterning of the driving drain electrode layer T1d and the driving source electrode layer T1s is performed. At this time, in the portion functioning as a channel in the semiconductor layer 13, damage due to etching is suppressed. The holding drain electrode layer T2d and the holding source electrode layer T2s are formed in the same manner, and the drain electrode layer of the selection transistor T3 and the source electrode layer of the selection transistor T3 are formed in the same manner.

[Off-state current of holding transistor T2]
With reference to FIGS. 22 and 23, the relationship between the on-current and the gate-source voltage Vgs and the relationship between the off-current and the gate-source voltage Vgs will be described. FIG. 22 is a graph showing the relationship between the gate-source voltage Vgs and the drain current Id flowing between the source and drain, and shows the relationship when the drain-source voltage Vds is set to 15V. . FIG. 23 is a graph showing an estimate of the off-state current of the holding transistor T2 in the light emission operation, and when the light emission level Vcss (= 15 V) is set in the relationship between the gate-source voltage Vgs and the drain current Id. It is the graph which added the gate-drain voltage Vgd in the holding transistor T2.

  As shown in FIG. 22, the drain current Id flowing between the gate and the source is a value determined by the gate-source voltage Vgs, and the gate-source voltage Vgs is from 0 V to 10 V, which is an example of the first level. When increasing, the drain current Id increases rapidly as an on-current. Such rising of the on-current tends to be observed in any of the driving transistor T1, the holding transistor T2, and the selection transistor T3, and whether the etching stopper layer exposure is front surface exposure or back surface exposure. Almost no dependence.

  On the other hand, when the gate-source voltage Vgs is between 0 V and −10 V, the drain current Id does not flow, and the thin film transistor maintains the off state. When the gate-source voltage Vgs decreases from −10 V, which is an example of the second level, to −30 V, the drain current Id gradually increases as an off current. Such a rise in off-current tends to be observed in any of the driving transistor T1, the holding transistor T2, and the selection transistor T3.

  The off current of the drive transistor T1 and the selection transistor T3 is a curve LCB indicated by a solid line in FIG. 22, and the off current of the holding transistor T2 is a curve LCF indicated by a broken line in FIG. In a thin film transistor whose channel length is determined by backside exposure, such as the driving transistor T1 and the selection transistor T3, when the gate-source voltage Vgs decreases from −10 V, the off-current starts to flow. On the other hand, in a thin film transistor whose channel length is determined by surface exposure like the holding transistor T2, when the gate-source voltage Vgs decreases from −18V, the off-current starts to flow. The off-state current of the holding transistor T2 is smaller than the off-state currents of the driving transistor T1 and the selection transistor T3 in the range from −10V to −30V.

  The off-current that flows in the n-channel thin film transistor includes a current in which holes generated due to defects included in the channel are carriers. Therefore, as indicated by an arrow ER in FIG. 22, the driving transistor T1 and the selection transistor T3, whose channel length is determined by the back surface exposure, have a larger variation than the holding transistor T2 formed by the front surface exposure.

  As shown in FIG. 23, in the light emission operation, when the light emission level Vcss of 15V is set in the power supply signal Vcc and the voltage of −14V is applied to the gate as the non-selection level L, the description has been given with reference to FIG. Thus, the gate-drain voltage of the holding transistor T2 is −29 V in black display. At this time, if the holding transistor T2 is formed by backside exposure, an off-current flows through the holding transistor T2, as indicated by a curve LCB in FIG.

  In this respect, since the holding transistor T2 described above is a thin film transistor whose channel length is determined by surface exposure, no off-current flows through the holding transistor T2, as indicated by the curve LCF in FIG. Therefore, the occurrence of bright spot defects in black display can be suppressed. Further, as described with reference to FIG. 7, the voltage between the gate and the drain of the holding transistor T2 is −31 V in white display. Also in this case, as indicated by the curve LCF in FIG. 23, no off-current flows through the holding transistor T2. Therefore, the occurrence of dark spot defects in white display can be suppressed.

According to the first embodiment, the effects listed below can be obtained.
(1) Since the off-state current of the holding transistor T2 can be suppressed, the occurrence of control defects in the EL device 100 can be suppressed.
(2) The holding channel length L2BL, which is a configuration for suppressing the off current, is determined by one holding etching stopper layer T2BL. Similarly, the holding gate electrode length L2g which is a configuration for suppressing the off-current is determined by one holding gate electrode layer T2g. Therefore, since the channel length in the holding transistor T2 and the channel length / gate electrode length difference in the holding transistor T2 are set by one layer structure for each, the setting is easy.

  (3) Since the holding transistor T2 has the largest gate electrode length among the three transistors and the smallest electrode width, the bottom-emission type EL can be obtained while the effect described in (1) can be obtained. If it is an apparatus, the fall of the aperture ratio in the pixel PIX can also be suppressed.

  (4) Since the driving transistor T1 has the largest electrode width among the three transistors and has a smaller gate electrode length than the holding transistor T2, this is also a pixel if it is a bottom emission type EL device. A decrease in the aperture ratio in PIX is suppressed.

  (5) In the driving transistor T1, since the source side channel length / gate electrode length difference L1gs and the drain side channel length / gate electrode length difference L1gd are equal to each other, a self-alignment technique is used for patterning the driving etching stopper layer T1BL. It is possible.

(6) Since the resist mask RM1 for patterning the driving etching stopper layer T1BL is formed by backside exposure using the driving gate electrode layer T1g as an exposure mask, the positions of the driving gate electrode layer T1g and the driving etching stopper layer T1BL Is easy to match.
(7) Since the non-selection level is located between the first level and the second level, it is possible to suppress the off current of the holding transistor from flowing in the light emitting operation.

[Second Embodiment]
With reference to FIGS. 24 to 28, an EL device according to a second embodiment that embodies the technique of the present disclosure will be described. The EL device according to the second embodiment is different from the EL device according to the above embodiment in the configuration of the selection line connected to one pixel PIX, the configuration of the selection driver for driving the selection line, and the signal level in the selection signal. On the other hand, the other configuration is the same as that of the EL device of the above embodiment. Therefore, in the following, differences between the EL device in the second embodiment and the EL device in the above embodiment will be mainly described, and the same components as those in the above embodiment are denoted by the same reference numerals. The detailed explanation is omitted. FIG. 24 is a diagram corresponding to FIG. 2 referred to in the description of the configuration of the pixel circuit in the above embodiment, and each of FIGS. 25 to 28 is from FIG. 4 referred to in the description of the operation of the pixel in the above embodiment. It is a figure corresponding to each of FIG.
As shown in FIG. 24, the EL device includes two selection drivers including a first selection driver 130A and a second selection driver 130B.

  For example, the first selection driver 130A includes a shift register that sequentially outputs a shift signal corresponding to each of the plurality of first selection lines Ls1 for each row based on a selection control signal SCON1 output from the system controller 120. ing. In addition, the first selection driver 130A uses, for example, the first selection signal Vsel1 obtained by converting the shift signal to the first selection level H1 based on the selection control signal SCON1 output from the system controller 120, in the row corresponding to the shift signal. An output buffer for outputting to the first selection line Ls1.

  For example, the second selection driver 130B includes a shift register that sequentially outputs a shift signal corresponding to each of the plurality of second selection lines Ls2 for each row based on a selection control signal SCON1 output from the system controller 120. ing. In addition, the second selection driver 130B performs, for example, a row corresponding to the shift signal by using the second selection signal Vsel2 obtained by converting the shift signal to the second selection level H2 based on the selection control signal SCON1 output from the system controller 120. An output buffer for outputting to the second selection line Ls2.

  The first selection driver 130A sequentially outputs the selection signal Vsel set to the first selection level H1 to each of the plurality of first selection lines Ls1 based on the selection control signal SCON1 output from the system controller 120. Each of the plurality of pixels PIX is set to a selected state for each row. For example, the first selection driver 130A outputs the selection signal Vsel set to the first selection level H1 to the first selection line Ls1 in the specific row in the writing operation of the pixel PIX located in the specific row. Then, the first selection driver 130A sequentially outputs the selection signal Vsel set to the first selection level H1 to each row, and sets each of the plurality of pixels PIX to the selected state sequentially for each row.

  The second selection driver 130B sequentially outputs the selection signal Vsel set to the second selection level H2 to each of the plurality of second selection lines Ls2 based on the selection control signal SCON1 output from the system controller 120. Each of the plurality of pixels PIX is set to a selected state for each row. For example, the second selection driver 130B outputs the selection signal Vsel set to the second selection level H2 to the second selection line Ls2 in the specific row in the writing operation of the pixel PIX located in the specific row. Then, the second selection driver 130B sequentially outputs the selection signal Vsel set to the second selection level H2 to each row, and sequentially sets each of the plurality of pixels PIX to the selected state for each row.

  The holding transistor T2 is an n-channel transistor, and the gate of the holding transistor T2 is electrically connected to the first selection line Ls1 through the node N4. The selection transistor T3 is an n-channel transistor, and the gate of the selection transistor T3 is electrically connected to the second selection line Ls2.

[Gate-drain voltage Vgd in black display]
With reference to FIG. 25 and FIG. 26, an example of a level that is the potential of each terminal during a black display write operation and an example of a level that is the potential of each terminal during a black display light emission operation will be described. To do.

  As shown in FIG. 25, in the writing operation in black display, the first selection driver 130A inputs the first selection signal Vsel1 set to 15V, which is an example of the first selection level H1, to the gate of the holding transistor T2. Then, the holding transistor T2 is changed to the ON state. The second selection driver 130B inputs the second selection signal Vsel2 set to 15V, which is an example of the second selection level H2, to the gate of the selection transistor T3, and causes the selection transistor T3 to transition to the on state. As a result, the gate of the driving transistor T1 and the drain of the driving transistor T1 become conductive, and the driving transistor T1 is diode-connected.

  On the other hand, the power supply driver 150 sets 0 V equal to the reference level Vss to the potential of the power supply line Lv as an example of the write level Vccw, as in the above embodiment. The data driver 140 is an example of the gradation level Vdata for black display, and sets 0 V equal to the reference level Vss to the potential of the data line Ld. As a result, the source potential of the drive transistor T1 is set to 0V, and the gate potential of the drive transistor T1 is set equal to the potential of the drain of the drive transistor T1. Then, 0V is written in the storage capacitor Cs as the gate-source voltage Vgs.

  In the holding operation in the black display, the first selection driver 130A is a first selection signal that is higher than the non-selection level L of the above embodiment and is set to −2V, which is an example of the first non-selection level L1. Vsel1 is input to the gate of the holding transistor T2. As a result, the holding transistor T2 transitions to an off state, the gate of the driving transistor T1 and the drain of the driving transistor T1 are rendered non-conductive, and the diode connection in the driving transistor T1 is released.

  The second selection driver 130B receives the second selection signal Vsel2 that is the same level as the non-selection level L of the above embodiment and is set to −14V, which is an example of the second non-selection level L2, as the selection transistor T3. Enter the gate. As a result, the select transistor T3 transitions to the off state, and the source of the drive transistor T1 and the data line Ld become non-conductive.

  As shown in FIG. 26, in the light emission operation in the black display, the first selection driver 130A applies the first selection signal Vsel1 set to −14V, which is an example of the first non-selection level L1, to the gate of the holding transistor T2. Continue typing. Thus, the first selection driver 130A maintains the holding transistor T2 in the off state.

  On the other hand, the second selection driver 130B receives the second selection signal Vsel2 which is the same level as the non-selection level L of the above embodiment and is set to −14V which is an example of the second non-selection level L2. Input continues to the gate of the select transistor T3. Accordingly, the second selection driver 130B maintains the selection transistor T3 in the off state.

  On the other hand, the power supply driver 150 sets 15V, which is a level higher than the reference level Vss, to the potential of the power supply line Lv as an example of the light emission level Vcss. The data driver 140 continues to set 0V equal to the reference level Vss as the gradation level Vdata to the data line Ld. As a result, the drain-source current Ids does not flow between the drain and source of the drive transistor T1, and the EL element OEL does not emit light.

  At this time, the first non-selection level L1 which is higher than the second non-selection level L2 is set as the gate potential of the holding transistor T2. As a result, a voltage of −17 V corresponding to the difference between the first non-selection level L1 and the light emission level Vcss is applied between the gate of the holding transistor T2 and the node N3, and this voltage is the second non-selection level. It is smaller than the difference between L2 and the light emission level Vcss. Therefore, as described with reference to FIG. 5, the gate and node of the holding transistor T2 are compared with the configuration in which the gate of the holding transistor T2 and the gate of the selection transistor T3 are selected by one selection line Ls. It is possible to suppress the voltage between N3. Further, the leakage current caused by the gate-drain voltage Vgd of the holding transistor T2 flows to the holding transistor T2, and further, the occurrence of a bright spot defect in the black light emitting operation is further suppressed.

[Gate-drain voltage Vgd in white display]
Referring to FIGS. 27 and 28, an example of a level that is a potential of each terminal during a white display writing operation and an example of a level that is a potential of each terminal during a white display light emitting operation will be described. To do.

  As shown in FIG. 27, in the writing operation in the white display, the first selection driver 130A inputs the first selection signal Vsel1 set to 15V, which is an example of the first selection level H1, to the gate of the holding transistor T2. Then, the holding transistor T2 is changed to the ON state. The second selection driver 130B inputs the second selection signal Vsel2 set to 15V, which is an example of the second selection level H2, to the gate of the selection transistor T3, and causes the selection transistor T3 to transition to the on state. As a result, the gate of the driving transistor T1 and the drain of the driving transistor T1 become conductive, and the driving transistor T1 is diode-connected.

  On the other hand, the power supply driver 150 sets 0 V equal to the reference level Vss to the potential of the power supply line Lv as an example of the write level Vccw, as in the above embodiment. The data driver 140 is an example of a gray level Vdata for white display, and sets −12V, which is a level lower than the reference level Vss, to the potential of the data line Ld. As a result, the source potential of the drive transistor T1 is set to −10V, and the gate potential of the drive transistor T1 is set equal to the potential of the drain of the drive transistor T1. Then, a voltage of 10 V is written in the storage capacitor Cs as the gate-source voltage Vgs.

  In the holding operation in white display, the first selection driver 130A has a first selection signal that is higher than the non-selection level L of the above embodiment and is set to −2V, which is an example of the first non-selection level L1. Vsel1 is input to the gate of the holding transistor T2. As a result, the holding transistor T2 transitions to an off state, the gate of the driving transistor T1 and the drain of the driving transistor T1 are rendered non-conductive, and the diode connection in the driving transistor T1 is released.

  The second selection driver 130B receives the second selection signal Vsel2 that is the same level as the non-selection level L of the above embodiment and is set to −14V, which is an example of the second non-selection level L2, as the selection transistor T3. Enter the gate. As a result, the selection transistor T3 is turned off, and the source of the driving transistor T1 and the data line Ld become non-conductive.

  As shown in FIG. 28, in the light emission operation in the white display, the first selection driver 130A is at a level higher than the non-selection level L of the above embodiment, and is −2V, which is an example of the first non-selection level L1. The set first selection signal Vsel1 is continuously input to the gate of the holding transistor T2. Thus, the first selection driver 130A maintains the holding transistor T2 in the off state.

  On the other hand, the second selection driver 130B receives the second selection signal Vsel2 which is the same level as the non-selection level L of the above embodiment and is set to −14V which is an example of the second non-selection level L2. Input continues to the gate of the select transistor T3. Accordingly, the second selection driver 130B maintains the selection transistor T3 in the off state.

  On the other hand, the power supply driver 150 sets 15V, which is a level higher than the reference level Vss, to the potential of the power supply line Lv as an example of the light emission level Vcss. The data driver 140 is an example of the gray level Vdata for white display, and sets −12V, which is a level lower than the reference level Vss, to the potential of the data line Ld. As a result, the drain potential of the drive transistor T1 is set to a level higher than that of the source of the drive transistor T1, and the drain-source current Ids corresponding to 10 V which is the gate-source voltage Vgs held in the holding capacitor Cs. However, it flows between the drain and source of the driving transistor T1, and the EL element OEL emits light.

At this time, a voltage of −19 V corresponding to the difference between the first non-selection level L1 and the level of the node N1 is applied between the gate of the holding transistor T2 and the node N1, and this voltage is It is smaller than the difference between the selection level L2 and the level of the node N1. As a result, as described with reference to FIG. 7, the gate and node of the holding transistor T2 are compared with the configuration in which the gate of the holding transistor T2 and the gate of the selection transistor T3 are selected by one selection line Ls. It is possible to suppress the voltage between N1. Further, the leakage current caused by the gate-drain voltage Vgd of the holding transistor T2 flows to the holding transistor T2, and further, the occurrence of a dark spot defect in the white display light emitting operation is further suppressed.
According to the second embodiment, in addition to the effects according to the above (1) to (7), the effects listed below can be obtained.

  (8) The first non-selection level L1 input to the holding transistor T2 and the second non-selection level L2 input to the selection transistor T3 can be set to different levels. As a result, it is possible to set the first non-selection level L1 input to the holding transistor T2 to a level specialized for suppressing the off-current in the holding transistor T2.

(9) The configuration in which the channel length / gate electrode length difference of the holding transistor T2 is larger than that of the driving transistor T1 and the selection transistor T3 also exhibits an effect of suppressing variation in off-current in the holding transistor T2. Setting the first non-selection level L1 to a level specialized for suppressing the off-current not only suppresses the flow of the off-current but also increases the certainty in the configuration in which the variation in the off-current is small. Also raise it.
The embodiment described above can be implemented with the following modifications.

[Stopper layer]
A configuration in which the channel length of the holding transistor T2 is larger than the channel length of the driving transistor T1, and the channel length / gate electrode length difference of the holding transistor T2 is larger than the channel length / gate electrode length difference of the driving transistor T1. For example, at least one of the driving etching stopper layer T1BL and the holding etching stopper layer T2BL may be omitted.

  Even when the driving etching stopper layer T1BL is omitted, the desired source side channel length / gate electrode length difference L1gs and the drain side channel length / gate electrode length difference L1gd can be obtained by etching the terminal metal film. Is possible. Even if the holding etching stopper layer T2BL is omitted, the desired source side channel length / gate electrode length difference L1gs and the drain side channel length / gate electrode length difference L1gd can be obtained by etching the terminal metal film. It is possible to get. If the thin film transistor has an etching stopper layer, damage to the channel can be suppressed during etching of the terminal metal film, and the channel length, which is the distance between the two electrode layers, is determined in advance by one etching stopper layer. It is possible.

  In the driving transistor T1, the source side channel length / gate electrode length difference L1gs and the drain side channel length / gate electrode length difference L1gd may be different from each other. At this time, the channel length of the holding transistor T2 is larger than the channel length of the driving transistor T1, and the channel length / gate electrode length difference of the holding transistor T2 is larger than the channel length / gate electrode length difference of the driving transistor T1. Any configuration may be used. If the exposure light irradiation amount and irradiation angle from the back side of the substrate 11 are different from each other between the source side of the drive gate electrode layer T1g and the drain side of the drive gate electrode layer T1g, the substrate The above-described dimensions can be set even when exposure is performed from the back surface side. That is, the source side channel length / gate electrode length difference L1gs and the drain side channel length / gate electrode length difference L1gd can be set to different sizes.

[Exposure method]
At least one of the resist mask for forming the etching stopper layer of the selection transistor T3 and the resist mask RM1 for forming the driving etching stopper layer T1BL may be formed by exposure from the surface side of the substrate 11. Good. At this time, it is preferable that the resist mask for forming the holding etching stopper layer T2BL is formed at the same time as the resist mask for forming the other etching stopper layer in order to reduce the number of manufacturing steps.

  Even exposure from the surface side of the substrate 11 has a length slightly smaller than the drive gate electrode length L1g in the channel length direction and a width slightly smaller than the drive electrode width W1 in the channel width direction. It is possible to form a resist mask having the same. Therefore, effects according to the above (1) to (5) and the above (7) to (9) can be obtained. If exposure is performed from the back side of the substrate 11, alignment between the position of the drive gate electrode layer T1g and the position of the resist mask RM1 is easier than exposure from the front side of the substrate 11. High accuracy is also obtained.

[Pixel circuit]
The driving transistor T1, the holding transistor T2, and the selection transistor T3 may be p-channel thin film transistors. At this time, the source of the driving transistor T1 is electrically connected to the power supply line Lv, and the drain of the driving transistor T1 is electrically connected to the node N2. The source of the holding transistor T2 is electrically connected to the source of the driving transistor T1, and the drain of the holding transistor T2 is electrically connected to the gate of the driving transistor T1. The drain of the selection transistor T3 is electrically connected to the data line Ld, and the source of the selection transistor T3 is electrically connected to the drain of the driving transistor T1.

  The pixel circuit included in the pixel PIX is not limited to the 3Tr1C type described above, and the connection form between the plurality of thin film transistors may be another connection form. For example, a plurality of pixels PIX are arranged in a one-dimensional direction, and one pixel circuit may be a 2Tr1C type including a driving transistor that is two thin film transistors, a holding transistor, and one capacitor element. Good. In other words, the selection transistor T3 may be omitted in the pixel circuit. The pixel circuit included in the pixel PIX may include a driving transistor and a holding transistor, and may have four or more thin film transistors.

  Each functional layer such as a gate electrode layer, a gate insulating layer, a semiconductor layer, a source electrode layer, and a drain electrode layer has a different hierarchy between the driving transistor T1 and the holding transistor T2, and is formed separately. May be.

  In short, the EL device includes a holding transistor that connects a holding capacitor and a power supply line to hold the voltage in the holding capacitor, and a drive transistor that passes a current corresponding to the voltage held in the holding capacitor to the EL element. The channel length / gate electrode length difference of the holding transistor may be larger than the channel length / gate electrode length difference of the driving transistor.

[EL device]
-The EL layer OELL may be composed of, for example, only a light emitting layer that serves both hole transport and electron transport, or may have a laminated structure composed of a hole transporting light emitting layer and an electron transport layer, A laminated structure in which a charge transport layer is sandwiched between these layers may be employed.

The EL element OEL whose emission is controlled by the pixel circuit DC may be, for example, an organic EL element, an inorganic EL element, a light emitting diode, or a drive type light emitting element If it is.
The EL device can be used in a display unit of various electronic devices such as a digital camera, a mobile personal computer, and a portable device.

  In the EL device, the pixel arrangement direction is not limited to the two-dimensional direction, and may be a one-dimensional direction. For example, the EL device is an exposure device that is mounted on a photosensitive drum as a light emitting element array substrate in which a plurality of pixels PIX are arranged in a one-dimensional direction, and irradiates the photosensitive drum with light emitted from the light emitting element array substrate. Can also be used.

  H: Selection level, L: Non-selection level, BL: Etching stopper film, Cs: Retention capacitance, D1: Gradation data, DC: Pixel circuit, H1: First selection level, H2: Second selection level, Id: Drain Current, L1g: Drive gate electrode length, L2g: Holding gate electrode length, Ld ... Data line, Ls ... Selection line, Lv ... Power supply line, MK ... Photomask, N1, N2, N3, N4 ... Node, Po ... Operating point RL ... resist coating film, T1 ... drive transistor, T2 ... hold transistor, T3 ... select transistor, W1 ... drive electrode width, W2 ... hold electrode width, W3 ... select electrode width, Iel ... drive current, LCB, LCF ... curve , Ls1 ... first selection line, Ls2 ... second selection line, Mka ... closed portion, OEL ... EL element, PIX ... pixel, PMe ... light emission operating point, PMh ... operating point, RM1, RM2 ... Dist mask, SIG ... Video signal, SPe ... Load line, SPh, SPo, SPw ... Characteristic line, T1d ... Drive drain electrode layer, T1g ... Drive gate electrode layer, T1s ... Drive source electrode layer, T2d ... Holding drain electrode layer, T2g ... holding gate electrode layer, T2s ... holding source electrode layer, T3d ... selected drain electrode layer, T3g ... selected gate electrode layer, T3s ... selected source electrode layer, Tem ... light emission operation period, Vcc ... power supply signal, Vel ... drive voltage , Vpo, pinch-off voltage, Vss, reference voltage, Vth, threshold voltage, L1BL, drive channel length, L2BL, holding channel length, OELL, EL layer, SCLK, timing signal, T1BL, driving etching stopper layer, T2BL, holding etching stopper. Layer, SCON1 ... selection control signal, SCON2 ... data control signal, CON3 ... Power control signal, Vsel1 ... first selection signal, Vsel2 ... second selection signal, 11 ... substrate, 12 ... gate insulating layer, 13 ... semiconductor layer, 14 ... ohmic contact layer, 100 ... EL device, 110 ... display signal Generating unit, 120 ... system controller, 130 ... selection driver, 130A ... first selection driver, 130B ... second selection driver, 140 ... data driver, 150 ... power supply driver, 160 ... EL panel.

Claims (9)

A holding transistor that connects the holding capacitor and the power line to hold the voltage in the holding capacitor;
A driving transistor for passing a current corresponding to the voltage held by the holding capacitor to the EL element;
A plurality of thin film transistors including
The thin film transistor
A gate electrode layer;
Two terminal electrode layers connected to one surface of the semiconductor layer, wherein each of the two terminal electrode layers is opposed to the end of the gate electrode layer in the channel length direction with the semiconductor layer interposed therebetween An electrode layer,
The distance between the two terminal electrode layers along the channel length direction is the channel length, the length of the gate electrode layer along the channel length direction is the gate electrode length, and the gate electrode length and the channel length Is the difference in channel length / gate electrode length,
The channel length / gate electrode length difference of the holding transistor is larger than the channel length / gate electrode length difference of the driving transistor,
EL device. The thin film transistor
The EL device according to claim 1, further comprising a stopper layer connected to the one surface and positioned between the two terminal electrode layers and defining the channel length between the two terminal electrode layers. The two electrode terminal layers are composed of a source electrode layer and a drain electrode layer,
Of the both ends of the stopper layer in the channel length direction, the end close to the source electrode layer is a first stopper end, and the end close to the drain electrode layer is a second stopper end,
Of the both ends of the gate electrode layer in the channel length direction, the end close to the source electrode layer is the first electrode end, and the end close to the drain electrode layer is the second electrode end,
The distance along the channel length direction between the first stopper end and the first electrode end is a source side channel length / gate electrode length difference,
The distance along the channel length direction between the second stopper end and the second electrode end is a drain side channel length / gate electrode length difference,
In the driving transistor,
The stopper layer is an upper layer than the gate electrode layer,
The EL device according to claim 2, wherein the source-side channel length / gate electrode length difference and the drain-side channel length / gate electrode length difference are equal to each other. Of the two electrodes of the storage capacitor, the electrode connected to the storage transistor is the first electrode, and the electrode different from the first electrode is the second electrode,
The plurality of thin film transistors includes:
A selection transistor that connects a data line and the second electrode and applies a gradation voltage in the data line to the second electrode;
4. The EL device according to claim 1, wherein a channel length / gate electrode length difference of the holding transistor is larger than a channel length / gate electrode length difference of the selection transistor. 5. Of the two electrodes of the storage capacitor, the electrode connected to the storage transistor is the first electrode, and the electrode different from the first electrode is the second electrode,
The plurality of thin film transistors includes:
A selection transistor that connects a data line and the second electrode and applies a gradation voltage in the data line to the second electrode;
In the selection transistor,
The stopper layer is an upper layer than the gate electrode layer,
The EL device according to claim 3, wherein the source side channel length / gate electrode length difference and the drain side channel length / gate electrode length difference are equal to each other. A first selection line to which a first selection signal that changes between a first selection level and a first non-selection level is input;
A second selection line to which a second selection signal that changes between a second selection level and a second non-selection level is input;
With
The gate electrode layer of the holding transistor is connected to the first selection line;
The EL device according to claim 4, wherein the gate electrode layer of the selection transistor is connected to the second selection line. A selection driver for changing the selection signal into a selection level and a non-selection level;
The holding transistor has a gate to which the selection signal is input, and by inputting the selection level, the holding capacitor and the power supply line are electrically connected to write a voltage to the holding capacitor,
The selected driver is
In a write operation, the selection signal is set to a selection level,
In the light emitting operation, the selection signal is set to the non-selection level,
In the input of the gate in the light emitting operation,
The voltage at which the on-current rises is the first level,
The voltage at which the off current rises is the second level,
The EL device according to claim 6, wherein the non-selection level is set between the first level and the second level. A holding transistor that connects the holding capacitor and the power line to hold the voltage in the holding capacitor;
A driving transistor for passing a current corresponding to the voltage held by the holding capacitor to the EL element;
A method of manufacturing an EL device including a plurality of thin film transistors including:
The step of forming the thin film transistor includes
Forming a gate electrode layer on the surface of the substrate;
Covering the gate electrode layer with a gate insulating layer;
Covering the gate insulating layer with a semiconductor layer;
Forming two ohmic contact layers and two terminal electrode layers on the semiconductor layer, the ohmic contact layers and the terminal electrode layers at positions facing the end portions of the gate electrode layers in a channel length direction; Forming in this order,
Including
The distance between the terminal electrode layers along the channel length direction is the channel length, the length of the gate electrode layer along the channel length direction is the gate electrode length, and the gate electrode length and the channel length The difference is the channel length / gate electrode length difference,
In the step of forming the terminal electrode layer,
A method for manufacturing an EL device, wherein the difference in channel length / gate electrode length of the holding transistor is larger than the difference in channel length / gate electrode length of the driving transistor. The step of forming the thin film transistor includes
Before forming the terminal electrode layer, laminating a stopper film on the semiconductor layer;
Forming a resist film on the stopper film, and forming a resist mask on a portion facing the gate electrode layer by exposing and developing the resist film; and
Forming a stopper layer by etching the stopper film using the resist mask,
The step of forming the terminal electrode layer includes:
The terminal is formed such that an ohmic contact thin film and a terminal metal film covering the stopper layer are formed in this order on the semiconductor layer, and the terminal metal film and the ohmic contact thin film are divided on the stopper layer. Etching the metal film for use and the thin film for ohmic contact,
In the step of forming the resist mask,
Forming the resist mask for determining the channel length of the driving transistor by exposure from the back side of the substrate using the gate electrode layer as a mask;
The method for manufacturing an EL device according to claim 8, wherein the resist mask for determining a channel length of the holding transistor is formed by exposure from a surface side of the substrate.

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