JP2015179138A - liquid crystal display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce power consumption due to writing operation to an image display part formed of plural pixels, compared with that on a conventional device, without significantly changing a circuit structure.SOLUTION: Respective output terminals of first inverters inv1, inv1in an initial stage storage part are coupled to drains of second switching transistors nmos2, nmos2in a second stage storage part in a same pixel and coupled to sources of first switching transistors nmos1, nmos1in an initial stage storage part on pixels 12, 12on an upper line by one line (not shown). An initial stage storage part connection circuit in which the output terminals of first inverters on the respective initial stage storage part and the sources of the first switching transistors nmos in the initial stage storage part on the upper line by one line are coupled, in n pixels 12-12in same one row, forms a shift register VSR1 in a vertical direction. The shift register in the vertical direction shifts the pixel data from the pixel in the lowermost row to the pixel in the uppermost row in a column direction and holds the pixel data.

Description

  The present invention relates to a liquid crystal display device, and more particularly, to a digital drive type liquid crystal display device that performs gradation display by combining a plurality of subframes based on subframe data.

  In recent years, a liquid crystal on silicon (LCOS) type liquid crystal display device is often used as a central part for projecting an image in a projector device or a projection television. As a display method of this LCOS type liquid crystal display device, digital video data obtained by subjecting a video signal to pulse width modulation (PWM) to a semiconductor element such as a complementary metal oxide semiconductor (CMOS) is used as a pixel electrode of the liquid crystal display element. There is a digital driving method in which the liquid crystal is driven by switching the alignment of the liquid crystal in time. The digital driving method has an advantage that it is strong against burn-in, although it is inferior in gradation display as compared with the analog driving method in which an analog video signal is applied to the pixel electrode of the liquid crystal display element.

  Further, in a digital drive type liquid crystal display device, for example, gradation display is performed by combining a plurality of subframes based on subframe data. In this digital drive method, one frame, which is a display unit of one image of a video signal to be displayed, is divided into a plurality of subframes having a display period shorter than one frame period, and the plurality of subframes are displayed. A pixel is driven by a combination of subframes corresponding to the gradations to be displayed by selectively turning on and off with 1-bit subframe data which is a digital signal in accordance with the power gradations.

  In such a digital drive type liquid crystal display device, each pixel has a first shift register that holds 1-bit subframe data supplied via a column data line, and a subframe that is held in the first shift register. There is known a liquid crystal display device including a second shift register that transfers data and applies it to pixel electrodes of a liquid crystal display element (see, for example, Patent Document 1).

  The first shift register holds a first switching transistor that samples 1-bit subframe data supplied via a column data line by a row selection signal, and subframe data sampled by the first switching transistor. And a first inverter. The second shift register is turned on when a trigger pulse is supplied via the common signal line, and the second switching transistor transfers the subframe data held in the first inverter, and the second switching transistor And a second inverter that applies the subframe data transferred to the pixel electrode.

  According to the liquid crystal display device described in Patent Document 1, subframe data held as a dynamic random access memory (DRAM) in the gate portion of the first inverter is transferred to all pixels via the second switching transistor. At the same time, it can be transferred to the pixel electrode. For this reason, the voltage of the subframe data applied to the pixel electrode can be synchronized in all pixels with the common electrode voltage waveform that drives the common electrode facing the pixel electrode of the liquid crystal display element. The polarity of the voltage applied to the liquid crystal (the potential difference between the pixel electrode voltage and the common electrode voltage) can be reversed for each subframe, and image quality deterioration such as burn-in can be suppressed. In addition, it is possible to switch between video signals that are different on the left and right for stereoscopic video display and the like, and it is possible to obtain an effect that the black data display for reducing the brightness becomes unnecessary. Further, in the liquid crystal display device described in Patent Document 1, since both the first shift register and the second shift register are composed of inverters, the number of transistors can be reduced, and thereby the pixel can be miniaturized. There is also.

JP2013-101285A

  However, the liquid crystal display device described in Patent Document 1 has a problem of high power consumption. In the digital drive type liquid crystal display device, power is consumed mainly by an external data input unit and a pixel unit performing a writing operation. In particular, since the power supply voltage in the pixel portion is higher than that of the external data input portion, the power consumption is greatly affected. Further, the number of pixels and the length of wiring increase as the number of pixels increases in the pixel portion as in a liquid crystal display device having a horizontal pixel count of 4096 and a vertical pixel count of 2400 (hereinafter referred to as a “4K2K panel”). By increasing the length, the load capacitance value of the wiring increases, so that the power consumption of the driver that outputs a signal to the column data line increases.

  In addition, in a multi-pixel configuration such as a 4K2K panel, the amount of data is very large, and when one frame of grayscale display is performed in 64 subframes using 44-bit width subframe data, 4096 pixels are obtained in units of horizontal lines. Even if simultaneous writing is performed, it is necessary to perform a writing operation once every 10 MHz in 60 Hz progressive display, which requires a high-speed operation and has a very large influence on power consumption. The required data rate is 37.749 Gbps (≈ 1/60/64 / (4096 × 2400)), and when transmitting with 44 channels of low amplitude differential signaling (LVDS), per channel The minimum data rate is about 857.9Mbps. Actually, it takes about 1 Gbps because it requires time other than sending data by LVDS.

  Here, since the power consumption P at the time of signal writing to the pixel of the liquid crystal display device described in Patent Document 1 is CMOS logic, it is expressed by the following equation.

P = N × Fc × CL × Vdd ² + N × Psc + N × Plk (1)
In equation (1), N is the number of column data lines, Fc is the drive frequency, CL is the load capacity of the column data lines, Vdd is the signal voltage, Psc is a driver and pixel that outputs subframe data to the column data lines The power consumption due to the through current of the first inverter, Plk is the power consumption due to the leakage current of the driver or the like. The power consumption Psc is smaller than the power consumption of the load capacity, and the power consumption Plk due to the leakage current is almost negligible. Therefore, when the power consumption generated in CL is larger than (N × Psc + N × Plk) and when the number N of column data lines is large, equation (1) is expressed by the following equation.

P ≒ N x Fc x CL x Vdd ² (2)
Here, the load capacitance CL of the column data line is several pF. For example, when 0 and 1 are rewritten for each line, the charge / discharge current for driving the column data line is the largest. In the case of a 4K2K panel, since there are 4000 or more column data lines, assuming that the load capacity per column data line is 2 pF, the load capacity CL of all the column data lines exceeds 8000 pF.

  In addition, when driving a row scanning line, 4000 pixels or more of one line are driven simultaneously, so one line selection cycle is 100 ns (≈ 1/60/64/2400), which is not fast, but 4000 pixels or more. In order to drive the first switching transistor (pixel selection transistor) of each pixel, the load capacitance is about several pF to 10 pF. Therefore, the power consumption increases as compared with a full high-definition liquid crystal display device.

  Furthermore, since the data transfer from the first inverter, which is the first stage storage unit of the input subframe data in the pixel, to the second inverter of the second stage storage unit is performed almost simultaneously in all pixels at the time of pixel readout, the parasitic load Charging / discharging to the capacity and writing current to the second inverter are generated, and in some cases, charging / discharging occurs in the second inverter having 8 million pixels (= 4096 × 2400), so the power consumption is extremely large. Become.

  For the above reason, the power consumption Plk in the equation (1) is a level that can be almost ignored. However, the conventional liquid crystal display device described in Patent Document 1 has a problem that the power consumption P is very large. The large current consumption causes a voltage variation due to the parasitic resistance of the power supply GND wiring in the chip, and as a result, there is a problem that malfunction of the logic part is likely to occur.

  The present invention has been made in view of the above points, and is a digital drive system that can reduce power consumption due to a writing operation to an image display unit composed of a plurality of pixels as compared with the conventional one without significantly changing the circuit configuration. An object is to provide a liquid crystal display device.

In order to achieve the above-described object, the present invention provides a plurality of pixels that are arranged in a two-dimensional matrix in the row direction and the column direction to constitute the image display unit.
The first stage storage unit configured to sample the pixel data supplied at the time of writing by the first switching element and store it in the first memory, and the first stage storage unit through the second switching element that is controlled to be turned on at the time of reading. Liquid crystal is filled and sealed between the second-stage storage unit configured to temporarily store the pixel data read from the first memory in the second memory, and the pixel electrode and the common electrode that are arranged to face each other. A liquid crystal display element for displaying an image by applying the pixel data stored in the second memory of the unit to the pixel electrode,
Connecting the output terminal of the first stage storage unit in one of two adjacent pixels among the plurality of pixels arranged in the same column to the input terminal of the first switching element of the first stage storage unit in the other pixel A column-by-column shift register configured by repeating in one direction from one to the other of each pixel in the bottom row and each pixel in the top row,
The pixel data to be displayed is supplied and stored in the first row storage unit of the bottom row or the top row of pixels constituting the first row of the shift register for each column, and the stored pixel data is supplied to the last row of the shift register for each column. And shift register control means for shifting in synchronization with the shift clock.

  According to the present invention, it is possible to reduce the power consumption due to the writing operation to the image display unit as compared with the prior art without significantly changing the circuit configuration.

It is a block diagram of one embodiment of a liquid crystal display device of the present invention. FIG. 3 is a circuit diagram of a main part of the first embodiment of two adjacent pixels among n pixels arranged in the same pixel column in the liquid crystal display device of the present invention. 3 is a timing chart for explaining an operation at the time of writing in the pixel shown in FIG. 2. It is a circuit diagram of the principal part of 2nd Embodiment of two adjacent pixels among the n pixels arrange | positioned in the same pixel row | line in the liquid crystal display device of this invention. It is a circuit diagram of the principal part of 3rd Embodiment of two adjacent pixels among n pixels arrange | positioned at the same pixel row | line in the liquid crystal display device of this invention. It is a circuit diagram of the principal part of 4th Embodiment of two adjacent pixels among the n pixels arrange | positioned in the same pixel row | line in the liquid crystal display device of this invention. FIG. 14 is a circuit diagram of a main part of a fifth embodiment of two adjacent pixels among n pixels arranged in the same pixel column in the liquid crystal display device of the present invention.

  Next, embodiments of the present invention will be described with reference to the drawings.

  FIG. 1 shows a block diagram of an embodiment of a liquid crystal display device according to the present invention. In the figure, the liquid crystal display device 10 of the present embodiment includes an image display unit 11 in which a plurality of pixels 12 are arranged in a two-dimensional matrix, a high-speed interface (I / F) circuit 13, and a data selector (D / S). ) With parallel D-type flip-flop (DFF) 14, pixel adjustment shift register 15, horizontal signal driver 16, control circuit 17, first stage storage unit shift clock driver / transfer inverter chain drive circuits 18 and 19, This is a liquid crystal display device of a digital drive system composed of

  The image display units 11 are arranged m (m is a natural number of 2 or more) in the row direction (horizontal direction) and n (n is a natural number of 2 or more) in the column direction (vertical direction). In this configuration, n pixels 12 are arranged in a two-dimensional matrix. Each pixel 12 is schematically shown as one rectangle in FIG. Each pixel 12 has a liquid crystal display element (not shown) having a known structure in which liquid crystal is filled and sealed between a common electrode and a pixel electrode (or a liquid crystal driving electrode) that are provided facing each other. As is well known, pixel electrodes are provided separately for each pixel, and a common electrode is provided in common for all pixels.

  The m pixels 12 arranged in the horizontal direction are arranged in parallel to the horizontal direction in which both ends are connected to the first stage storage unit shift clock driver / transfer inverter chain drive circuits 18 and 19, respectively, and alternately n / 2. They are separately connected to the forward shift clock signal line and the inverted shift clock signal line arranged one by one. That is, of the adjacent two lines of m pixels, m pixels on one line are connected to the normal shift clock signal line, and m pixels on the other line are connected to the inverted shift clock signal line. ing. On the other hand, among the n pixels 12 arranged in the vertical direction, for example, the pixel arranged at the lowest position in the image display unit 11 is parallel to the vertical direction in which one end is connected to the horizontal signal driver 16. The m column data lines are connected separately. That is, one column data line is connected to the pixel 12 in the lowermost row (nth line) among n pixels in the same column provided correspondingly. The liquid crystal display device 10 of the present embodiment has a configuration in which a pixel 12 has a first-stage storage unit, a second-stage storage unit, and a pixel electrode connected in series as will be described later, and the first-stage storage unit includes n stages in the vertical direction. This is characterized in that the shift register is configured. The n-stage shift register in which the first-stage storage units are connected in the vertical direction constitutes a shift register for each column of the present invention.

  The high-speed I / F circuit 13 receives pixel data (here, subframe data) of an image supplied from the outside with a high-speed I / F using LVDS or the like, and supplies it to the parallel DFF 14 with D / S. The parallel DFF 14 with D / S correctly arranges pixel data supplied from the high-speed I / F circuit 13 through, for example, a 64-bit digital signal bus at a horizontal pixel position in units of 64 bits by a data selector (D / S). It is held and output to the pixel adjustment shift register 15. The pixel adjustment shift register 15 shifts the pixel data supplied from the D / S-attached parallel DFF 14 and adjusts the horizontal position. Here, for example, when the number m of pixels for one line is “4096”, assuming that about four adjustment pixels for adjusting the display position are arranged on both sides thereof, the pixel adjustment shift register 15 is 4100. A shift operation is performed by a shift register of (= 4096 + 4) stages. As a result, pixel data can be written to the pixel to be displayed as a result.

  The horizontal signal driver 16 constitutes the pixel data generating means of the present invention, and outputs each subframe data of one line supplied from the pixel adjustment shift register 15 to the column data line of the corresponding pixel. The control circuit 17 controls the operations of the parallel DFF with D / S 14, the pixel adjustment shift register 15, and the horizontal direction signal driver 16 based on the signal supplied from the high-speed I / F circuit 13.

  For example, the control circuit 17 generates an enable signal for selecting a signal by D / S and a clock for latching in the D / S-attached parallel DFF 14. Further, the control circuit 17 generates a shift clock and a load signal for parallel input to the pixel adjustment shift register 15. For the first stage storage unit shift clock driver and transfer inverter chain drive circuits 18 and 19 corresponding to the vertical drive circuit, a shift clock and a control signal for adjusting the timing are generated. Command bits input from the LVDS are the basis for them.

  The first stage storage unit shift clock driver and the transfer inverter chain drive circuit in the transfer inverter chain drive circuits 18 and 19 transfer transfer pulses applied to the second stage storage unit in each pixel 12 little by little through the inverter chain circuit. This is to delay the transfer circuit so that the transfer circuit is not turned on at the same time. In addition, as shown in 18 and 19, two first-stage storage unit shift clock drivers and transfer inverter chain drive circuits having the same configuration are provided on the left and right sides of the image display unit 11. This is because of the problem that the number of pixels is large and one drive capacity is insufficient. However, in principle, one is sufficient. The first stage storage unit shift clock driver and transfer inverter chain drive circuits 18 and 19 and the first stage storage unit shift clock driver and the control circuit 17 constitute shift register control means in the present invention.

  Next, each embodiment of the pixel 12 which is a main part of the liquid crystal display device of the present invention will be described in detail.

  FIG. 2 is a circuit diagram of a main part of the first embodiment of two adjacent pixels among n pixels arranged in the same pixel column in the liquid crystal display device according to the present invention. In the liquid crystal display device 10 according to the present embodiment, when writing pixels, control is performed in units of two adjacent pixel groups. Therefore, in FIG. 2, only two pixels in the same column among the two pixel groups in the control unit are shown in FIG. (However, only the pixel electrode is shown in the liquid crystal display element in the pixel).

In FIG. 2, a pixel 12 _n is a pixel on the _n- th line, a pixel 12 _n-1 is a pixel on the (n-1) -th line, and each of them is an N-channel MOS field effect transistor (hereinafter referred to as a first switching element). , NMOS transistors), first _- stage storage units composed of first switching transistors nmos1 _n , nmos1 _n-1 and first inverters inv1 _n , inv1 _n-1, and NMOS transistors constituting the second switching element 2 switching transistors nmos2 _n and nmos2 _n−1 and a second-stage storage unit including second inverters inv2 _n and inv2 _n−1 . The first stage storage unit constitutes a DRAM. The first inverters inv1 _n and inv1 _n-1 constitute a first memory, and the second inverters inv2 _n and inv2 _n-1 constitute a second memory.

The output terminals of the first inverters inv1 _n and inv1 _n-1 in the first-stage storage unit are connected to the drains of the second switching transistors nmos2 _n and nmos2 _n-1 in the second-stage storage unit in the same pixel. The pixels 12 _n-1 and 12 _n-2 (not shown) on one line are connected to the sources of the first switching transistors nmos1 _n-1 and nmos1 _n-2 in the first stage storage unit. Note that in the pixels 12 _{n-2 to} 12 ₂ in the same column as the pixels 12 _{n to} 12 _n-1 not shown in FIG. 2, the output terminals of the output terminals of the first inverter in the first-stage storage unit are on one line. The pixels 12 _{n-3 to} 12 ₁ (all not shown) are connected to the source of the first switching transistor in the first-stage storage unit.

In the n pixels 12 _{n to} 12 ₁ in the same one column, the output terminal of the first inverter of each first-stage storage unit and the source of the first switching transistor nmos in the first-stage storage unit of the pixels on one line are The connected first stage storage unit connection circuit constitutes a vertical shift register VSR1 corresponding to the shift register for each column of the present invention. The output terminals of the second inverters inv2 _n and 2 _n-1 are connected to the pixel electrodes of the liquid crystal display elements in the pixels 12 _n and 12 _n-1 . Note that the DRAM constituting the first-stage storage unit is used when writing pixels, and the second-stage storage unit is used when reading pixels.

The gate of nmos1 _n is connected to a normal shift clock signal line gn having both ends connected to the first stage storage unit shift clock driver / transfer inverter chain drive circuits 18 and 19. The gate of nmos1 _n-1 is connected to an inverted shift clock signal line gn-1 having both ends connected to the first stage storage unit shift clock driver / transfer inverter chain drive circuits 18 and 19. The normal shift clock transmitted by the normal shift clock signal line and the inverted shift clock transmitted by the inverted shift clock signal line are first-stage storage unit shift clocks that are always in an inverse logic value relationship. Therefore, when one of nmos1 _n and nmos1 _n-1 is on, the other is off.

On the other hand, the gate of nmos2 _n is connected to a first transfer signal line trga having both ends connected to the first stage storage unit shift clock driver / transfer inverter chain drive circuits 18 and 19. Further, the gate of nmos2 _n-1 is connected to a second transfer signal line trgb whose both ends are connected to the first-stage storage unit shift clock driver / transfer inverter chain drive circuits 18 and 19. The first and second transfer signals transmitted by the first and second transfer signal lines trga and trgb are transfer clocks having a slight phase difference due to the inverter chain drive circuit. Therefore, when one of nmos2 _n and 2 _n-1 is turned on, the other is turned on with a slight time delay.

  Conventionally, sub-frame data to be supplied to the column data line is written by a driver immediately before the sub-frame period, and is written in the first-stage storage unit of each pixel selected in units of one row by a pixel selection signal (row scanning signal). On the other hand, in the liquid crystal display device 10 of the present embodiment, the output terminal of the first inverter of the first stage storage unit of each pixel 12 is connected to the pixel on one line, except for the column data line and its driver as in the conventional device. By connecting to the source of the first switching transistor of the first-stage storage unit, the shift register VSR1 is configured in the vertical direction, and writing to each pixel 12 is performed. The sub-frame data to be written in the first-stage storage unit is moved by the horizontal line shift operation, whereby the writing to the pixel 12 is performed.

  That is, the subframe data is written to the initial stage storage unit in one of the pixels in two adjacent rows immediately before each subframe period, and then the initial stage in the other pixel in the adjacent two rows of pixels. By performing a shift operation that alternately repeats reading and writing the subframe data written in the first-stage storage unit in one pixel in the storage unit in units of two rows, subframe data is stored in the first-stage storage unit of all pixels. Write.

  After the end of writing, the subframe data stored in the first stage storage unit in each pixel of two adjacent rows is transferred only once at the beginning of the subframe period according to the control of the first and second transfer signals. The data is transferred to the second-stage storage unit with a slight shift and applied to the pixel electrode. The second-stage storage unit of all the pixels is sequentially controlled with a slight shift for each row by the transfer signal. Accordingly, sub-frame data is applied to the pixel electrodes in the pixels almost simultaneously at the beginning of the sub-frame period, and sub-frame display is performed for all the pixels.

Next, the writing operation of the pixel shown in FIG. 2 will be described in more detail with reference to the timing chart of FIG. Each 1-bit sub-frame data output in parallel from the horizontal direction signal driver 16 of FIG. 1 is pixel data to be first displayed on the pixels 12 of the first line. Hereinafter, subframe data to be displayed in each pixel 12 from the second line to the nth line is output and input to the _nth pixel 12n of the image display unit 11. However, when data is transferred from the first-stage storage unit in the pixels on the lower line of the adjacent two lines of pixels 12 to the first-stage storage unit in the pixels on one line, the subframe data is inverted and output. Therefore, from the horizontal signal driver 16, the normal subframe data indicating the original logical value of the binary subframe data and the inverted subframe data indicating the reverse logical value are shifted to the vertical vertical register described later. It is output alternately every clock cycle.

That is, among the n pixels arranged in a certain column, the source of nmos1 _n in the first-stage storage unit of the pixel 12 _n of the n-th line shown in FIG. 2 is the first as shown in FIG. Normal subframe data d1 displayed on the line, inverted subframe data / d2 displayed on the second line, normal subframe data d3 displayed on the third line, inverted subframe displayed on the fourth line Up to normal subframe data dn displayed on the nth line in the order of data / d4...

On the other hand, the second shift clock shown in FIG. 3A is supplied to the signal line gn _-1 in synchronization with the output timing of the subframe data, and the first shift clock shown in FIG. There is supplied to the signal line g _n. These first and second shift clocks are symmetrical square waves that have an inverse logic relationship with each other and have the same period as the subframe data output period. Also, the period from time t1 to t2 in the first half of the period from time t1 to t3 when subframe data d1 is supplied to the source of nmos1 _n in the first stage storage unit of pixel 12 _n that is the first stage of the vertical shift register. is applied to the gate of NMOS1 _n via the first shift clock signal line g _n of "H" level as shown in FIG. 3 (B), FIG. as shown in (a) "L" level Since the second shift clock is applied to the gate of nmos1 _n-1 via the signal line gn _-1 , nmos1 _n is controlled to be on and nmos1 _n-1 is controlled to be off. Therefore, the sub-frame data d1 is applied to the inverter inv1 _n via NMOS1 _n in the first stage the storage unit of the pixel 12 _n, it is held in the gate.

Next, in the period from the time t2 to t3 in the latter half of the period from the time t1 to t3 when the subframe data d1 is supplied to the first stage storage unit of the pixel 12 _n , as shown in FIG. "first shift clock level via the signal line g _n is applied to the gate of NMOS1 _n, FIG as shown in (a)" second shift clock H "level signal line g _n-1 Is applied to the gate of nmos1 _n-1 , so that nmos1 _n is turned off and nmos1 _n-1 is turned on. Therefore, the inverter subframe data d1 that has been held in the gate of the inverter inv1 _n via the NMOS1 _n-1 in the first stage the storage unit of the pixels 12 _n-1 as is the polarity reversal / d1 by the inverter inv1 _n inv1 _{n- It} is transferred to ₁ and held at its gate.

Subsequently, the inverted subframe data / d2 obtained by inverting the polarity of the subframe data d2 is supplied to the initial stage storage unit of the pixel 12 _n for a period from time t3 to t5. During the period from the time t3 to the time t4 in the first half, as shown in FIG. 3B, the first shift clock of H ″ level is applied to the gate of nmos1 _n via the signal line gn. As shown in FIG. 2, since the second shift clock of “L” level is applied to the gate of nmos1 _n-1 via the signal line g _n-1 , nmos1 _n is turned on and nmos1 _n-1 is turned off. Therefore, the inverted subframe data / d2 is applied to the inverter inv1 _n via nmos1 _n in the first-stage storage unit of the pixel 12 _n and held at the gate thereof.

Subsequently, in the period from time t4 to t5 in the latter half of the period from time t3 to t5 during which the inverted subframe data / d2 is supplied to the initial stage storage unit of the pixel 12 _n , as shown in FIG. "L" first shift clock level via the signal line g _n is applied to the gate of NMOS1 _n, as shown in FIG. (a) "H" second shift clock signal line g _n levels _Since it is applied to the gate of nmos1 _n-1 via _-1 , nmos1 _n is controlled to be off and nmos1 _n-1 is controlled to be on. Therefore, the sub-frame data / d2 is NMOS1 _n-1 of the polarity inversion has been pixel first-stage storage portion 12 _n-1 as the original polarity of the sub-frame data d2 by the inverter inv1 _n held in the gate of the inverter inv1 _n Is transferred to the inverter inv1 _n-1 through and held at its gate.

Hereinafter, similarly, the first switching transistor nmos in the first-stage storage unit of each pixel from the upper (n-2) th line to the first line of the pixel 12 _n-1 is also connected to the lower n-1 line. The operation of inverting and transferring the subframe data held in the first inverter of the first stage storage unit of each pixel up to the second line is repeated. Thereby, the subframe data schematically shown in FIG. 3C is stored in the inverter inv1 _n in the first stage storage unit of the pixel 12 _n , and the inverter inv1 _{n-1 in} the first stage storage unit of the pixel 12 _n-1 is stored in the inverter inv1 _n-1 in the first stage storage unit. The subframe data schematically shown in FIG. 3D is stored. 3 (E), (F), (G), (H), (I), and (J) are pixel 12 _n-2 , pixel 12 _n-3 , pixel 12 ₄ , pixel 12 ₃ , pixel 12 ₂ schematically shows subframe data held in the first-stage storage unit of the pixel 12 ₁ .

In this way, the n-th shift clock is transmitted through the signal line gn and the normal rotation subframe data dn is supplied to the first-stage storage unit of the pixel 12 _n at time t6 as schematically shown in FIG. As shown schematically, the subframe data dn is stored and held in the first-stage storage unit of the pixel 12 _n on the n-th line, and at the same time t6, as schematically shown in FIGS. , in all the pixels 12 _n-2 from the (n-1) line to the first line to the pixel 12 _1, d1 from the forward subframe data dn-1 respectively stored and held, the write operation by the shift operation is completed . Of course, the same write operation is performed in parallel with the above write operation for each of the n pixels 12 in the other columns.

Note that the vertical shift register VSR1 configured by the first-stage storage units of the _n pixels 12 _{n to} 12 _{1 in} the same column is in one cycle of the shift clock shown in FIGS. to shift the two lines data, number largest number n shift clock supplied to the first stage of the pixel 12 _n in the vertical direction of the shift register VSR1, the shift clock supplied to the last pixel 12 ₁ The number is n / 2, and the number of shift clocks until the original data is stored differs depending on the number of pixels. Therefore, the shift clock for data transfer is configured by the driver so as to be different for each line. Specifically, it can be realized by gating a clock with a gate circuit using a counter for counting a shift clock and a circuit for decoding the output.

  Next, it will be described that the power consumption during writing, which is an effect of the present embodiment, is lower than the power consumption during writing of the conventional liquid crystal display device.

As described above, in the present embodiment, the subframe data written to the pixel 12 is the first stage of the vertical shift register VSR1 configured by the first stage storage units of the _n pixels 12 _{n to} 12 _{1 in} the same column. writing to the write period of 1 per line than the pixel 12 _n (e.g., 10 MHz) will be shift operation, the first stage storage portion for all pixels by performing a shift operation to the pixel 12 ₁ of the last of the n-th stage The operation ends. Since the shift operation of the vertical shift register VSR1 is always performed synchronously for all pixels, the power consumption P1 at the time of writing in this embodiment is expressed by the following equation.

P1 = L × N × Fc × CLm × Vdd ² + N × Pscm + N × Plkm (3)
In equation (3), L is the number of vertical lines (n in the above example), N is the number of signal lines in the vertical direction (n in the above example), Fc is the drive frequency, and CLm is shown in FIG. Further, the load capacity of the first-stage storage unit of one pixel (mainly the junction capacity of nmos1 _n-1 and the parasitic capacity accompanying the signal wiring between the lines), Vdd is a signal voltage to be shifted. Pscm is the power consumption due to the through current of the first-stage storage unit, and is a small value. Since there is no through current of the conventional column data line driver, it is a very small value. Plkm is the power consumption due to the leakage current of the first-stage storage unit, which is almost negligible, and is a value smaller by the leakage current of the conventional column data line driver.

  Here, there is the following difference between the power consumption P1 at the time of writing of this embodiment and the power consumption at the time of writing of the conventional liquid crystal display device shown in the equation (2).

CL ≠ CLm × L (4)
N x Psc >> N x Pscm (5)
N × Plk ≫ N × Plkm (6)
Here, Psc is the sum of the power consumption of the driver that outputs the subframe data to the conventional column data line and the power consumption due to the through current of the first inverter of the pixel, whereas Pscm in this embodiment is the pixel. This is only the power consumption due to the through current of the first stage storage section. Therefore, equation (5) can be rewritten as:

N x (Pscm + Pscd) >> N x Pscm (7)
In equation (7), Pscd is the power consumption related to the through current of the driver of the column data line. Also, equation (6) can be rewritten into the following equation.

N × (Plkm + Plkd) >> N × Plkm (8)
However, in the equation (8), Plkd is the power consumption related to the leakage current of the column data line driver.

  Although CL may be almost the same value as CLm, the junction capacitance of the driver of the vertical signal line (column data line) is small. Therefore, equation (4) can also be rewritten as

CL> CLm × L (9)
Therefore, the power consumption by the column data line driver in the conventional liquid crystal display device represented by the equations (7) and (8) can be reliably reduced in the liquid crystal display device of this embodiment.

As described above, according to the liquid crystal display device 10 of the present embodiment, the pixel data (specifically, subframe data) written in the pixel via the column data line in the conventional liquid crystal display device is stored in the initial stage storage unit of the pixel. (DRAM circuit composed of switching transistors nmos1 _n to _{1 1} and inverters inv1 _n to _{1 1} ) are connected so that a shift register can be configured in the vertical direction, and finally the pixel data to be input to the second-stage storage unit of the pixel It was set as the structure hold | maintained to the line of the front | former stage. Further, in the liquid crystal display device of this embodiment, since the column data lines in the vertical direction are eliminated, a driver circuit with high power consumption for driving them can be omitted, and it is not necessary to drive a large load capacity. Therefore, power consumption can be reduced by optimizing the design of the vertical shift register.

  In addition, according to the liquid crystal display device of the present embodiment, the storage pixel data is applied to the pixel electrode of each of the pixels from the first-stage storage unit almost simultaneously, thereby improving the reliability and the brightness factor.

  Next, a second embodiment of the pixel 12 that is a main part of the liquid crystal display device of the present invention will be described in detail. FIG. 4 is a circuit diagram of a main part of the second embodiment of two adjacent pixels among n pixels arranged in the same pixel column in the liquid crystal display device according to the present invention. Note that only the pixel electrode is shown in the liquid crystal display element in the pixel. In the figure, the same components as those in FIG.

In FIG. 4, a pixel 12 _n is a pixel on the _n- th line, a pixel 12 _n-1 is a pixel on the (n-1) -th line, and the first-stage storage unit, the second-stage storage unit, and the pixel electrode of the liquid crystal display element, respectively. Is the same as the pixel of the first embodiment in that it is connected in series, but the configuration of the initial storage unit and the configuration of the vertical shift register are different from those of the pixel of the first embodiment.

That is, the first-stage storage portion of the pixel 12 _n is the first source of the switching transistor NMOS1 _n by NMOS transistors, respectively connected to the input terminal of the first inverter inv3 _n and the output terminal of the second inverter inv4 _n configuration It is. Similarly, the first _- stage storage unit of the pixel 12 _n-1 has an input terminal of the _first inverter inv3 _n-1 and a second inverter inv4 _n-1 connected to the source of the _first switching transistor nmos1 _n-1 by the NMOS transistor. The output terminal is connected to each other. The inverter inv3 _n and the inverter inv4 _n constitute a self-holding memory in which each input terminal is connected to one output terminal, and constitutes a static random access memory (SRAM) together with the switching transistor nmos1 _n. ing. Similarly, the inverter inv3 _n-1 and the inverter inv4 _n-1 constitute a self-holding memory in which each input terminal is connected to one output terminal, and the SRAM is configured with the switching transistor nmos1 _n-1. doing.

Further, the output terminals of the SRAM constituting the first stage storage unit (the output terminals of the inverters inv3 _n and inv3 _{n-1 and} the input terminals of the inverters inv4 _n and inv4 _n-1 ) are included in the second stage storage unit in the same pixel. While connected to the drains of the second switching transistors nmos2 _n and nmos2 _n−1 , the switching transistors nmos1 _n−1 in the first-stage storage section of the pixels 12 _n−1 and 12 _n-2 (not shown) on _{one line} , Nmos1 _n-2 and the input terminal of the self-holding memory (input terminals of inverters 3 _n , 3 _n-1 and output terminals of inverters 4 _n , 4 _n-1 ). Note that in the pixels 12 _{n-2 to} 12 ₂ in the same column as the pixels 12 _{n to} 12 _n-1 not shown in FIG. 2, the SRAM output terminal of the first-stage storage unit has pixels 12 _n-3 to 12 on one line. 12 ₁ (both not shown) are connected to a common connection point between the source of the first switching transistor and the input terminal of the self-holding memory in the first-stage storage unit.

In these same one column of n pixels 12 _{n to} 12 ₁ , the output terminal of the SRAM of each first stage storage unit, the source of the first switching transistor nmos in the first stage storage unit of the pixel on one line, and the self-holding memory The first-stage storage unit connection circuit connected to the connection point with the input terminal of the first terminal constitutes a vertical shift register VSR2. The output terminals of the second inverters inv2 _n and 2 _n-1 are connected to the pixel electrodes of the liquid crystal display elements in the pixels 12 _n and 12 _n-1 . Note that the first-stage storage unit is used when writing pixels, and the second-stage storage unit is used when reading pixels.

Similarly to the first embodiment, the sub-frame data written to the pixels 12 in this embodiment is a vertical shift register configured by the first-stage storage units of _n pixels 12 _{n to} 12 _{1 in} the same column. The first stage storage unit of all pixels is shifted by the write operation (for example, 10 MHz) for each line from the first stage pixel 12 _n of the VSR 2 and is shifted to the last nth stage pixel 12 _1. The write operation is completed. The vertical shift register VSR2 is a static shift register and operates up to a lower frequency than the dynamic shift register. The power consumption P2 at the time of writing in this embodiment is expressed by the following equation.

P2 = L × N × Fc × CLm × Vdd 2 + N × Psrm + N × Plkm (10)
In Equation (10), L is the number of vertical lines (n in the above example), N is the number of signal lines in the vertical direction (n in the above example), Fc is the drive frequency, and CLm is shown in FIG. Further, the load capacity of the first-stage storage unit of one pixel (mainly the junction capacity of nmos1 _n-1 and the parasitic capacity accompanying the signal wiring between the lines), Vdd is a signal voltage to be shifted. Psrm is power for rewriting the SRAM of the first storage unit, and is basically represented by a value obtained by multiplying the drive current for inverting the SRAM by the signal voltage Vdd. Plkm is the power consumption due to the leakage current of the first stage storage unit.

  The power consumption P2 at the time of writing in the present embodiment expressed by the equation (10) is the same as the power consumption P1 at the time of writing in the first embodiment expressed by the equation (3). ) And (8) show that it is possible to reduce the power consumption.

  That is, (N × Psrm) in equation (10) is considered the same as (N × Pscm) in equation (5). That is, the through current of the first-stage storage unit and the power consumption when rewriting the SRAM are the same due to the relationship between the conventional power consumption and the power consumption of the present embodiment. That is, the relationship is as shown in equation (11).

N x (Psrm + Pscd) >> N x Psrm (11)
In equation (11), Pscd is the power consumption related to the through current of the driver of the column data line.

  Further, in this embodiment, since it is not necessary to make a driver circuit, the area can be reduced, which can contribute to cost reduction.

  Next, a third embodiment of the pixel 12 which is a main part of the liquid crystal display device of the present invention will be described in detail. FIG. 5 shows a circuit diagram of a main part of the third embodiment of two adjacent pixels among n pixels arranged in the same pixel column in the liquid crystal display device according to the present invention. Note that only the pixel electrode is shown in the liquid crystal display element in the pixel. In the figure, the same components as those in FIG. 4 are denoted by the same reference numerals, and the description thereof is omitted.

In FIG. 5, a pixel 12 _n is a pixel on the _n- th line, a pixel 12 _n-1 is a pixel on the (n-1) -th line, and each of the first-stage storage unit, the second-stage storage unit, and the pixel electrode of the liquid crystal display element Are the same as the pixels in the first and second embodiments, and the configuration of the vertical shift register is the same as that of the VSR 2 in the second embodiment. The configuration of the eye storage unit is different from the pixel of the second embodiment.

In other words, the second-stage memory portion of the pixel 12 _n is a transmission gate composed of an NMOS transistor nmos3 _n and a P-channel MOS field effect transistor (hereinafter referred to as PMOS transistor) pmos1 _n whose drains and sources are connected to each other. comprising a storage capacitor CL _n and. The transmission gate constitutes a second switching element. Similarly, the second-stage storage unit of the pixel 12 _n-1 includes a transmission gate and a storage capacitor CL, each of which includes an NMOS transistor nmos3 _n-1 and a PMOS transistor pmos1 _n-1 whose drains and sources are connected to each other. _n-1 . One terminal of the transmission gate in each second-stage storage unit in each of the pixels 12 _n and 12 _n-1 is connected to the SRAM output terminal of the first-stage storage unit of the same pixel, and the other terminal is the storage capacitor CL _{n of the} same pixel. , CL _n−1 and the pixel electrodes PE _n , PE _n-1 are connected to a common connection point.

The gate of nmos3 _n is connected to the first transfer signal line trga having both ends connected to the first stage memory unit shift clock driver / transfer inverter chain drive circuits 18 and 19, and the gate of pmos1 _n is shifted to the first stage memory unit. Are connected to a third transfer signal line / trga having both ends connected to the clock driver / transfer inverter chain drive circuits 18 and 19. The gate of nmos2 _n-1 is connected to a second transfer signal line trgb having both ends connected to the first stage storage unit shift clock driver / transfer inverter chain drive circuits 18 and 19, and the gate of pmos1 _n-1 is The first stage storage unit shift clock driver and transfer inverter chain drive circuits 18 and 19 are connected to a fourth transfer signal line / trgb having both ends connected. The first and third transfer signals transmitted by the first and third transfer signal lines trga and / trga are always in an inverse logic value relationship. Similarly, the second and fourth transfer signals transmitted by the second and fourth transfer signal lines trgb and / trgb are always in an inverse logic value relationship. Further, the first and second transfer signals have the same phase relationship as in the first and second embodiments.

As a result, when the transmission gate of the second-stage storage unit of the pixel 12 _n is turned on during pixel readout, the subframe data output from the SRAM of the first-stage storage unit of the same pixel is supplied to the holding capacitor CL _n through the transmission gate. It is held and applied to the pixel electrode PE _n to cause the liquid crystal display element to perform subframe period display. At a timing slightly shifted from this, the transmission gate of the second-stage storage unit of the pixel 12 _n-1 is turned on, and the subframe data output from the SRAM of the first-stage storage unit of the same pixel passes through the transmission gate. The liquid crystal display element is displayed in the subframe period by being supplied to and held in the holding capacitor CL _n-1 and applied to the pixel electrode PE _n-1 . In the present embodiment, the same power consumption reduction effect as in the first embodiment can be obtained.

  Next, a fourth embodiment of the pixel 12 that is a main part of the liquid crystal display device of the present invention will be described in detail. FIG. 6 is a circuit diagram of a main part of the fourth embodiment of two adjacent pixels among n pixels arranged in the same pixel column in the liquid crystal display device according to the present invention. Note that only the pixel electrode is shown in the liquid crystal display element in the pixel. In the figure, the same components as those in FIGS. 2 and 5 are denoted by the same reference numerals, and the description thereof is omitted.

In FIG. 6, a pixel 12 _n is a pixel on the _n- th line, a pixel 12 _n-1 is a pixel on the (n-1) -th line, and the first-stage storage unit, the second-stage storage unit, and the pixel electrode of the liquid crystal display element, respectively. Are the same as the pixels of the first to third embodiments, and the configuration of the vertical shift register is the same as that of the VSR 1 of the first embodiment. Unlike the pixels of the first and second embodiments, the configuration of the eye storage unit is the same as that of the third embodiment.

In the embodiment shown in FIG. 6, when reading out the pixels 12 _n and 12 _n−1 , the subframe data output by inverting the polarity from the DRAM of the first stage storage unit of the same pixel is output via the transmission gate via the storage capacitor CL. _n and CL _n−1 and are applied to the pixel electrodes PE _n and PE _n−1 to cause the liquid crystal display element to display during the subframe period. In this embodiment, the same power consumption reduction effect as in the first to third embodiments can be obtained.

  Next, a fifth embodiment of the pixel 12 that is a main part of the liquid crystal display device of the present invention will be described in detail. FIG. 7 is a circuit diagram of a main part of the fifth embodiment of two adjacent pixels among n pixels arranged in the same pixel column in the liquid crystal display device according to the present invention. Note that only the pixel electrode is shown in the liquid crystal display element in the pixel. In the figure, the same components as those in FIGS. 4 and 6 are denoted by the same reference numerals, and the description thereof is omitted.

In FIG. 7, a pixel 12 _n is a pixel on the _n- th line, a pixel 12 _n-1 is a pixel on the (n-1) -th line, and each of the first-stage storage unit, the second-stage storage unit, and the pixel electrode of the liquid crystal display element Are the same as the pixels of the first to fourth embodiments, and the configuration of the vertical shift register is the same as that of the VSR2 of the second and third embodiments. In this embodiment, the configuration of the second-stage storage unit is different from the configurations of the first to fourth embodiments.

That is, the second-stage storage unit of the pixel 12 _n and the pixel 12 _n-1 of the present embodiment is the same as the second-stage storage unit of the pixel of the third and fourth embodiments shown in FIGS. The comparison is characterized in that inverters 2 _n and 2 _n-1 similar to those of the first and second embodiments are provided instead of the holding capacitors CL _n and CL _n-1 .

That is, in the pixel 12 _n and the pixel 12 _n-1 of this embodiment, the first _- stage storage unit has the SRAM configuration as in the second and third embodiments shown in FIG. As in the third and fourth embodiments shown in FIG. 6, the transmission gate is equivalent to the second switching element, and the inverter is equivalent to the second memory. In the present embodiment, the same power consumption reduction effect as in the first to fourth embodiments can be obtained.

  Note that the present invention is not limited to the above embodiment, and for example, the present invention can be applied to a digital drive type liquid crystal display device that displays an image based on pixel data other than subframe data. Further, the pixel data to be displayed has been described as shifting from the bottom row pixel to the top row pixel, but it is needless to say that the pixel data may be configured to shift in the reverse direction.

10 liquid crystal display device 11 an image display unit 12, 12 ₁ to 12 _n pixel 13 high-speed interface (I / F) circuit 14 data selector (D / S) with a parallel D-type flip-flop (DFF)
15 Pixel Adjustment Shift Register 16 Horizontal Signal Driver 17 Control Circuits 18 and 19 Clock Driver for First Stage Storage Unit Shift / Inverter Chain Drive Circuit for Transfer
nmos1 _n , nmos1 _n-1 first switching NMOS transistor in the _first stage memory section
nmos2 _n , nmos2 _n-1 Second switching NMOS transistor in the second stage memory section
inv1 _n , inv1 _n-1 first inverter in the _first stage storage unit
inv2 _n , inv2 _n-1 second inverter in the second stage storage
nmos3 _n , nmos3 _n-1 Third switching NMOS transistor in the second stage memory section
pmos1 _n , pmos1 _n-1 first switching PMOS transistors CL _n , CL _{n-1 in the} second-stage storage unit holding capacitors PE _n , PE _n-1 pixel electrodes VSR1, VSR2 in the vertical direction Shift register

Claims (4)

Each of the plurality of pixels that are arranged in a two-dimensional matrix in the row direction and the column direction and constitute the image display unit,
A first-stage storage unit configured to sample pixel data supplied at the time of writing by the first switching element and store the sampled data in the first memory;
A second-stage storage unit configured to temporarily store, in a second memory, the pixel data read from the first memory of the first-stage storage unit through a second switching element that is controlled to be turned on at the time of reading;
A liquid crystal is filled and sealed between the pixel electrode and the common electrode arranged opposite to each other, and the pixel data stored in the second memory of the second-stage storage unit is applied to the pixel electrode to display an image. A liquid crystal display element for performing
The output terminal of the first stage storage unit in one of the two adjacent pixels among the plurality of pixels arranged in the same column is the input terminal of the first switching element of the first stage storage unit in the other pixel. A shift register for each column configured by repeating in one direction from one to the other of each pixel in the bottom row and each pixel in the top row, and
The pixel data to be displayed is supplied to and stored in the first-stage storage unit of the pixel in the lowermost row or the uppermost row constituting the first stage of the shift register for each column, and the stored pixel data is shifted for each column. And a shift register control means for shifting to the final stage of the register in synchronization with the shift clock.   The first-stage storage unit is a self-holding type in which the first switching element is a switching transistor, and the first memory is a single inverter or two inverters whose output terminals are connected to each other's input terminals. 2. The liquid crystal display device according to claim 1, wherein the liquid crystal display device is a memory.   3. The liquid crystal display device according to claim 1, wherein in the second-stage storage unit, the second switching element is a switching transistor or a transmission gate, and the second memory is an inverter or a capacitor. The shift clock includes first and second shift clocks having opposite logic values,
The shift register control means performs writing to the first stage of the shift register for each column and shifting of the odd-numbered storage pixel data to the adjacent even-numbered stage by the first shift clock, and by the second shift clock. Shifting the even-numbered storage pixel data of the even-numbered stages of the shift register for each column to adjacent odd-numbered stages,
Pixel data for outputting the normal pixel data indicating the original logical value of the binary pixel data and the inverted pixel data indicating the reverse logical value alternately as the pixel data to be displayed every cycle of the first shift clock 4. The liquid crystal display device according to claim 1, further comprising generating means.

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