JP2014130219A - Liquid crystal display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a liquid crystal display device with a downsized configuration.SOLUTION: The liquid crystal display device comprises: a holding section 161 that samples and holds a gradation voltage outputted from a gradation voltage selection circuit 14 via a column data line V, in accordance with a row selection signal outputted from a vertical scan circuit 12 via a row scan line G; an output section 162 that outputs a pixel driving voltage according to the gradation voltage held by the holding section 161; a pixel section 164 that drives a liquid crystal LC in accordance with a potential difference between the pixel driving voltage outputted from the output section 162 and applied to a pixel electrode PE and a voltage applied to a common electrode CE; and an application control section 163 that applies the pixel driving voltage to the pixel electrode and controls the pixel electrode, selectively.

Description

  The present invention relates to a liquid crystal display device that displays an image by alternating-current driving a liquid crystal element.

  Conventionally, as this type of technology, for example, one described in Patent Document 1 shown below is known. In this document, a liquid crystal element is AC driven by repeating an operation of alternately writing a positive pixel signal and a negative pixel signal to a pixel drive electrode and an operation of reading (displaying) the written pixel signal. A liquid crystal display device is described. This apparatus has two data lines for one liquid crystal element. The apparatus also includes two lines of writing circuits for writing pixel signals corresponding to two lines of data lines, and two lines of reading circuits.

  The positive pixel signal is written into the liquid crystal element using the data line and the writing circuit of one system. The written pixel signal is read and displayed on the liquid crystal element by the readout circuit of one system. The negative pixel signal is written into the liquid crystal element by using the data line of the other system and the writing circuit. The written pixel signal is read and displayed on the liquid crystal element by the readout circuit of the other system.

JP 2009-223289 A

  In the above conventional technique, two lines of data lines, two lines of writing circuits and reading circuits are required for one liquid crystal element in order to AC drive the liquid crystal element. For this reason, the problem that the structure enlarges was invited.

  An object of the present invention is to provide a liquid crystal display device with a reduced size.

  In the present invention, a pixel circuit (16) is arranged at each of a plurality of intersections where a plurality of column data lines (V) and a plurality of row scanning lines (G) intersect, and each frame is divided into one frame period. It is composed of a plurality of sub-frames having a display period that is a short time, and the pixel circuit is driven by a plurality of pixel driving voltages in accordance with the gradation to display each sub-frame to display an image of one frame. A display unit (11) that performs display in a combination of subframes corresponding to gradations, a vertical scanning circuit (12) that sequentially outputs a row selection signal for selecting the plurality of row scanning lines, and the plurality of columns A horizontal scanning circuit (13) for outputting a gradation voltage selection signal for selecting a gradation voltage corresponding to each of the data lines, and a plurality of gradations based on the gradation voltage selection signal output from the horizontal scanning circuit Alternative voltage And a gradation voltage selection circuit (14) for selecting and outputting the selected gradation voltage to the corresponding column data line, and the pixel circuit outputs from the vertical scanning circuit via the corresponding row scanning line. A holding unit (161) for sampling and holding the grayscale voltage output from the grayscale voltage selection circuit via the corresponding column data line in response to the row selection signal, and the holding unit An output unit (162) that outputs a pixel drive voltage corresponding to the gradation voltage, a pixel drive voltage that is output from the output unit and applied to the pixel electrode (PE), and a voltage that is applied to the common electrode (CE) A liquid crystal display device comprising: a pixel portion (164) that drives a liquid crystal according to a potential difference between the pixel electrode and an application control unit (163) that selectively applies and controls a pixel driving voltage to the pixel electrode. To do.

  According to the liquid crystal display device of the present invention, it is possible to reduce the size of the entire device by reducing the size of the pixel circuit.

It is a figure which shows the whole structure of the liquid crystal display device which concerns on 1st Embodiment of this invention. It is a figure which shows one circuit structure of a pixel circuit. It is a figure which shows the input-output characteristic of a source follower circuit. 3 is a timing chart for explaining an example of a driving method of the liquid crystal display device according to the first embodiment of the present invention. 5 is a timing chart showing detailed timings of FIGS. 4B, 4C, and 4D.

  Hereinafter, embodiments for carrying out the present invention will be described with reference to the drawings.

(First embodiment)
With reference to FIG. 1, the structure of the liquid crystal display device which concerns on 1st Embodiment of this invention is demonstrated. 1, the liquid crystal display device includes a display unit 11, a vertical scanning circuit 12, a horizontal scanning circuit 13, a gradation voltage selection circuit 14, a control signal generation circuit 15, and a pixel circuit 16.

  The display unit 11 includes a plurality (m × n) of pixels arranged in a matrix at each intersection of the m column data lines V (V1 to Vm) and the n row scanning lines G (G1 to Gn). A pixel circuit 16 is provided. The display unit 11 configures each frame of the image signal to be displayed by a plurality of subframes having a display period shorter than one frame period. Each subframe is composed of a first half and a second half.

  The display unit 11 drives the pixel circuit 16 with a plurality of pixel drive voltages in accordance with the grayscale at which each subframe is to be displayed. As a result, an image is displayed with a combination of sub-frames corresponding to the gradation in which an image of one frame is to be displayed.

  The vertical scanning circuit 12 is connected to each row scanning line G1 to Gn. Based on the vertical scanning start signal and the vertical scanning clock signal, the vertical scanning circuit 12 sequentially supplies row selection signals to, for example, the row scanning lines G1 to Gn to the row scanning lines G1 to Gn, and the row scanning lines G1 to Gn. Gn is selected sequentially.

  The horizontal scanning circuit 13 is connected to each column data line V1 to Vm. The horizontal scanning circuit 13 outputs a gradation voltage selection signal SV (SV1 to SVm) for selecting a gradation voltage corresponding to each column data line V1 to Vm.

  The horizontal scanning circuit 13 includes a shift register circuit 131, a latch circuit 132, and a decoder 133.

  The shift register circuit 131 sequentially shifts and inputs selection data based on the shift clock signal. The selection data is composed of 2-bit data for selecting four gradation voltages Vp (Vp1 to Vp4), and is provided corresponding to each column data line V1 to Vm. The shift register circuit 131 inputs 2-bit selection data corresponding to each of the column data lines V1 to Vm for m column data lines V1 to Vm. That is, the shift register circuit 131 inputs selection data corresponding to each of the m pixel circuits 16 connected to one row scanning line G in one shift input.

  The latch circuit 132 collectively latches and holds the selection data input to the shift register circuit 131 based on the latch signal.

  The decoder 133 decodes the 2-bit selection data latched by the latch circuit 132, and generates a gradation voltage selection signal SV corresponding to each column data line V1 to Vm. The decoder 133 outputs the generated gradation voltage selection signal SV to the gradation voltage selection circuit 14.

  The gradation voltage selection circuit 14 includes a plurality of switch circuits SW (SW1 to SWm). The switch circuits SW1 to SWm are provided in one-to-one correspondence with the column data lines V1 to Vm. Four gradation voltages Vp (Vp1 to Vp4) having different voltage values are input to each switch circuit SW from the outside. The magnitude relationship of the voltages of the four gradation voltages Vp1 to Vp4 is set to satisfy, for example, 0 <Vp1 <Vp2 <Vp3 <Vp4 ≦ VDD (power supply voltage). Each switch circuit SW selects one of the four gradation voltages Vp based on the corresponding gradation voltage selection signal SV. Each switch circuit SW outputs the selected gradation voltage Vp to the corresponding column data line V.

  Of the switch circuits SW, for example, the switch circuit SW1 is representative, the switch circuit SW1 is supplied with four gradation voltages Vp1 to Vp4 at its input, and its output is connected to the column data line V1. The switch circuit SW1 selects any one of the four gradation voltages Vp1 to Vp4 based on the gradation voltage selection signal SV1, and outputs the selected gradation voltage Vp to the column data line V1. To do.

  For example, when the 2-bit selection data is “00”, the gradation voltage Vp1 is selected. When the selection data is “01”, the gradation voltage Vp2 is selected. When the selection data is “10”, the gradation voltage Vp3 is selected. When the selection data is “11”, the gradation voltage Vp4 is selected.

  The control signal generation circuit 15 is connected to n application control signal lines SL (SL1 to SLn) and n constant current setting signal lines CurL (CurL1 to CurLn).

  The n application control signal lines SL1 to SLn are provided in one-to-one correspondence with the n row scanning lines G1 to Gn. Each of the application control signal lines SL1 to SLn is commonly connected to the m pixel circuits 16 connected to the corresponding row scanning lines G1 to Gn. For example, the application control signal line SL1 is commonly connected to the m pixel circuits 16 connected to the row scanning line G1.

  The n constant current setting signal lines CurL1 to CurLn are provided in one-to-one correspondence with the n row scanning lines G1 to Gn. Each constant current setting signal line CurL1 to CurLn is connected in common to m pixel circuits 16 connected to the corresponding row scanning lines G1 to Gn. For example, the constant current setting signal line CurL1 is commonly connected to the m pixel circuits 16 connected to the row scanning line G1.

  The control signal generation circuit 15 receives a generation start signal, a generation clock signal, a constant current command signal, and a drive pixel selection signal, and generates an application control signal S and a constant current setting signal Cur based on these inputs. Output.

  The application control signal S is a signal for controlling whether or not to apply a pixel drive voltage to a pixel electrode PE (described later) of the pixel circuit 16. The constant current setting signal Cur is a signal for determining a constant current value flowing in a source follower circuit described later of the pixel circuit 16. The drive pixel selection signal is a signal for setting the number of rows of the pixel circuits 16 that are driven simultaneously among the n rows of pixel circuits 16 constituting the display unit 11.

  The control signal generation circuit 15 generates the application control signal S based on the generation start signal and the generation clock signal, and outputs the generated application control signal S to the application control signal line SL. The control signal generation circuit 15 generates a constant current setting signal Cur based on the generation start signal, the generation clock signal, and the constant current command signal, and outputs the generated constant current setting signal Cur to the constant current setting signal line CurL. To do. The application control signal S and the constant current setting signal Cur are always output in pairs.

  The control signal generation circuit 15 outputs the generated application control signal S simultaneously to the n application control signal lines SL simultaneously or sequentially one by one based on the drive pixel selection signal. Alternatively, the control signal generation circuit 15 simultaneously outputs the generated application control signal S to the group of k (1 <k <n) application control signal lines SL at the same time based on the drive pixel selection signal. Output sequentially for each group of k application control signal lines SL.

  The control signal generation circuit 15 outputs the generated constant current setting signal Cur to the n constant current setting signal lines CurL simultaneously or sequentially one by one based on the drive pixel selection signal. Alternatively, the control signal generation circuit 15 simultaneously outputs the generated constant current setting signal Cur to the group of k (1 <k <n) constant current setting signal lines CurL simultaneously based on the drive pixel selection signal. Then, it outputs sequentially for each group of k constant current setting signal lines CurL.

  When the application control signal S and the constant current setting signal Cur are collectively output to the corresponding signal lines, all the pixel circuits 16 constituting the display unit 11 are driven simultaneously. When the application control signal S and the constant current setting signal Cur are sequentially output to the corresponding signal lines one by one, the pixel circuit 16 constituting the display unit 11 is sequentially driven row by row in synchronization with each signal. . When the application control signal S and the constant current setting signal Cur are sequentially output to the corresponding signal lines by k lines for each group, the pixel circuit 16 constituting the display unit 11 sequentially sequentially for k rows in synchronization with each signal. Driven.

  The configuration of the pixel circuit 16 having the circuit configuration shown in FIG. 2 will be described as a representative of a plurality of pixel circuits 16 arranged in a matrix. The pixel circuit 16 shown in FIG. 2 intersects any one column data line V among the column data lines V1 to Vm and any one row scanning line G among the row scanning lines G1 to Gn. One pixel circuit arranged in the unit. The pixel circuit 16 includes a holding unit 161, an output unit 162, an application control unit 163, and a pixel unit 164.

  The holding unit 161 samples the gradation voltage output from the gradation voltage selection circuit 14 via the column data line V in accordance with the row selection signal output from the vertical scanning circuit 12 via the row scanning line G. Hold. The holding unit 161 includes a first transistor T1 and a capacitor C. The first transistor T1 is formed of, for example, a MOS type N-channel field effect transistor, and has a gate terminal connected to the row scanning line G and a drain terminal connected to the column data line V. One end of the capacitor C is connected to the source terminal of the first transistor T1, and the other end is grounded.

  In the holding unit 161, when a high-level row selection signal is supplied to the gate terminal of the first transistor T1, the first transistor T1 is turned on. When the first transistor T1 becomes conductive, the holding unit 161 takes in the gradation voltage applied to the column data line V through the first transistor T1. The holding unit 161 holds the fetched gradation voltage in the capacitor C.

  The output unit 162 outputs pixel drive voltages Vo (Vo1 to Vo4) corresponding to the gradation voltages Vp (Vp1 to Vp4) held in the holding unit 161. The output unit 162 includes a second transistor T2 and a third transistor T3. The second transistor T2 is configured by, for example, a MOS type P-channel field effect transistor, the gate terminal is connected to the constant current setting signal line CurL, and the power supply voltage VDD is applied to the source terminal. The third transistor T3 is formed of, for example, a MOS type P-channel field effect transistor. The third transistor T3 has a gate terminal connected to the source terminal of the first transistor T1, a source terminal connected to the drain terminal of the second transistor T2, and a drain terminal grounded.

  The output unit 162 forms a source follower circuit by the second transistor T2 and the third transistor T3. In the source follower circuit, the second transistor T2 constitutes a constant current source, and the third transistor T3 constitutes a drive circuit.

  The second transistor T2 supplies a constant current corresponding to the constant current setting signal Cur supplied to the gate terminal via the constant current setting signal line CurL to the third transistor T3. The value of the constant current supplied to the third transistor T3 can be appropriately set according to the specification of the liquid crystal display device, for example.

  The third transistor T3 is held in the capacitor C and outputs from the source terminal a pixel driving voltage Vo corresponding to the gradation voltage Vp applied to the gate terminal as an input voltage. The pixel drive voltage Vo is approximately a value obtained by adding the absolute value of the threshold voltage of the third transistor T3 to the gradation voltage Vp.

Therefore, the magnitude relationship of the pixel drive voltages Vo1 to Vo4 is, for example, 0 <Vo1 <Vo2 <Vo3 <Vo4 ≦ VDD (power supply voltage).

  Note that the input / output characteristics of the source follower circuit are nonlinear as the input voltages Vp1 to Vp4 increase as the input voltages Vp1 to Vp4 increase, as shown by the solid line in FIG. For this reason, when the output voltages Vo1 to Vo4 are changed linearly, it is necessary to set the input voltage according to the input / output characteristics of the source follower circuit.

  For example, in FIG. 3, when the input voltage is higher than Vp3 and has input / output characteristics indicated by a broken line, the change between the input voltage and the output voltage is almost linear without the output voltage being saturated with respect to the input voltage. Sex is maintained. However, as shown by the solid line in FIG. 3, the actual input / output characteristics saturate the output voltage as the input voltage increases. Therefore, in order to change the output voltages Vo1 to Vo4 linearly, it is necessary to set the input voltage corresponding to the output voltage Vo4 higher than the input voltage having the input / output characteristics indicated by the broken line in FIG.

  The source follower circuit constituting the output unit 162 is configured using a P-channel transistor in the first embodiment, but may be configured using an N-channel transistor instead of the P-channel transistor. In this case, the gate terminal of the N-channel second transistor T2 is connected to the source terminal of the first transistor T1, and the gate terminal of the N-channel third transistor is connected to the constant current setting signal line CurL.

  Returning to FIG. 2, the application control unit 163 selectively controls the pixel drive voltage Vo to be applied to the pixel electrode PE of the pixel unit 164. The application control unit 163 includes a fourth transistor T4. The fourth transistor T4 is formed of, for example, a MOS type N-channel field effect transistor.

  The fourth transistor T4 has a gate terminal connected to the application control signal line SL, a drain terminal connected to the output of the source follower circuit, that is, a source terminal of the third transistor T3, and a source terminal connected to the pixel electrode PE of the pixel portion 164. It is connected. The application control unit 163 applies the pixel drive voltage Vo output from the output unit 162 to the pixel electrode PE when the application control signal S of a high level is supplied to the gate terminal of the fourth transistor T4 and the fourth transistor T4 becomes conductive. To give.

  The pixel unit 164 is driven according to the absolute value of the potential difference between the pixel drive voltage Vo output from the output unit 162 and the common pixel voltage VC for each subframe, and performs gradation display. The pixel unit 164 includes a pixel electrode PE connected to the source terminal of the fourth transistor T4, a common electrode CE that is spaced from and opposed to the pixel electrode PE, and a liquid crystal LC. The liquid crystal LC is filled and sealed between the pixel electrode PE and the common electrode CE. The pixel drive voltage Vo is applied to the pixel electrode PE, and the common pixel voltage VC is applied to the common electrode CE.

  Next, an example of a driving method including a writing operation and a reading (display) operation of the pixel circuit 16 of the liquid crystal display device according to the first embodiment will be described with reference to timing charts of FIGS.

  4, (a) of FIG. 4 schematically shows writing and reading (display) with respect to all the pixel circuits 16 of the display unit 11, where the hatched portion indicates writing, and the lower horizontal line portion following the hatched portion. Indicates reading (display).

  B0, B1, B2, B3, and B4 in FIG. 4A indicate subframes, respectively, and five subframes B0, B1, B2, B3, and B4 constitute one frame. Each subframe B0, B1, B2, B3, B4 is divided into a first half subframe bB0, bB1, bB2, bB3, bB4 and a second half subframe nB0, nB1, nB2, nB3, nB4. The periods of the subframes B0 to B4 are the same, and the periods of the first half and the second half of the subframes B0 to B4 are the same.

  TbB0, TbB1, TbB2, TbB3, and TbB4 attached to the horizontal lines in FIG. 4A indicate the display periods of the first half subframes bB0, bB1, bB2, bB3, and bB4, respectively. TnB0, TnB1, TnB2, TnB3, and TnB4 attached to the horizontal line portion in FIG. 4A indicate the display periods of the second half subframes nB0, nB1, nB2, nB3, and nB4, respectively.

  First, a write operation and a read operation in subframes B1, B2, B3, and B4 will be described in order from subframe B0. In the following description, it is assumed that n row scanning lines G1 to Gn are sequentially scanned from the row scanning lines G1 to Gn. Note that the same operation can be performed even if scanning is sequentially performed from the row scanning lines Gn to G1.

  The subframe B0 is written in the first half subframe bB0, and then in the second half subframe nB0. In the first half subframe bB0, selection data for selecting the gradation voltage Vp of each pixel circuit 16 connected to the row scanning line G1 is input to the shift register circuit 131 and latched by the latch circuit 132. The selection data latched by the latch circuit 132 is decoded by the decoder 133, and the gradation voltage selection signal SV is generated.

  The generated gradation voltage selection signal SV is supplied to the corresponding switch circuit SW of the gradation voltage selection circuit 14. Thereby, in each switch circuit SW, one of the four gradation voltages Vp1 to Vp4 is selected based on the gradation voltage selection signal SV. Each selected gradation voltage Vp is applied to each column data line V connected to the switch circuit SW that has selected the gradation voltage Vp.

  The gradation voltages Vp applied to the column data lines V1 to Vm are at the timings shown in FIGS. 4B and 5A. That is, at time t1 in FIG. 5, any one of the gradation voltages Vp1 to Vp4 selected according to the gradation voltage selection signal SV is applied to each column data line V1 to Vm. Given.

  Thereafter, as shown in FIG. 4C and FIG. 5B, during the period from time t2 to time t3 after time t1, the vertical scanning circuit 12 passes the high level (for example, the power supply voltage VDD) via the row scanning line G1. ) Row selection signal is output. This row selection signal is supplied in common to the m pixel circuits 16 connected to the row scanning line G1, and these pixel circuits 16 are selected.

  Thereby, in the pixel circuit 16, the first transistor T1 is turned on. The gradation voltage Vp supplied from the column data line V is given to the capacitor C through the first transistor T1 in a conductive state. Thereafter, as shown in FIG. 5B, when the row selection signal shifts from the high level to the low level at time t3 and the first transistor T1 is turned off, the gradation voltage Vp is held in the capacitor C. . The writing operation of the gradation voltage Vp for the row scanning line G1 is simultaneously performed by the m pixel circuits 16 connected to the row scanning line G1.

  When the writing operation of the gradation voltage Vp is completed for the m pixel circuits 16 connected to the row scanning line G1, the gradation voltage Vp is continuously applied to the m pixel circuits 16 connected to the row scanning line G2. The write operation is performed. In this writing operation, selection data for selecting the gradation voltage Vp written to each pixel circuit 16 connected to the row scanning line G2 is input, and the row scanning line G2 is selected, except that the row scanning line G2 is selected. This is performed in the same manner as the writing operation for the pixel circuit 16.

  In this manner, the writing operation of the gradation voltage Vp is performed on each pixel circuit 16 connected to all n row scanning lines G1 to Gn. Accordingly, the gradation voltage Vp corresponding to the subframe bB0 in the first half of the subframe B0 is written and held in all the pixel circuits 16 of the display unit 11. That is, in all the pixel circuits 16 of the display unit 11, any one of the four gradation voltages Vp1 to Vp4 is written individually and independently.

  Next, the process proceeds to a read (display) operation in the first half subframe bB0. In the following description, it is assumed that readout operations are performed simultaneously from all the pixel circuits 16 of the display unit 11. As described in the description of the application control signal S and the constant current setting signal Cur, each row of pixel circuits 16 connected to one row scanning line G or a plurality of row scanning lines. It is also possible to sequentially perform a read operation for each of the plurality of rows of pixel circuits 16 connected to G.

  In the read operation, first, as shown in FIGS. 4D and 5C, the application control signal S at the high level (for example, the power supply voltage VDD) is applied to the application control signal line SL during the period from time t4 to time t5. Is output. As shown in FIGS. 4D and 5D, the constant current setting signal Cur is output to the constant current setting signal line CurL during the period from time t4 to time t5.

  The voltage value of the constant current setting signal Cur is set according to the characteristics and size of the second transistor T2 so that the second transistor T2 of the pixel circuit 16 can supply a preset constant current. Since the second transistor T2 is configured by the P channel, the voltage value of the constant current setting signal Cur is set to a value lower than the value obtained by subtracting the absolute value of the threshold value Vt of the P channel transistor from the power supply voltage VDD. Is set.

  The application control signal S output to the application control signal line SL is applied to the gate terminal of the fourth transistor T4 of the pixel circuit 16, and the fourth transistor T4 becomes conductive. At the same time, the constant current setting signal Cur output to the constant current setting signal line CurL is applied to the gate terminal of the second transistor T2 of the pixel circuit 16. Thus, the second transistor T2 supplies a constant current corresponding to the voltage value of the applied constant current setting signal Cur to the second transistor T2.

  As a result, the source follower circuit of the output unit 162 is driven. As a result, a pixel drive voltage Vo having a voltage value corresponding to the gradation voltage Vp held in the capacitor C of the pixel circuit 16 is output from the source follower circuit. The pixel drive voltage Vo output from the source follower circuit is applied to the pixel electrode PE of the pixel portion 164 via the conductive fourth transistor T4.

  Thereafter, as shown in FIGS. 5C and 5D, at time t5, the application control signal S shifts to a low level (eg, ground potential), and the constant current setting signal Cur shifts to the power supply voltage VDD. As a result, the source follower circuit is in a non-driven state, and the fourth transistor T4 is in a non-conductive state.

  On the other hand, common pixel voltages VC (VCc, VCd) having opposite polarities in the first half and the second half of the subframe are alternately applied to the common electrode CE of the pixel portion 164. As shown in FIG. 4F, the common pixel voltage VCc is applied in the display period of the first half subframe bB0 (the period of the horizontal line portion indicated by TbB0 in FIG. 4A). Further, as shown in FIG. 4F, the same applies to the display periods of the subframes bB1 to bB4 in the first half of the subframes B1 to B4.

  On the other hand, as shown in FIG. 4F, the common pixel voltage VCd is applied in the display period of the second half subframe nB0 (the period of the horizontal line portion indicated by TnB0 in FIG. 4A). The same applies to the display periods of the subframes nB1 to nB4 in the latter half of each of the subframes B1 to B4 as shown in FIG.

  Here, the relationship between the pixel drive voltages Vo1 to Vo4 and the common pixel voltages VCc and VCd and the display color of the liquid crystal LC will be described.

The magnitude relationship between the pixel drive voltages Vo1 to Vo4 is set to Vo1 <Vo2 <Vo3 <Vo4. The magnitude relationship between the common pixel voltages VCc and VCd is set to VCc <VCd. In such a magnitude relationship, the common pixel voltage VCc is set to be approximately the same as the pixel drive voltage Vo1. Therefore, when the pixel drive voltage Vo1 is applied to the pixel electrode PE and the common pixel voltage VCc is applied to the common electrode CE, there is almost no potential difference across the liquid crystal LC, and the liquid crystal LC displays black.

  The common pixel voltage VCd is set to be substantially the same as the pixel drive voltage Vo4. Therefore, when the pixel drive voltage Vo4 is applied to the pixel electrode PE and the common pixel voltage VCd is applied to the common electrode CE, the liquid crystal LC displays black as described above.

  When the pixel drive voltage Vo4 and the common pixel voltage VCc, or the pixel drive voltage Vo1 and the common pixel voltage VCd are applied to both ends of the liquid crystal LC, the liquid crystal LC displays white. Accordingly, the voltage difference between the pixel drive voltages Vo1 and Vo4 is set so that white is displayed on the liquid crystal LC when both voltages are applied to the liquid crystal LC.

  The absolute value of the difference between the pixel drive voltage Vo2 and the common pixel voltage VCc and the absolute value of the difference between the pixel drive voltage Vo3 and the common pixel voltage VCd are set to be substantially the same. Thereby, the absolute value of the difference between the pixel drive voltage Vo2 and the common pixel voltage VCd and the absolute value of the difference between the pixel drive voltage Vo3 and the common pixel voltage VCc are substantially the same. Also, the absolute value of the difference between the pixel drive voltage Vo2 and the common pixel voltage VCc (= the absolute value of the difference between the pixel drive voltage Vo3 and the common pixel voltage VCd) <the absolute value of the difference between the pixel drive voltage Vo2 and the common pixel voltage VCd. Value (= the absolute value of the difference between the pixel drive voltage Vo3 and the common pixel voltage VCc).

  Because of such a voltage magnitude relationship, when the potential difference of the absolute value of the difference between the pixel drive voltage Vo2 and the common pixel voltage VCc is given to both ends of the liquid crystal LC, the liquid crystal LC is on the black side between white and black. A dark gray close to is displayed. Similarly, when the potential difference of the absolute value of the difference between the pixel drive voltage Vo3 and the common pixel voltage VCd is given to both ends of the liquid crystal LC, the liquid crystal LC displays dark gray.

  On the other hand, when the potential difference of the absolute value of the difference between the pixel drive voltage Vo2 and the common pixel voltage VCd is given to both ends of the liquid crystal LC, the liquid crystal LC displays a light gray near the white side between white and black. . Similarly, when the potential difference of the absolute value of the difference between the pixel drive voltage Vo3 and the common pixel voltage VCc is given to both ends of the liquid crystal LC, the liquid crystal LC displays light gray.

  As described above, the pixel unit 164 performs display with gradation according to the absolute value of the potential difference between the pixel drive voltage of the pixel electrode PE and the common pixel voltage VC of the common electrode CE applied to both ends of the liquid crystal LC.

  Here, in describing an example of gradation display, as shown in FIGS. 4B and 4C, for example, the column data line Vi (1 ≦ i ≦ m) and the row scanning line Gj (1 ≦ j ≦ m). The pixel circuit 16 connected to () is a pixel circuit of interest. Assume that, for example, a pixel drive voltage Vo4 is applied to the pixel electrode PE of the pixel circuit 16 of interest in the first half of the subframe B0, as shown in FIG. On the other hand, the common pixel voltage VCc is applied to the common electrode CE as described above.

  Thereby, in the sub-frame bB0 in the first half of the sub-frame B0, as shown in FIG. 4G, the difference voltage (Vo4-VCc) between the pixel drive voltage Vo4 and the common pixel voltage VCc is present at both ends of the liquid crystal LC. An absolute value of the potential difference is applied. As a result, the pixel circuit 16 of interest displays white as described above.

  In this way, in the first half subframe bB0 of the subframe B0, the writing operation and the reading operation are performed on all the pixel circuits 16 of the display unit 11, and gradation display is performed in each pixel circuit 16. .

  Subsequently, the write operation and the read (display) operation of the subframe nB0 in the latter half of the subframe B0 are sequentially performed. The write operation of the second half subframe nB0 is performed in the same manner as the write operation of the first half subframe bB0. The writing operation of the second half subframe nB0 is performed within the display period TbB0 of the first half subframe bB0 after the application control signal S shifts to the low level and the constant current setting signal Cur shifts to the high level.

  The read operation in the second half subframe nB0 of the subframe B0 is performed in the same manner as the read operation in the first half subframe bB0. In the readout operation in the subframe nB0, the pixel drive voltage Vo1 is applied to the pixel electrode PE of the pixel circuit 16 of interest as shown in FIG. On the other hand, the common pixel voltage VCd is applied to the common electrode CE as described above.

  As a result, in the second half subframe nB0, the absolute value of the difference voltage (Vo1−VCd) between the pixel drive voltage Vo1 and the common pixel voltage VCd is shown at both ends of the liquid crystal LC as shown in FIG. A potential difference is applied. As a result, the pixel circuit 16 of interest displays white as described above in the second half subframe nB0.

  Therefore, in the subframe B0, the pixel circuit 16 of interest displays white.

  Further, as shown in FIG. 4G, the voltage applied to the liquid crystal LC is reversed between the first half subframe bB0 and the second half subframe nB0. That is, the pixel electrode PE side is higher in the first half, while the common electrode CE side is higher in the second half. Thereby, in the sub-frame B0, the liquid crystal LC is AC driven, and the burn-in of the liquid crystal LC can be suppressed.

  Next, the write operation and the read (display) operation of the subframe bB1 in the first half of the subframe B1 are sequentially performed. The write operation of the first half subframe bB1 is performed in the same manner as the write operation of the second half subframe nB0 of the previous subframe B0. The write operation of the first half subframe bB1 is performed within the display period TnB0 of the second half subframe nB0 of the previous subframe B0 after the application control signal S shifts to the low level and the constant current setting signal Cur shifts to the high level. Done.

  The read operation in the first half subframe bB1 of the subframe B1 is performed in the same manner as the read operation in the second half subframe nB0 of the previous subframe B0. In the readout operation in the subframe bB1, it is assumed that, for example, a pixel drive voltage Vo2 is applied to the pixel electrode PE of the pixel circuit 16 of interest as shown in FIG. On the other hand, the common pixel voltage VCc is applied to the common electrode CE as described above.

  As a result, in the first half subframe bB1, the absolute value of the difference voltage (Vo2−VCc) between the pixel drive voltage Vo2 and the common pixel voltage VCc is formed at both ends of the liquid crystal LC as shown in FIG. A potential difference is applied. As a result, the pixel circuit 16 of interest displays dark gray as described above in the first half sub-frame bB1.

  Subsequently, the write operation and the read (display) operation of the subframe nB1 in the latter half of the subframe B1 are sequentially performed. The write operation of the second half subframe nB1 is performed in the same manner as the write operation of the previous first half as described above. The write operation of the subframe nB1 is performed within the display period TbB1 of the first half subframe bB1 after the application control signal S shifts to the low level and the constant current setting signal Cur shifts to the high level.

  The read operation in the subframe nB1 in the latter half of the subframe B1 is performed in the same manner as the read operation in the subframe bB1 in the previous first half. In the read operation in the subframe nB1, the pixel drive voltage Vo3 is applied to the pixel electrode PE of the pixel circuit 16 of interest as shown in FIG. On the other hand, the common pixel voltage VCd is applied to the common electrode CE as described above.

  As a result, in the second half subframe bB1, the absolute value of the difference voltage (Vo3-VCd) between the pixel drive voltage Vo3 and the common pixel voltage VCd is shown at both ends of the liquid crystal LC as shown in FIG. A potential difference is applied. As a result, the pixel circuit 16 of interest displays dark gray as described above in the second subframe nB1.

  Therefore, in the subframe B1, the pixel circuit 16 of interest displays dark gray.

  Further, as shown in FIG. 4G, the level of the voltage applied to the liquid crystal LC is reversed between the first half subframe bB1 and the second half subframe nB1. That is, the pixel electrode PE side is higher in the first half, while the common electrode CE side is higher in the second half. Thereby, in the sub-frame B1, the liquid crystal LC is AC driven, and the burn-in of the liquid crystal LC can be suppressed.

  Next, the write operation and the read (display) operation of the subframe bB2 in the first half of the subframe B2 are sequentially performed. The write operation of the first half subframe bB2 is performed in the same manner as the write operation of the second half subframe nB1 of the previous subframe B1. The writing operation of the subframe bB2 is performed within the display period TnB1 of the subframe nB1 in the second half of the previous subframe B1 after the application control signal S shifts to the low level and the constant current setting signal Cur shifts to the high level.

  The read operation in the first half subframe bB2 of the subframe B2 is performed in the same manner as the read operation in the second half subframe nB1 of the previous subframe B1. In the readout operation in the subframe bB2, it is assumed that, for example, a pixel drive voltage Vo3 is applied to the pixel electrode PE of the pixel circuit 16 of interest as shown in FIG. On the other hand, the common pixel voltage VCc is applied to the common electrode CE as described above.

  As a result, in the first half subframe bB2, the absolute value of the difference voltage (Vo3-VCc) between the pixel drive voltage Vo3 and the common pixel voltage VCc is formed at both ends of the liquid crystal LC as shown in FIG. A potential difference is applied. As a result, the pixel circuit 16 of interest displays light gray as described above in the first half subframe bB2.

  Subsequently, the write operation and the read (display) operation of the subframe nB2 in the latter half of the subframe B2 are sequentially performed. As described above, the write operation of the second half subframe nB2 is performed in the same manner as the previous first half write operation. The write operation of the subframe nB2 is performed within the display period TbB2 of the first half subframe bB2 after the application control signal S shifts to the low level and the constant current setting signal Cur shifts to the high level.

  The read operation in the second half subframe nB2 of the subframe B2 is performed in the same manner as the read operation in the first half subframe bB2 of the previous subframe B2. In the readout operation in the subframe nB2, the pixel drive voltage Vo2 is applied to the pixel electrode PE of the pixel circuit 16 of interest as shown in FIG. On the other hand, the common pixel voltage VCd is applied to the common electrode CE as described above.

  As a result, in the second half subframe nB2, as shown in FIG. 4G, the absolute value of the difference voltage (Vo2-VCd) between the pixel drive voltage Vo2 and the common pixel voltage VCd is provided at both ends of the liquid crystal LC. A potential difference is applied. As a result, the pixel circuit 16 of interest displays light gray as described above in the second subframe nB2.

  Therefore, in the subframe B2, the pixel circuit 16 of interest displays light gray.

  Further, as shown in FIG. 4G, the level of the voltage applied to the liquid crystal LC is reversed between the first half subframe bB2 and the second half subframe nB2. That is, the pixel electrode PE side is higher in the first half, while the common electrode CE side is higher in the second half. Thereby, in the sub-frame B2, the liquid crystal LC is AC driven, and the burn-in of the liquid crystal LC can be suppressed.

  Next, the write operation and the read (display) operation of the subframe bB3 in the first half of the subframe B3 are sequentially performed. The write operation of the first half subframe bB3 is performed in the same manner as the write operation of the second half subframe nB2 of the previous subframe B2. The write operation of the first half subframe bB3 is performed within the display period TnB2 of the second half subframe nB2 of the previous subframe B2 after the application control signal S shifts to the low level and the constant current setting signal Cur shifts to the high level. Done.

  The read operation in the first half subframe bB3 of the subframe B3 is performed in the same manner as the read operation in the second half subframe nB2 of the previous subframe B2. In the readout operation in the subframe bB3, for example, the pixel drive voltage Vo1 is applied to the pixel electrode PE of the pixel circuit 16 of interest as shown in FIG. On the other hand, the common pixel voltage VCc is applied to the common electrode CE as described above.

  As a result, in the first half subframe bB3, the absolute value of the difference voltage (Vo1−VCc) between the pixel drive voltage Vo1 and the common pixel voltage VCc is formed at both ends of the liquid crystal LC as shown in FIG. A potential difference is applied. As a result, the pixel circuit 16 of interest displays black in the first half subframe bB3 as described above.

  Subsequently, the write operation and the read (display) operation of the subframe nB3 in the latter half of the subframe B3 are sequentially performed. As described above, the write operation of the second half subframe nB3 is performed in the same manner as the previous first half write operation. The write operation of the subframe nB3 is performed within the display period TbB3 of the first half subframe bB3 after the application control signal S shifts to the low level and the constant current setting signal Cur shifts to the high level.

  The read operation in the second half subframe nB3 of the subframe B3 is performed in the same manner as the read operation in the first half subframe bB3 of the previous subframe B3. In the reading operation in the subframe nB3, the pixel drive voltage Vo4 is applied to the pixel electrode PE of the pixel circuit 16 of interest as shown in FIG. On the other hand, the common pixel voltage VCd is applied to the common electrode CE as described above.

  As a result, in the second half subframe nB3, the absolute value of the difference voltage (Vo4-VCd) between the pixel drive voltage Vo4 and the common pixel voltage VCd is provided at both ends of the liquid crystal LC as shown in FIG. A potential difference is applied. As a result, the pixel circuit 16 of interest displays black in the second half subframe nB3 as described above.

  Therefore, in the subframe B3, the pixel circuit 16 of interest displays black.

  Further, as shown in FIG. 4G, the level of the voltage applied to the liquid crystal LC is reversed between the first half subframe bB3 and the second half subframe nB3. That is, the pixel electrode PE side is higher in the first half, while the common electrode CE side is higher in the second half. Thereby, in the sub-frame B3, the liquid crystal LC is AC driven, and the burn-in of the liquid crystal LC can be suppressed.

  Next, the write operation and the read (display) operation of the subframe bB4 in the first half of the subframe B4 are sequentially performed. The write operation of the first half subframe bB4 is performed in the same manner as the write operation of the second half subframe nB3 of the previous subframe B3. The write operation of the first half subframe bB4 is performed within the display period TnB3 of the second half subframe nB3 of the previous subframe B3 after the application control signal S shifts to the low level and the constant current setting signal Cur shifts to the high level. Done.

  The read operation in the first half subframe bB4 of the subframe B4 is performed in the same manner as the read operation in the second half subframe nB3 of the previous subframe B3. In the readout operation in the subframe bB4, for example, the pixel drive voltage Vo2 is applied to the pixel electrode PE of the pixel circuit 16 of interest as shown in FIG. On the other hand, the common pixel voltage VCc is applied to the common electrode CE as described above.

  As a result, in the first half subframe bB4, the absolute value of the difference voltage (Vo2−VCc) between the pixel drive voltage Vo2 and the common pixel voltage VCc is formed at both ends of the liquid crystal LC as shown in FIG. A potential difference is applied. As a result, the pixel circuit 16 of interest displays dark gray as described above in the first half subframe bB4.

  Subsequently, the write operation and the read (display) operation of the subframe nB4 in the latter half of the subframe B4 are sequentially performed. The write operation of the second half subframe nB4 is performed in the same manner as the previous first half write operation, as described above. The writing operation of the subframe nB4 is performed within the display period TbB4 of the first half subframe bB4 after the application control signal S shifts to the low level and the constant current setting signal Cur shifts to the high level.

  The read operation in the second half subframe nB4 of the subframe B4 is performed in the same manner as the read operation in the first half subframe bB4 of the previous subframe B4. In the readout operation in the subframe nB4, the pixel drive voltage Vo3 is applied to the pixel electrode PE of the pixel circuit 16 of interest as shown in FIG. On the other hand, the common pixel voltage VCd is applied to the common electrode CE as described above.

  As a result, in the second half subframe nB4, the absolute value of the difference voltage (Vo3-VCd) between the pixel drive voltage Vo3 and the common pixel voltage VCd is shown at both ends of the liquid crystal LC as shown in FIG. A potential difference is applied. As a result, the pixel circuit 16 of interest displays dark gray as described above in the second subframe nB4.

  Therefore, in the subframe B4, the pixel circuit 16 of interest displays dark gray.

  Further, as shown in FIG. 4G, the level of the voltage applied to the liquid crystal LC is reversed between the first half subframe bB4 and the second half subframe nB4. That is, the pixel electrode PE side is higher in the first half, while the common electrode CE side is higher in the second half. Thereby, in the sub-frame B3, the liquid crystal LC is AC driven, and the burn-in of the liquid crystal LC can be suppressed.

  As described above, the writing operation and the reading operation of the subframes B0 to B4 are sequentially performed, and one frame image composed of five subframes is displayed. In the pixel circuit 16 of interest, white, dark gray, light gray, black, and dark gray are displayed in five subframes in a display period of one frame. As a result, one pixel of one frame is displayed in grayscale with a mixed display color obtained by combining these display colors.

  Therefore, in the liquid crystal display device, in all the pixel circuits 16 constituting the display unit 11, any one display color of white, black, dark gray, and light gray is independently applied to each of the five subframes. To display. Thereby, the liquid crystal display device can display an image of one frame in gradation.

  Note that the number of subframes constituting one frame is not limited to five adopted in the first embodiment, and can be arbitrarily set as appropriate. The periods of the sub-frames B0 to B4 constituting one frame are not limited to the same as those employed in the first embodiment, and may be different for each of the sub-frames B0 to B4, for example.

  The number of gradation voltages Vp is not limited to four employed in the first embodiment, and can be arbitrarily set as appropriate. For example, the number of gradation voltages Vp can be configured by three or more voltages having different voltage values. Therefore, the number of bits of selection data for selecting the gradation voltage Vp is appropriately set according to the gradation voltage Vp.

  As described above, in the first embodiment according to the present invention, the pixel circuit 16 is connected to one row scanning line G and one column data line V, and is connected to one set of holding unit 161 and an output. Part 162. By adopting such a configuration, the liquid crystal display device according to the first embodiment has a pixel circuit compared to a conventional configuration in which two sets of holding units and output units are connected to two column data lines. Can be miniaturized.

  Thereby, the area of the display unit 11 having a large number of pixel circuits 16 can be reduced, and the entire apparatus can be downsized. For example, when the device is integrated, the chip area can be reduced by miniaturizing the display unit 11.

  The pixel circuit 16 includes one row scanning line G and column data line V, four transistors, one capacitor, and liquid crystal LC. By adopting such a configuration, the configuration of the pixel circuit 16 can be reduced to about half compared to the conventional configuration having two sets of holding units and output units connected to two column data lines. Is possible. As a result, the pixel circuit 16 of the first embodiment can be remarkably reduced in size as compared with the conventional configuration.

  The source follower circuit constituting the output unit 162 sets the gradation voltage Vp according to the input / output characteristics of the source follower circuit so that the output pixel drive voltage Vo is linear. As a result, gradation display can be performed faithfully to the gradation voltage Vp, and gradation display with good accuracy can be performed.

  After the gradation voltage is held and written in all the pixel circuits 16 constituting the display unit 11, the liquid crystal LC is driven and displayed by the pixel circuit 16 for each row. By adopting such a configuration, it is possible to suppress the circuits that are activated at a time as compared with the case where the liquid crystal LC of all the pixel circuits 16 of the display unit 11 is collectively driven and displayed. Become. As a result, the power consumption of the apparatus can be reduced.

  On the other hand, after the gradation voltage is held and written in all the pixel circuits 16 constituting the display unit 11, the liquid crystals LC of all the pixel circuits 16 in the display unit 11 are simultaneously driven and displayed. . By adopting such a configuration, the display speed can be increased as compared with the case where the liquid crystal LC is driven and displayed for each row.

  In addition, when the apparatus of the first embodiment is applied to a liquid crystal display device that displays a so-called 3D (three-dimensional) image that provides a viewer with a stereoscopic view on a flat screen, the display image is displayed. Brightness can be improved.

  In a 3D liquid crystal display device, in a line scan method in which liquid crystal is driven and displayed for each row, it is generally necessary to drive the liquid crystal at a quadruple speed. In the quadruple speed display, an image for the left eye is displayed on the screen of the display unit, black is once displayed on the screen, and then an image for the right eye is displayed and black is displayed again.

  On the other hand, when a black image is not sandwiched, a left-eye image and a right-eye image are simultaneously displayed in one frame image, which may cause crosstalk in 3D display. In order to avoid this, a black image is displayed. However, by displaying a black image, the brightness of the display image is reduced by half, and it is difficult to ensure sufficient brightness of the display image.

  On the other hand, in the technique adopted in the first embodiment described above, the image for the left eye and the image for the right eye are mixed in one frame image after the display image has shifted to the next frame. Only the period of the first read operation is set. That is, it is a very short time that the image for the left eye and the image for the right eye are mixed in one frame image. Therefore, there is no possibility of causing crosstalk in 3D display without inserting a black image between the left eye image and the right eye image.

  As a result, the left-eye image and the right-eye image can be displayed alternately, and the brightness of the display screen can be sufficiently secured and improved. As a result, the liquid crystal display device of the first embodiment can be applied to a liquid crystal display device that displays 3D video images without reducing the brightness of the display image.

  Also, when displaying a color image by switching the display in order of red (R), green (R), and blue (B) in the single-plate method, red (R) and green (R) are displayed on the display image of one frame. , Green (R) and blue (B), and blue (B) and red (B) are prevented from being mixed. Thus, when the liquid crystal display device of the first embodiment is applied to a single-plate color liquid crystal display device, a good color image with little color mixture can be obtained.

  In the liquid crystal display device according to the first embodiment, the liquid crystal LC is driven and displayed with a pixel drive voltage corresponding to gradation voltages having a plurality of voltage values of three or more. This reduces the number of write operations and read operations, and the number of subframes when performing similar gradation display, as compared to the conventional configuration in which liquid crystal is driven and displayed with two voltages of positive polarity and negative polarity. It becomes possible. As a result, power consumption can be reduced.

DESCRIPTION OF SYMBOLS 11 ... Display part 12 ... Vertical scanning circuit 13 ... Horizontal scanning circuit 14 ... Gradation voltage selection circuit 15 ... Control signal generation circuit 16 ... Pixel circuit 131 ... Shift register circuit 132 ... Latch circuit 133 ... Decoder 161 ... Holding part 161 ... Output Unit 162 ... Output unit 163 ... Application control unit 164 ... Pixel unit G (G1 to Gn) ... Row scanning line V (V1 to Vm) ... Column data line SW (SW1 to SWm) ... Switch circuit T1 ... First transistor T2 ... Second transistor T3 ... Third transistor T4 ... Fourth transistor LC ... Liquid crystal PE ... Pixel electrode CE ... Common electrode C ... Capacitance

Claims (5)

A pixel circuit is arranged at each of a plurality of intersections where a plurality of column data lines and a plurality of row scanning lines intersect, and each frame is composed of a plurality of subframes having a display period shorter than one frame period. The pixel circuit is driven by a plurality of pixel driving voltages in accordance with gradations for displaying each sub-frame, and display is performed with a combination of sub-frames corresponding to the gradation for displaying one frame image. A display unit;
A vertical scanning circuit for sequentially outputting a row selection signal for selecting the plurality of row scanning lines;
A horizontal scanning circuit for outputting a gradation voltage selection signal for selecting a gradation voltage corresponding to each of the plurality of column data lines;
A gradation voltage selection that selectively selects a plurality of gradation voltages based on a gradation voltage selection signal output from the horizontal scanning circuit and outputs the selected gradation voltages to the corresponding column data lines. A circuit,
The pixel circuit includes:
In accordance with a row selection signal output from the vertical scanning circuit via the corresponding row scanning line, the gradation voltage output from the gradation voltage selection circuit via the corresponding column data line is sampled and held. A holding part;
An output unit that outputs a pixel driving voltage corresponding to the gradation voltage held in the holding unit;
A pixel unit that drives a liquid crystal according to a potential difference between a pixel driving voltage that is output from the output unit and applied to the pixel electrode, and a voltage applied to the common electrode;
An application control unit for selectively applying a pixel drive voltage to the pixel electrode;
A liquid crystal display device comprising: The holding unit includes a first transistor having a gate terminal connected to the row scanning line and a drain terminal connected to the column data line, and a capacitor connected to the source terminal of the first transistor to hold a gradation voltage. And consists of
The output unit includes a third transistor that has a gate terminal connected to one end of the capacitor, and outputs a pixel driving voltage corresponding to a grayscale voltage applied to the gate terminal from a source terminal, and a drain terminal connected to the third transistor. A source follower circuit comprising a second transistor connected to the source terminal and supplying a constant current to the third transistor according to a constant current setting signal applied to the gate terminal;
The application controller includes a fourth transistor that controls application of a pixel driving voltage to the pixel electrode in accordance with an application control signal applied to a gate terminal via a corresponding application control signal line. Item 2. A liquid crystal display device according to item 1. The source follower circuit sets the plurality of gradation voltages so that a plurality of pixel drive voltages output according to the plurality of gradation voltages are linear according to input / output characteristics of the source follower circuit 3. The liquid crystal display device according to claim 1, wherein the liquid crystal display device is a liquid crystal display device. In the pixel circuit, after the gradation voltage is held and written in all the pixel circuits constituting the display unit, the liquid crystal of the pixel circuit is driven and displayed for each row, or two or more rows are displayed. The liquid crystal display device according to claim 1, wherein the liquid crystal display device is driven and displayed at the same time in a lump. 5. The liquid crystal display device according to claim 1, wherein the gradation voltage is composed of three or more voltages having different voltage values.

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