JP2015171182A - 半導体モジュール - Google Patents
半導体モジュール Download PDFInfo
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- JP2015171182A JP2015171182A JP2014042761A JP2014042761A JP2015171182A JP 2015171182 A JP2015171182 A JP 2015171182A JP 2014042761 A JP2014042761 A JP 2014042761A JP 2014042761 A JP2014042761 A JP 2014042761A JP 2015171182 A JP2015171182 A JP 2015171182A
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- semiconductor switch
- terminal
- switch element
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- semiconductor module
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/0601—Structure
- H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
- H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
- H01L2224/49113—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19107—Disposition of discrete passive components off-chip wires
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Abstract
Description
最初に本発明の実施形態を列記して説明する。なお、本明細書において「電気的に接続」とは、2つの要素の直接の接続によって、それら2つの要素の間の電気的伝導が生じる場合に限定されず、2つの要素の間の電気的伝導が、それら2つの要素の間に配置される別の要素を介在して生じる場合を含む。
以下、本発明の実施の形態について図に基づいて説明する。なお、以下の図面において、同一または相当する部分には同一の参照番号を付し、その説明は繰り返さない。
図1は、本発明の一実施形態に係る半導体モジュール100の外形を示した上面図である。図2は、図1に示した半導体モジュール100の内部透視図である。
図5は、実施の形態2に係る半導体モジュールの構成を示した回路図である。図3および図5を参照して、実施の形態2に係る半導体モジュールは、フィルタ70A,70Bが追加される点で、実施の形態1に係る半導体モジュールと異なる。
2A,2B ダイオード素子
3A,3B ダイパッド
4 駆動IC
6A,6B チップ抵抗
7A,7B,8A,8B,9A,9B,10A,10B,10C ワイヤ
11A,11B ゲートパッド
12A,12B ソースパッド
21A,21B アノード電極
31〜36,41〜46,51〜53,T1〜T16 端子
31A,31B,41A,41B 信号配線部
31C,41C 端子部
61A,61B 寄生容量
62 インダクタンス成分
70A,70B フィルタ
71A,71B コンデンサ
72A,72B 抵抗素子
100 半導体モジュール
101 収容部材
CV1,CV2,CV3 曲線。
Claims (6)
- 制御電極を有する半導体スイッチ素子と、
前記半導体スイッチ素子の前記制御電極に、前記半導体スイッチ素子を駆動するための駆動信号を与える駆動回路と、
前記半導体スイッチ素子および前記駆動回路を収容する収容部材と、
前記収容部材の内部から前記収容部材の外部に引出される外部端子とを備え、
前記外部端子は、
前記収容部材の内部に配置されて、前記駆動回路から出力された前記駆動信号を前記半導体スイッチ素子の前記制御電極に伝達する信号配線部と、
前記収容部材の内部において前記信号配線部に電気的に接続されるとともに、前記収容部材の内部から前記収容部材の外部へと引出される端子部とを含む、半導体モジュール。 - 前記半導体モジュールは、
前記収容部材の内部に配置されて、前記駆動回路と、前記半導体スイッチ素子の前記制御電極との間に、前記信号配線部に電気的に直列に接続される第1の抵抗素子をさらに備える、請求項1に記載の半導体モジュール。 - 前記半導体スイッチ素子は、ソース電極をさらに有し、
前記半導体モジュールは、
前記収容部材の内部に配置されて、前記半導体スイッチ素子の前記ソース電極に電気的に接続されるソース配線部と、
前記収容部材の内部に配置されて、前記信号配線部と、前記半導体スイッチ素子の前記制御電極とを電気的に接続するワイヤとをさらに備え、
前記信号配線部は、前記ソース配線部よりも前記半導体スイッチ素子の近くに配置される、請求項1または請求項2に記載の半導体モジュール。 - 前記半導体モジュールは、
前記端子部に電気的に接続されるコンデンサをさらに備える、請求項1〜請求項3のいずれか1項に記載の半導体モジュール。 - 前記半導体モジュールは、
前記端子部に、前記コンデンサと電気的に直列に接続される第2の抵抗素子をさらに備える、請求項4に記載の半導体モジュール。 - 前記半導体スイッチ素子は、炭化珪素半導体素子である、請求項1〜請求項5のいずれか1項に記載の半導体モジュール。
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JP2014042761A JP6379525B2 (ja) | 2014-03-05 | 2014-03-05 | 半導体モジュール |
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JP2015171182A true JP2015171182A (ja) | 2015-09-28 |
JP6379525B2 JP6379525B2 (ja) | 2018-08-29 |
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Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2017168951A1 (ja) * | 2016-03-29 | 2017-10-05 | 三菱電機株式会社 | 過熱保護制御装置 |
WO2018056213A1 (ja) * | 2016-09-23 | 2018-03-29 | 三菱電機株式会社 | 電力用半導体モジュール及び電力用半導体装置 |
WO2019077871A1 (ja) * | 2017-10-19 | 2019-04-25 | 株式会社デンソー | 半導体モジュール |
WO2021044715A1 (ja) * | 2019-09-02 | 2021-03-11 | ローム株式会社 | スイッチ駆動回路 |
JP7422371B1 (ja) | 2023-02-14 | 2024-01-26 | 株式会社アレックス | 駆動回路及び駆動制御システム |
Citations (4)
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JP2009022106A (ja) * | 2007-07-12 | 2009-01-29 | Renesas Technology Corp | Dc−dcコンバータ、ドライバic、およびシステムインパッケージ |
JP2009225648A (ja) * | 2008-03-19 | 2009-10-01 | Toyota Central R&D Labs Inc | 半導体素子駆動回路 |
JP2010273541A (ja) * | 2010-08-04 | 2010-12-02 | Renesas Electronics Corp | 半導体装置 |
JP2013125806A (ja) * | 2011-12-14 | 2013-06-24 | Mitsubishi Electric Corp | 電力用半導体装置 |
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2014
- 2014-03-05 JP JP2014042761A patent/JP6379525B2/ja active Active
Patent Citations (4)
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JP2009022106A (ja) * | 2007-07-12 | 2009-01-29 | Renesas Technology Corp | Dc−dcコンバータ、ドライバic、およびシステムインパッケージ |
JP2009225648A (ja) * | 2008-03-19 | 2009-10-01 | Toyota Central R&D Labs Inc | 半導体素子駆動回路 |
JP2010273541A (ja) * | 2010-08-04 | 2010-12-02 | Renesas Electronics Corp | 半導体装置 |
JP2013125806A (ja) * | 2011-12-14 | 2013-06-24 | Mitsubishi Electric Corp | 電力用半導体装置 |
Cited By (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2017168951A1 (ja) * | 2016-03-29 | 2017-10-05 | 三菱電機株式会社 | 過熱保護制御装置 |
JPWO2017168951A1 (ja) * | 2016-03-29 | 2018-11-22 | 三菱電機株式会社 | 過熱保護制御装置および車載用電力回路装置 |
US10658921B2 (en) | 2016-03-29 | 2020-05-19 | Mitsubishi Electric Corporation | Overheat protection control device and vehicle-mounted power circuit device |
WO2018056213A1 (ja) * | 2016-09-23 | 2018-03-29 | 三菱電機株式会社 | 電力用半導体モジュール及び電力用半導体装置 |
CN109804465A (zh) * | 2016-09-23 | 2019-05-24 | 三菱电机株式会社 | 电力用半导体模块以及电力用半导体装置 |
WO2019077871A1 (ja) * | 2017-10-19 | 2019-04-25 | 株式会社デンソー | 半導体モジュール |
JP2019075523A (ja) * | 2017-10-19 | 2019-05-16 | 株式会社デンソー | 半導体モジュール |
WO2021044715A1 (ja) * | 2019-09-02 | 2021-03-11 | ローム株式会社 | スイッチ駆動回路 |
JP7422371B1 (ja) | 2023-02-14 | 2024-01-26 | 株式会社アレックス | 駆動回路及び駆動制御システム |
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