JP2015170778A - 半導体装置およびその製造方法 - Google Patents
半導体装置およびその製造方法 Download PDFInfo
- Publication number
- JP2015170778A JP2015170778A JP2014045679A JP2014045679A JP2015170778A JP 2015170778 A JP2015170778 A JP 2015170778A JP 2014045679 A JP2014045679 A JP 2014045679A JP 2014045679 A JP2014045679 A JP 2014045679A JP 2015170778 A JP2015170778 A JP 2015170778A
- Authority
- JP
- Japan
- Prior art keywords
- pad
- semiconductor device
- dummy
- protective film
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/74—Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts
- H01L21/743—Making of internal connections, substrate contacts
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/10—Containers; Seals characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/585—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries comprising conductive layers or plates or strips or rods or rings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/03—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/07—Structure, shape, material or disposition of the bonding areas after the connecting process
- H01L24/09—Structure, shape, material or disposition of the bonding areas after the connecting process of a plurality of bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
- H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
- H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
- H01L2224/02165—Reinforcing structures
- H01L2224/02166—Collar structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
- H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
- H01L2224/02233—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body not in direct contact with the bonding area
- H01L2224/02235—Reinforcing structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/03—Manufacturing methods
- H01L2224/03001—Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate
- H01L2224/03009—Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate for protecting parts during manufacture
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/03—Manufacturing methods
- H01L2224/036—Manufacturing methods by patterning a pre-deposited material
- H01L2224/0361—Physical or chemical etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/03—Manufacturing methods
- H01L2224/038—Post-treatment of the bonding area
- H01L2224/0382—Applying permanent coating, e.g. in-situ coating
- H01L2224/03827—Chemical vapour deposition [CVD], e.g. laser CVD
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05553—Shape in top view being rectangular
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05556—Shape in side view
- H01L2224/05557—Shape in side view comprising protrusions or indentations
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/05624—Aluminium [Al] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/061—Disposition
- H01L2224/0612—Layout
- H01L2224/06179—Corner adaptations, i.e. disposition of the bonding areas at the corners of the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48153—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate
- H01L2224/48175—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being metallic
- H01L2224/48177—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/485—Material
- H01L2224/48505—Material at the bonding interface
- H01L2224/48599—Principal constituent of the connecting portion of the wire connector being Gold (Au)
- H01L2224/486—Principal constituent of the connecting portion of the wire connector being Gold (Au) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/48617—Principal constituent of the connecting portion of the wire connector being Gold (Au) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950 °C
- H01L2224/48624—Aluminium (Al) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
- H01L23/3192—Multilayer coating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/562—Protection against mechanical damage
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
- H01L2924/3512—Cracking
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Wire Bonding (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
【解決手段】ダミー配線DMLは、パッドPD1を構成する複数の辺のうち、角部CNRに最も近い辺SD1に対して、離間しながら並行するように設けられたダミー部DMP1と、パッドPD1を構成する複数の辺のうち、半導体チップCHPの端辺ESに最も近い辺SD2に対して、離間しながら並行するように設けられたダミー部DMP2とを含んでいる。つまり、ダミー配線DMLは、パッドPD1の辺SD1に沿って延在するダミー部DMP1と、パッドPD1の辺SD2に沿って延在するダミー部DMP2とから構成されている。
【選択図】図9
Description
<半導体装置(QFPパッケージ)の構成例>
半導体装置のパッケージ構造には、例えば、BGA(Ball Grid Array)パッケージやQFP(Quad Flat Package)パッケージなどのように様々な種類がある。本実施の形態における技術的思想は、これらのパッケージに適用可能であり、以下に、一例として、QFPパッケージからなる半導体装置の構成について説明する。
図4は、パッドPDを含むパッドPDの近傍領域の構造を示す断面図である。図4に示すように、例えば、アルミニウムを主成分とするパッドPDを覆うように、例えば、酸化シリコン膜OXFと窒化シリコン膜SNFとの積層膜からなる表面保護膜PASが形成されている。そして、この表面保護膜PASには、開口部OPが形成されており、この開口部OPの底部からパッドPDの表面の一部が露出している。一方、パッドPDの端部は、表面保護膜PASで覆われている。すなわち、パッドPDの端部においては、パッドPDの厚みに起因する段差を覆うように表面保護膜PASが形成されている。さらに、開口部OPから露出するパッドPDの表面には、例えば、金線からなるワイヤWが接続されており、ワイヤWが接続されたパッドPDの表面を含む表面保護膜PAS上は、例えば、樹脂MRで覆われている。
図8は、本実施の形態における半導体チップCHPのレイアウト構成を示す図である。図8において、半導体チップCHPは、例えば、矩形形状をしており、半導体チップCHPの端辺に沿って、アルミニウムを主成分とする複数のパッドPDが配置されている。これらの複数のパッドPDのそれぞれにおいて、図8では図示されていないが、パッドPDの表面の大部分は、表面保護膜に設けられた開口部から露出している一方、パッドPDの端部は、表面保護膜で覆われている。
続いて、本実施の形態における特徴点について説明する。図9は、図8の領域C1を拡大した拡大図である。図9において、半導体チップCHPは、端辺ESを有しており、この端辺ESに沿って、端辺ESの内側領域に、矩形形状をした複数のパッドPDが配置されている。詳細には、まず、半導体チップCHPの端辺ESの内側領域に、ダミー領域DMRが形成されており、このダミー領域DMRの内側領域に、シールリング領域SRRが形成されている。ダミー領域DMRには、ダイシング時に発生するおそれのあるクラックの半導体チップCHP内(チップ領域内)への進行を抑制するダミーパターンが設けられており、シールリング領域SRRには、半導体チップCHPの内部への異物の侵入を抑制するシールリングが設けられている。なお、ダミー領域DMRのダミーパターンは必ずしも必要ではない。しかし、上述のクラック防止や、各配線層の形成時に行われるCMP工程での平坦性向上のため、ダミーパターンを設ける方が好ましい。
本実施の形態における半導体装置は、上記のように構成されており、以下に、その製造方法について図面を参照しながら説明する。
本実施の形態における技術的思想によって得られる代表的な効果をまとめると以下のようになる。
図22は、実施の形態の変形例1を示す模式図であって、図8の領域C1を拡大した拡大図に相当する図である。図22において、本変形例1の特徴は、ダミー配線DMLが、辺SD1に沿って離間しながら並行するダミー部DMP1と、辺SD2に沿って離間しながら並行するダミー部DMP2と、さらに、ダミー部DMP1とダミー部DMP2とを接続する傾斜部SLPから構成されている点にある。本変形例1においては、図22に示す傾斜部SLPを設けることにより、半導体チップCHPの角部CNRに最も近いパッドPD1の角部に加わる応力を緩和することができるため、さらに、半導体装置の信頼性を向上することができる。
図23は、実施の形態の変形例2を示す模式図であって、図8の領域C1を拡大した拡大図に相当する図である。図23において、本変形例2でも、ダミー配線DMLが、ダミー部DMP1とダミー部DMP2から構成されている点で、実施の形態と共通するが、本変形例2において、ダミー部DMP1およびダミー部DMP2は、それぞれ、複数のドットパターンから形成されている。この場合も、実施の形態と同様に、半導体チップの角部に最も近いパッドにおいて、このパッドの端部を覆う表面保護膜の被覆形状の急峻化が緩和され、かつ、パッドの端部を覆う表面保護膜の膜厚が厚くなる。この結果、樹脂からの応力が抑制されることになり、これによって、本変形例2においても、半導体チップの角部に最も近いパッドの端部を覆う表面保護膜にクラックが発生することを抑制することができる。これにより、本変形例2においても、半導体装置の信頼性を向上することができる。
図24は、実施の形態の変形例3を示す模式図であって、図8の領域C1を拡大した拡大図に相当する図である。図24において、本変形例3は、上述した変形例1と変形例2とを組み合わせた構成である。具体的に、ダミー配線DMLは、ダミー部DMP1とダミー部DMP2と傾斜部SLPから構成されており、かつ、ダミー部DMP1およびダミー部DMP2は、それぞれ、複数のドットパターンから形成されている。この場合も、実施の形態と同様に、半導体チップの角部に最も近いパッドにおいて、このパッドの端部を覆う表面保護膜の被覆形状の急峻化が緩和され、かつ、パッドの端部を覆う表面保護膜の膜厚が厚くなる。この結果、樹脂からの応力が抑制されることになり、これによって、本変形例3においても、半導体チップの角部に最も近いパッドの端部を覆う表面保護膜にクラックが発生することを抑制することができる。これにより、本変形例3においても、半導体装置の信頼性を向上することができる。
図25は、実施の形態の変形例4を示す模式図であって、図8の領域C1を拡大した拡大図に相当する図である。図25において、本変形例4は、基本的にダミー配線DMLが、ダミー部DMP1とダミー部DMP2と傾斜部SLPから構成されている点で、変形例1と共通する。一方、本変形例4では、図25に示すように、ダミー部DMP2が、複数のパッドPDと半導体チップCHPの端辺ESとの間に位置しながら、半導体チップCHPの端辺ESに沿って延在している点に特徴点がある。これにより、本変形例4によれば、半導体チップCHPの角部に最も近いパッドPD1だけでなく、その他の複数のパッドPDにおいても、パッドPDの端部を覆う表面保護膜にクラックが発生することを抑制することができる。このことから、本変形例4によれば、半導体チップCHPに形成されている複数のパッドPD全体にわたって、パッドPDの端部を覆う表面保護膜のクラック耐性を高めることができるため、さらなる半導体装置の信頼性を向上することができる。
図26は、実施の形態の変形例5を示す模式図である。図12と図26とを比較するとわかるように、図26に示す本変形例5におけるダミー配線DMLの幅は、図12に示す実施の形態におけるダミー配線DMLの幅よりも小さくなっている。具体的に、例えば、図12に示す実施の形態におけるダミー配線DMLの幅(上底の幅)が2μm程度であるのに対し、図26に示す本変形例5におけるダミー配線DMLの幅(上底の幅)は、1μm程度である。この場合、本変形例5では、パッドPD1の表面の高さとダミー配線DMLの表面の高さとが同一である一方、ダミー配線DMLを覆う表面保護膜PASの高さH2は、パッドPD1を覆う表面保護膜PASの高さH1よりも低くなる構成が実現される。なぜなら、表面保護膜PASの一部を構成する酸化シリコン膜OXFは、高密度プラズマCVD法で形成されるからである。すなわち、この高密度プラズマCVD法は、エッチングしながら膜を堆積するという特性を有していることから、図26に示すように、幅の大きなパッドPD1上には厚い膜厚の酸化シリコン膜OXFが堆積する一方、幅の小さなダミー配線DML上では、エッチングの効果が顕著となり、ダミー配線DML上に形成される酸化シリコン膜OXFの膜厚が、パッドPD1上に形成される酸化シリコン膜OXFの膜厚よりも小さくなるからである。
A1 領域
AF アルミニウム膜
B1 領域
BCF1 バリア導体膜
BCF2 バリア導体膜
C1 領域
D1 領域
E1 領域
CHP 半導体チップ
CLK クラック
CNR 角部
CR チップ領域
DML ダミー配線
DMP1 ダミー部
DMP2 ダミー部
DMR ダミー領域
DP ダミーパターン
ES 端辺
FL ファイン層
GL グローバル層
H1 高さ
H2 高さ
ICR 集積回路領域
IL 層間絶縁膜
IL1 インナーリード
MR 樹脂
OL アウターリード
OP 開口部
OXF 酸化シリコン膜
PAS 表面保護膜
PD パッド
PD1 パッド
Q 電界効果トランジスタ
R1 周辺領域
SA1 半導体装置
SCR スクライブ領域
SD1 辺
SD2 辺
SLP 傾斜部
SNF 窒化シリコン膜
SRG シールリング
SRR シールリング領域
TAB チップ搭載部
W ワイヤ
WF 半導体ウェハ
Claims (20)
- 矩形形状をした半導体チップを備え、
前記半導体チップは、
(a)前記半導体チップの端辺に沿って配置された複数のパッド、
(b)前記複数のパッドのうち、前記半導体チップの角部に最も近い位置に配置された第1パッドであって、矩形形状をした前記第1パッドの周辺に設けられたダミー配線、
を有し、
前記ダミー配線は、
(b1)前記第1パッドを構成する複数の辺のうち、前記角部に最も近い第1辺に対して、離間しながら並行するように設けられた第1ダミー部、
(b2)前記第1パッドを構成する前記複数の辺のうち、前記半導体チップの前記端辺に最も近い第2辺に対して、離間しながら並行するように設けられた第2ダミー部、
を含む、半導体装置。 - 請求項1に記載の半導体装置において、
前記半導体チップには、半導体素子が形成されており、
前記ダミー配線は、前記半導体素子と電気的に接続されておらず、配線として機能しない、半導体装置。 - 請求項2に記載の半導体装置において、
前記ダミー配線の電位は、フローティングである、半導体装置。 - 請求項1に記載の半導体装置において、
前記ダミー配線は、前記第1パッドと同層で形成されている、半導体装置。 - 請求項4に記載の半導体装置において、
前記ダミー配線の表面の高さは、前記第1パッドの表面の高さと同一である、半導体装置。 - 請求項1に記載の半導体装置において、
前記第2ダミー部と前記半導体チップの前記端辺との間に、前記半導体チップの内部への異物の侵入を抑制するシールリングが形成されている、半導体装置。 - 請求項6に記載の半導体装置において、
前記半導体チップには、半導体素子が形成されており、
前記第1パッドと前記シールリングとの間には、前記半導体素子と電気的に接続される配線は存在しない、半導体装置。 - 請求項1に記載の半導体装置において、
前記第1ダミー部と前記第2ダミー部とは、一体的に形成されている、半導体装置。 - 請求項8に記載の半導体装置において、
前記第1ダミー部と前記第2ダミー部は、傾斜部によって接続されている、半導体装置。 - 請求項8に記載の半導体装置において、
前記第2ダミー部は、前記複数のパッドと前記半導体チップの前記端辺との間に位置しながら、前記半導体チップの前記端辺に沿って延在している、半導体装置。 - 請求項1に記載の半導体装置において、
前記第1ダミー部は、複数のドットパターンから構成され、
前記第2ダミー部は、複数のドットパターンから構成されている、半導体装置。 - 請求項11に記載の半導体装置において、
前記第2ダミー部は、前記複数のパッドと前記半導体チップの前記端辺との間に位置しながら、前記半導体チップの前記端辺に沿って延在している、半導体装置。 - 請求項1に記載の半導体装置において、
前記複数のパッドおよび前記ダミー配線を覆うように表面保護膜が形成され、
前記表面保護膜には、前記複数のパッドのそれぞれの表面の一部を露出する開口部が形成されている、半導体装置。 - 請求項13に記載の半導体装置において、
前記第1パッドの表面の高さは、前記ダミー配線の表面の高さと同一である一方、
前記ダミー配線を覆う前記表面保護膜の高さは、前記第1パッドを覆う前記表面保護膜の高さよりも低い、半導体装置。 - 請求項13に記載の半導体装置において、
前記半導体チップは、樹脂を含む封止体で封止されている、半導体装置。 - (a)矩形形状のチップ領域と、前記チップ領域を区画するスクライブ領域とを有する半導体基板を用意する工程、
(b)前記チップ領域と前記スクライブ領域との境界線に沿って、前記チップ領域内に矩形形状の複数のパッドを形成し、かつ、前記複数のパッドのうち、前記チップ領域の角部に最も近い第1パッドの周辺にダミー配線を形成する工程、
を備え、
前記(b)工程で形成される前記ダミー配線は、
前記第1パッドを構成する複数の辺のうち、前記チップ領域の角部に最も近い第1辺に対して、離間しながら並行する第1ダミー部と、
前記第1パッドを構成する前記複数の辺のうち、前記境界線に最も近い第2辺に対して、離間しながら並行する第2ダミー部と、
を含む、半導体装置の製造方法。 - 請求項16に記載の半導体装置の製造方法において、
(c)前記複数のパッドおよび前記ダミー配線を覆う表面保護膜を形成する工程、
(d)前記表面保護膜に前記複数のパッドのそれぞれの表面の一部を露出する開口部を形成する工程、
(e)前記(d)工程後、前記スクライブ領域に沿って、前記半導体基板をダイシングすることにより、半導体チップを取得する工程、
(f)前記(e)工程後、前記開口部から露出する前記複数のパッドのそれぞれの表面にワイヤを接続する工程、
(g)前記(f)工程後、前記半導体チップを封止する工程、
を有する、半導体装置の製造方法。 - 請求項17に記載の半導体装置の製造方法において、
前記(g)工程後、温度サイクル試験を実施する工程を有する、半導体装置の製造方法。 - 請求項17に記載の半導体装置の製造方法において、
前記(c)工程は、
(c1)前記複数のパッドおよび前記ダミー配線を覆うように酸化シリコン膜を形成する工程、
(c2)前記酸化シリコン膜上に窒化シリコン膜を形成する工程、
を含む、半導体装置の製造方法。 - 請求項19に記載の半導体装置の製造方法において、
前記(c1)工程は、高密度プラズマCVD法により実施する、半導体装置の製造方法。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2014045679A JP6262573B2 (ja) | 2014-03-07 | 2014-03-07 | 半導体装置およびその製造方法 |
US14/639,062 US20150255420A1 (en) | 2014-03-07 | 2015-03-04 | Semiconductor device and manufacturing method thereof |
US15/009,473 US9607962B2 (en) | 2014-03-07 | 2016-01-28 | Semiconductor device and manufacturing method thereof |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2014045679A JP6262573B2 (ja) | 2014-03-07 | 2014-03-07 | 半導体装置およびその製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2015170778A true JP2015170778A (ja) | 2015-09-28 |
JP6262573B2 JP6262573B2 (ja) | 2018-01-17 |
Family
ID=54018123
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2014045679A Expired - Fee Related JP6262573B2 (ja) | 2014-03-07 | 2014-03-07 | 半導体装置およびその製造方法 |
Country Status (2)
Country | Link |
---|---|
US (2) | US20150255420A1 (ja) |
JP (1) | JP6262573B2 (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2017056297A1 (ja) * | 2015-10-01 | 2017-04-06 | ルネサスエレクトロニクス株式会社 | 半導体装置およびその製造方法 |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9966371B1 (en) | 2016-11-04 | 2018-05-08 | General Electric Company | Electronics package having a multi-thickness conductor layer and method of manufacturing thereof |
US20180130732A1 (en) * | 2016-11-04 | 2018-05-10 | General Electric Company | Electronics package having a multi-thickness conductor layer and method of manufacturing thereof |
US10700035B2 (en) | 2016-11-04 | 2020-06-30 | General Electric Company | Stacked electronics package and method of manufacturing thereof |
US9966361B1 (en) | 2016-11-04 | 2018-05-08 | General Electric Company | Electronics package having a multi-thickness conductor layer and method of manufacturing thereof |
CN111480225A (zh) * | 2017-12-20 | 2020-07-31 | 索尼半导体解决方案公司 | 半导体装置 |
JP7149907B2 (ja) * | 2019-09-04 | 2022-10-07 | 三菱電機株式会社 | 半導体装置および半導体素子 |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0353843U (ja) * | 1989-09-29 | 1991-05-24 | ||
JPH10242204A (ja) * | 1997-02-27 | 1998-09-11 | Sanyo Electric Co Ltd | 半導体装置および半導体装置の製造方法 |
US20090008803A1 (en) * | 2006-07-12 | 2009-01-08 | United Microelectronics Corp. | Layout of dummy patterns |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH05235085A (ja) | 1992-02-26 | 1993-09-10 | Nec Corp | 半導体装置 |
KR100319883B1 (ko) * | 1999-03-16 | 2002-01-10 | 윤종용 | 패드 주위에 더미 패턴을 구비한 반도체소자 |
JP2003045876A (ja) | 2001-08-01 | 2003-02-14 | Seiko Epson Corp | 半導体装置 |
JP4639245B2 (ja) * | 2008-05-22 | 2011-02-23 | パナソニック株式会社 | 半導体素子とそれを用いた半導体装置 |
JP5323406B2 (ja) | 2008-06-24 | 2013-10-23 | ルネサスエレクトロニクス株式会社 | 半導体集積回路装置の製造方法 |
-
2014
- 2014-03-07 JP JP2014045679A patent/JP6262573B2/ja not_active Expired - Fee Related
-
2015
- 2015-03-04 US US14/639,062 patent/US20150255420A1/en not_active Abandoned
-
2016
- 2016-01-28 US US15/009,473 patent/US9607962B2/en not_active Expired - Fee Related
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0353843U (ja) * | 1989-09-29 | 1991-05-24 | ||
JPH10242204A (ja) * | 1997-02-27 | 1998-09-11 | Sanyo Electric Co Ltd | 半導体装置および半導体装置の製造方法 |
US20090008803A1 (en) * | 2006-07-12 | 2009-01-08 | United Microelectronics Corp. | Layout of dummy patterns |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2017056297A1 (ja) * | 2015-10-01 | 2017-04-06 | ルネサスエレクトロニクス株式会社 | 半導体装置およびその製造方法 |
JPWO2017056297A1 (ja) * | 2015-10-01 | 2018-06-07 | ルネサスエレクトロニクス株式会社 | 半導体装置およびその製造方法 |
Also Published As
Publication number | Publication date |
---|---|
US20160148897A1 (en) | 2016-05-26 |
JP6262573B2 (ja) | 2018-01-17 |
US9607962B2 (en) | 2017-03-28 |
US20150255420A1 (en) | 2015-09-10 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP6262573B2 (ja) | 半導体装置およびその製造方法 | |
US11810869B2 (en) | Semiconductor device and method of manufacturing the same | |
JP5443827B2 (ja) | 半導体装置 | |
US20150115269A1 (en) | Semiconductor Device and Method for Manufacturing Semiconductor Device | |
US11545454B2 (en) | Semiconductor device | |
KR20180013711A (ko) | 반도체 장치 및 그 제조 방법 | |
TWI540616B (zh) | 晶圓級晶片陣列及其製造方法 | |
JP2015220248A (ja) | 半導体装置の製造方法および半導体装置 | |
JP6677832B2 (ja) | 半導体チップ | |
US20220102319A1 (en) | Method for manufacturing semiconductor structure | |
JP7441923B2 (ja) | 半導体チップ | |
JP5702844B2 (ja) | 半導体装置 | |
JP6473790B2 (ja) | 半導体装置 | |
JP2008085043A (ja) | 半導体ウェハ、半導体チップおよび半導体チップの製造方法。 | |
JP2014057086A (ja) | 半導体装置 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20161024 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20170616 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20170627 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20170815 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20171205 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20171214 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 6262573 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
LAPS | Cancellation because of no payment of annual fees |