JP2015142152A - Trigger detection circuit and trigger detection ic chip - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a trigger detection circuit capable of detecting a trigger signal for periodic trigger input, and to provide a trigger detection IC chip.SOLUTION: A trigger detection circuit can detect a trigger signal by resetting to the same initial state for periodic trigger input. An input signal VIN of pulse waveform is inputted to a capacitive element 3. A detection circuit 4 detects a trigger signal Vtrig from an output signal COMPIN of the capacitive element 3. Since the input signal VIN is attenuated by first and second resistive elements and connected with a capacitive element 3 for DC cut, the DC component of the input signal VIN is not transmitted to COMPIN. This COMPIN is detected by the detection circuit 4 and COMPOUT is created.

Description

  The present invention relates to a trigger detection circuit and a trigger detection IC chip, and more particularly to a trigger detection circuit and a trigger detection IC chip that can detect a trigger signal with respect to a periodic trigger input.

  2. Description of the Related Art Conventionally, a control device that determines a vehicle sensor and a vehicle state and a system using the vehicle sensor are known. A wireless rotational speed sensor used for this vehicle sensor is also known. The rotational speed sensor measures the rotational speed of the vehicle wheel or vehicle tire, and the measurement value recorded by the rotational speed sensor is processed into a data message representing the rotational speed of the wheel. Send wirelessly.

  FIG. 1 is a diagram showing a timing chart in which a trigger voltage is periodically input in PSI5 communication mainly used for in-vehicle products. The input signal VIN is an input signal in which a trigger signal Vtrig having a pulse waveform is superimposed on the power supply voltage VDD. In PSI5 (Peripheral Sensor Interface 5) communication, the communication is performed by superimposing the trigger signal Vtrig for each Tcyc on the power supply voltage level VDD of normal operation, so that the input becomes a high voltage. In addition to the rotation speed sensor, there is a form in which an in-vehicle linear Hall IC using a magnetic sensor similarly performs PSI5 communication.

  FIG. 2 is a diagram illustrating a general comparator circuit. The comparator (comparator) 30 has two inputs (VIN and VREF). When a trigger is detected with such a configuration, for example, VREF = VDD + (Vtrig / 2) is required. COMPOUT indicates an output signal of the comparator 30.

  However, while the trigger signal Vtrig is defined by the standard, there is a problem that the power supply voltage VDD varies from product to product depending on usage. For this reason, it is necessary to adjust and set the reference voltage VREF according to the application.

  For example, Patent Document 1 relates to a system having a vehicle sensor, a control device for determining a vehicle state, and at least one vehicle sensor, and the vehicle sensor has an interface for transmitting cable connection data. The interface is configured to connect the vehicle sensor and the control device for data transmission by a cable that can be implemented electrically or optically. An example of such cable connection data transmission is the so-called PSI 5 (Peripheral Sensor Interface 5). Depending on the required data transmission rate, installation conditions and costs, other cable connection transmissions are possible and this cable connection data transmission can also be carried out unidirectionally or bidirectionally.

  Further, the one described in Patent Document 2 relates to a sensor device and a method for supplying a signal for a rotation angle and a signal for a rotation torque, and a PSI5 protocol for a digital interface is used for the sensor element. .

Special table 2012-528032 gazette JP 2013-142699 A

However, it has been difficult to obtain a circuit that detects a periodic trigger signal without depending on the power supply level in a 2-wire IF such as PSI5 communication that has been used conventionally.
In Patent Documents 1 and 2 described above, an input signal having a pulse waveform is input in a trigger detection circuit that can detect a trigger signal by returning to the same initial state with respect to a periodic trigger input as in the present invention. There is no disclosure of a configuration that includes a capacitive element that is configured and a detection circuit that detects a trigger signal from an output signal of the capacitive element.

  The present invention has been made in view of such circumstances, and an object thereof is to provide a trigger detection circuit and a trigger detection IC chip that can detect a trigger signal with respect to a periodic trigger input. There is.

The present invention has been made to achieve such an object, and the invention according to claim 1 is a trigger detection circuit which can detect a trigger signal with respect to a periodic trigger input, A capacitive element (3) to which an input signal (VIN) having a pulse waveform is inputted, and a detection circuit (4) for detecting a trigger signal (Vtrig) from the output signal (COMPIN) of the capacitive element (3) are provided. It is characterized by that. (FIG. 3; embodiment)
According to a second aspect of the present invention, in the first aspect of the present invention, the input signal (VIN) is an input signal in which a trigger signal (Vtrig) having a pulse waveform is superimposed on a power supply voltage (VDD). It is characterized by that. (Figure 1)

According to a third aspect of the present invention, in the first or second aspect of the invention, the detection circuit (4) includes a first reference voltage (VREF0) and an output signal of the capacitive element (3) ( It has a comparator (9) for comparing with (COMPIN). (FIG. 4; Example 1)
According to a fourth aspect of the present invention, in the third aspect of the present invention, the detection circuit (4) includes an inverting input terminal (-) to which the first reference voltage (VREF0) is input, A comparator (9) having a non-inverting input terminal (+) to which an output signal (COMPIN) of the capacitive element (3) is input, and a non-inverting input terminal (+) of the comparator (9) and the inverting input It has a resistance component (7; R0) connected between the terminal (−) and a sink current source (5) connected to the non-inverting input terminal (+).

According to a fifth aspect of the present invention, in the invention according to the fourth aspect, the detection circuit (4) generates a control signal based on an output of the comparator (9). ) And a switch (6) connected between the non-inverting input terminal (+) and the inverting input terminal (−) of the comparator (9) and controlled based on the control signal. It is characterized by.
According to a sixth aspect of the present invention, in the fifth aspect of the present invention, when the control signal generation circuit (10) detects the falling edge of the trigger signal (Vtrig), the switch (6) The voltage of the non-inverting input terminal (+) is connected to the first reference voltage (8; VREF0).

According to a seventh aspect of the present invention, in the sixth aspect of the present invention, the control signal generation circuit (10) detects the falling edge of the trigger signal (Vtrig) after a predetermined time has elapsed. And the switch (6) is connected.
According to an eighth aspect of the present invention, in the first or second aspect of the present invention, the detection circuit (4) has an inverting input terminal (-) to which the first reference voltage (14; VREF1) is input. ) And a non-inverting input terminal (+) to which the output signal (COMPIN) of the capacitive element (3) is input, and a resistance component connected to the non-inverting input terminal (+) (11), and a second reference voltage (15; VREF2) lower than the first reference voltage (14; VREF1) is connected to the non-inverting input terminal (+ ). (FIG. 5; Example 2)

According to a ninth aspect of the present invention, there is provided the control signal generation circuit (16) according to the eighth aspect, wherein the detection circuit (4) generates a control signal based on an output of the comparator (13). And a switch (12) connected in parallel with the resistance component (11) and controlled based on the control signal.
According to a tenth aspect of the present invention, in the invention according to the ninth aspect, when the control signal generation circuit (16) detects the falling edge of the trigger signal (Vtrig), the switch (12) The voltage of the non-inverting input terminal (+) is connected to the second reference voltage (14; VREF2).

According to an eleventh aspect of the present invention, in the tenth aspect of the present invention, the control signal generation circuit (16) detects the falling edge of the trigger signal (Vtrig) after a predetermined time has elapsed. And the switch (12) is connected.
The invention described in claim 12 is a power supply PAD (21) to which an input signal in which a trigger signal (Vtrig) having a pulse waveform is superimposed on a power supply voltage (VDD) is connected to the power supply PAD (21). And a detection circuit (24) that detects a trigger signal from the output of the capacitance element (23). (FIG. 7; Example 3)

According to a thirteenth aspect of the invention, in the twelfth aspect of the invention, a current output circuit (26) that outputs an output current to the power supply PAD (21) based on the trigger signal (Vtrig) is further provided. It is characterized by having.
The invention according to claim 14 is the invention according to claim 12 or 13, characterized in that the capacitive element (23) is connected to the power supply PAD (21) through resistance division. To do.
The invention described in claim 15 is the invention described in any one of claims 12-14, wherein a trigger signal (Vtrig) having a pulse waveform is supplied from the power supply PAD (21) to the power supply voltage (VDD). PSI5 communication in which the superimposed input signal is input and the current output circuit (26) outputs an output current to the power supply PAD (21) based on the trigger signal (Vtrig) detected by the detection circuit (24) It is characterized by performing.

  According to the present invention, since a simple circuit configuration, that is, a capacitive element to which an input signal having a pulse waveform is input and a detection circuit that detects a trigger signal from the output signal of the capacitive element, a periodic circuit is provided. The trigger input of VDD can be detected without depending on the level of VDD.

It is a figure which shows the timing chart in which a trigger voltage is periodically injected | thrown-in by PSI5 communication mainly used with a vehicle-mounted product etc. FIG. It is a figure which shows a general comparator circuit. It is a circuit block diagram for demonstrating embodiment of the trigger detection circuit based on this invention. FIG. 4 is a circuit configuration diagram for explaining Example 1 of the detection circuit constituting the trigger detection circuit of the present invention shown in FIG. 3. FIG. 4 is a circuit configuration diagram for explaining Example 2 of the detection circuit constituting the trigger detection circuit of the present invention shown in FIG. 3. (A) thru | or (d) is a figure which shows a timing chart when a trigger is input from the input signal VIN regularly. It is a circuit block diagram for demonstrating the trigger detection IC chip as Example 3 provided with the trigger detection circuit of this invention.

Embodiments of the present invention will be described below with reference to the drawings. The present invention is a detection circuit capable of performing optimal detection with respect to a periodic trigger input. The characteristics of this trigger detection circuit are as follows.
1) Usable in I / F with high voltage.
2) It does not depend on the input DC level.
3) By switching the switch, it can be detected by returning to the same initial state every time for a periodic trigger input.

[Embodiment]
FIG. 3 is a circuit configuration diagram for explaining an embodiment of the trigger detection circuit according to the present invention, in which reference numeral 1 denotes a first resistance element (resistance component / attenuator resistance), and 2 denotes a second resistance element. (Resistance component / Attenuator resistor), 3 is a capacitive element (DC cut capacitor), and 4 is a detection circuit.
The trigger detection circuit according to the present invention is a trigger detection circuit which can detect a trigger signal by returning to the same initial state with respect to a periodic trigger input.

The capacitive element 3 receives an input signal VIN having a pulse waveform. The detection circuit 4 detects the trigger signal Vtrig from the output signal COMPIN of the capacitive element 3.
That is, since the input signal VIN is attenuated by the first and second resistance elements and is connected to the capacitor element 3 for DC cut, the DC component of the input signal VIN is not transmitted to COMPIN. This COMPIN is detected by the detection circuit 4 to generate COMPOUT.

  FIG. 4 is a circuit configuration diagram for explaining the first embodiment of the detection circuit constituting the trigger detection circuit of the present invention shown in FIG. 3, in which reference numeral 5 denotes a sink current source (IREF0), and 6 denotes a switch ( SW), 7 is a resistance component (R0), 8 is a reference voltage (reference voltage VREF0), 9 is a comparator (comparator), and 10 is a control signal generation circuit. In addition, the same code | symbol is attached | subjected to the component which has the same function as FIG.

The detection circuit 4 according to the first embodiment of the present invention includes a comparator 9, a sink current source (IREF 0) 5, and a control signal generation circuit 10.
The detection circuit 4 includes a comparator 9 that compares the reference voltage (VREF0) 8 with the output signal COMPIN of the capacitive element 3.
The detection circuit 4 includes a comparator 9 having an inverting input terminal (−) to which the reference voltage (VREF0) 8 is input and a non-inverting input terminal (+) to which the output signal COMPIN of the capacitor 3 is input. The resistance component (R0) 7 connected between the non-inverting input terminal (+) and the inverting input terminal (−) of the comparator 9 and the sink current source 5 connected to the non-inverting input terminal (+) And have.

The detection circuit 4 is connected between a control signal generation circuit 10 that generates a control signal based on the output of the comparator 9, and a non-inverting input terminal (+) and an inverting input terminal (−) of the comparator 9. The switch SW6 is controlled based on the control signal.
When the control signal generation circuit 10 detects the falling edge of the trigger signal Vtrig, the control signal generation circuit 10 connects with the switch SW6 and sets the voltage at the non-inverting input terminal (+) as the reference voltage (VREF0) 8.

Further, the control signal generation circuit 10 is configured to output a control signal after a predetermined time has elapsed after detecting the falling edge of the trigger signal Vtrig and to connect the switch SW6.
That is, COMPIN, which is the output of the capacitive element 3, is input to the non-inverting input terminal (+) of the comparator 9, and the reference voltage VREF0 is input to the inverting input terminal (−). Further, the current IREF0 of the sink current source 5 is forced at the non-inverting input terminal (+).
The switch SW6 controlled by the SW signal generated from the output COMPOUT of the comparator 9 via the control signal generation circuit 10 is connected between the non-inverting input terminal (+) and the inverting input terminal (−). It is connected to the. The reference voltage VREF0 is connected to the non-inverting input terminal (+) of the comparator 9 via the resistance component (R0) 7.

When the trigger signal is not input, the voltage of VREF0−IREF0 × R0 is input to the non-inverting input terminal (+), and the voltage of VREF0 is input to the inverting input terminal (−). COMPOUT becomes LOW.
When the trigger signal Vtrig is input, if R0 and IREF0 are set so as to satisfy R0 × IREF0 <Vtrig, VREF0−IREF0 × R0 + Vtrig> VREF0 is established, so that the output COMPOUT of the comparator 9 becomes HIGH.
By having the resistance component (R0) 7, it is possible to prevent the minute deviation of the COMPIN level due to the trigger input from being accumulated and COMPOUT from being stacked.

  Further, the SW signal generated by the control signal generation circuit 10 can be used to switch the switch SW6 to short-circuit the COMPIN node to VREF0. Specifically, the SW signal is configured to detect a falling edge of COMPOUT and output a pulse after a predetermined time has elapsed. When the SW signal is Hi, the switch SW6 is turned on to short the COMPIN node to VREF2.

  Since the level of COMPIN is lower at the time of falling of the input signal than that at the time of rising, the level of COMPIN may be lower than VREF0-IREF0 × R0 due to the influence of the trigger falling edge at the time of falling. is there. After that, due to the resistance component 7, the voltage level converges to VREF0-IREF0 × R0. However, since there are variations in resistance values and capacitance values in the IC, convergence to VREF2 may not be in time before the next trigger. However, this problem can be solved by the switch operation described above. Thereby, it is possible to return to the same initial state and detect a periodic trigger signal.

  FIG. 5 is a circuit diagram for explaining a second embodiment of the detection circuit constituting the trigger detection circuit of the present invention shown in FIG. 3, in which reference numeral 11 denotes a resistance component, 12 denotes a switch (SW), 13 Is a comparator, 14 is a first reference voltage (reference voltage VREF1), 15 is a second reference voltage (reference voltage VREF2), and 16 is a control signal generation circuit. In addition, the same code | symbol is attached | subjected to the component which has the same function as FIG.

The detection circuit 4 according to the second embodiment of the present invention includes a comparator 13, a resistance component 11, and a control signal generation circuit 106.
The detection circuit 4 includes a comparator 13 having an inverting input terminal (−) to which the first reference voltage (VREF1) 14 is input and a non-inverting input terminal (+) to which the output signal COMPIN of the capacitive element 3 is input. And a resistance component 11 connected to the non-inverting input terminal (+).
A second reference voltage (VREF2) 15 lower than the first reference voltage (VREF1) 14 is input to the non-inverting input terminal (+) via the resistance component 11.

The detection circuit 4 includes a control signal generation circuit 16 that generates a control signal based on the output of the comparator 13, and a switch SW12 that is connected in parallel with the resistance component 11 and controlled based on the control signal. ing.
Further, when the control signal generation circuit 16 detects the falling edge of the trigger signal Vtrig, the control signal generation circuit 16 uses the switch SW12 to connect the non-inverting input terminal (+) to the second reference voltage (VREF2) 15.
Further, the control signal generation circuit 16 is configured to output a control signal after a predetermined time has elapsed after detecting the falling edge of the trigger signal Vtrig and connect the switch SW12.

That is, COMPIN which is the output of the capacitive element 3 is input to the non-inverting input terminal (+) of the comparator 13, and the first reference voltage (VREF1) 14 is input to the inverting input terminal (−). . The second reference voltage (VREF2) 15 is input to the non-inverting input terminal (+) via the resistance component 11.
A switch SW12 controlled by an SW signal generated from the output COMPOUT of the comparator 13 via the control signal generation circuit 16 is connected in parallel with the resistance component 11.

When the trigger signal is not input, the voltage of the second reference voltage (VREF2) 15 is input to the non-inverting input terminal (+), and the voltage of the first reference voltage (VREF1) 14 is input to the inverting input terminal (−). Since the voltage is input and VREF2 <VREF1, the output COMPOUT of the comparator 13 becomes LOW.
When the trigger signal Vtrig is input, if VREF1 and VREF2 are set so that VREF1−VREF2 <Vtrig, VREF2 + Vtrig> VREF1 is established, and therefore the output COMPOUT of the comparator 13 becomes HIGH.

Since the resistance component 11 is present, it is possible to prevent the minute deviation of the COMPIN level due to the trigger input from accumulating and COMPOUT from being stacked.
Further, the SW signal generated by the control signal generation circuit 16 can be used to switch the switch SW12 to short-circuit the COMPIN node to VREF2. Specifically, the SW signal is configured to detect a falling edge of COMPOUT and output a pulse after a predetermined time has elapsed. When the SW signal is Hi, the switch 12 is turned ON to short the COMPIN node to VREF2.

  Since the level of COMPIN is lower at the time of falling of the input signal due to the influence of the discharge than at the time of rising, the level may be lower than VREF2 due to the trigger falling edge at the time of falling. Thereafter, the voltage level converges to VREF2 due to the resistance component 11. However, since there are variations in resistance values and capacitance values in the IC, convergence to VREF2 may not be in time before the next trigger. However, this problem can be solved by the switch operation described above. Thereby, it is possible to return to the same initial state and detect a periodic trigger signal.

Hereinafter, the description will be focused on the case of FIG. 5 by assuming that VREF1−VREF2 = Vtrig−α (α> 0).
FIGS. 6A to 6D are timing charts when a trigger is periodically input from the input signal VIN.

Since COMPIN exceeds the level of VREF1 by α at time t0 when the trigger signal rises, COMPOUT is inverted in output and becomes Hi.
At this time, if the resistance value of the resistance component 11 is too small, the PIN voltage drop between t0 and t1 is large, so that the PIN level falls below VREF1 and the output of COMPOUT also falls to Lo before reaching t1. The resistance component 11 needs to have a certain high resistance value.
Since the falling edge of the trigger is input at time t1, COMPIN falls below VREF1, and COMPOUT is inverted in output and becomes Lo.

  At this time, COMPIN is at a level lower than VREF2 due to the trigger falling edge at time t1 because COMPIN has a lower level than time t0 due to the effect of discharge at time t1. Thereafter, the level converges to VREF2 through the resistance component 11. However, since there are variations in resistance value and capacitance value in the IC, convergence to VREF2 may not be in time by the next trigger.

As a countermeasure, a process of shorting the COMPIN node to VREF2 by the SW signal is performed. In FIGS. 6A to 6D, the SW signal detects the falling edge of COMPOUT and outputs a pulse after a delay of Tdelay. Assume that the COMPIN node is short-circuited to VREF2 when the SW signal is Hi.
By adding the above processing, the initial state of COMPIN = VREF2 can be maintained at the time t2 after Tcyc at the time of the trigger without depending on the variation in the IC.

FIG. 7 is a circuit configuration diagram for explaining a trigger detection IC chip as a third embodiment provided with the trigger detection circuit of the present invention, in which reference numeral 21 is a power supply PAD, 22 is a regulator circuit, 23 is a capacitive element, Reference numeral 24 denotes a detection circuit, 25 denotes a digital circuit, and 26 denotes a current output circuit.
The trigger detection IC chip according to the third embodiment of the present invention includes a power supply PAD 21, a capacitive element 23, and a detection circuit 24.

The power supply PAD 21 receives an input signal in which a trigger signal Vtrig having a pulse waveform is superimposed on the power supply voltage VDD. Further, the capacitive element 23 is connected to the power supply PAD21 through resistance division. The detection circuit 24 detects a trigger signal from the output of the capacitive element 23. The detected trigger signal Vtrig is calculated by a digital circuit, and a current output that outputs an output current to the power supply PAD21 based on the output signal. A circuit 26 is further provided. Further, a regulator circuit 22 connected to the power supply PAD21 is further provided.

  That is, the trigger detection IC chip according to the third embodiment includes a power supply PAD21 to which an input signal in which a trigger signal having a pulse waveform is superimposed on a power supply voltage, a capacitive element 23 connected to the power supply PAD21, and the capacitive element. And a detection circuit 24 for detecting a trigger signal from the output of 23. A current output circuit 26 that outputs a predetermined signal as a current to the power supply PAD 21 based on the detected trigger signal Vtrig is provided. In the third embodiment, since the trigger signal can be detected without depending on the level of the power supply voltage VDD input from the outside, the current output can be accurately communicated from the power supply PAD in the PSI5 communication. it can.

A regulator circuit 22 is connected to the power supply PAD 21 and generates a power supply voltage for operating the detection circuit 24 and the like.
As described above, in the third embodiment, a trigger signal can be detected with respect to a trigger signal input from the power supply PAD regardless of the power supply voltage.

1 First resistance element (resistance component / attenuator resistance)
2 Second resistance element (resistance component / attenuator resistance)
3,23 Capacitance element (Capacity for DC cut)
4,24 Detection circuit 5 Sink current source (IREF0)
6,12 Switch (SW)
7 Resistance component (R0)
8 Reference voltage (reference voltage VREF0)
9, 13, 30 Comparator
10, 16 Control signal generation circuit 11 Resistance component 14 First reference voltage (reference voltage VREF1)
15 Second reference voltage (reference voltage VREF2)
21 Power PAD
22 Regulator circuit 25 Digital circuit 26 Current output circuit

Claims (15)

A trigger detection circuit capable of detecting a trigger signal in response to a periodic trigger input,
A capacitive element to which an input signal (VIN) having a pulse waveform is input;
And a detection circuit that detects a trigger signal from the output signal of the capacitive element.   The trigger detection circuit according to claim 1, wherein the input signal is an input signal in which a trigger signal having a pulse waveform is superimposed on a power supply voltage. The detection circuit includes:
The trigger detection circuit according to claim 1, further comprising a comparator that compares the first reference voltage and an output signal of the capacitive element. The detection circuit includes:
A comparator having an inverting input terminal to which the first reference voltage is input and a non-inverting input terminal to which an output signal of the capacitive element is input;
A resistance component connected between the non-inverting input terminal of the comparator and the inverting input terminal;
The trigger detection circuit according to claim 3, further comprising: a sink current source connected to the non-inverting input terminal. The detection circuit includes:
A control signal generation circuit for generating a control signal based on the output of the comparator;
The trigger detection according to claim 4, further comprising: a switch connected between the non-inverting input terminal and the inverting input terminal of the comparator and controlled based on the control signal. circuit.   6. The control signal generation circuit according to claim 5, wherein when the falling edge of the trigger signal is detected, the control signal generation circuit is connected by the switch, and the voltage of the non-inverting input terminal is used as the first reference voltage. The trigger detection circuit described.   The trigger detection circuit according to claim 6, wherein the control signal generation circuit outputs a control signal after a predetermined time has elapsed after detecting a fall of the trigger signal, and connects the switch. The detection circuit includes:
A comparator having an inverting input terminal to which the first reference voltage is input; a non-inverting input terminal to which an output signal of the capacitor is input; and a resistance component connected to the non-inverting input terminal. And
3. The trigger detection circuit according to claim 1, wherein a second reference voltage lower than the first reference voltage is input to the non-inverting input terminal via the resistance component. The detection circuit includes:
A control signal generation circuit for generating a control signal based on the output of the comparator;
The trigger detection circuit according to claim 8, further comprising: a switch connected in parallel with the resistance component and controlled based on the control signal.   10. The control signal generation circuit according to claim 9, wherein when the falling edge of the trigger signal is detected, the control signal generation circuit is connected by the switch, and the voltage of the non-inverting input terminal is used as the second reference voltage. The trigger detection circuit described.   11. The trigger detection circuit according to claim 10, wherein the control signal generation circuit outputs a control signal after a predetermined time has elapsed after detecting a fall of the trigger signal and connects the switch. A power supply PAD that receives an input signal in which a trigger signal having a pulse waveform is superimposed on a power supply voltage;
A capacitive element connected to the power supply PAD;
A trigger detection IC chip comprising: a detection circuit that detects a trigger signal from the output of the capacitive element.   The trigger detection IC chip according to claim 12, further comprising a current output circuit that outputs an output current to the power supply PAD based on the trigger signal.   The trigger detection IC chip according to claim 12 or 13, wherein the capacitive element is connected to the power supply PAD through a resistance division.   An input signal in which a trigger signal having a pulse waveform is superimposed on a power supply voltage is input from the power supply PAD, and the current output circuit outputs an output current to the power supply PAD based on the trigger signal detected by the detection circuit. The trigger detection IC chip according to any one of claims 12 to 14, which performs PSI5 communication.

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