JP2008215897A - Average current measurement circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an average current measurement circuit for preventing a test time from being excessive, if the difference between measurement values at the previous measurement and the current measurement is small. <P>SOLUTION: The average current measurement circuit comprises an A/D converter 2 for binarizing a measured current averaged by a low-pass filter circuit 1; and a data acquisition control circuit 13 for acquiring binarized data at predetermined timing, and outputting averaged data. The data acquisition control circuit 13 acquires the binarized data from the A/D converter 2 at a predetermined time interval, and outputs the currently-acquired binarized data as averaged data, when predetermined upper bits are matched in a plurality of the successively-acquired binarized data. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to an improvement in the efficiency of measuring an average current of a device power source in a semiconductor tester or the like.

  2. Description of the Related Art Conventionally, in a semiconductor test apparatus or the like, power consumption current (hereinafter referred to as IDD) is measured under various operating conditions for a device such as a MOS LSI. For this reason, an average current measuring circuit is usually used.

  FIG. 3 is a block diagram showing a conventional average current measuring circuit. A low-pass filter (hereinafter referred to as LPF) 1 is composed of an amplification integration circuit, and inputs an IDD detection signal (voltage) Vin obtained by current / voltage conversion of IDD, and outputs a voltage V1 corresponding to the average current value. In the LPF1, the resistor R1 has one end applied with the IDD detection signal Vin and the other end connected to the inverting input terminal of the operational amplifier A1. The resistor R2 has one end connected to the inverting input terminal of the operational amplifier A1 and the other end connected to the output terminal. A series circuit comprising a contact circuit of the relay RL1 and an integrating capacitor C1 is connected in parallel with the resistor R2. The non-inverting input terminal of the operational amplifier A1 is connected to GND (ground). The A / D conversion circuit 2 receives the output voltage V1 of the LPF 1 and converts it into digital data (hereinafter referred to as binarized data), and outputs the binarized data when a strobe signal is sent to the strobe terminal. The data acquisition control circuit 3 is composed of an FPGA (Field Programmable Gate Array), sends a relay control signal to the relay RL1, prepares a measurement system for measuring average current, and sends a strobe signal to the A / D conversion circuit 2. Binary data after A / D conversion is acquired. The CPU 4 sends a start signal to the data acquisition control circuit 3 to start average current measurement, and obtains binary data by sending a strobe signal after a predetermined time from the start signal by a timer function.

  The operation of the average current measuring circuit configured as shown in FIG. 3 will be described below. When a start signal is sent from the CPU 4 to the data acquisition circuit 3, this triggers the data acquisition circuit 3 to turn on the relay RL1 of the LPF 1, so that the integration capacitor C1 is connected in parallel with the resistor R2, and the LPF 1 uses a low-pass filter. Constitute. Here, when the IDD detection signal Vin corresponding to the power consumption current IDD of the device is input to the LPF 1, it is amplified by the amplifier circuit composed of the operational amplifier A1 and the resistors R1 and R2, and is integrated by the integration capacitor C1. At this time, after a predetermined waiting time sufficiently considering the time constant of the integration capacitor C1 so that the amount of charge charged in the integration capacitor C1 is constant, the A / D conversion from the CPU 4 via the data acquisition control circuit 3 The strobe signal is sent to the device 2, and the output binarized data of the A / D converter 2 is acquired by the data acquisition control circuit 3 at the timing. The binarized data of the data acquisition control circuit 3 is further sent to the CPU 4.

  Prior art documents related to the average current measuring circuit include the following.

JP 2003-121503 A

  According to the circuit of FIG. 3, the LPF 1 does not have a circuit for discharging the integration capacitor C1, so that when the binarized data acquisition is completed, the integration capacitor C1 remains charged. Due to this residual charge amount, when the integration capacitor C1 is charged at the next IDD measurement, the charging time until the charge amount becomes constant varies.

  FIG. 4 is a time chart showing the change of the charge amount of the integration capacitor C1 with respect to the measurement time. When the difference in average current measured between the previous measurement and the current measurement is large (curve 5), the charging time is longer than when the difference is small (curve 6). That is, the charging time varies depending on the measurement value at the previous measurement. In the circuit of FIG. 3, in the device measurement program, the maximum (longest) value that can be considered in terms of hardware configuration is set as the strobe time (waiting time), so the difference in average current measured between the previous measurement and the current measurement is If it is small, a value larger than the originally required strobe time is set, leading to an increase in test time.

  The present invention is intended to solve such a problem, and provides an average current measurement circuit in which the test time does not become excessive when the difference between the measurement values at the previous measurement and the current measurement is small. Objective.

In order to achieve such a problem, an average current measuring circuit according to the invention described in claim 1 of the present invention includes:
In an average current measurement circuit in which a measurement current averaged by a low-pass filter circuit is binarized by an A / D converter, and the binarized data is acquired by a data acquisition control circuit at a predetermined timing and output as averaged data. ,
The data acquisition control circuit includes:
Obtaining the binarized data from the A / D converter at predetermined time intervals;
When a plurality of the binarized data acquired successively match in a predetermined upper bit, the binarized data acquired most recently is output as averaged data.

The invention according to claim 2
The average current measuring circuit according to claim 1,
The CPU acquires the averaged data from the data acquisition circuit in response to an interrupt signal from the data acquisition circuit.

The invention described in claim 3
The average current measuring circuit according to claim 1 or 2,
The plurality is two.

The invention according to claim 4
The average current measuring circuit according to any one of claims 1 to 3,
The measurement current is a power consumption current of the device.

  As is apparent from the above description, according to the present invention, the measurement current averaged by the low-pass filter circuit is binarized by the A / D converter, and the binarized data is subjected to data acquisition control at a predetermined timing. In the average current measurement circuit that the circuit acquires and outputs as averaged data, the data acquisition control circuit acquires the binarized data from the A / D converter at predetermined time intervals and continuously acquires the data. When a plurality of the binarized data match at a predetermined upper bit, the latest binarized data is output as averaged data, so that the difference in measured value between the previous measurement and the current measurement is It is possible to provide an average current measurement circuit in which the test time does not become excessive when it is small.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  FIG. 1 is a block diagram showing an example of an average current measuring circuit according to an embodiment of the present invention. The same parts as those in FIG. 3 are denoted by the same reference numerals, and different parts will be mainly described. The CPU 14 sends a start signal to the data acquisition control circuit 13 to start average current measurement, and receives an interrupt signal from the data acquisition control circuit 13 to acquire binary data. The data acquisition control circuit 13 is composed of an FPGA (Field Programmable Gate Array), sends a relay control signal to the relay RL1 using a start signal sent from the CPU 14 as a trigger, and prepares a measurement system for measuring the average current. In addition to sending a strobe signal to the A / D conversion circuit 2 to obtain binary data after A / D conversion and outputting an interrupt signal to the CPU 14, it has a binary data comparison determination function and a timeout processing function. .

  The operation of the average current measuring circuit having the configuration of FIG. 1 will be described below with reference to the flowchart of FIG.

First, the CPU 14 sets a timeout time (step S1).

When a start signal is sent from the CPU 14 to the data acquisition circuit 13 (step S2), the data acquisition circuit 13 turns on the relay RL1 of the LPF 1 using this as a trigger (step S3), so that the integration capacitor C1 is in parallel with the resistor R2. The connected LPF 1 constitutes a low-pass filter.

Here, when the IDD detection signal Vin corresponding to the power consumption current IDD of the device is input to the LPF 1, it is amplified by the amplifier circuit composed of the operational amplifier A1 and the resistors R1 and R2, and is integrated by the integration capacitor C1.

In this state, a strobe signal is sent from the data acquisition control circuit 13 to the A / D converter 2 at regular time intervals (step S4), and the output binary data of the A / D converter 2 is subjected to data acquisition control at each timing. The data is taken into the circuit 13 (step S5).

The data acquisition control circuit 13 compares the acquired binarized data with the previously acquired binarized data, and determines whether or not the values of the upper bits ignoring the predetermined lower-order bits match (step S6). ).

If the values are different, the strobe signal is output from the data acquisition control circuit 13 to the A / D converter 2 at regular time intervals (step S4), and the binarized data is taken into the data acquisition control circuit 13. (Step S5).

The data acquisition control circuit 13 compares the acquired binarized data with the previously acquired binarized data, and determines whether the values match as in the previous time (step S6). The above operation is repeated until the values of the binarized data match.

When the values match, an interrupt signal is output to the CPU 14 and the relay RL1 of the LPF 1 is turned off, and the LPF 1 is switched from the low-pass filter to the amplifier circuit (step S7).

Receiving the interrupt signal, the CPU 14 receives the latest binarized data as averaged data from the data acquisition control circuit 13 (step S9).

If the value does not converge by the time-out time, the data acquisition control circuit 13 performs time-out processing (step S10), and outputs an error interrupt signal to the CPU 14 (step S11).

The CPU 14 recognizes the error and displays an alarm or a predetermined error display (step S12).

Note that the integration capacitor C1 after the measurement has been charged with the charge as in the conventional circuit.

The aforementioned “predetermined lower-order bits” corresponds to a portion below the accuracy obtained by the waiting time in consideration of the time constant of the LPF 1 in the data acquisition control circuit 13 of the conventional circuit. For example, when the accuracy obtained in the conventional circuit is ± 0.05%, the lower 5 bits of the 16-bit A / D converter correspond to this.

According to the average current measurement circuit configured as described above, the optimum strobe value is automatically detected by hardware, thereby shortening the test time when the difference between the previous measurement and the current measurement is small. be able to. For example, the strobe value for the average current measurement is normally set to a constant multiple of LPF1 time constant (about 100 ms), but only if there is almost no difference between the previous measurement and the current measurement. Since the measurement time is close to 0 ms, the time-saving effect is close to 100 ms per average current. Usually, in the device test program, the device power supply current is often measured for 10 to 20 tests, so that a time-saving effect of about 1 to 2 seconds can be expected. This is a great time-saving effect when measuring a large number of devices.

Further, in the conventional circuit, the CPU 4 operates a timer during the average current measurement, and there is a waiting time during which another process cannot be performed. In the above embodiment, the average current value is acquired by hardware. Since the CPU 14 is interrupted, the CPU 14 can perform another process during the average current measurement. Therefore, it is possible to contribute to speeding up the software processing.

In addition, it is applicable not only to a semiconductor test apparatus but to all apparatuses that measure an average current using a low-pass filter.

Moreover, not only an amplification integration circuit but any kind of low-pass filter circuit can be used.

In the above embodiment, the latest binarized data is used as the averaged data when the two binarized data continuously acquired by the data acquisition control circuit 13 match. Matching of a plurality of arbitrary data as described above may be detected. In this case, the accuracy of the averaged data can be further improved.

It is a block diagram showing an example of an average current measurement circuit according to an embodiment of the present invention. 2 is a flowchart showing the operation of the circuit of FIG. It is a block diagram showing a conventional average current measurement circuit. FIG. 4 is a time chart showing a change with respect to a measurement time of a charge amount of an integration capacitor C1 in the circuit of FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Low pass filter circuit 2 A / D converter 13 Data acquisition control circuit 14 CPU
IDD measurement current

Claims (4)

In an average current measurement circuit in which a measurement current averaged by a low-pass filter circuit is binarized by an A / D converter, and the binarized data is acquired by a data acquisition control circuit at a predetermined timing and output as averaged data. ,
The data acquisition control circuit includes:
Obtaining the binarized data from the A / D converter at predetermined time intervals;
An average current measurement circuit characterized in that, when a plurality of the binarized data acquired successively match in predetermined upper bits, the binarized data acquired the latest is output as averaged data. The average current measurement circuit according to claim 1, wherein the CPU acquires the averaged data from the data acquisition circuit in response to an interrupt signal from the data acquisition circuit. The average current measuring circuit according to claim 1, wherein the plurality is two. The average current measurement circuit according to claim 1, wherein the measurement current is a power consumption current of a device.

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