JP2015133523A - Electronic component - Google Patents

Abstract

PROBLEM TO BE SOLVED: To secure flatness of an upper surface of a conductor pattern of the uppermost layer by suppressing height variation of each conductor layer when laminating conductor patterns.SOLUTION: An electronic component includes: a first conductor layer including a first conductor pattern P1; a first insulating layer covering the first conductor layer; a first opening h1 which penetrates the first insulating layer to expose an upper surface and a side surface of the first conductor pattern P1; and a second conductor layer which is provided on the first insulating layer and includes a second conductor pattern P2 connected to the first conductor pattern P1 through the first opening h1. A first opening region being a plane region inside the first opening h1 has a first region where the first conductor pattern P1 is formed and a second region where the first conductor pattern P1 is not formed. The second conductor pattern P2 is embedded in both the first region and the second region of the first opening h1.

Description

  The present invention relates to an electronic component and a method for manufacturing the same, and more particularly to the structure of a coil component such as a common mode filter.

  A common mode filter, which is one of electronic components, is widely used as a noise countermeasure component for differential transmission lines. Due to recent advances in manufacturing technology, common mode filters are also provided as extremely small surface-mounted chip components (see, for example, Patent Document 1), and coil patterns can also be made very small and spaced apart. ing. However, since the direct current resistance increases if the coil pattern is too thin, it is desired to form the planar coil pattern as thick as possible to prevent the direct current resistance from increasing.

JP 2011-14747 A

  In the common mode filter, other conductor patterns such as contact hole conductors and internal terminal electrodes are formed on the same plane as the planar coil pattern. When the coil pattern is to be formed thick by plating, the plating conditions are optimized according to the coil pattern. However, if a coil pattern and another conductor pattern are formed simultaneously under such plating conditions, the plating growth of other conductor patterns having a relatively large area proceeds excessively, and the height of the conductor pattern within the same conductor layer is increased. There is a problem that the variation becomes large.

  In particular, as shown in FIG. 12A, in the case of the conductor pattern 32 having a width (large area) slightly larger than the coil pattern 31, there is a tendency that the central portion of the upper surface of the conductor pattern 32 becomes a raised convex pattern. It is done. Also, as shown in FIG. 12B, in the case of the conductor pattern 33 having a very wide width (large area) compared to the coil pattern 31, the vicinity of the outer peripheral portion of the upper surface of the conductor pattern 33 is raised and the center portion is reversed. There is a tendency for the concave pattern to sink.

  As shown in FIGS. 12A and 12B, such a variation in the thickness of the conductor pattern becomes more prominent as the thickness of the coil pattern 31 increases, and is further emphasized by overlapping the layers. If an attempt is made to realize a multilayer structure by laminating conductor layers having height variations as they are, the flatness of the upper surface of the uppermost conductor pattern is significantly deteriorated due to the accumulation of height variations, and the uppermost conductor pattern P2 becomes an insulating layer. It may be exposed from the top surface of the metal and cause insulation failure.

  Further, when the insulating layer covering the conductor pattern is exposed to form an opening, if the upper surface of the conductor pattern serving as the underlying surface has bumps or sinks, it causes irregular reflection of light on the upper surface, causing the exposure apparatus to defocus. As a result, there is a problem that the pattern processing accuracy deteriorates. For the above reasons, it is preferable that all the conductor patterns in the conductor layer have almost the same height as the coil pattern and that the upper surface is flat, and countermeasures are desired.

  Accordingly, an object of the present invention is to provide an electronic component capable of suppressing the height variation of the upper surface of the conductor pattern of each conductor layer when the conductor patterns are laminated, and a manufacturing method thereof.

  In order to solve the above-described problems, an electronic component according to the present invention includes a first conductor layer including a first conductor pattern, a first insulating layer covering the first conductor layer, and the first insulating layer. A first opening penetrating through and exposing an upper surface and a side surface of the first conductor pattern; and provided on the first insulating layer; and through the first opening, the upper surface of the first conductor pattern and the first conductor pattern And a second conductor layer including a second conductor pattern connected to both of the side surfaces, wherein the first conductor pattern is formed in a first opening region which is a planar region inside the first opening. And a second region where the first conductor pattern is not formed, and the second conductor pattern includes the first region of the first opening and the first region. It is characterized by being embedded in both areas.

  According to the present invention, the first conductor pattern is formed so that the first opening region has a concavo-convex pattern opposite to the final concavo-convex shape, and the second conductor pattern is formed thereon. The uneven shape of the upper layer and the uneven shape of the upper layer can be offset, the variation in the height of the conductor pattern of each conductor layer can be suppressed, and the upper surface of the second conductor pattern can be made as flat as possible. Moreover, since the upper conductor pattern can be connected to the side surface of the lower conductor pattern, the bonding strength between the two can be improved.

  In the present invention, the first region is a region excluding at least the central portion of the opening region, and the second region is a region excluding the first region of the opening region. It is preferable. In this case, it is preferable that the first conductor pattern is a closed loop pattern or a U-shaped pattern, and the second region includes a region inside the closed loop pattern or the U-shaped pattern. When the conductor formation area is a little wide, the central portion of the upper surface of the uppermost conductor pattern tends to rise. However, when the shape of the first conductor pattern is as described above, the concave shape of the lower layer and the convex shape of the upper layer can be offset, and the variation in the height of the conductor pattern of each conductor layer can be suppressed. It is possible to make the upper surface of the upper conductor pattern as flat as possible.

  In the present invention, the second region is a region obtained by removing at least the central portion from the opening region, and the first region is a region obtained by removing the second region from the opening region. preferable. In this case, it is preferable that the first conductor pattern is an island pattern, and the second region includes a region around the island pattern. When the conductor formation area is very large, the vicinity of the outer peripheral portion of the upper surface of the upper conductor pattern is raised, and the central portion tends to sink. However, when the shape of the first conductor pattern is as described above, the convex shape of the lower layer and the concave shape of the upper layer can be offset, and the variation in the height of the conductor pattern of each conductor layer can be suppressed. It is possible to make the upper surface of the upper conductor pattern as flat as possible.

  The first conductor layer preferably further includes a planar coil pattern. In this case, it is particularly preferable that the planar coil pattern is a spiral conductor, and the first conductor pattern is connected to an inner peripheral end or an outer peripheral end of the spiral conductor. If an attempt is made to increase the thickness of a planar coil pattern such as a spiral conductor in order to reduce the DC resistance, the uneven shape of the first conductor pattern formed on the same plane as this is more emphasized, and the first conductor pattern located on the upper layer is emphasized. The uneven shape of the conductor pattern 2 becomes more prominent. However, when the shape of the first conductor pattern is as described above, the concave shape of the lower layer and the convex shape of the upper layer can be offset, and the upper surface of the upper conductor pattern can be made as flat as possible. .

  The electronic component according to the present invention includes a second insulating layer that covers the second conductor layer, and a second opening that penetrates the second insulating layer and exposes an upper surface and side surfaces of the second conductor pattern. A third conductor pattern provided on the second insulating layer and connected to both an upper surface and a side surface of the second conductor pattern through the second opening, and the inner side of the second opening. The second opening region, which is a planar region, has a portion overlapping the first region in plan view, a third region in which the second conductive pattern is formed, and the second conductive pattern And the third region has a size different from that of the first region, and the third conductor pattern includes the second region of the second opening. It is preferable to be embedded in both the third region and the fourth region. In the case of the three-layer structure, the uneven shape of the uppermost conductor pattern becomes more prominent, but according to the present invention, the uneven shape of the lower layer and the uneven shape of the upper layer can be offset, and the third conductor pattern The top surface can be made as flat as possible. Moreover, since the upper conductor pattern can be connected to the side surface of the lower conductor pattern, the bonding strength between the two can be improved.

  In the present invention, it is preferable that the first conductor layer further includes a first spiral conductor, and the second conductor layer further includes a second spiral conductor that is magnetically coupled to the first spiral conductor. . According to this configuration, in a common mode filter having a laminated structure of two spiral conductors, it is possible to reduce the variation in the height of the conductor pattern and improve the connection reliability.

  The method for manufacturing an electronic component according to the present invention includes a step of forming a first conductor layer including a first conductor pattern, a step of forming a first insulating layer covering the first conductor layer, Forming a first opening in the first insulating layer such that an upper surface and a side surface of the first conductor pattern are exposed; and a second conductor including a second conductor pattern on the first insulating layer Forming a layer and connecting the second conductor pattern to the first conductor pattern through the first opening, the first opening region being a planar region inside the first opening Has a first region in which the first conductor pattern is formed and a second region in which the first conductor pattern is not formed, and the second conductor pattern includes the first conductor pattern. Embedded in both the first region and the second region of the opening; And features.

  According to the present invention, the first conductor pattern is formed so that the first opening region has a concavo-convex pattern opposite to the final concavo-convex shape, and the second conductor pattern is formed thereon. The uneven shape of the upper layer and the uneven shape of the upper layer can be offset, and the upper surface of the second conductor pattern can be made as flat as possible. Moreover, since the upper conductor pattern can be connected to the side surface of the lower conductor pattern, the bonding strength between the two can be improved.

  In the present invention, it is preferable that the step of forming the first conductor layer includes a step of forming a planar coil pattern together with the first conductor pattern. If an attempt is made to increase the thickness of a planar coil pattern such as a spiral conductor in order to reduce the DC resistance, the uneven shape of the first conductor pattern formed on the same plane as this is more emphasized, and the first conductor pattern located on the upper layer is emphasized. The uneven shape of the conductor pattern 2 becomes more prominent. However, when the shape of the first conductor pattern is as described above, the concave shape of the lower layer and the convex shape of the upper layer can be offset, and the variation in the height of the conductor pattern of each conductor layer can be suppressed. It is possible to make the upper surface of the upper conductor pattern as flat as possible.

  ADVANTAGE OF THE INVENTION According to this invention, when laminating | stacking a conductor pattern, the upper surface of the conductor pattern can provide the electronic component which can make the upper surface flat as much as possible without a depression | depression, and its manufacturing method. .

FIG. 1 is a schematic perspective view showing the structure of a coil component 1 which is an electronic component according to the first embodiment of the present invention. FIG. 2 is a schematic exploded perspective view showing the layer structure of the coil component 1 in detail. FIG. 3 is an exploded plan view showing each layer of the coil component 1. FIGS. 4A to 4C are schematic cross-sectional views showing a two-layer laminated structure of a conductor pattern for preventing the uppermost layer from being raised. FIG. 5 is a schematic cross-sectional view showing a laminated structure of four layers of conductor patterns for preventing the uppermost layer from being raised. 6A to 6F are schematic plan views showing modifications of the planar layout of the lower-layer conductor pattern shown in FIG. FIGS. 7A to 7C are schematic cross-sectional views showing a two-layer laminated structure of a conductor pattern for preventing the uppermost layer from sinking. FIG. 8 is a schematic cross-sectional view showing a laminated structure of four layers of conductor patterns for preventing the uppermost layer from being raised. FIG. 9 is a schematic plan view showing another example of the planar layout of each conductor layer. FIG. 10 is a schematic plan view showing a planar layout of the collective substrate. FIG. 11 is a flowchart showing a method for manufacturing the coil component 1. 12 (a) and 12 (b) are schematic cross-sectional views showing a conventional laminated structure of conductor patterns.

  Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

  FIG. 1 is a schematic perspective view showing the structure of a coil component 1 which is an electronic component according to the first embodiment of the present invention.

  As shown in FIG. 1, the coil component 1 according to the present embodiment is a common mode filter, and includes a substrate 10 and a thin film coil layer 11 including a common mode filter element provided on one main surface (upper surface) of the substrate 10. And the first to fourth bump electrodes 12a to 12d provided on the main surface (upper surface) of the thin film coil layer 11 and the main surface of the thin film coil layer 11 excluding the formation positions of the bump electrodes 12a to 12d. And a magnetic resin layer 13.

  The coil component 1 is a substantially rectangular parallelepiped surface-mounted chip component having two side surfaces 10a and 10b parallel to the longitudinal direction (X direction) and other two side surfaces 10c and 10d orthogonal to the longitudinal direction. Yes. The first to fourth bump electrodes 12 a to 12 d are provided at the corners of the coil component 1, and are formed so that the outer peripheral surface of the coil component 1 also has an exposed surface. Among these, the first bump electrode 12a has an exposed surface on both the side surface 10a and the side surface 10c, and the second bump electrode 12b has an exposed surface on both the side surface 10b and the side surface 10c. The third bump electrode 12c has an exposed surface on both the side surface 10a and the side surface 10d, and the fourth bump electrode 12d has an exposed surface on both the side surface 10b and the side surface 10d. It should be noted that, when mounted, it is turned upside down and used with the bump electrodes 12a to 12d facing downward.

  The substrate 10 serves as a closed magnetic circuit for the common mode filter while ensuring the mechanical strength of the coil component 1. As a material of the substrate 10, for example, a magnetic ceramic material such as sintered ferrite can be used. Although not particularly limited, when the chip size is 0605 type (0.6 × 0.5 × 0.5 (mm)), the thickness of the substrate 10 is about 0.1 to 0.3 mm. be able to.

  The thin film coil layer 11 is a layer including a common mode filter element provided between the substrate 10 and the magnetic resin layer 13. As will be described in detail later, the thin film coil layer 11 has a multilayer structure formed by alternately laminating insulating layers and conductor patterns. Thus, the coil component 1 according to the present embodiment is a so-called thin film type, and is distinguished from a winding type having a structure in which a conductive wire is wound around a magnetic core.

  The magnetic resin layer 13 is a layer that constitutes the mounting surface (bottom surface) of the coil component 1, protects the thin film coil layer 11 together with the substrate 10, and plays a role as a closed magnetic circuit of the coil component 1. However, since the mechanical strength of the magnetic resin layer 13 is smaller than that of the substrate 10, it has an auxiliary role in terms of strength. As the magnetic resin layer 13, an epoxy resin (composite ferrite) mainly containing ferrite powder can be used. Although not particularly limited, when the chip size is 0605 type, the thickness of the magnetic resin layer 13 can be about 0.02 to 0.1 mm.

  FIG. 2 is a schematic exploded perspective view showing the layer structure of the coil component 1 in detail. FIG. 3 is an exploded plan view showing each layer.

  As shown in FIG. 2, the thin film coil layer 11 is formed on the first insulating layer 15 a and the first to fourth insulating layers 15 a to 15 d that are sequentially stacked from the substrate 10 side toward the magnetic resin layer 13 side. A first conductor layer including the formed first spiral conductor 16 and internal terminal electrodes 24a to 24d, and a second spiral conductor 17 and internal terminal electrodes 24a to 24d formed on the second insulating layer 15b are provided. And a second conductor layer including the first and second lead conductors 20 and 21 and internal terminal electrodes 24a to 24d formed on the third insulating layer 15c. Bump electrodes 12a to 12d are provided on the fourth insulating layer 15d, and conductor patterns such as internal terminal electrodes are not formed.

  The first to fourth insulating layers 15a to 15d serve to insulate conductor patterns provided in different conductor layers and ensure flatness of a plane on which the conductor patterns are formed. In particular, the first insulating layer 15a serves to absorb irregularities on the surface of the substrate 10 and increase the processing accuracy of the spiral conductor pattern. As the material for the insulating layers 15a to 15d, it is preferable to use a resin that is excellent in electrical and magnetic insulating properties and easy to finely process, and is not particularly limited, but a polyimide resin or an epoxy resin is used. Can do.

  The inner peripheral end 16a of the first spiral conductor 16 has a first contact hole conductor 18, a first lead conductor 20, and a first internal terminal electrode 24a penetrating the second and third insulating layers 15b and 15c. And is connected to the first bump electrode 12a. The outer peripheral end 16b of the first spiral conductor 16 is connected to the second bump electrode 12b through the second internal terminal electrode 24b.

  The inner peripheral end 17a of the second spiral conductor 17 is connected to the fourth contact hole conductor 19, the second lead conductor 21, and the fourth internal terminal electrode 24d that penetrate the third insulating layer 15c. Is connected to the bump electrode 12d. Further, the outer peripheral end 17b of the second spiral conductor 17 is connected to the third bump electrode 12c through the third internal terminal electrode 24c.

  The first and second spiral conductors 16 and 17 have substantially the same planar shape, and are provided at the same position in plan view. Since the first and second spiral conductors 16 and 17 overlap each other, a strong magnetic coupling is generated between them. The first spiral conductor 16 is counterclockwise from the inner peripheral end 16a to the outer peripheral end 16b, and the second spiral conductor 17 is also counterclockwise from the outer peripheral end 17b to the inner peripheral end 17a. Therefore, the direction of the magnetic flux generated by the current flowing from the first bump electrode 12a toward the second bump electrode 12b and the magnetic flux generated by the current flowing from the third bump electrode 12c toward the second bump electrode 12d. The direction of is the same, and the overall magnetic flux is strengthened. With the above configuration, the conductor pattern in the thin film coil layer 11 forms a common mode filter.

  The outer shapes of the first and second spiral conductors 16 and 17 are both circular spirals. The circular spiral conductor can be preferably used as a high-frequency inductance because the high-frequency signal component is less attenuated. In addition, although the spiral conductors 16 and 17 by this embodiment are ellipses, they may be a perfect circle and an ellipse. Moreover, it may be substantially rectangular.

  The first and second spiral conductors 16 and 17 preferably have a certain thickness in order to reduce their DC resistance. The aspect ratio (height / width) of the cross section of the spiral conductor is preferably 1 or more.

  In the central region of the first to fourth insulating layers 15a to 15d and inside the first and second spiral conductors 16 and 17, an opening hg penetrating the first to fourth insulating layers 15a to 15d is formed. A through-hole magnetic body 14 for forming a magnetic path is provided inside the opening hg. The through-hole magnetic body 14 is preferably made of the same material as the magnetic resin layer 13 and formed integrally therewith.

  The first and second lead conductors 20 and 21 are formed on the surface of the third insulating layer 15c. One end of the first lead conductor 20 is connected to the upper end of the contact hole conductor 18, and the other end is connected to the internal terminal electrode 24a. One end of the second lead conductor 21 is connected to the upper end of the contact hole conductor 19, and the other end is connected to the internal terminal electrode 24d.

  First to fourth bump electrodes 12 a to 12 d are provided on the fourth insulating layer 15 d constituting the surface layer of the thin film coil layer 11, respectively. The first to fourth bump electrodes 12a to 12d are external terminal electrodes and are connected to the internal terminal electrodes 24a to 24d, respectively. In the present specification, the “bump electrode” is a thick film plating electrode formed by a plating process, different from the one formed by thermocompression bonding of metal balls such as Cu and Au using a flip chip bonder. Means. The thickness of the bump electrode is equal to or greater than the thickness of the magnetic resin layer 13 and can be about 0.02 to 0.1 mm. That is, the thickness of the bump electrodes 12 a to 12 d is thicker than the conductor pattern in the thin film coil layer 11, and in particular, has a thickness five times or more that of the spiral conductor pattern in the thin film coil layer 11.

  The planar shapes of the first to fourth bump electrodes 12a to 12d are substantially the same. According to this configuration, since the bump electrode pattern on the bottom surface of the coil component 1 has symmetry, it is possible to provide a terminal electrode pattern having a good appearance without restrictions on the mounting direction.

  A magnetic resin layer 13 is formed on the fourth insulating layer 15d together with the first to fourth bump electrodes 12a to 12d. The magnetic resin layer 13 is provided so as to fill the periphery of the bump electrodes 12a to 12d. The side surfaces of the bump electrodes 12a to 12d that are in contact with the magnetic resin layer 13 are preferably curved surfaces having no edges. The magnetic resin layer 13 is formed by pouring a composite ferrite paste after forming the bump electrodes 12a to 12d. At this time, if there are corners with edges on the side surfaces of the bump electrodes 12a to 12d, the bump electrode is formed. The paste is not completely filled around and tends to contain air bubbles. However, when the side surfaces of the bump electrodes 12a to 12d are curved surfaces, the fluid resin spreads to every corner, so that the dense magnetic resin layer 13 containing no bubbles can be formed. In addition, since the adhesion between the magnetic resin layer 13 and the bump electrodes 12a to 12d is increased, the reinforcement to the bump electrodes 12a to 12d can be enhanced.

  The second insulating layer 15 b is further provided with openings ha to hd corresponding to the first to fourth internal terminal electrodes 24 a to 24 d and an opening he corresponding to the first contact hole conductor 18. The openings ha to he are provided to ensure electrical connection between the upper and lower conductor layers. Part of the internal terminal electrodes 24a to 24d formed on the second insulating layer 15b is embedded in the openings ha to hd of the second insulating layer 15b provided immediately below the internal terminal electrodes 24a to 24d (FIG. 4 ( b)), thereby being electrically connected to the internal terminal electrodes 24a to 24d on the first insulating layer 15a. Note that the openings ha to hd corresponding to the internal terminal electrodes are not provided in the first insulating layer 15a.

  The third insulating layer 15c is further provided with an opening hf corresponding to the second contact hole conductor 19 in addition to the openings ha to he. Part of the internal terminal electrodes 24a to 24d formed on the third insulating layer 15c is embedded in the openings ha to hd of the third insulating layer 15c provided immediately below the internal terminal electrodes 24a to 24d (FIG. 4 ( b)), thereby being electrically connected to the internal terminal electrodes 24a to 24d on the second insulating layer 15b.

  Although the openings ha to hd are provided in the fourth insulating layer 15d, the openings he and hf corresponding to the first and second contact hole conductors 18 and 19 are not provided. Part of the bump electrodes 12a to 12d is embedded in the openings ha to hd of the fourth insulating layer 15d. Thus, the bump electrodes 12a to 12d are connected to the upper surfaces of the internal terminal electrodes 24a to 24d on the third insulating layer 15c through the openings ha to hd formed in the fourth insulating layer 15d, respectively.

  As shown in FIG. 3, the contact hole conductors 18 and 19 and the internal terminal electrodes 24a to 24d formed on the third insulating layer 15c are formed on the entire surface of the desired formation region. On the other hand, the contact hole conductors 18 and 19 and the internal terminal electrodes 24a to 24d formed on the second insulating layer 15b are conductors in the central portion as compared with those formed on the third insulating layer 15c. The donut shape is eliminated. Further, the contact hole conductors 18 and 19 and the internal terminal electrodes 24a to 24d formed on the first insulating layer 15a, which is the lower layer, have a conductor width of the loop as compared with that formed on the second insulating layer 15b. Is thin (the area of the central conductor non-forming region is large).

  Since the contact hole conductors 18 and 19 and the internal terminal electrodes 24a to 24d are conductor patterns having a relatively large area, plating is likely to grow at the center thereof, and desired contact layers in all the conductor layers from the bottom layer to the top layer. If it is formed on the entire surface of the formation region, an increase in the thickness of the conductor pattern is emphasized, and a bulge tends to occur on the upper surface of the uppermost conductor pattern. In particular, when the thickness of the spiral conductors 16 and 17 is increased in order to reduce the direct current resistance (the aspect ratio is increased), the contact hole conductors 18 and 19 and the internal terminal electrodes 24a to 24d formed at the same time are also increased in thickness. The in-plane variation tends to be large. That is, the upper surface of the uppermost conductor pattern is prominent. However, the flatness of the upper surface of the uppermost layer can be improved by providing a cavity at the center in the planar direction of the lower conductor pattern as in this embodiment and gradually reducing the plane size of the cavity as the upper layer is formed. .

  Hereinafter, a laminated structure of conductor patterns for preventing the uppermost layer from rising will be described in detail.

  4A to 4C are schematic cross-sectional views showing a laminated structure of two layers of a conductor pattern for preventing the uppermost layer from being raised, and FIG. 4A is a diagram of the conductor pattern of the lower layer (first layer). The planar shape, (b) is the planar shape of the upper layer (second layer) conductor pattern, and (c) is a cross-sectional view taken along line X1-X1 ′ in (a) and (b). In the following example, the shape of the conductor pattern is a rectangle, but the planar shape of the conductor pattern is limited to a rectangle like the contact hole conductors 18 and 19 and the internal terminal electrodes 24a to 24d shown in FIGS. However, it can be arbitrarily set according to its function and arrangement.

  As shown in FIGS. 4A to 4C, the conductor pattern P1 (first conductor pattern) of the lower layer (first conductor layer LC1) is formed in a predetermined conductor formation region S1, and its plane The shape is a donut shape (closed loop shape) having a cavity C1 at the center thereof. The periphery of the conductor pattern P1 is covered with an insulating layer LI1, and is exposed from an opening h1 (first opening) that penetrates the insulating layer LI1.

  In FIG. 4A, a planar region (first opening region) inside the opening h1 indicated by a broken line is formed by a region (first region) where the conductor pattern P1 indicated by hatching is formed and the conductor pattern P1. And a region that is not formed (second region). The first region is a region of the first opening region excluding the central cavity C1 and the second region is the region of the opening region excluding the first region, that is, the cavity C1. It is.

  The conductor pattern P2 (second conductor pattern) of the upper layer (second conductor layer LC2) provided so as to overlap the conductor pattern P1 of the lower layer is formed on the entire surface of the conductor formation region S2, and the conductor pattern P2 is viewed in plan view. And covers the entire surface of the conductor pattern P1. A part of the conductor pattern P2 is also embedded inside the central cavity C1 of the conductor pattern P1. That is, the conductor pattern P2 is embedded in both the first region and the second region of the opening h1. An insulating layer LI2 is filled around the conductor pattern P2.

  As shown in FIG. 12A, when the conductor pattern of each conductor layer is formed on the entire surface of the formation region, the bulge is likely to occur due to the concentration of the plating current, and the bulge is more emphasized as it goes to the upper layer. It becomes a shape. However, as shown in FIG. 4, when the hollow portion C1 is provided at the center of the lower conductor pattern P1 and the center of the conductor pattern P1 is depressed, the depression of the lower layer and the bulge of the upper layer are offset. The upper surface of the upper conductor pattern P2 can be made substantially flat.

  In the formation of the laminated structure shown in FIG. 4, first, the conductor pattern P1 is formed in the first conductor formation region S1, the insulating layer LI1 is formed thereon, the opening h1 is formed in the insulating layer LI1, and the conductor pattern P1 is formed. To expose. At this time, the upper surface and the side surface of the conductor pattern P1 are exposed from the opening h1. Next, the conductor pattern P2 is formed in the second conductor formation region S2 that overlaps the first conductor formation region S1 in plan view on the upper surface of the insulating layer LI1. The conductor pattern P2 is formed so as to cover the entire surface of the conductor pattern P1 in plan view, thereby connecting the first conductor pattern P1 and the second conductor pattern P2.

  FIG. 5 is a schematic cross-sectional view showing a laminated structure of four layers of conductor patterns for preventing the uppermost layer from being raised.

  As shown in FIG. 5, when the number of conductor patterns is further increased, the area of the hollow portion of the conductor pattern may be gradually reduced toward the upper layer. That is, the planar shapes of the first to third layers of conductor patterns P1 to P3 are donut shapes each having a cavity C1 to C3 at the center thereof, and the size of the cavity C2 of the second layer of conductor pattern P2 is one layer. The size of the cavity C3 of the third-layer conductor pattern P3 is smaller than that of the second layer and smaller than that of the second layer. The uppermost layer, the fourth conductor pattern P4, is formed on the entire surface of the formation region S4, and a part of the conductor pattern P4 is also embedded inside the cavity C3 of the conductor pattern P3. Even when the number of conductor patterns stacked in this way increases, the uppermost layer of the uppermost conductor pattern can be substantially flattened because the intentional depression of the lowermost layer is gradually flattened toward the upper layer.

  6A to 6F are schematic plan views showing modifications of the planar layout of the lower-layer conductor pattern shown in FIG.

  The lower conductor pattern P1 shown in FIGS. 6A and 6B is a closed loop pattern having a cavity C1 at the center of a rectangular pattern, as in FIG. 4A. Among these, in FIG. 6A, the opening h1 of the insulating layer LI2 formed in the upper layer of the conductor pattern P1 is accommodated inside without protruding outside the outer periphery of the conductor pattern P1. In FIG. 6B, the opening h1 formed in the upper insulating layer is formed so as to protrude outside the outer periphery of the conductor pattern P1. Here, the direction in which the opening h1 protrudes is a direction (Y direction) orthogonal to the longitudinal direction of the conductor pattern P1.

  The lower-layer conductor pattern P1 shown in FIGS. 6C and 6D is a substantially U-shaped pattern in which one side parallel to the longitudinal direction of the rectangular pattern is cut out. This U-shaped pattern can also be regarded as one of the patterns having the cavity C1 at the center of the rectangular pattern. Among these, FIG. 6C is formed so that the opening h1 formed in the upper insulating layer fits inside the outer periphery of the conductor pattern P1. In FIG. 6D, the opening h1 formed in the upper insulating layer is formed so as to protrude outside the outer periphery of the conductor pattern P1. Here, the direction in which the opening h1 protrudes is the direction in which the conductor pattern P1 is notched.

  The lower-layer conductor pattern P1 shown in FIGS. 6E and 6F is a substantially U-shaped pattern in which one side orthogonal to the longitudinal direction of the rectangular pattern is cut out. This U-shaped pattern can also be regarded as one of the patterns having the cavity C1 at the center of the rectangular pattern. Among these, in FIG. 6E, the opening h1 formed in the upper insulating layer is formed so as to fit inside the outer periphery of the conductor pattern P1. In FIG. 6F, the opening h1 formed in the upper insulating layer is formed so as to protrude outside the outer periphery of the conductor pattern P1. Here, the direction in which the opening h1 protrudes is the direction in which the conductor pattern P1 is notched.

  6 (a) to 6 (f), the lower conductor pattern P1 has a shape having a cavity C1 at the center thereof, and therefore, the upper conductor pattern provided to overlap the lower conductor pattern P1 is formed on the entire surface of the formation region. Even when the upper conductor pattern is formed, the upper surface of the upper conductor pattern is restrained from being raised, so that the upper surface of the uppermost conductor pattern can be made substantially flat. Further, since the upper conductor pattern is in contact with the side surface as well as the upper surface of the lower conductor pattern, the bonding strength between the two can be improved. In particular, in FIGS. 6B, 6D, and 6F, the opening h1 is widened to expose not only the inner side surface of the lower conductor pattern P1, but also the outer side surface. Can be improved.

  Next, the laminated structure of the conductor pattern for preventing the depression of the uppermost layer will be described in detail.

  FIGS. 7A to 7C are schematic cross-sectional views showing a laminated structure of two layers of a conductor pattern for preventing the depression of the uppermost layer, and FIG. 7A shows a conductor pattern of a lower layer (first layer). The planar shape, (b) is the planar shape of the upper layer (second layer) conductor pattern, and (c) is a cross-sectional view taken along line X1-X1 ′ in (a) and (b). In the following examples, the shape of the conductor pattern is rectangular, but the planar shape of the conductor pattern is limited to a rectangle like the contact hole conductors 18 and 19 and the internal terminal electrodes 24a to 24d shown in FIGS. However, it can be arbitrarily set according to its function and arrangement.

  As shown in FIGS. 7A to 7C, the conductor pattern P1 (first conductor pattern) of the lower layer (first conductor layer LC1) is formed in a predetermined conductor formation region S1, and its plane The shape is an island pattern formed only at substantially the center of the conductor formation region S1. The island pattern is not a solitary island pattern surrounded by an insulating region but a peninsula pattern. The island pattern is drawn out in one direction toward the outside of the formation region. Since the conductor pattern is formed only in the central part of the formation region, it can be said that the cavity C1 is provided around. The periphery of the conductor pattern P1 is covered with an insulating layer LI1, and is exposed from an opening h1 (first opening) that penetrates the insulating layer LI1.

  In FIG. 7A, a planar region (first opening region) inside the opening h1 indicated by a broken line is formed by a region (first region) where the conductor pattern P1 indicated by hatching is formed and the conductor pattern P1. And a region that is not formed (second region). The second region is a region excluding at least the central portion of the first opening region, that is, the cavity C1, and the first region is a region excluding the second region of the opening region.

  The conductor pattern P2 (second conductor pattern) of the upper layer (second conductor layer LC2) provided so as to overlap the conductor pattern P1 of the lower layer is formed on the entire surface of the conductor formation region S2, and the conductor pattern P2 is viewed in plan view. And covers the entire surface of the conductor pattern P1. A part of the conductor pattern P2 is also embedded in the cavity C1 around the conductor pattern P1. That is, the conductor pattern P2 is embedded in both the first region and the second region of the opening h1. An insulating layer LI2 is filled around the conductor pattern P2.

  As shown in FIG. 12B, when the conductor pattern of each conductor layer is formed on the entire surface of the wide formation region, a depression is likely to occur at the center, and the depression is emphasized as it goes to the upper layer. End up. However, as shown in FIG. 7, when the cavity C1 is provided around the lower conductor pattern P1 and the center of the conductor pattern P1 is relatively raised, the lower layer protrusion and the upper layer depression cancel each other. Therefore, the upper surface of the upper conductor pattern P2 can be made substantially flat.

  FIG. 8 is a schematic cross-sectional view showing a laminated structure of four layers of conductor patterns for preventing the uppermost layer from being raised.

  As shown in FIG. 8, when the number of conductor patterns stacked is larger, the area of the conductor pattern may be gradually increased toward the upper layer. That is, the planar shapes of the first to third layers of conductor patterns P1 to P3 are formed only at the center thereof, and are raised shapes having cavities C1 to C3 around them, respectively. The length is larger than that of the first layer, and the size of the conductive pattern P3 of the third layer is larger than that of the second layer. The uppermost layer, the fourth conductive pattern P4, is formed on the entire surface of the formation region S4, and a part of the conductive pattern P4 is also embedded in the cavity C3 around the conductive pattern P3. Even when the number of conductor patterns is increased in this way, the intentional bulge in the lowermost layer is gradually flattened toward the upper layer, so that the upper surface of the uppermost conductor pattern can be substantially flattened. .

  The in-plane variation in the height of the conductor pattern varies depending on the plane size. When the planar size (especially the minimum width) of the conductor pattern is a little wider than the line width of the spiral conductor, the central portion of the upper surface of the uppermost layer of the conductor pattern is likely to rise. However, when the planar size of the conductor pattern is sufficiently large, the central portion of the upper surface of the uppermost layer of the conductor pattern is likely to be depressed. If the area is too large, the plating current tends to flow to the end, so that the plating concentrates on the end and the thickness increases. Therefore, the end portion is raised and the center portion is relatively depressed. In any case, since the upper surface of the uppermost layer is not easily flattened by simply laminating the conductor patterns, the lower conductor pattern in the present invention has an appropriate shape (a bulge prevention pattern or a depression prevention pattern) shown below. This ensures the flatness of the top layer.

  Whether to use the ridge prevention pattern shown in FIGS. 4 to 6 or the depression prevention pattern shown in FIGS. 7 and 8 may be determined from the results of actual trial manufacture using a conventional method. For the conductor pattern having a width of about 1.5 to 4 times the line width of the spiral conductor, a “protrusion prevention pattern (closed loop pattern or U-shaped pattern)” is adopted, and the line width of the spiral conductor is adopted. For the conductor pattern having a width of four times or more, a “sag prevention pattern” may be adopted.

  The contact hole conductors 18 and 19 are formed within a very limited range inside the spiral conductors 16 and 17, and when the through-hole magnetic body 14 is provided, the formation range is further limited. Therefore, the area of the contact hole conductors 18 and 19 is relatively small, and the top layer is likely to be raised. Therefore, it is preferable to employ a bulge prevention pattern for the contact hole conductors 18 and 19.

  On the other hand, the internal terminal electrodes 24 a to 24 d are provided outside the spiral conductors 16 and 17 and can be formed larger than the contact hole conductors 18 and 19. Further, in a mass production process in which a large number of elements are formed on a collective substrate, when a large internal terminal electrode common to adjacent elements is formed, the area of the internal terminal electrode becomes very large. As described above, when the area of the internal terminal electrode is relatively large and the uppermost layer is likely to be depressed, it is preferable to employ a depression prevention pattern for the internal terminal electrodes 24a to 24d.

  However, when the loop size of the spiral conductors 16 and 17 is increased or the through-hole magnetic body 14 is omitted, the relatively large contact hole conductors 18 and 19 can be formed. It is better to adopt a depression prevention pattern for the conductors 18 and 19. In addition, when the loop size of the spiral conductors 16 and 17 is increased and the formation region of the internal terminal electrodes 24a to 24d is very limited, the area of the internal terminal electrodes 24a to 24d is reduced. It is better to adopt a bulge prevention pattern for the internal terminal electrodes 24a to 24d.

  FIG. 9 is a schematic plan view showing another example of the planar layout of each conductor layer. As shown in the figure, when the through-hole magnetic body 14 (see FIG. 3) inside the spiral conductors 16 and 17 is omitted and the size of the contact hole conductors 18 and 19 is increased, the contact hole conductors 18 and 19 are depressed. It is better to adopt a prevention pattern.

  FIG. 10 is a schematic plan view showing a planar layout of the collective substrate. As shown in the figure, when the internal terminal electrodes 24a to 24b are positioned at the corners of the four adjacent elements, they are formed as a unified terminal electrode BB, and the area thereof becomes very large. In this case, it is preferable to employ a depression prevention pattern for the collective terminal electrode BB.

  FIG. 11 is a flowchart showing a method for manufacturing the coil component 1.

  In manufacturing the coil component 1, first, a magnetic wafer is prepared (step S11), and the thin film coil layer 11 in which a number of common mode filter elements are laid out is formed on the surface of the magnetic wafer (step S12).

  The thin film coil layer 11 can be formed by repeating the process of forming a conductor pattern on the surface of the insulating layer after forming the insulating layer. Hereafter, the formation process of the thin film coil layer 11 is demonstrated in detail.

  In the formation of the thin film coil layer 11, the insulating layer 15a is first formed, and then the first spiral conductor 16 and the internal terminal electrodes 24a to 24d are formed on the insulating layer 15a. Next, after forming the insulating layer 15b on the insulating layer 15a, the second spiral conductor 17 and the internal terminal electrodes 24a to 24d are formed on the insulating layer 15b. Next, after forming the insulating layer 15c on the insulating layer 15b, the first and second lead conductors 20 and 21 and the internal terminal electrodes 24a to 24d are formed on the insulating layer 15c. Further, an insulating layer 15d is formed on the insulating layer 15c (see FIG. 2).

  Here, each of the insulating layers 15a to 15d can be formed by spin coating a photosensitive resin or a photosensitive resin film on a base surface, and exposing and developing the same. In particular, the opening hg is formed in the first insulating layer 15a, the openings ha to he and hg are formed in the second insulating layer 15b, and the openings ha to hg are formed in the third insulating layer 15c. Openings ha to hd and an opening hg are formed in the fourth insulating layer 15d.

  Cu is preferably used as the material for the conductor pattern. The conductor pattern is formed by forming a conductor layer by vapor deposition or sputtering, then forming a patterned resist layer thereon, applying electroplating thereto, and removing the resist layer and unnecessary underlying conductor layers. be able to.

  At this time, the insides of openings (through holes) he and hf for forming the contact hole conductors 18 and 19 are filled with the plating material, whereby the contact hole conductors 18 and 19 are formed. Moreover, the insides of the openings ha to hd for forming the internal terminal electrodes 24 a to 24 b are also filled with a plating material, thereby forming the internal terminal electrodes 24 a to 24 d.

  Next, the bump electrode 12 that is an aggregate of the bump electrodes 12a to 12d is formed on the insulating layer 15d that is the surface layer of the thin film coil layer 11 (step S13). The bump electrode 12 is formed by first forming a base conductor layer on the entire surface of the insulating layer 15d by sputtering. Cu or the like can be used as the material for the underlying conductor layer. Thereafter, the dry film is attached, exposed and developed to selectively remove the dry film at the position where the bump electrodes 12a to 12d and the first and second lead conductors 20 and 21 are to be formed. Forming a layer and exposing the underlying conductor layer; The formation of the bump electrode is not limited to a method using a dry film.

  Further, electrolytic plating is performed to grow exposed portions of the underlying conductor layer, thereby forming thick bump electrodes 12a to 12d. At this time, the insides of the openings ha to hd formed in the insulating layer 15d are filled with the plating material, whereby the bump electrodes 12a to 12d and the internal terminal electrodes 24a to 24d are electrically connected.

  Thereafter, the dry film layer is removed, and the entire surface is etched to remove an unnecessary underlying conductor layer, whereby the substantially columnar bump electrode 12 is completed. In this example, the substantially columnar bump electrode 12 is formed as an electrode common to four chip components adjacent in the X direction and the Y direction, but the bump electrode may be formed individually. The bump electrode 12 is divided into four by dicing, which will be described later, whereby individual bump electrodes 12a to 12d corresponding to each element are formed.

  Next, the magnetic wafer on which the bump electrode 12 is formed is filled with a composite ferrite paste and cured to form the magnetic resin layer 13 (step S14). Further, by filling the inside of the opening hg with the composite ferrite paste, the through-hole magnetic body 14 is simultaneously formed. At this time, in order to reliably form the magnetic resin layer 13, a large amount of paste is filled, so that the bump electrode 12 is buried in the magnetic resin layer 13. Therefore, the magnetic resin layer 13 is polished to a predetermined thickness and the surface is smoothed until the upper surface of the bump electrode 12 is exposed (step S15). Further, the magnetic wafer is also polished so as to have a predetermined thickness (step S15).

  Thereafter, each common mode filter element is separated (chiped) by dicing the magnetic wafer (step S16). At this time, as shown in FIG. 10, the cutting line D1 extending in the X direction and the cutting line D2 extending in the Y direction pass through the center of the bump electrode 12, and the cut surfaces of the obtained bump electrodes 12a to 12d are formed into chips. The exposed parts (chip parts) are exposed. Since the two side surfaces of the bump electrodes 12a to 12d serve as solder fillet formation surfaces during mounting, the fixing strength during solder mounting can be increased.

  Next, after barrel-polishing the chip part to remove the edge (step S17), electroplating is performed (step S18), thereby completing the bump electrodes 12a to 12d shown in FIG. As described above, by barrel polishing the outer surface of the chip component, it is possible to manufacture a coil component that is unlikely to be damaged such as chip chipping. Moreover, since the surface of bump electrode 12a-12d exposed to the outer peripheral surface of a chip component is plated, the surface of bump electrode 12a-12d can be made into a smooth surface.

  As described above, according to the electronic component and the manufacturing method thereof according to the present embodiment, the electronic component capable of suppressing the height variation of the upper surface of the conductor pattern of each conductor layer when the conductor pattern is stacked can be simplified and It can be manufactured at low cost. Moreover, since the magnetic resin layer 13 is formed around the bump electrodes 12a to 12d, the bump electrodes 12a to 12d can be reinforced, and peeling of the bump electrodes 12a to 12d can be prevented. Moreover, since the bump electrodes 12a to 12d are formed by plating in the method for manufacturing the coil component 1 according to the present embodiment, it is possible to provide a stable external terminal electrode with higher processing accuracy than when formed by sputtering, for example. it can. Furthermore, man-hour reduction and cost reduction can be achieved.

  The present invention is not limited to the above embodiment, and various modifications can be made without departing from the spirit of the present invention, and it goes without saying that these are also included in the present invention. Yes.

  For example, in the above embodiment, the magnetic resin layer is filled around the bump electrode. However, in the present invention, the magnetic resin layer is not limited, and a simple insulator layer without magnetism may be used. Further, the through-hole magnetic body 14 can be omitted.

  Moreover, in the said embodiment, although the thin film coil layer 11 of the 3 layer conductor layer structure was mentioned as an example, in the present invention, the number of lamination | stacking of a conductor layer may be any number and it is not limited to a 3 layer structure. In the above embodiment, the common mode filter is exemplified as the coil component. However, the present invention is not limited to the common mode filter, and may be applied to other various coil components such as a transformer and a power supply coil. Applicable. Furthermore, the present invention can be applied not only to coil components but also to various electronic components in which a thin film pattern is formed by plating.

1 Coil parts (electronic parts)
DESCRIPTION OF SYMBOLS 10 Board | substrate 10a, 10b, 10c, 10d Side surface 11 Thin film coil layer 12, 12a-12d Bump electrode 13 Magnetic resin layer 14 Through-hole magnetic body 15a-15d Insulating layer 16, 17 Spiral conductor 16a, 17a Inner edge 16b of spiral conductor , 17b Spiral conductor outer peripheral edges 18, 19 Contact hole conductors 20, 21 Lead conductors 24a-24d Internal terminal electrodes BB Collecting terminal electrodes C1-C3 Cavities D1, D2 Cutting lines LC1, LC2 Conductive layers LI1, LI2 Insulating layers P1- P4 Conductor patterns S1 to S4 Conductor formation region h1 Opening ha to hg Opening

Claims (12)

A first conductor layer including a first conductor pattern;
A first insulating layer covering the first conductor layer;
A first opening penetrating the first insulating layer and exposing an upper surface and a side surface of the first conductor pattern;
A second conductor layer including a second conductor pattern provided on the first insulating layer and connected to both an upper surface and a side surface of the first conductor pattern through the first opening;
The formation region of the first conductor pattern includes a first region excluding at least a central portion of a planar region inside the first opening,
The formation region of the second conductor pattern includes the first region and a second region excluding the first region in a planar region inside the first opening,
The shape of the formation region of the second conductor pattern overlaps the shape of the formation region of the first conductor pattern in plan view. The first conductor layer further includes a first spiral conductor;
The first conductor pattern is connected to an outer peripheral end or an inner peripheral end of the first spiral conductor;
2. The electronic component according to claim 1, wherein a minimum width of each of the first and second conductor patterns is wider than a line width of the first spiral conductor.   The electronic component according to claim 2, wherein a minimum width of each of the first and second conductor patterns is 1.5 to 4 times a line width of the first spiral conductor.   The electronic component according to claim 2, wherein an aspect ratio of a cross section of the first spiral conductor is 1 or more. A second insulating layer covering the second conductor layer;
A second opening that penetrates the second insulating layer and exposes an upper surface and a side surface of the second conductor pattern;
A third conductor layer including a third conductor pattern provided on the second insulating layer and connected to both an upper surface and a side surface of the second conductor pattern through the second opening;
The formation region of the third conductor pattern includes the first and second regions and a third region excluding the first and second regions in a planar region inside the second opening. Including
2. The electronic component according to claim 1, wherein a shape of the formation region of the third conductor pattern overlaps with a shape of the formation region of the first and second conductor patterns in a plan view. The first conductor layer further includes a first spiral conductor;
The second conductor layer further includes a second spiral conductor magnetically coupled to the first spiral conductor;
The electronic component according to claim 5, wherein a minimum width of each of the first to third conductor patterns is wider than a width of the first and second spiral conductors.   The electronic component according to claim 6, wherein a minimum width of each of the first and third conductor patterns is 1.5 to 4 times a line width of the first and second spiral conductors.   The electronic component according to claim 6 or 7, wherein an aspect ratio of a cross section of each of the first and second spiral conductors is 1 or more. A first terminal electrode connected to an outer peripheral end of the first spiral conductor;
A second terminal electrode connected to an outer peripheral end of the second spiral conductor;
Each of the first and second terminal electrodes has the first to third conductor patterns,
An outer peripheral end of the first spiral conductor is connected to the first conductor pattern constituting the first terminal electrode;
The electronic component according to any one of claims 6 to 8, wherein an outer peripheral end of the second spiral conductor is connected to the second conductor pattern constituting the second terminal electrode. A first contact hole conductor connected to an inner peripheral end of the first spiral conductor;
A second contact hole conductor connected to an inner peripheral end of the second spiral conductor,
The first contact hole conductor has the first to third conductor patterns,
The second contact hole conductor has the second and third conductor patterns,
An inner peripheral end of the first spiral conductor is connected to the first conductor pattern constituting the first contact hole conductor;
10. The electronic component according to claim 9, wherein an inner peripheral end of the second spiral conductor is connected to the second conductor pattern constituting the second contact hole conductor. The third conductor layer further includes first and second lead conductors;
One end of the first lead conductor is connected to the third conductor pattern constituting the first contact hole conductor,
11. The electronic component according to claim 10, wherein one end of the second lead conductor is connected to the third conductor pattern constituting the second contact hole conductor. A third terminal electrode connected to the other end of the first lead conductor;
A fourth terminal electrode connected to the other end of the second lead conductor,
Each of the third and fourth terminal electrodes has the first to third conductor patterns,
The other end of the first lead conductor is connected to the third conductor pattern constituting the third terminal electrode;
12. The electronic component according to claim 11, wherein the other end of the second lead conductor is connected to the third conductor pattern constituting the fourth terminal electrode.

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