JP2015132506A - Electrostatic capacitance detection circuit and input device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an electrostatic capacitance detection circuit in which an expansion in circuit scale or an increase in power consumption is suppressed, and the influence of noise is suppressed, and with which it is possible to detect a minute change in electrostatic capacitance stably with a high S/N ratio.SOLUTION: The present circuit comprises: a charge amplifier (10) having an operational amplifier (11) provided with a capacitor (Cfb) in a feedback path, into which a signal that includes a detection charge of the inter-electrode capacitance (Cm) of a sensor electrode (2) and a charge due to exogenous noise flows; switching circuits (SW4-1, 5-1, 4-2, 5-2), capable of switching the direction of the capacitor (Cfb) connected via the feedback path to the input/output terminal of the charge amplifier (10), for switching the direction of the capacitor (Cfb) in accordance with the direction of a charge flowing in from the detection-side electrode of the sensor electrode due to a drive signal applied to the sensor electrode (2); and a correction capacitor Clc provided in a feedback path of the operational amplifier (11) in parallel with the capacitor (Cfb).

Description

  The present invention relates to a capacitance detection circuit and an input device that detect minute changes in capacitance on a sensor such as a touch pad or a touch sensor.

  Conventionally, a capacitance detection circuit suitable for detecting a minute change in capacitance between sensor electrodes in an input device such as a touch pad or a touch sensor in a noisy environment has been proposed.

  For example, in the capacitance detection circuit disclosed in Japanese Patent No. 4275865, in order to detect the mutual capacitance between the sensor electrodes, the charge from the mutual capacitance is generated at the timing when the rising edge of the drive pulse is generated with respect to the integration capacitor. A configuration for performing transfer is adopted. In addition, the capacitance detection circuit disclosed in the specification of US Patent Application Publication No. 2011-0273400 performs charge transfer from the mutual capacitance to the two integration circuits at the timing when both edges of the drive pulse occur, thereby reducing the low frequency. The filtering effect against noise is improved.

Japanese Patent No. 4275865 US Patent Application Publication No. 2011-0273400

  By the way, the interelectrode capacitance (mutual capacitance) between the drive electrode and the detection electrode forming the sensor is usually a small value of several pF, but the amount of change due to the proximity of the finger is even smaller and less than the order of several hundred fF. For this reason, the influence of mixed noise is enormous. The causes of mixed noise include noise from the power supply of the system in which the touch pad and touch sensor are incorporated and the drive signal of the liquid crystal panel in the system. The influence of these noise sources is ignored due to the complexity of the equipment. It is no longer possible.

  In the case of the detection circuit described in Japanese Patent No. 4275865, charge transfer to the integrating capacitor is performed only for the rising edge of the drive pulse. Therefore, if noise is applied to the operation body itself such as a finger or noise is applied to the power supply of the system that detects the capacitance, the noise is mixed into the transferred charge. When the frequency of the noise applied to the integration period is lowered, the averaging of the mixed noise is not sufficient in the integration period, and there is a drawback that the influence of noise appears more greatly in the output data.

  In the case of the detection circuit described in US Patent Application Publication No. 2011-0273400, a charge transfer is performed at both edges of the drive pulse, so that the filtering effect is improved against low frequency noise. Two integration circuits are required, which increases the circuit scale and power consumption.

  The present invention has been made in view of such circumstances, and suppresses an increase in circuit scale and power consumption, suppresses the influence of noise even in an environment with a lot of external noise, and changes in a minute capacitance. It is an object of the present invention to provide a capacitance detection circuit capable of stably detecting a high S / N ratio.

  The capacitance detection circuit of the present invention includes a charge amplifier that accumulates charges according to the detected charge of the interelectrode capacitance of the sensor electrodes, and an A / D converter that converts the output of the charge amplifier from an analog signal to a digital signal. The charge amplifier is provided between the operational amplifier having a first feedback path and a second feedback path positioned in parallel with each other, and the interelectrode capacitance provided in the first feedback path. A first capacitor for accumulating the charge transferred at the first feedback path, and a plurality of changeover switches for switching the direction of supplying the charge from the detection-side electrode of the sensor electrode to the first capacitor in the first feedback path, Based on a drive signal applied to the drive electrode of the sensor electrode, the changeover switch is controlled so that the direction in which the charge is supplied to the first capacitor is alternately reversed. A switching circuit for sequentially integrating the detected charge in the first capacitor, characterized by comprising a second capacitor for correction provided in the second feedback path.

  According to the electrostatic capacitance detection circuit, the low-frequency external noise is averaged by continuously integrating the charge transferred based on the drive signal by the first capacitor, thereby affecting the influence of the external noise. Can be reduced. Further, when there is no second capacitor for correction, there is a possibility that an error component is added to the integrated charge due to the influence of the parasitic capacitance or the like of the changeover switch every time the changeover switch is changed. However, the error component can be canceled by providing the first capacitor.

The second capacitor of the capacitance detection circuit of the present invention performs correction so that charges due to parasitic capacitance caused by the changeover switch are not sequentially integrated into the first capacitor.
Thereby, it is possible to prevent error components from being accumulated in the integrated charge due to the influence of the parasitic capacitance of the changeover switch and the like.

  The capacitance detection circuit includes a capture switch for controlling a flow period of a signal including a detection charge proportional to an interelectrode capacitance of the sensor electrode and a charge due to external noise to the charge amplifier, and charging is performed by the capture switch. An analog signal as an amplifier output is captured in accordance with analog / digital conversion timing.

  As a result, low frequency noise is continuously integrated by the capacitor in the feedback path of the operational amplifier by the charge amplifier, and the influence of external noise on the analog signal output of the charge amplifier during repeated sampling can be suppressed.

  In the capacitance detection circuit, any one of a resistance element, an impedance element, an active element, or a circuit network that combines an impedance element and an active element is connected in parallel to the feedback path in the feedback path of the operational amplifier. It is characterized by.

  As a result, in the switching circuit that switches the direction of the signal applied to the capacitor in the feedback path of the operational amplifier, the operational amplifier is affected by the charge injection effect of the switch at the timing when all the switch connection states are turned off during the switching. Output fluctuation can be suppressed.

  In the capacitance detection circuit, the A / D converter converts an analog signal having a potential difference between an output potential of the charge amplifier and a reference potential into a digital signal.

  This makes it possible to efficiently perform analog / digital conversion of the output of the charge amplifier in accordance with the dynamic range of change in the detected capacitance.

  In the capacitance detection circuit, the A / D converter includes an output potential of the charge amplifier corresponding to a rising edge of the drive signal, and an output potential of the charge amplifier corresponding to a falling edge of the drive signal. It is characterized in that an analog signal composed of the potential of the difference is converted into a digital signal.

As a result, the output of the charge amplifier is changed to a pseudo-differential output with a time difference, so that the dynamic range of the output signal is expanded, and analog / digital conversion can be performed with less influence of noise.

  In the capacitance detection circuit, a third feedback for feeding back a signal corresponding to an output obtained by converting an analog signal having a difference between the output potential of the charge amplifier and a reference potential into a digital signal to the input of the charge amplifier. A circuit is provided.

  As a result, it is possible to realize a delta-sigma analog / digital converter having a higher resolution by using an analog / digital converter having a lower resolution.

  In the capacitance detection circuit, an analog signal comprising a difference potential between the output potential of the charge amplifier corresponding to the rising edge of the drive signal and the output potential of the charge amplifier corresponding to the falling edge of the drive signal And a third feedback circuit that feeds back a signal corresponding to an output obtained by converting the signal into a digital signal to the input of the charge amplifier.

  As a result, the output of the charge amplifier is pseudo-differentiated to reduce the influence of noise, and a delta-sigma analog / digital converter with higher resolution and higher S / N ratio can be realized using an analog / digital converter with less resolution. Is possible.

  An input device according to the present invention includes a sensor electrode in which an X electrode group and a Y electrode group that are orthogonal to each other are arranged in a matrix, and a capacitance detection circuit that detects a change in capacitance between the sensor electrodes. In the input device, the capacitance detection circuit may take any one of the configurations described above.

  According to the present invention, an increase in circuit scale and an increase in power consumption are suppressed, the influence of noise is suppressed even in an environment with a lot of external noise, and a small change in electrostatic capacitance is stably achieved with a high S / N ratio. A detectable capacitance detection circuit can be provided.

FIG. 3 is a diagram in which sensor electrodes are connected to the capacitance detection circuit according to the first embodiment. It is a block diagram of the electrostatic capacitance detection circuit corresponding to the intersection where the interelectrode capacitance Cm is formed and the sensor component. 3 is a diagram illustrating a specific configuration example of a charge amplifier according to the first embodiment. FIG. FIG. 3 is a diagram illustrating a timing chart for explaining operations in the first embodiment. FIG. 4 is a diagram for explaining a parasitic capacitance Cog in a charge amplifier by paying attention to paths of a switch SW4-1, a feedback capacitor Cfb, and a switch SW4-2 shown in FIG. It is a figure for demonstrating the function of the correction | amendment capacitor | condenser Clc in the charge amplifier which paid its attention to the path | route of switch SW4-1 shown in FIG. 3, feedback capacitor Cfb, and switch SW4-2. It is a figure which shows the relationship between the time (a horizontal axis) corresponding to the frequency | count of integration, and the output voltage of a charge amplifier. It is a figure which shows the internal structure of an analog / digital converter. It is a figure which shows the relationship between the output Aout when there exists external noise, and the comparator output Cout. FIG. 2 is a diagram in which a comparator has a latch function, and a track / hold circuit added immediately before the comparator. It is a figure which shows signals (phi) 1 and (phi) 2 used as a non-overlap signal. It is a figure which shows a mode that the spike-like noise was input into the operational amplifier when the feedback path | route is an open state. 6 is a diagram illustrating a specific configuration example of a charge amplifier according to Embodiment 2. FIG. FIG. 6 is a diagram illustrating a configuration of a charge amplifier 10 and an analog / digital converter 20 applied to the third embodiment. FIG. 10 is a diagram illustrating a timing chart for explaining the operation of the third embodiment. 6 is a block diagram of a capacitance detection circuit according to a fourth embodiment. FIG. FIG. 10 is a diagram illustrating a timing chart for explaining the operation of the fourth embodiment. FIG. 10 is a configuration diagram of a capacitance detection circuit according to a fifth embodiment. FIG. 10 is a diagram illustrating a timing chart for explaining the operation of the fifth embodiment.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

(Embodiment 1)
FIG. 1 shows a state in which sensor electrodes 2 such as a touch pad and a touch sensor are connected to the capacitance detection circuit 1 according to the first embodiment. The sensor electrode 2 is formed on a two-dimensional plane, and an X electrode group 3 and a Y electrode group 4 which are orthogonal to each other are arranged in a matrix. By arranging the X electrode group 3 and the Y electrode group 4 of the sensor electrode 2 in a matrix, it is possible to detect the proximity position of a human finger.

  Each electrode (X electrode, Y electrode) of the X electrode group 3 and the Y electrode group 4 has a GND capacitance Cp for a shield plate or the like. Although only one location is shown in FIG. 1, an interelectrode capacitance Cm is generated at each intersection of the X electrode and the Y electrode. Since the interelectrode capacitance Cm decreases when the finger approaches, the proximity position of the finger can be specified by detecting the capacitance at each intersection.

  FIG. 2 shows a sensor configuration part (corresponding to an intersection where an interelectrode capacitance Cm is formed) of one X electrode and one Y electrode representative in FIG. 1 and capacitance detection corresponding to the sensor configuration part. A block diagram of circuit 1 is shown. A drive signal such as a rectangular wave is output from the drive electrode node Sin as a node (drive electrode node) Sin when the X electrode in FIG. 1 is used as a drive electrode and a node (detection electrode node) Ain when the Y electrode is used as a detection electrode. As a result, the charge amplifier 10 converts the amount of charge corresponding to the size of the interelectrode capacitance Cm into a voltage. A switch SW1 that is ON / OFF controlled by the signal PU is provided on the voltage source VDD terminal side of the drive electrode node Sin, and a switch SW2 that is ON / OFF controlled by the signal PD is provided on the GND terminal side of the drive electrode node Sin. It is done.

  FIG. 3 shows a specific configuration example of the charge amplifier 10. A capture switch SW3, which is ON / OFF controlled by a signal APT, is provided in series on the negative input path of the operational amplifier 11 from the detection electrode node Ain, and a charge amplifier 10 for a signal including the charge of the interelectrode capacitance Cm and the charge due to external noise. Control the inflow period. That is, the capture switch SW3 controls the inflow period of charge into the charge amplifier 10, so that the output of the charge amplifier 10 changes when a signal including charge flows into the charge amplifier 10 during the ON period, and the charge during the OFF period. Inflow of the signal including the signal is stopped, and the output of the charge amplifier 10 is held. From this, the capture switch SW3 controls the inflow period to the charge amplifier 10, whereby the analog signal that becomes the charge amplifier output can be accurately captured in accordance with the timing of analog / digital conversion.

In the feedback path from the output of the operational amplifier 11 to the negative input, a circuit module MOD and a correction capacitor Clc are provided in parallel.
In the circuit module MOD, a switch SW that is ON / OFF controlled by a signal φ1 is provided in the feedback path from the output of the operational amplifier 11 to the negative input.
Four changeover switches SW5-1 and 5-2 that are ON / OFF-controlled by 4-1 and 4-2 and a signal φ2 are provided. These changeover switches SW4-1, 5-1, 4-2, and 5-2 constitute a changeover circuit. The switching circuit is configured such that the two terminals of the feedback capacitor Cfb can be switched and connected in the opposite direction. A reference potential VR is connected to the positive input of the operational amplifier 11. The reference potential VR is set, for example, near the midpoint of the power supply of the operational amplifier 11 so that the dynamic range of the output signal can be increased.

As will be described later, the correction capacitor Clc increases the accumulated charge of the feedback capacitor Cfb due to the parasitic capacitance Cog each time the changeover switches SW4-1, 5-1, 4-2, and 5-2 are switched, and reaches the saturation level. To avoid reaching. This improves noise immunity and linearity.
That is, in the circuit module MOD, the parasitic capacitance Cog hangs from the signal lines at both ends of the changeover switches SW4-1, 5-1, 4-2, and 5-2. The accumulated charge Q (Cog) due to the parasitic capacitance Cog is supplied to the feedback capacitor Cfb. Since the direction of the feedback capacitor Cfb is reversed by the switching operation of the changeover switches SW4-1, 5-1, 4-2, and 5-2, the accumulated charge Q (Cog) is accumulated and accumulated in the feedback capacitor Cfb. Try to. The correction capacitor Clc functions to suppress the accumulated charge Q (Cog) from being accumulated in the feedback capacitor Cfb.

  The output Aout of the charge amplifier 10 is input to the analog / digital converter 20 (see FIG. 2). The analog / digital converter 20 receives the conversion timing defining signal AQ, and converts the potential of the difference between the output Aout and the reference potential VR into a digital signal Dout at the rising timing of the signal AQ. That is, the supplemental switch SW3 controls the inflow of a signal containing charge to the charge amplifier 10, and AD conversion is performed in response to the rising edge of the signal AQ while the output of the charge amplifier 10 is held when the capture switch SW3 is OFF. To eliminate the negative effects of the noise filter effect.

  FIG. 4 shows a timing chart for explaining the operation of the present embodiment. The signals PU and PD are signals for giving a rectangular wave to the drive electrode node Sin by ON / OFF control of the switches SW1 and SW2. When the switch SW1 is turned on when the signal PU is turned on, the potential of VDD is set to the drive electrode node Sin. When the signal SW is turned on and the switch SW2 is turned on, the potential of GND is set to the drive electrode node Sin. . The signals PU and PD for controlling ON / OFF of the switch SW1SW5-2 are normally non-overlapping signals (ON periods do not overlap), but inverter logic that inverts a simple digital signal as it is can be substituted.

  T1 to T6 indicate the timing of the edge of the drive signal. In this example, the voltage of the output Aout obtained by integrating the transfer charge for six times at both the rising and falling edges is measured as a difference from the reference potential VR. This is an example.

  First, in the reset sequence, any signal of APT, φ1, φ2 (capture switch SW3, changeover switch SW4-1, 5-1, 4-2, 5-2) is turned on to reset the charge of the feedback capacitor Cfb. At the same time, the detection electrode node Ain is set to the reference potential VR. Next, the APT, φ1, and φ2 signals (switches SW3, SW4-1, 5-1, 4-2, and 5-2) are turned off to complete the reset sequence.

By turning on the signal PU at the next timing T1, the switch SW1 is turned on to cause the drive electrode node Sin to transition to VDD, and at the same time, the signal APT and the signal φ1 are turned on. At this time, the operational amplifier 11 performs a negative feedback operation to maintain the negative input potential at the same potential as the reference potential VR via the feedback capacitor Cfb, so that the output Aout is output from the reference potential VR by the charge transferred from the sensor electrode 2. The potential drops from. In a state where there is no external noise, the potential change ΔAout of the output Aout due to each edge of the drive signal is expressed by the following equation (1) from the amount of charge transferred.
In the equation in the present embodiment, Cfb represents the capacitance of the feedback capacitor Cfb.

  ΔAout = VDD × Cm / Cfb (1)

  In FIG. 4, the length of the arrow at the timing of the change in the output Aout indicates the magnitude of ΔAout. Next, the exchange of charges between the sensor electrode 2 and the charge amplifier 10 is blocked by turning off the signal APT and turning off the capture switch SW3. Further, the signals PU and φ1 are turned OFF, and the switches SW1, SW4-1, SW4-2 are turned OFF.

  At the next timing T2, the signal PD is turned on to cause the drive electrode node Sin to transition to GND. At the same time, when the signal APT and the signal φ2 are turned ON, the charge transfer in the opposite direction to that at the timing T1 occurs between the sensor electrode 2 and the charge amplifier 10, but the connection of the feedback capacitor Cfb is opposite to that at the time of the signal φ1. Therefore, the charge is accumulated in the positive direction with respect to the reference potential VR, and thus changes as a positive potential with respect to the reference potential VR.

  After such an operation is repeated from T3 to T6, analog / digital conversion is performed by using the difference potential between the output Aout of the charge amplifier 10 and the reference potential VR at the timing of the rising edge of the signal AQ.

  While the series of reset sequence and detection sequence is repeated, the size of the interelectrode capacitance Cm is detected. In this embodiment, even if external noise is mixed, it is taken into the charge amplifier 10 adjacent in time. As shown at the bottom of FIG. 4, the noise charge amount is canceled by the noise N1-1, 1-2, 1-3 portion and the noise N2-1, 2-2, 2-3 portion. Therefore, noise resistance as a detection circuit is greatly improved.

  In the present invention, the detection sequence is not limited to six times, and the detection sequence is repeated as many times as possible in the range where the potential output as the output Aout falls within the range of GND and VDD or the operating power supply range of the charge amplifier 10. Noise reduction effect is increased. Further, the noise reduction effect is further increased by performing the same number of charge transitions at the rising and falling edges of the drive signal.

  In the operation shown in FIG. 4 described above, the correction capacitor Clc functions as follows to suppress the accumulated charge Q (Cog) of the parasitic capacitance Cog from being accumulated and accumulated in the feedback capacitor Cfb.

FIG. 5 is a diagram for explaining the parasitic capacitance Cog generated in the charge amplifier 10 by paying attention to the path of the switch SW4-1, the feedback capacitor Cfb, and the switch SW4-2.
As shown in FIG. 5, in the charge amplifier 10 shown in FIG. 3, a parasitic capacitance Cog mainly caused by the switches SW4-2 and SW5-2 is generated.

In the following, all voltages and charges are expressed on the basis of VR. Consider VR = 0.
Let Q be the integrated charge amount of the first charge amplifier 10. At this time, Ain = VR, Q (Cfb) = Q, and Aout = Q / Cfb.
The accumulated charge Q (Cog) of the parasitic capacitance Cog is expressed by the following equation (2).

  Q (Cog) = − Q * Cog / Cfb (2)

Here, for example, when the switches SW4-1 and SW4-2 are switched from ON to OFF and the switches SW5-1 and SW5-2 are switched from OFF to ON, the parasitic capacitance Cog is connected to the node Ain side. . Therefore, the accumulated charge of the parasitic capacitance Cog is integrated (accumulated) and accumulated in the feedback capacitor Cfb.
As a result, the charge stored in the feedback capacitor Cfb is expressed by the following equation (3).
That is, the charge of the feedback capacitor Cfb changes from Q to -Q due to inversion. The charge Q (Cog) in the above formula (2) is added thereto.

Q (Cfb) = − Q−Q * Cog / Cfb
= −Q * (Cfb + Cog) / Cfb (3)

Q (Cfb) at the first stage is Q, and the expected value due to inversion is -Q, but the value of the above equation (3) is obtained due to the influence of the parasitic capacitance Cog. This indicates that the integrated charge absolute value increases.
That is, the error component of the accumulated charge Q (Cfb) of the feedback capacitor Cfb increases. The increase in the error component increases in proportion to the absolute value of the voltage across the feedback capacitor Cfb.

  The correction capacitor Clc plays a role of preventing the charge due to the parasitic capacitance Cog from being accumulated in the feedback capacitor Cfb described above every time the switches SW4-1, SW4-2, SW5-1, and SW5-2 are switched. . That is, it acts to cancel the increase in the accumulated charge in the feedback capacitor Cfb.

FIG. 6 is a diagram for explaining the function of the correction capacitor Clc in the charge amplifier 10 by paying attention to the path of the switch SW4-1, the feedback capacitor Cfb, and the switch SW4-2.
Let Q be the first integrated charge amount of the charge amplifier 10. At this time, Ain = VR, Q (Cfb) + Q (Clc) = Q. Since Q is distributed to the feedback capacitor Cfb and the correction capacitor Clc, and the distribution ratio is equal to the capacitance ratio, the following equations (4) and (5) are established.
In the formula in the present embodiment, Clc indicates the capacitance of the correction capacitor Clc.

  Q (Cfb) = Q * Cfb / (Cfb + Clc) (4)

  Q (Clc) = Q * Clc / (Qfb + Clc) (5)

  By switching the switches SW4-1, SW4-2, SW5-1, and SW5-2, the feedback capacitor Cfb is inverted, but the correction capacitor Clc is not inverted. For this reason, the integrated total charge amount after inversion is expressed by the following equation (6). That is, the absolute value of the charge after inversion decreases.

  (Integrated total charge) = − Q (Cfb) + Q (Clc) = − Q * (Cfb−Clc) / (Cfb + Clc) (6)

  The above equations (3) and (6) both have the effect of multiplying Q by a constant coefficient. Therefore, the integrated total charge amount of the charge amplifier 10 after inversion due to both influences is expressed by the following equation (7).

  (Integrated total charge) = − Q * {(Cfb + Cog) / Cinteg} * {(Cfb−Clc) / (Cfb + Clc)} (7)

  Therefore, if the correction capacitor Clc is set so that the following equation (8) is established, the influence of the parasitic capacitance Cog can be completely canceled in the calculation.

{(Cfb + Cog) / Cfb} * {(Cfb-Clc) / (Cfb + Clc)} = 1 (8)

  From the above equation (8), the appropriate correction capacitor value is Clc≈Cog / 2. Actually, as a result of adjusting the value of Clc to about Cog / 2 and performing the operation, the accumulated charge of the feedback capacitor Cfb increases every time the changeover switches SW4-1, 5-1, 4-2, and 5-2 are switched. The noise tolerance and linearity could be improved.

FIG. 7 is a diagram showing the relationship between the time corresponding to the number of integrations (with the horizontal axis) and the output voltage of the charge amplifier 10.
In FIG. 7, the thick line shows the waveform 60 of the output voltage of the charge amplifier 10 shown in FIG. 3, and the thin line shows the waveform 62 of the output voltage when the correction capacitor Clc is not provided in the configuration shown in FIG.
As shown in FIG. 7, in the waveform 62 when the correction capacitor Clc is not provided, the voltage level increases exponentially and reaches the saturation level. Such an increase in voltage level adversely affects offset fluctuation and frequency characteristics, and also adversely affects linearity.
On the other hand, the waveform 60 of the output voltage of the charge amplifier 10 provided with the correction capacitor Clc changes only at the initial stage, and thereafter, only the inversion is repeated, and the integrated charge is inverted with almost no fluctuation.

  As described above, in the charge amplifier 10, by providing the correction capacitor Clc, the accumulated charge of the feedback capacitor Cfb increases every time the changeover switches SW4-1, 5-1, 4-2, and 5-2 are switched. Thus, it is possible to avoid reaching the saturation level and improve noise resistance and linearity.

  As a means for capturing the timing of converting the analog signal of the charge amplifier 10 into a digital signal, the case where the capture switch SW3 that is ON / OFF controlled by the signal APT is introduced has been described. Here, the capture switch SW3 (signal ATP) ) Explain the problem when not introducing. For example, it is assumed that the output Aout is connected to the analog / digital converter 20 without providing the capture switch SW3 that is ON / OFF controlled by the signal APT. Since many analog / digital converters 20 have a comparator inside, for example, the case of a comparator using an analog / digital converter as a 1-bit output will be exemplified. As shown in FIG. 8, the output of the comparator 21 is Cout, and the output of the latch circuit 22 that latches the output Cout with the signal AQ is Dout. FIG. 9 shows the relationship between the output Aout and the comparator output Cout when there is external noise. For example, assuming that a single frequency noise is mixed and the phases are different, the comparator output when the phase is N1 is Cout1, and the comparator output when the phase is N2 is Cout2. The comparator 21 compares the output Aout with the reference potential VR and outputs High / Low. However, there is actually a time delay and a delay as shown in FIG. 9 occurs. Even if the analog / digital conversion timing is defined at the timing of the signal AQ at which the voltage of the output Aout is exactly the same between N1 and N2, the latched digital signal has a different value, resulting in noise in the charge amplifier 10. The filtering effect is greatly impaired.

  Therefore, the original filtering effect is exhibited by capturing the analog signal with the capture switch SW3 (signal APT) at the timing of converting the output Aout into a digital signal. As shown in FIG. 10A, the comparator 21 itself of the analog / digital converter 20 may have a latch function, or a track / hold circuit 23 for the output Aout signal may be added immediately before the comparator 21 as shown in FIG. 10B. An effect similar to that of the switch SW3 controlled by the signal APT can be obtained.

(Embodiment 2)
Next, a second embodiment in which a part of the charge amplifier 10 is modified will be described.
Since the switching circuits (switching switches SW4-1, 5-1, 4-2, and 5-2) controlled by the signals φ1 and φ2 are normally controlled so that the switches are not turned on at the same time, the signals φ1 and φ2 are The non-overlap signal is as shown in FIG. Further, an actual switch carries a data signal, and capacitive coupling is generated between a data signal input / output unit input / output to / from the switch and a control signal input unit to which a control signal for controlling the switch is input. . In order to cancel the coupling by design, a technique such as providing a dummy transistor is taken, but there is a case where an influence which cannot be ignored remains. In this case, as shown in FIGS. 11 and 12, spike-like noise Nin may occur. During the period when the signals φ1 and φ2 are both OFF at the time of noise generation, the operational amplifier 11 does not receive negative feedback and becomes an open loop, so that a large output change occurs in the output Aout. When the signals φ1 and φ2 are turned on next from this state, unnecessary charge may flow into the feedback capacitor Cfb, and the SN ratio of the charge amplifier output may deteriorate.

  Therefore, the charge amplifier 10 applied to the second embodiment has a configuration in which a resistance element 12 having a resistance value Rfb is connected to the feedback path of the negative input and output of the operational amplifier 11 as shown in FIG. In FIG. 13, the same parts as those of the charge amplifier 10 shown in FIG. In the charge amplifier 10 having such a configuration, even if spike-like noise Nin occurs, the negative feedback control from the output is always performed through the resistance element 12, so that a large change does not occur in the output Aout. . Therefore, it is possible to avoid a large deterioration in the SN ratio of the output Aout. However, if Cfb × Rfb (time constant) becomes smaller than the sampling period, charge leakage due to the resistance element 12 cannot be ignored. Therefore, it is necessary to take care such that Cfb × Rfb (time constant) is set to such a magnitude that the influence of leakage can be ignored.

In addition, what is connected to the feedback path is not limited to the resistance element 12, and an active element such as a transistor or a diode, or a circuit network in which an impedance element and an active element are combined may be used. For example, by using a device that uses the OFF characteristics of a transistor instead of the resistance element 12, it is possible to contribute to the reduction of the manufacturing process.
Also in the present embodiment, like the first embodiment, the correction capacitor Clc is provided, so that the feedback capacitor Cfb every time the changeover switches SW4-1, 5-1, 4-2, and 5-2 are switched. Therefore, it is possible to prevent the accumulated charge from increasing and reach a saturation level, and to improve noise resistance and linearity.

(Embodiment 3)
Next, a third embodiment of the present invention will be described. In the third embodiment, the output Aout is sampled to the sampling capacitor Csn at the rising edge of the drive electrode node Sin, and is sampled to the sampling capacitor Csp at the falling edge of the drive electrode node Sin.

  FIG. 14 shows the configuration of the charge amplifier 10 and the analog / digital converter 20 applied to the third embodiment. In FIG. 14, the same parts as those of the charge amplifier 10 shown in FIG. The sampling capacitor Csn is connected to the negative input (N) of the analog / digital converter 20, and the output Aout of the operational amplifier 11 is output via the switch SW4-3 controlled by the signal φ1. Further, the sampling capacitor Csp is connected to the positive input (P), and the output Aout of the operational amplifier 11 is output via the switch SW5-3 controlled by the signal φ2.

FIG. 15 shows a timing chart for explaining the operation of the third embodiment. The description of the same operation part as in FIG. 4 is omitted. The switch SW4-3 and SW5-3 for distributing the output Aout of the operational amplifier 11 to the sampling capacitors Csn and Csp are set to a period shorter than the signals φ1 and φ2 instead of the signals φ1 and φ2, thereby acquiring the capture switch SW3 (APT). It is also possible to substitute the function of.

  Also in this example, the integration operation is performed at timings T1 to T6. At timings T1, T3, and T5, the negative charge amplifier output is accumulated in the sampling capacitor Csn, and at timings T2, T4, and T6, the sampling capacitor Csp is positive. Are stored. When analog / digital conversion is performed at the end of the detection sequence, the potential difference (P−N) between the sampling capacitors Csn and Csp is used as a measurement value.

As a result, the dynamic range of the charge amplifier output can be used effectively, and an output twice as an analog signal can be obtained. Therefore, the SN ratio can be further improved by adding a few circuit elements. In addition, since the comparison target of the comparator 21 is the positive (P) and negative (N) voltage, the low frequency noise is converted to the common mode, so that the noise filter effect due to both the integration effect and the differential effect is achieved. can get.
Also in the present embodiment, like the first embodiment, the correction capacitor Clc is provided, so that the feedback capacitor Cfb every time the changeover switches SW4-1, 5-1, 4-2, and 5-2 are switched. Therefore, it is possible to prevent the accumulated charge from increasing and reach a saturation level, and to improve noise resistance and linearity.

(Embodiment 4)
Next, a fourth embodiment of the present invention will be described. In the fourth embodiment, a delta sigma type analog / digital converter is realized using a 1-bit output comparator 24 as the analog / digital converter 20.

  FIG. 16 is a block diagram of a capacitance detection circuit according to the fourth embodiment. The analog / digital converter 20 is a delta sigma type analog / digital converter composed of a comparator 24 having a 1-bit output and a digital filter 25. The output of the comparator 24 is fed back to the input via the delta sigma feedback capacitor Cds, thereby performing delta sigma modulation. The feedback timing of the delta sigma feedback capacitor Cds is controlled by the delta sigma feedback control logic 30.

  FIG. 17 shows a timing chart for explaining the operation of the fourth embodiment. The operation of generating a drive signal and taking charge from the sensor electrode into the charge amplifier 10 by the control signals APT, φ1, and φ2 is the same as in the first embodiment.

In the reset sequence, the process is the same as in the first embodiment until the charge of the feedback capacitor Cfb is reset by turning on the changeover switches SW4-1, 5-1, SW4-2, and 5-2 by the signals φ1 and φ2. . Subsequently, in the integration operation at both rising and falling edges (T1, T2) of the first driving signal, the initial charge is transferred to the feedback capacitor Cfb by changing the signal Dds in the opposite direction to the driving signal. At this time, charge transfer by the drive signal generated at the drive electrode node Sin is also performed at the same time. The initial charge Qds corresponding to one edge of the signal Dds transferred to the feedback capacitor Cfb via the delta-sigma feedback capacitor Cds due to the change of the signal Dds is expressed by the following equation when the magnitude of change of Dds is the same VDD as the drive signal: It is expressed as (9).
Qds = VDD × Cds (9)

  In FIG. 17, the output waveform of the output Aout corresponding to the amount of charge is indicated by a broken line. Usually, the magnitude of Qds is set to be larger than the charge corresponding to the interelectrode capacitance (VDD × Cm). When the charge transferred by the signal is subtracted in the direction of the arrow, a solid line waveform is obtained. Since the initial charge is transferred to the feedback capacitor Cfb at both edges of T1 and T2, a total of twice the charge of equation (2) is transferred to the feedback capacitor Cfb as the initial charge.

  Since the charge corresponding to the interelectrode capacitance Cm is transferred at the edges from timing T1 to T5 by the drive signal, the charge amplifier output is transferred in a form that is subtracted from the initial charge of the feedback capacitor Cfb. Get closer to. While the signal AQ rises after completion of charge transfer in units of rising and falling edges of the drive signal edge, a comparison result signal (1 bit) indicating the result of comparing the output Aout and the reference potential VR is captured in the digital filter 25. It is converted into a multi-bit output Dout ′ by a digital filtering process such as an FIR filter and output. A value obtained by latching the comparison result (0 or 1) of the comparator 24 with the signal AQ by the digital filter 25 is shown below the output Aout in FIG.

  After the charge transfer at the driving edge of T6, when the output Aout becomes larger than the reference potential VR, the output of the comparator 24 becomes High, and the digital filter 25 latches [1] at the rising timing of the signal AQ, and the delta-sigma feedback control logic 30 The information is transmitted, and the signal Dds is fed back as a feedback signal of delta-sigma modulation at timings T7 and T8 of the next drive signal edge. The charge transfer by the signal Dds at this time is also performed using both edges of Dds as in the transfer of the initial charge. Further, the gain of the output digital value can be adjusted by changing the magnitude of the delta-sigma feedback capacitor Cds.

As in this series of operations, the charge integration operation is performed in such a manner that the charge corresponding to the size of the interelectrode capacitance Cm by the drive signal is subtracted from the initial charge (VDD × Cds × 2), and the output result of the comparator 24 is converted into a delta sigma. A charge according to the capacitance value is fed back via the feedback capacitor Cds, whereby a capacitance detection circuit including an analog / digital converter having high noise resistance can be configured with a simple configuration.
Also in the present embodiment, like the first embodiment, the correction capacitor Clc is provided, so that the feedback capacitor Cfb every time the changeover switches SW4-1, 5-1, 4-2, and 5-2 are switched. Therefore, it is possible to prevent the accumulated charge from increasing and reach a saturation level, and to improve noise resistance and linearity.

(Embodiment 5)
Next, a fifth embodiment of the present invention will be described. In the fifth embodiment, a delta sigma type analog / digital converter is realized by using a 1-bit output comparator 24 as the analog / digital converter 20. Since the basic configuration and operation are the same as those of the fourth embodiment, differences from the fourth embodiment will be mainly described here.

  FIG. 18 is a configuration diagram of a capacitance detection circuit according to the fifth embodiment. The same parts as those in the capacitance detection circuit shown in FIGS. 14 and 16 are denoted by the same reference numerals.

  The input of the comparator 24 is configured to sample the output Aout into the sampling capacitor Csn at the rising edge of the drive electrode node Sin and to sample into the sampling capacitor Csp at the falling edge of the drive electrode node Sin. Therefore, after the falling edge of the drive signal, the positive input (Csp potential) is compared with the negative input (Csn potential) of the comparator 24, and delta-sigma modulation is performed based on the result.

  In the timing chart of FIG. 19, since the negative input (N) <the positive input (P) at the input of the comparator 24 after the falling edge of the drive signal at T6, the comparison result [1] is transferred to the digital filter 25 and the delta A delta sigma feedback operation is performed via the sigma feedback control logic 30 and the delta sigma feedback capacitor Cds.

In this case, since the comparison target of the comparator 24 is the voltage of P and N as in the third embodiment, the low-frequency noise is converted to the common mode, so that both the integration effect and the differential effect are obtained. Thus, a capacitance detection circuit including an analog / digital converter with high noise resistance can be configured with a simple configuration.
Also in the present embodiment, like the first embodiment, the correction capacitor Clc is provided, so that the feedback capacitor Cfb every time the changeover switches SW4-1, 5-1, 4-2, and 5-2 are switched. Therefore, it is possible to prevent the accumulated charge from increasing and reach a saturation level, and to improve noise resistance and linearity.

  In addition, this invention is not limited to the said embodiment, It can change and implement variously. In the above-described embodiment, the size and shape of the sensor electrode illustrated in the accompanying drawings are not limited to this, and can be appropriately changed within a range in which the effect of the present invention is exhibited. In addition, various modifications can be made without departing from the scope of the object of the present invention.

DESCRIPTION OF SYMBOLS 1 Capacitance detection circuit 2 Sensor electrode 3 X electrode group 4 Y electrode group 10 Charge amplifier 11 Operation amplifier 12 Resistive element 20 Analog / digital converter 21, 24, 121 Comparator 22 Latch circuit 23 Track / hold circuit 25 Digital filter 30 Delta-sigma feedback control logic 110 Charge integration circuit 111 Differential amplifier 112 Feedback path Cfb Feedback capacitor Clc Correction capacitor
SW3 capture switch SW4-1, SW5-1, SW4-2, SW5-2, SWf1, SWf2, SWr1, SWr2 changeover switch (switching circuit)
Cm Interelectrode capacitance Cp GND capacitance Csn, Csp Sampling capacitance Cds Delta sigma feedback capacitance gmA First current output circuit gmB Second current output circuit gm1, gm2, gm1 ′, gm2 ′ mutual conductance element

Claims (9)

A charge amplifier that accumulates charges according to the detected charge of the interelectrode capacitance of the sensor electrodes;
An A / D converter for converting the output of the charge amplifier from an analog signal to a digital signal;
With
The charge amplifier is
An operational amplifier having a first feedback path and a second feedback path;
A first capacitor provided in the first feedback path for accumulating charges transferred to and from the interelectrode capacitance;
A plurality of changeover switches for switching a direction of supplying electric charge from the detection side electrode of the sensor electrode to the first capacitor in the first feedback path, and a drive signal applied to the drive side electrode of the sensor electrode; In response, a switching circuit that sequentially integrates the detected charges with the first capacitor by controlling the changeover switch so that the direction in which the charge is supplied to the first capacitor is alternately reversed;
And a second capacitor for correction provided in the second feedback path. The second capacitor supplies the first capacitor with a charge that cancels out the charge accumulated in the first capacitor due to the parasitic capacitance of the changeover switch when the changeover switch performs a changeover operation. The capacitance detection circuit according to claim 1.   It has a capture switch that controls the inflow period to the charge amplifier of a signal including a charge detected by the interelectrode capacitance of the sensor electrode and a charge due to external noise, and an analog signal that becomes a charge amplifier output by this capture switch, 3. The capacitance detection circuit according to claim 1, wherein the capacitance is captured in accordance with an analog / digital conversion timing.   2. The feedback path of the operational amplifier, wherein any one of a resistance element, an impedance element, an active element, or a circuit network in which an impedance element and an active element are combined is connected in parallel to the feedback path. The capacitance detection circuit according to claim 3.   5. The electrostatic according to claim 1, wherein the A / D converter converts an analog signal having a potential difference between an output potential of the charge amplifier and a reference potential into a digital signal. Capacitance detection circuit.   The A / D converter is an analog signal composed of a difference potential between the output potential of the charge amplifier corresponding to the rising edge of the drive signal and the output potential of the charge amplifier corresponding to the falling edge of the drive signal. The capacitance detection circuit according to claim 1, wherein the capacitance detection circuit is converted into a digital signal.   And a third feedback circuit that feeds back a signal corresponding to an output obtained by converting an analog signal having a difference between an output potential of the charge amplifier and a reference potential into a digital signal to an input of the charge amplifier. The capacitance detection circuit according to claim 5.   An analog signal composed of a difference potential between the output potential of the charge amplifier corresponding to the rising edge of the drive signal and the output potential of the charge amplifier corresponding to the falling edge of the drive signal is converted into a digital signal. 6. The capacitance detection circuit according to claim 5, further comprising a third feedback circuit that feeds back a corresponding signal to the input of the charge amplifier. An input device comprising the capacitance detection circuit according to claim 1.