JP2012164083A - Capacitance detection circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To shorten a data update rate without deteriorating precision (quantization noise) of a delta sigma AD converter in a capacitance detection circuit.SOLUTION: The frequency of a sampling clock ADC_CLK of a delta sigma AD converter 16 is set to be higher than the frequency of an amplifier clock AMP_CLK of a charge amplifier 14 so as to shorten the data update rate of N-bit digital data AD_OUT output from the delta sigma AD converter 16. Further, a track holding circuit 15 is interposed between the charge amplifier 14 and delta sigma AD converter 16 so as to periodically take in and hold only an output voltage AMP_OUT in a charge transfer mode of the charge amplifier 14.

Description

  The present invention relates to a capacitance detection circuit used for a capacitance type touch sensor.

  Conventionally, a capacitive touch sensor is known as an input device of various electronic devices such as a mobile phone, a portable audio device, a portable game device, a television, and a personal computer.

  A capacitive touch sensor basically forms a plurality of capacitances on a capacitive touch panel, and detects a change in the capacitance value of the capacitance due to the touch of a human finger or the like. By detecting by this, the touch position of a human finger or the like is detected.

  The capacitance detection circuit includes a charge amplifier that converts a change in capacitance value into an output voltage proportional to the capacitance value, and a delta-sigma that AD-converts the output voltage of the charge amplifier and outputs N-bit digital data. It is composed of a type AD converter. In this case, the charge amplifier operates in accordance with a sensing clock that senses capacitance, and the delta-sigma AD converter operates in accordance with a sampling clock that samples the output voltage of the charge amplifier.

JP 2010-182290 A

In order to speed up the operation of the capacitive touch sensor, it is necessary to reduce the data update rate of N-bit digital data, which is the output of the delta-sigma AD converter. However, since the capacitive touch panel has parasitic resistance values and capacitance values, the sensing clock has an upper limit. (Generally around 250KHz)
Further, in the conventional capacitance detection circuit, the frequency of the sampling clock of the charge amplifier and the sampling clock of the delta-sigma type AD converter are the same. Therefore, the data update rate is determined by the upper limit frequency of the sensing clock, and there is a problem that the data update rate cannot be further reduced.

Therefore, the capacitance detection circuit of the present invention is a capacitance detection circuit that detects a difference between the capacitance values of the first capacitance and the second capacitance formed on the touch panel.
A clock generation circuit for generating a first clock, a second clock, and a third clock; and a capacitance value of the first capacitance and the second capacitance when the first clock is at a first level. A charge amplifier that outputs an output voltage corresponding to a difference between the capacitance value of the first capacitor and a reset voltage when the first clock is at a second level, and according to the second clock, When the first clock is at the first level, a holding circuit that captures and holds the output voltage, and according to the third clock, the output voltage held in the holding circuit is sampled, and digitally And a delta-sigma type AD converter that outputs data, wherein the frequency of the third clock is set higher than the frequency of the first clock.

  According to the capacitance detection circuit of the present invention, the frequency of the sampling clock of the delta sigma type AD converter is made higher than the frequency of the amplifier clock (= sensing clock) of the charge amplifier, and the charge amplifier and the delta sigma type are provided. By inserting a holding circuit that holds the output voltage of the charge amplifier between the AD converter, the data update rate can be shortened without degrading the accuracy (quantization noise) of the delta-sigma AD converter. Is possible.

It is a figure which shows the whole structure of the electrostatic capacitance type touch sensor containing the electrostatic capacitance detection circuit in embodiment of this invention. FIG. 6 is an operation timing chart of the drive circuit. It is a circuit diagram of the electrostatic capacitance detection circuit in the embodiment of the present invention. It is an operation | movement timing diagram of the electrostatic capacitance detection circuit in embodiment of this invention. It is a circuit diagram of the electrostatic capacitance detection circuit in a reference example. It is an operation | movement timing diagram of the electrostatic capacitance detection circuit in a reference example. It is sectional drawing of a touch panel. It is a circuit diagram of a charge amplifier. It is a figure explaining operation | movement of a charge amplifier. It is a figure which shows the characteristic of a charge amplifier. It is a circuit diagram which shows the structure of a track hold circuit. It is a block diagram which shows the structure of a delta-sigma type AD converter.

  FIG. 1 is a diagram showing an overall configuration of a capacitive touch sensor including a capacitance detection circuit according to an embodiment of the present invention.

  The capacitive touch sensor includes a touch panel 1 and a capacitance detection circuit 11. The touch panel 1 is formed of a substrate 1a made of an insulator such as glass, and m X lines XL1 to XLm are formed in the X direction on the substrate 1a. On the substrate 1a, n Y lines YL1 to YLn are formed in the Y direction so as to intersect the X lines XL1 to XLm. The X lines XL1 to XLm and the Y lines YL1 to YLn are insulated from each other through an insulating layer and capacitively coupled. These X lines XL1 to XLm and Y lines YL1 to YLn are formed of transparent electrodes such as ITO or normal electrodes.

  The capacitance detection circuit 11 detects the touch position by selectively driving the X lines XL1 to XLm of the touch panel 1 and detecting capacitance changes of the Y lines YL1 to YLn. In this case, the X lines XL1 to XLm are drive lines, and the Y lines YL1 to YLn are sense lines.

  The capacitance detection circuit 11 includes a drive circuit composed of switches SX1 to SXm and an X selection circuit 12, a Y selection circuit 13, a charge amplifier 14, a track hold circuit 15, a delta-sigma type AD converter 16, and a clock generation circuit 17. It is comprised including.

  The clock generation circuit 17 generates an amplifier clock AMP_CLK (sensing clock) that is an operation clock of the charge amplifier 14, a track hold clock TH_CLK of the track hold circuit 15, and a sampling clock ADC_CLK of the delta sigma type AD converter 16. .

  The amplifier clock AMP_CLK from the clock generation circuit 17 is applied to the first terminal of the switch SXi (i = 1 to m) via the buffer 18. The amplifier clock AMP_CLK is a clock that repeats the H level and the L level. The H level is the power supply voltage VDD of the capacitance detection circuit 11, and the L level is 0V. As the H level of the amplifier clock AMP_CLK, a voltage Vref different from VDD can be used instead of the power supply voltage VDD. In this case, however, a circuit must be configured with an operational amplifier. By using the power supply voltage VDD as the H level of the amplifier clock AMP_CLK, it is possible to configure a circuit with a logic circuit such as a normal inverter or buffer, and considering the LSI chip size, it is advantageous in that no operational amplifier is used. It is.

  The corresponding X line XLi (i = 1 to m) is connected to the second terminal of the switch SXi (i = 1 to m). When the switch SXi is turned on, the amplifier clock AMP_CLK is supplied to the X line XLi. The X selection circuit 12 outputs control signals φ1 to φm for controlling on / off of the switches SX1 to SXm. The control signals φ1 to φm are pulse signals.

  FIG. 2 is an example of an operation timing chart of the drive circuit configured by the switches SX1 to SXm and the X selection circuit 12 as described above. First, while the control signal φ1 is at the H level, the other control signals φ2 to φm are at the L level, and only the switch SX1 is turned on. Therefore, during this period, the amplifier clock AMP_CLK is supplied only to the X line XL1. Next, while the control signal φ2 is at the H level, the other control signals φ1, φ3 to φm are at the L level, and only the switch SX2 is turned on. Therefore, during this period, the amplifier clock AMP_CLK is supplied only to the X line XL2. Thereafter, scanning is similarly performed. The scanning method may be random instead of sequential.

  The Y selection circuit 13 sequentially selects the first Y line YLs and the second Y line YLs + 1 from the Y lines YL1 to YLn for each period in which the switches SX1 to SXm are on. That is, the first Y line YL1 and the second Y line YL2 are selected, then the third Y line YL3 and the fourth Y line YL4 are selected, and then the fifth Y line YL5 and the second Y line are selected. Scanning is performed such that six Y lines YL6 are selected. The scanning method may be random instead of sequential.

  The selected first and second Y lines YLs and YLs + 1 are input to the non-inverting input terminal (+) and the inverting input terminal (−) of the charge amplifier 14, respectively. The charge amplifier 14 includes a first capacitance value between the first Y line YLs and the X line XLi selected by the X selection circuit 12, and the second Y line YLs + 1 and the X selection circuit 12 selected by the X selection circuit 12. An output voltage AMP_OUT corresponding to the difference from the second capacitance value with the line XLi is output.

  FIG. 3 is a circuit diagram of the capacitance detection circuit 11 extracted from FIG. In this example, the X selection circuit 12 selects the X line XL1, and the Y selection circuit 13 selects the first Y line YL1 and the second Y line YL2. Accordingly, the first Y line YL1 is connected to the non-inverting input terminal (+) of the charge amplifier 14 while the amplifier clock AMP_CLK is supplied to the X line XL1, and the second Y line YL2 is connected to the charge amplifier. 14 inverting input terminals (−).

  Then, the charge amplifier 14 is set to the charge transfer mode when the amplifier clock AMP_CLK is at the L level, and the charge capacitance of the first capacitance C1 formed between the first Y line YL1 and the X line XL1 is set. The output voltage AMP_OUT corresponding to the difference between the first capacitance value CA1 and the second capacitance value CA2 of the second capacitance C2 formed between the second Y line YL2 and the X line XL1 is output. The charge amplifier 14 is set to the charge accumulation mode when the amplifier clock AMP_CLK is at the H level, and the output voltage AMP_OUT is reset to a constant reset voltage.

  The track hold circuit 15 takes in and holds the output voltage AMP_OUT when the amplifier clock AMP_CLK is at the H level in accordance with the track hold clock TH_CLK. Specifically, the track hold circuit 15 samples the output voltage AMP_OUT of the charge amplifier 14 in response to the rise of the track hold clock TH_CLK, and in response to the fall of the track hold clock TH_CLK, the charge amplifier 14 at that time. Output voltage AMP_OUT.

  The delta sigma type AD converter 16 samples the output voltage T / H_OUT of the track hold circuit 15 according to the sampling clock ADC_CLK, and outputs N-bit digital data AD_OUT.

  In this case, in order to shorten the data update rate of the N-bit digital data AD_OUT output from the delta sigma type AD converter 16, the frequency of the sampling clock ADC_CLK of the delta sigma type AD converter 16 is the charge amplifier 14 charge. It is set higher than the frequency of the amplifier clock AMP_CLK in the transfer mode. At this time, the frequency of the amplifier clock AMP_CLK of the charge amplifier 14 is preferably set to an upper limit value (generally about 250 KHz) for high-speed operation of the capacitive touch sensor. In the example of FIG. 3, the upper limit value of the frequency of the amplifier clock AMP_CLK of the charge amplifier 14 is a specific frequency determined by the parasitic resistance and parasitic capacitance of the X line XL1 formed on the touch panel 1.

  The track hold circuit 15 is provided for interpolating the output voltage AMP_OUT of the charge amplifier 14. That is, when the frequency of the sampling clock ADC_CLK of the delta sigma type AD converter 16 is made higher than the frequency of the amplifier clock AMP_CLK of the charge amplifier 14, the delta sigma type AD converter 16 is an effective output voltage of the charge amplifier 14. In addition to the output voltage AMP_OUT in the charge transfer mode, the reset voltage in the charge accumulation mode of the charge amplifier 14 is sampled. Therefore, by inserting the track hold circuit 15 between the charge amplifier 14 and the delta sigma type AD converter 16, only the output voltage AMP_OUT in the charge transfer mode of the charge amplifier 14 is periodically captured and held. .

  Further, since it takes a certain time for the output voltage AMP_OUT of the charge amplifier 14 to stabilize when the amplifier clock AMP_CLK is at the L level, the track hold circuit 15 takes in the stabilized output voltage AMP_OUT, In order to hold the output voltage AMP_OUT, the rising timing of the track hold clock TH_CLK is preferably delayed from the falling timing (change from H level to L level) of the amplifier clock AMP_CLK.

== Operation of Capacitance Detection Circuit 11 ==
Next, the operation of the capacitance detection circuit 11 will be described with reference to FIG. First, when the standby signal STBY becomes L level, the standby state of the capacitance detection circuit 11 is released. Then, the clock generation circuit 17 starts to operate after a predetermined waiting time (Wait Time), for example, 2 μsec, and generates the amplifier clock AMP_CLK, the track hold clock TH_CLK, and the sampling clock ADC_CLK. As a result, the charge amplifier 14, the track hold circuit 15, and the delta sigma type AD converter 16 are in an operating state.

  The track hold circuit 15 samples the output voltage AMP_OUT in the charge transfer mode of the charge amplifier 14 in response to the rise of the track hold clock TH_CLK, and the charge amplifier 14 at that time in response to the fall of the track hold clock TH_CLK. Holds the output voltage AMP_OUT. As will be described later, the charge amplifier 14 outputs two voltages Vop and Vom in a differential format, and the output voltage AMP_OUT is defined by Vop−Vom. In FIG. 4, waveforms of Vop and Vom are shown.

  The delta sigma type AD converter 16 samples the output voltage T / H_OUT of the track hold circuit 15 according to the sampling clock ADC_CLK, and outputs N-bit digital data AD_OUT. In this case, N bits are 96 bits, for example. In FIG. 4, digital data BIT_STREAM output from the quantizer 22 of the delta sigma type AD converter 16 is shown. The digital data BIT_STREAM is output as N-bit digital data AD_OUT through the digital filter 24 as described later.

  Since the frequency of the sampling clock ADC_CLK of the delta sigma type AD converter 16 is set higher than the frequency of the amplifier clock AMP_CLK of the charge amplifier 14, N-bit digital data output from the delta sigma type AD converter 16. AD_OUT data update rate can be shortened. That is, when the delta sigma type AD converter 16 is constituted by a second order delta sigma type AD converter and a three-stage CIC (cascode integrated comb filter) is used as the digital filter in the output stage, the AD In order to ensure the conversion accuracy, for example, when the oversampling ratio OSR = 32, it is necessary to input 96 sampling clocks ADC_CLK to the delta sigma type AD converter 16. In this case, by increasing the frequency of the sampling clock ADC_CLK, the data update rate can be shortened without degrading AD conversion accuracy.

  FIG. 5 is a circuit diagram of a capacitance detection circuit in a reference example, and FIG. 6 is an operation timing chart thereof. In the capacitance detection circuit in the reference example, the frequency of the sampling clock ADC_CLK of the delta sigma type AD converter 16 and the frequency of the amplifier clock AMP_CLK of the charge amplifier 14 are the same. Since the delta sigma type AD converter 16 samples the output voltage AMP_OUT in the charge transfer mode of the charge amplifier 14, the track hold circuit 15 is also not provided. For this reason, the data update rate of the delta sigma type AD converter 16 is determined by the upper limit value (generally about 250 KHz) of the frequency of the amplifier clock AMP_CLK, and the data update rate cannot be further reduced. .

== Operation as a capacitive touch sensor ==
Next, the overall operation of the capacitive touch sensor will be described. FIG. 7 is a cross-sectional view of the touch panel 1. As illustrated, an X line XL1 is disposed on the substrate 1a, and a first Y line YL1 and a second Y line YL1 are disposed above the insulating layer 30 with the insulating layer 30 interposed therebetween.

  In a state where the human finger is not touching, the first capacitance value CA1 of the first capacitance C1 formed between the first Y line YL1 and the X line XL1, and the second Y line YL2 And the second capacitance value CA2 of the second capacitance C2 formed between the X line XL1 and the X line XL1 are equal. When (CA1 = CA2), the output voltage AMP_OUT in the charge transfer mode of the charge amplifier 14 is 0V. When a human finger touches the point P1 at the intersection of the first Y line YL1 and the X line XL1, the first capacitance value CA1 changes with respect to the second capacitance value CA2. This is because when the human finger is conductive and acts as a ground ground, a change occurs in the electric lines of force between the finger and the X line XL1, and between the finger and the first Y line YL1, and the capacitance is reduced. Because it changes.

  As a result, for example, when CA1 <CA2, the output voltage AMP_OUT of the charge amplifier 14 becomes a negative (−) voltage. Thereafter, scanning is performed by the Y selection circuit 13, but the output voltage AMP_OUT of the charge amplifier 14 for the other two Y lines selected by the Y selection circuit 13 (for example, the Y line YL3 and the Y line YL4) is Always 0V. In this way, the touch position can be detected based on the output voltage AMP_OUT of the charge amplifier 14.

  Next, multi-touch detection will be described. As shown in FIG. 1, it is assumed that points P1 and P2 on the touch panel 1 are touched simultaneously. In this case, the point P1 is similarly detected while the X line XL1 is driven as described above.

  The point P2 is detected while the next X line XL2 is driven. When the first Y line YL1 and the second Y line YL2 are selected by the Y selection circuit 13, the first Y line YL1 is charged by the charge amplifier 14 while the amplifier clock AMP_CLK is supplied to the X line XL2. The second Y line YL2 is connected to the inverting input terminal (−) of the charge amplifier 14. In this case, since the second capacitance value CA2 decreases with respect to the capacitance value CA1, the output voltage AMP_OUT of the charge amplifier 14 becomes a positive (+) voltage. In this way, the point P2 is detected. As described above, each intersection on the touch panel 1 is individually detected by scanning in the X and Y directions, so that the touches of the points P1 and P2 as shown in FIG. 1 and the touches of the points P3 and P4 can be distinguished. Is possible.

  Moreover, according to this embodiment, since the differential capacitance detection method is adopted, noise resistance can be improved. For example, when noise is applied to the selected first Y line YL 1 and second Y line YL 2, the noise is canceled out and the influence of the noise is suppressed from appearing in the output voltage AMP_OUT of the charge amplifier 14. .

  The Y selection circuit 13 sequentially selects the first Y line YLs and the second Y line YLs + 1 adjacent to each other from the Y lines YL1 to YLn, but the Y selection circuit 13 includes two non-adjacent ones. The Y line may be selected at random.

  Further, the Y selection circuit 13 may sequentially select only one first Y line YLs. In this case, the first Y line YLs selected by the Y selection circuit 13 is connected to the non-inverting input terminal (+) of the charge amplifier 14. One of the Y lines YL1 to YLn is connected to the inverting input terminal (−) of the charge amplifier 14. Alternatively, a dummy Y line other than the Y lines YL1 to YLn may be connected to the inverting input terminal (−) of the charge amplifier 14. The dummy Y line intersects with the X lines XL1 to XLm similarly to the Y lines YL1 to YLn.

As described above, the output voltage AMP_OUT of the charge amplifier 14 is input to the delta sigma type AD converter 16 via the track hold circuit 15, and the N-bit digital data AD_OUT is input.
Is converted to The N-bit digital data AD_OUT is output to the outside of the touch sensor via the interface circuit. And it is received by a microcomputer (not shown) provided outside, and signal processing for determining the touch position is performed.

  Hereinafter, specific configurations of the charge amplifier 14, the track hold circuit 15, and the delta-sigma type AD converter 16 will be described.

== Configuration of Charge Amplifier 14 ==
A specific configuration of the charge amplifier 14 will be described with reference to FIGS. As shown in FIG. 8, a portion surrounded by a broken line is a substrate 1a, and a first capacitance C1 and a second capacitance C2 are formed. The first capacitance C1 and the second capacitance C2 correspond to C1 and C2 in FIG. 7, respectively.

  An amplifier clock AMP_CLK is applied to a connection point between the first capacitance C1 and the second capacitance C2. The amplifier clock AMP_CLK can be generated by a switch circuit including switches SW1 and SW2 that are alternately switched. That is, when the switch SW1 is closed and the switch SW2 is opened, the ground voltage (0 V) is output, and when the switch SW1 is opened and the switch SW2 is closed, the power supply voltage VDD (plus voltage) is output.

  In addition, a third capacitance C3 is connected in series to the first capacitance C1, and a fourth capacitance C4 is connected in series to the second capacitance C2. Here, the capacitance values CA3 and CA4 of C3 and C4 are preferably equal to each other and approximately the same as CA1 and CA2.

  An inverting amplifier clock * AMP_CLK is applied to a connection point between the third capacitance C3 and the fourth capacitance C4. The inverted amplifier clock * AMP_CLK is an inverted version of the amplifier clock AMP_CLK. The amplifier clock AMP_CLK can be generated by a switch circuit including switches SW3 and SW4 that are alternately switched. That is, when the switch SW3 is closed and the switch SW4 is opened, the ground voltage (0 V) is output, and when the switch SW3 is opened and the switch SW4 is closed, the power supply voltage VDD (plus voltage) is output.

  Reference numeral 19 denotes a general differential amplifier. A non-inverted input terminal (+) is connected to wiring drawn from a connection point of the first and third capacitances C1 and C3, and an inverted input terminal thereof. The wiring drawn from the connection point of the second and fourth capacitances C2 and C4 is connected to (−).

  A feedback capacitor Cf is connected between the inverting output terminal (−) and the non-inverting input terminal (+) of the differential amplifier 19, and the non-inverting output terminal (+) and the inverting input terminal (−) of the differential amplifier 19. Are connected to the same feedback capacitor Cf. Let CAf be the capacitance value of the feedback capacitor Cf.

  Further, the switch SW5 is connected between the inverting output terminal (−) and the non-inverting input terminal (+) of the differential amplifier 19, and the switch SW6 is connected to the non-inverting output terminal (+) and the inverting input terminal ( -) Connected between. The switches SW5 and SW6 are switched simultaneously. That is, when the switches SW5 and SW6 are closed, the inverting output terminal (−) and the non-inverting input terminal (+) of the differential amplifier 19 are short-circuited, and the inverting output terminal (+) of the differential amplifier 19 is inverted. The input terminal (−) is short-circuited.

  When the voltage at the inverting output terminal (−) of the differential amplifier 19 is Vom and the voltage at the non-inverting output terminal (+) of the differential amplifier 19 is Vop, the difference voltage between them is the output voltage AMP_OUT (= Vop-Vom).

  Next, the operation of the circuit having the above configuration will be described with reference to FIG. This circuit has two operation modes of a charge accumulation mode and a charge transfer mode, and these two operation modes are alternately repeated many times.

  First, in the charge accumulation mode of FIG. 9A, the amplifier clock AMP_CLK is at the H level (VDD), and the inverting amplifier clock * AMP_CLK is at the L level (0 V). Then, the power supply voltage VDD is applied to the first and second capacitances C1 and C2. A ground voltage (0 V) is applied to the third and fourth capacitances C3 and C4.

  Further, SW5 and SW6 are closed. Thereby, the inverting output terminal (−) and the non-inverting input terminal (+) of the differential amplifier 19 are short-circuited, and the non-inverting output terminal (+) and the inverting input terminal (−) are short-circuited. As a result, the voltage at the node N1 (node connected to the inverting input terminal (−)), the voltage at the node N2 (node connected to the non-inverting input terminal (+)), the voltage Vom at the inverting output terminal (−), The voltage Vop at the non-inverting output terminal (+) becomes the reset voltage ½ VDD. However, the common mode voltage of the differential amplifier 19 is set to 1/2 VDD, which is 1/2 of the power supply voltage VDD.

  Next, in the charge transfer mode of FIG. 9B, the amplifier clock AMP_CLK is at the L level (0 V), and the inverted amplifier clock * AMP_CLK is at the H level (VDD). Then, the ground voltage (0 V) is applied to the first and second capacitances C1 and C2. Further, the power supply voltage VDD is applied to the third and fourth capacitances C3 and C4. In addition, SW5 and SW6 are opened.

  In this case, CA3 = CA4 = C, and the initial capacitance values of C1 and C2 are C. Further, a difference in capacitance between C1 and C2 when a human finger approaches the touch pad is assumed to be ΔC. That is, CA1−CA2 = ΔC. Then, CA1 = C + 1 / 2ΔC and CA2 = C−1 / 2ΔC are established.

  The charge amount of the node N1 is as follows.

In charge accumulation mode,
Charge amount of node N1 = (C−1 / 2ΔC) · (−1 / 2VDD) + C · (1 / 2VDD) + CAf · 0 (1)
Here, (C−1 / 2ΔC) · (−1 / 2VDD) is the charge amount of C2, C · (1 / 2VDD) is the charge amount of C4, and CAf · 0 (= 0) is the charge amount of Cf. It is.

In charge transfer mode
Charge amount of node N1 = (C−1 / 2ΔC) · (1 / 2VDD) + C · (−1 / 2VDD) + CAf · (Vop−1 / 2VDD) (2)
Here, (C−1 / 2ΔC) · (1 / 2VDD) is the charge amount of C2, C · (−1 / 2VDD) is the charge amount of C4, and CAf · (Vop−1 / 2VDD) is the charge amount of Cf. It is.

  In the charge accumulation mode and the charge transfer mode, the amount of charge at the node N1 is equal, and therefore, Expression (1) = Expression (2).

  Solving this equation for Vop yields:

Vop = (1 + ΔC / CAf) · (1 / 2VDD) (3)
Similarly, when the charge amount is obtained for the node N2, the charge conservation law is applied, and the equation is solved for Vom, the following expression is obtained.

Vom = (1−ΔC / CAf) · (1 / 2VDD) (4)
From the formulas (3) and (4), the output voltage AMP_OUT of the charge amplifier 14 is obtained.

AMP_OUT = Vop−Vom = (ΔC / CAf) · VDD (5)
That is, as shown in FIG. 10, the output voltage AMP_OUT of the charge amplifier 14 changes in proportion to the capacitance difference ΔC between the capacitance values CA1 and CA2.
== Configuration of Track Hold Circuit 15 ==
The configuration of the track hold circuit 15 will be described with reference to FIG. The output voltage AMP_OUT of the charge amplifier 14 is applied to the first and second input terminals IN1, IN2 of the track hold circuit 15. That is, the voltage Vom of the inverting output terminal (−) of the charge amplifier 14 is applied to the first input terminal IN1, and the voltage Vop of the non-inverting output terminal (+) of the charge amplifier 14 is applied to the second input terminal IN2. The A first analog switch ASW1 whose switching is controlled by a track hold clock TH_CLK is connected to the first input terminal IN1, and a first buffer Buff1 made of an operational amplifier is connected in series to the first analog switch ASW1. ing. A first holding capacitor CH1 is connected between the first analog switch ASW1 and the non-inverting input terminal (+) of the first buffer Buff1.

  Similarly, a second analog switch ASW2 whose switching is controlled by the track hold clock TH_CLK is connected to the second input terminal IN2, and a second buffer Buff2 made of an operational amplifier is connected in series to the second analog switch ASW2. It is connected to the. A second holding capacitor CH2 is connected between the second analog switch ASW2 and the non-inverting input terminal (+) of the second buffer Buff2.

  The track hold circuit 15 samples the output voltage AMP_OUT in the charge transfer mode of the charge amplifier 14 in response to the rise of the track hold clock TH_CLK, and in response to the fall of the track hold clock TH_CLK, the charge amplifier 14 at that time. Output voltage AMP_OUT is held by the first and second holding capacitors CH1 and CH2. The output voltage AMP_OUT of the charge amplifier 14 held by the first and second holding capacitors CH1 and CH2 is output from the output terminals OUT1 and OUT2 via the first and second buffers Buff1 and Buff2. Is output as

== Configuration of Delta-Sigma AD Converter 16 ==
The configuration of the delta sigma type AD converter 16 will be described with reference to FIG. The delta sigma type AD converter 16 is a second order delta sigma type AD converter 16, and includes a first integrator 20, a second integrator 21, a quantizer 22, a 1-bit DA converter 23, and a digital signal. A filter 24 is included. The input terminal IN is a differential input terminal, and the output voltage T / H_OUT of the track hold circuit 15 is input in a differential format.

  The delta sigma type AD converter 16 integrates the sum of the input signal (the output voltage T / H_OUT of the track hold circuit 15) and the output of the 1-bit DA converter 23 by the first integrator 20, The sum of the output of one integrator 20 and the output of the 1-bit DA converter 23 is further integrated by the second integrator 21, and the output of the second integrator 21 is quantized by the quantizer 22 to be 1 Bit digital data BIT_STREAM is generated.

  The digital data BIT_STREAM output from the quantizer 22 is converted into an analog signal by the 1-bit DA converter 23 and fed back to the respective inputs of the first integrator 20 and the second integrator 21. The digital data BIT_STREAM of the quantizer 22 is output through the digital filter 24 as N-bit digital data AD_OUT. The sampling clock ADC_CLK from the clock generation circuit 17 is input to the first integrator 20, the second integrator 21, and the digital filter 24.

DESCRIPTION OF SYMBOLS 1 Touch panel 1a Board | substrate 11 Capacitance detection circuit 12 X selection circuit 13 Y selection circuit 14 Charge amplifier 15 Track hold circuit 16 Delta-sigma type AD converter 17 Clock generation circuit 18 Buffer 19 Differential amplifier 20 1st integrator 21 1st integrator Integrator of 2 22 Quantizer 23 1-bit DA converter 24 Digital filter

Claims (6)

In the capacitance detection circuit that detects the difference between the capacitance values of the first capacitance and the second capacitance formed on the touch panel,
A clock generation circuit for generating a first clock, a second clock, and a third clock;
When the first clock is at the first level, an output voltage corresponding to the difference between the capacitance value of the first capacitance and the capacitance value of the second capacitance is output, and the first clock is output. A charge amplifier that outputs a reset voltage when the clock is at a second level;
A holding circuit that captures and holds the output voltage when the first clock is at a first level in response to the second clock;
A delta-sigma type AD converter that samples the output voltage held in the holding circuit in accordance with the third clock and outputs digital data, and sets the frequency of the third clock to the first clock A capacitance detection circuit, wherein the capacitance detection circuit is set higher than the frequency of one clock.   The second clock is delayed with respect to the second clock so that the holding circuit captures and holds the stabilized output voltage after the output voltage of the charge amplifier has stabilized. The capacitance detection circuit according to claim 1, wherein   The capacitance detection circuit according to claim 1, wherein the first clock and the second clock have the same frequency. In a capacitance detection circuit for detecting capacitance of a touch panel including a plurality of drive lines extending in one direction and a plurality of sense lines extending to intersect the plurality of drive lines,
A clock generation circuit for generating a first clock, a second clock, and a third clock;
A drive circuit that selects one drive line from the plurality of drive lines and applies the first clock to the selected drive line;
A selection circuit that sequentially selects adjacent first sense lines and second sense lines from the plurality of sense lines during a period in which the drive line is selected by the first selection circuit;
A capacitance value of a first capacitance formed between the first sense line and the drive line selected by the first selection circuit when the first clock is at a first level; Outputting an output voltage corresponding to a difference between a capacitance value of a second capacitance formed between the second sense line and the drive line selected by the first selection circuit; A charge amplifier that outputs a reset voltage when the first clock is at a second level;
A holding circuit that captures and holds the output voltage when the first clock is at a first level in response to the second clock;
A delta-sigma type AD converter that samples the output voltage held in the holding circuit in accordance with the third clock and outputs digital data, and sets the frequency of the third clock to the first clock A capacitance detection circuit, wherein the capacitance detection circuit is set higher than the frequency of one clock.   The second clock is delayed with respect to the second clock so that the holding circuit captures and holds the stabilized output voltage after the output voltage of the charge amplifier has stabilized. The capacitance detection circuit according to claim 4, wherein   The capacitance detection circuit according to claim 4, wherein the first clock and the second clock have the same frequency.

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