CN114327135B - Touch sampling circuit, touch sampling method and display device - Google Patents

Touch sampling circuit, touch sampling method and display device Download PDF

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CN114327135B
CN114327135B CN202111580766.8A CN202111580766A CN114327135B CN 114327135 B CN114327135 B CN 114327135B CN 202111580766 A CN202111580766 A CN 202111580766A CN 114327135 B CN114327135 B CN 114327135B
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sample
output
switch
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CN114327135A (en
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倪恩伟
杜含笑
其他发明人请求不公开姓名
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Beijing Eswin Computing Technology Co Ltd
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Beijing Eswin Computing Technology Co Ltd
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Abstract

The application provides a touch sampling circuit, a touch sampling method and a display device. The touch sampling circuit includes: the charge conversion circuit is used for converting the charge output by the touch output end into a first voltage signal and a second voltage signal based on the excitation voltage signal and outputting the first voltage signal and the second voltage signal; the circuit comprises a first switch circuit, a second switch circuit, a control circuit, a positive sampling and holding circuit, a negative sampling and holding circuit and an analog-to-digital converter; the control circuit is used for controlling the connection and disconnection of the first switch circuit and the second switch circuit based on the excitation voltage signal and the sampling signal; the first switch circuit is used for enabling the forward sampling holding circuit to receive the first voltage signal in a first sampling holding stage and outputting a first group of differential signals to the analog-to-digital converter based on the first voltage signal; the second switch circuit is used for enabling the negative direction sampling holding circuit to receive the second voltage signal in the second sampling holding stage and outputting a second group of differential signals to the analog-to-digital converter based on the second voltage signal.

Description

Touch sampling circuit, touch sampling method and display device
Technical Field
The application relates to the technical field of semiconductors, in particular to a touch sampling circuit, a touch sampling method and a display device.
Background
The display with the touch screen is convenient to use and simple to operate, so that the touch screen becomes a mainstream display screen of emerging electronic equipment such as mobile phones, tablets and smart watches. Touch screens are classified into resistive touch screens and capacitive touch screens according to touch methods, and no matter what touch screen is used, the problem that the performance of the touch screen cannot be avoided by improving the signal to noise ratio is solved.
The inventor of the present application finds that noise can be reduced by a Correlated Double Sampling (CDS) method, but the noise reduction of the existing CDS method is mainly achieved by analog filtering, which is fast and has a frequency of more than 1 mhz, but after the CDS method is converted into digital data and output, the digital filtering cannot be used for more flexible and complex source data algorithm processing.
Disclosure of Invention
The application provides a touch sampling circuit, a touch sampling method and a display device aiming at the defects of the existing method, and aims to solve the technical problems that the existing method for reducing the signal-to-noise ratio is single in noise filtering mode and inflexible in data processing.
In a first aspect, an embodiment of the present application provides a touch sampling circuit, including: the charge conversion circuit is used for converting the charge output by the touch output end into a first voltage signal and a second voltage signal based on the excitation voltage signal and outputting the first voltage signal and the second voltage signal, wherein the first voltage signal is a high-level signal, and the second voltage signal is a low-level signal;
the circuit comprises a first switch circuit, a second switch circuit, a control circuit, a positive sampling and holding circuit, a negative sampling and holding circuit and an analog-to-digital converter;
the control circuit is used for controlling the first switch circuit to be switched on and off and controlling the second switch circuit to be switched on and off based on the excitation voltage signal and the sampling signal;
the first switch circuit is used for enabling the forward sampling holding circuit to receive the first voltage signal and output a first group of differential signals to the analog-to-digital converter based on the first voltage signal in a first sampling holding stage under the control of the control circuit;
the second switch circuit is configured to, in a second sample-and-hold stage, under the control of the control circuit, enable the negative sample-and-hold circuit to receive the second voltage signal, and output a second set of differential signals to the analog-to-digital converter based on the second voltage signal;
the first sampling and holding stage corresponds to the first half cycle of the excitation voltage signal, and the second sampling and holding stage corresponds to the second half cycle of the excitation voltage signal.
Optionally, the first sample-and-hold phase includes a first sample phase and a first hold phase, and the second sample-and-hold phase includes a second sample phase and a second hold phase;
the first switch circuit is specifically configured to, under the control of the control circuit, conduct an input terminal of the forward sample-and-hold circuit with an output terminal of the charge conversion circuit in a first sampling phase, conduct an input terminal of the forward sample-and-hold circuit with the high-level reference signal terminal in a first holding phase, and conduct an output terminal of the forward sample-and-hold circuit with an input terminal of the analog-to-digital converter;
the second switch circuit is specifically configured to, under the control of the control circuit, conduct the input terminal of the negative-direction sample-and-hold circuit with the output terminal of the charge conversion circuit in a second sampling stage, conduct the input terminal of the negative-direction sample-and-hold circuit with the low-level reference signal terminal in a second holding stage, and conduct the output terminal of the negative-direction sample-and-hold circuit with the input terminal of the analog-to-digital converter.
Optionally, the first switch circuit includes a first forward input switch, a second forward input switch, a first forward output switch, and a second forward output switch;
the first forward input switch is respectively connected with the output end of the charge conversion circuit, the control circuit and the input end of the forward sampling and holding circuit and is configured to conduct the input end of the forward sampling and holding circuit with the output end of the charge conversion circuit in a first sampling stage;
the second forward input switch is respectively connected with the high-level reference signal end, the control circuit and the input end of the forward sampling and holding circuit and is configured to conduct the input end of the forward sampling and holding circuit and the high-level reference signal end in a first holding stage;
the first forward output switch is respectively connected with the first output end of the forward sample-and-hold circuit, the control circuit and the first input end of the analog-to-digital converter, and is configured to conduct the first output end of the forward sample-and-hold circuit and the first input end of the analog-to-digital converter in a first hold stage;
the second forward output switch is respectively connected with the second output end of the forward sample-and-hold circuit, the control circuit and the second input end of the analog-to-digital converter, and is configured to conduct the second output end of the forward sample-and-hold circuit and the second input end of the analog-to-digital converter in a first hold stage.
Optionally, the second switch circuit includes a first negative-direction input switch, a second negative-direction input switch, a first negative-direction output switch, and a second negative-direction output switch;
the first negative input switch is respectively connected with the output end of the charge conversion circuit, the control circuit and the input end of the negative sample-and-hold circuit, and is configured to connect the input end of the negative sample-and-hold circuit with the output end of the charge conversion circuit in a first sampling stage;
the second negative input switch is respectively connected with the low-level reference signal end, the control circuit and the input end of the negative sample-and-hold circuit, and is configured to conduct the input end of the negative sample-and-hold circuit with the low-level reference signal end in a first hold stage;
the first negative output switch is respectively connected with the first output end of the negative sample-and-hold circuit, the control circuit and the first input end of the analog-to-digital converter, and is configured to conduct the first output end of the negative sample-and-hold circuit and the second input end of the analog-to-digital converter in a first hold stage;
the second negative output switch is respectively connected to the second output end of the negative sample-and-hold circuit, the control circuit, and the second input end of the analog-to-digital converter, and is configured to connect the second output end of the negative sample-and-hold circuit to the first input end of the analog-to-digital converter in a first hold stage.
Optionally, the charge conversion circuit includes a charge amplifier, a first capacitor, a second capacitor, and a reset switch;
the first end of the first capacitor is connected with an excitation voltage signal end, the second end of the first capacitor is connected with the first input end of the charge amplifier, and the second input end of the charge amplifier is connected with the excitation voltage signal end;
the first end of the second capacitor is respectively connected with the first input end of the charge amplifier and the second end of the first capacitor, and the second end of the second capacitor is connected with the output end of the charge amplifier;
the first end of the reset switch is connected with the first end of the second capacitor, the second end of the reset switch is connected with the second end of the second capacitor, and the control end of the reset switch is connected with the control circuit;
the control circuit is further configured to control the reset switch to conduct during a reset phase.
Optionally, the forward sample-and-hold circuit includes a forward sample-and-hold circuit, a first forward sampling capacitor, a second forward sampling capacitor, a first forward hold capacitor, and a second forward hold capacitor;
the first input end of the forward sample and hold device is respectively connected with the second end of the first forward sampling capacitor and the first end of the first forward hold capacitor, the second input end of the forward sample and hold device is respectively connected with the second end of the second forward sampling capacitor and the first end of the second forward hold capacitor, the first output end of the forward sample and hold device is connected with the first forward output switch, and the second output end of the forward sample and hold device is connected with the second forward output switch;
a first end of the first forward sampling capacitor is connected with the first forward input switch and the second forward input switch; the first end of the second forward sampling capacitor is respectively connected with the high-level reference signal end and the second forward input switch;
the second end of the first forward holding capacitor is connected to the first output end of the forward sample holder, and the second end of the second forward holding capacitor is connected to the second output end of the forward sample holder.
Optionally, the negative-direction sample-and-hold circuit includes a negative-direction sample-and-hold circuit, a first negative-direction sampling capacitor, a second negative-direction sampling capacitor, a first negative-direction holding capacitor, and a second negative-direction holding capacitor;
a first input end of the negative sample holder is connected to a second end of the first negative sample capacitor and a first end of the first negative hold capacitor, respectively, a second input end of the negative sample holder is connected to a second end of the second negative sample capacitor and a first end of the second negative hold capacitor, respectively, a first output end of the negative sample holder is connected to the first negative output switch, and a second output end of the negative sample holder is connected to the second negative output switch;
a first end of the first negative-direction sampling capacitor is connected with the first negative-direction input switch and the second negative-direction input switch respectively, and a first end of the second negative-direction sampling capacitor is connected with the second negative-direction input switch and a low-level reference signal end;
a second end of the first negative holding capacitor is connected to a first output end of the negative sample-and-hold device, and a second end of the second negative holding capacitor is connected to a second output end of the negative sample-and-hold device.
In a second aspect, the present application provides a display device comprising a touch display panel and the touch sampling circuit according to the first aspect;
the touch display panel comprises a plurality of touch electrodes, and the touch electrodes are connected with the touch output ends.
In a third aspect, the present application discloses a touch sampling method based on the display device of the second aspect, including:
the charge conversion circuit receives the charge output by the touch control output end and the excitation voltage signal, and converts the charge into a first voltage signal and a second voltage signal;
in a first sample-and-hold stage, the first switch circuit receives a first control signal output by the control circuit, so that the forward sample-and-hold circuit receives the first voltage signal and outputs a first set of differential signals to the analog-to-digital converter based on the first voltage signal;
in a second sample-and-hold stage, the second switch circuit receives a second control signal output by the control circuit, so that the negative sample-and-hold circuit receives the second voltage signal and outputs a second set of differential signals to the analog-to-digital converter based on the second voltage signal.
Optionally, the first switch circuit includes a first forward input switch, a second forward input switch, a first forward output switch, and a second forward output switch;
the first switch circuit receives the first control signal output by the control circuit in the first sample-and-hold stage, so that the forward sample-and-hold circuit receives the first voltage signal and outputs a first set of differential signals to the analog-to-digital converter, comprising:
in a first sampling phase, the first forward input switch receives a first control signal output by the control circuit and is turned on, the input end of the forward sample-and-hold circuit is turned on with the output end of the charge conversion circuit, and the forward sample-and-hold circuit receives a voltage value of the first voltage signal;
in a first holding stage, the second forward input switch, the first forward output switch and the second forward output switch receive a first control signal output by the control circuit and are switched on, the input end of the forward sample-and-hold circuit is switched on with the high-level reference signal end, the output end of the forward sample-and-hold circuit is switched on with the input end of the analog-to-digital converter, and the forward sample-and-hold circuit outputs a first set of differential signals to the analog-to-digital converter.
Optionally, the second switch circuit includes a first negative-direction input switch, a second negative-direction input switch, a first negative-direction output switch, and a second negative-direction output switch;
in the second sample-and-hold stage, the second switch circuit receives the second control signal output by the control circuit, and the negative sample-and-hold circuit receives the second voltage signal and outputs a second set of differential signals to the analog-to-digital converter, including:
in a second sampling phase, the first negative input switch receives a second control signal output by the control circuit and is conducted, the input end of the negative sample-and-hold circuit is conducted with the output end of the charge conversion circuit, and the negative sample-and-hold circuit receives the voltage value of the first voltage signal;
in a second hold stage, the second negative-direction input switch, the first negative-direction output switch, and the second negative-direction output switch receive a second control signal output by the control circuit, the input end of the negative-direction sample-and-hold circuit is connected to the low-level reference signal end, the output end of the negative-direction sample-and-hold circuit is connected to the input end of the analog-to-digital converter, and the negative-direction sample-and-hold circuit outputs a second set of differential signals to the analog-to-digital converter.
Optionally, the touch sampling method further includes: in a first sampling and holding stage, the analog-to-digital converter receives the first group of differential signals, converts the first group of differential signals into digital signals and outputs the digital signals to a digital front-end module;
and in a second sampling and holding stage, the analog-to-digital converter receives the second group of differential signals, converts the second group of differential signals into digital signals and outputs the digital signals to the digital front-end module.
The beneficial technical effects brought by the technical scheme provided by the embodiment of the application comprise:
the touch-control sampling circuit that this application embodiment provided includes: the charge conversion circuit, the analog-to-digital converter, the positive sampling and holding circuit, the negative sampling and holding circuit, the control circuit, the first switch circuit and the second switch circuit; the charge conversion circuit is respectively connected with the touch output end, the first switch circuit and the second switch circuit, the charge output by the touch output end is converted into a first voltage signal and a second voltage signal based on an excitation voltage signal, the control circuit is respectively connected with the first switch circuit and the second switch circuit, the connection and disconnection of the first switch circuit are controlled, the connection and disconnection of the second switch circuit are controlled, and then the positive sampling circuit is selected to be used for sampling and holding or the negative sampling circuit is selected to be used for sampling and holding. This application carries out two-way sampling through adopting positive sample hold circuit and negative direction sample hold circuit, and positive sample hold circuit and negative direction sample hold circuit are direct to be connected with charge conversion circuit, carry out twice sampling in an excitation voltage cycle, export two sets of differential signal to adc to generate two sets of data signal in an excitation voltage cycle, make things convenient for follow-up flexibility to carry out digital filtering and handle, and then can effectively reduce the noise influence, promote signal to noise ratio.
The foregoing description is only an overview of the technical solutions of the embodiments of the present application, and the embodiments of the present application can be implemented according to the content of the description in order to make the technical means of the embodiments of the present application more clearly understood, and the detailed description of the embodiments of the present application will be given below in order to make the foregoing and other objects, features, and advantages of the embodiments of the present application more clearly understandable.
Drawings
The foregoing and/or additional aspects and advantages of the present application will become apparent and readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings of which:
fig. 1 is a touch circuit diagram according to an embodiment of the present disclosure;
fig. 2 is a schematic diagram of a touch front end according to an embodiment of the present disclosure;
fig. 3 is a schematic diagram of a charge conversion circuit according to an embodiment of the present application;
fig. 4 is a touch sampling circuit diagram according to an embodiment of the present disclosure;
fig. 5 is a diagram of another touch sampling circuit provided in the embodiment of the present application;
fig. 6 is a touch sampling analog waveform diagram provided in the embodiment of the present application;
fig. 7 is a schematic diagram of an analog-to-digital converter according to an embodiment of the present application;
FIG. 8 is a schematic diagram of another analog-to-digital converter provided in an embodiment of the present application;
fig. 9 is a schematic diagram of a touch sampling circuit according to an embodiment of the present disclosure;
fig. 10 is a waveform diagram of a partial signal of a touch sampling circuit according to an embodiment of the present disclosure;
fig. 11 is a flowchart of a touch sampling method according to an embodiment of the present disclosure.
Description of reference numerals:
1-touch capacitance; 2-parasitic capacitance; 3-touch control nodes; 100-touch sampling circuit; 110-a charge conversion circuit; 111-a first capacitance; 112-a charge amplifier; 113-a second capacitance; 114-a reset switch; 120-a forward sample and hold circuit; 121-a first forward sampling capacitance; 122-a first forward holding capacitance; 123-forward sample holder; 124-second forward sampling capacitance; 125-a second forward holding capacitance; 130-negative sample-and-hold circuit; 131-a first negative-going sampling capacitance; 132-a first negative-going holding capacitance; 133-negative-going sample-and-hold; 134-a second negative-going sampling capacitance; 135-a second negative-going holding capacitance; 140-an analog-to-digital converter; 141-a comparator; 142-a conversion module; 150-digital front end module; 210-a first switching circuit; 211-a first positive input switch; 212-a second positive input switch; 213 first positive output switch; 214-a second positive output switch; 220-a second switching circuit; 221-a first negative input switch; 222-a second negative input switch; 223 a first negative output switch; 224-a second negative output switch; 230-control circuit.
Detailed Description
Reference will now be made in detail to the present application, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to the same or similar parts or parts having the same or similar functions throughout. In addition, if a detailed description of the known art is not necessary for illustrating the features of the present application, it is omitted. The embodiments described below with reference to the drawings are exemplary only for the purpose of explaining the present application and are not to be construed as limiting the present application.
It will be understood by those within the art that, unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the prior art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
As used herein, the singular forms "a", "an", "the" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. It will be understood that when an element is referred to as being "connected" to another element, it can be directly connected to the other element or intervening elements may also be present. Further, "connected" as used herein may include wirelessly connected. As used herein, the term "and/or" includes all or any element and all combinations of one or more of the associated listed items.
Some terms appearing in the present application are explained first:
Signal-to-Noise ratio (SNR), also called Signal-to-Noise ratio, refers to the ratio of Signal to Noise in an electronic device or system. The signal inside refers to an electronic signal which comes from the outside of the device and needs to be processed by the device, the noise refers to an irregular extra signal which does not exist in an original signal generated after the device passes through, and the signal does not change along with the change of the original signal.
The research shows that the touch control sampling circuit adopted by the prior art mainly comprises a charge conversion circuit, an integrator, a sampling holding circuit and an analog-digital converter. The touch sampling circuit is used for collecting signals output by the touch panel after being touched, specifically, a charge conversion circuit included by the sampling circuit is connected with a touch output end of the touch panel, the charge conversion circuit converts charges output by the touch output end into voltage signals and outputs the voltage signals to an integrator, and the integrator processes the received voltage signals and sends the processed voltage signals to the sampling holding circuit. Touch sampling circuits in the prior art are all in single-ended output or unidirectional amplification mode. When the existing touch sampling circuit and the system framework thereof are adopted, the touch sampling circuit is characterized in that analog data processing and integration are realized, a high-frequency analog-to-digital converter is suitable, and the source data is difficult to add digital filtering processing.
Based on the above problems in the prior art, the application provides a touch sampling circuit, which applies correlated double sampling to the touch sampling circuit, so that two sets of sampling data are obtained after an analog-to-digital converter, and the influence of the noise of the middle and low frequency on the sampling data can be effectively reduced through further noise filtering, integration and processing of the digital circuit on the source data.
The following describes the technical solutions of the present application and how to solve the above technical problems with specific embodiments.
Referring to fig. 1, an embodiment of the present application provides a touch sampling circuit 100, including: the charge conversion circuit 110, the analog-to-digital converter 140, the positive sample-and-hold circuit 120, the negative sample-and-hold circuit 130, the control circuit 230, the first switch circuit 210, and the second switch circuit 220. The charge conversion circuit 110 is respectively connected to the touch output terminal, the first switch circuit 210 and the second switch circuit 220, and is configured to generate an excitation voltage signal V EX Converting the electric charge output by the touch output end into a first voltage signal V CA1 And a second voltage signal V CA2 And outputs a first voltage signal V CA1 Is a high level signal, a second voltage signal V CA2 Is a low level signal.
The control circuit 230 is respectively connected to the first switch circuit 210 and the second switch circuit 220, and is configured to be based on the excitation voltage signal (V) EX ) And a sampling Signal (SHA) that controls the turning on and off of the first switching circuit 210, and controls the turning on and off of the second switching circuit 220.
The first switch circuit 210 is respectively connected to the forward sample-and-hold circuit 120, the output terminal of the charge conversion circuit 110, the analog-to-digital converter 140 and the high level reference signal REFH terminal, and is used for enabling the forward sample-and-hold circuit 120 to receive the first voltage signal V in the first sample-and-hold stage under the control of the control circuit 230 CA1 And based on the first voltage signal V CA1 The first set of differential signals is output to the analog-to-digital converter 140.
The second switch circuits 220 are respectively connected with the negative sampling and holding circuitsThe circuit 130, the output terminal of the charge conversion circuit 110, the analog-to-digital converter 140 and the low-level reference signal REFL terminal are used for making the negative-direction sample-and-hold circuit 130 receive the second voltage signal V in the second sample-and-hold stage under the control of the control circuit 230 CA2 And based on the second voltage signal V CA2 Outputting a second set of differential signals to analog-to-digital converter 140; the first sample-and-hold stage corresponds to the first half cycle of the excitation voltage signal, and the second sample-and-hold stage corresponds to the second half cycle of the excitation voltage signal.
The various electrical signals that are input to the circuit in order to observe the characteristics of a circuit system are the excitation voltage signals V EX Excitation voltage signal V EX Also called as Guard Signal (Guard Signal), it can effectively eliminate the negative influence on the touch capacitance caused by the parasitic capacitance.
Optionally, the control circuit 230 in the embodiment of the present application may be a logic control circuit, and the logic control circuit receives the excitation voltage signal (V) EX ) And a sampling Signal (SHA) and based on the received excitation voltage signal (V) EX ) And the sampling Signal (SHA) outputs a control signal to the first switching circuit 210 and the second switching circuit 220.
This application embodiment is through adopting positive direction sample hold circuit 120 and negative direction sample hold circuit 130 to carry out two-way sampling, and positive direction sample hold circuit 120 and negative direction sample hold circuit 130 are direct to be connected with charge conversion circuit 110, can carry out twice sampling in an excitation voltage cycle, output two sets of difference signal to analog to digital converter to generate two sets of data signals in an excitation voltage cycle, make things convenient for subsequent digital filtering to handle, can effectively reduce the noise influence, promote signal to noise ratio.
When the digital filtering is adopted, the area of a single analog-to-digital converter can be smaller, source data generated by the analog-to-digital converter can be very easily processed through the digital filtering, the application flexibility of the data is higher, errors of data deviation can be obviously reduced, and the digital filtering can be well applied to a touch sampling circuit which has low requirement on the speed of the analog-to-digital converter, needs a small area and has more flexible data.
Alternatively, referring to fig. 1, when the control circuit 230 is specifically configured, the input terminal of the control circuit 230 may be configured to be connected to the excitation voltage signal V EX And a sampling signal SHA, the control circuit 230 based on the excitation voltage signal V EX The and-sampling signal SHA outputs a control signal to the first switch circuit 210 and the second switch circuit 220, controls the first switch circuit 210 to be turned on or off in the first sample-and-hold stage, and controls the second switch circuit 220 to be turned on or off in the second sample-and-hold stage. Those skilled in the art can select the signal connected to the input terminal of the control circuit 230 according to the actual design, so that the control signal output by the control circuit 230 satisfies the above condition.
In one embodiment, referring to fig. 2, the touch front end structure includes a touch capacitor C1, a parasitic capacitor C2, and a touch node 3. The touch screen generates a capacitance C1 from the touch node 3 to ground when touched by a finger, and since the electronic device inevitably has a parasitic capacitance C2, the parasitic capacitance C2 refers to the sum of parasitic capacitances from the touch node 3 to a signal line, such as a Gate (Gate) line or a Data (Data) line in the touch panel, and to other touch nodes. In practical application, the voltage V output by the touch output terminal can be adjusted I As a charge C due to touch.
Referring to fig. 3, the charge converting circuit 110 receives the charge C output by the touch output terminal (i.e. receives the voltage V output by the output terminal) I ) And converts the charge C into a voltage V, in one embodiment, the charge conversion circuit 110 includes a charge amplifier 112, a first capacitor 111, a second capacitor 113, and a reset switch 114; the first end of the first capacitor 111 is connected to the excitation voltage signal V EX A second terminal connected to a first input terminal, shown as the negative input terminal, of charge amplifier 112; the second input terminal (i.e., the positive input terminal in the figure) of the charge amplifier 112 is connected to the driving voltage signal V EX A terminal; a first end of the second capacitor 113 is connected with the first input end of the charge amplifier 112 and a second end of the first capacitor 111, and a second end of the second capacitor 113 is connected with the output end of the charge amplifier 112; a first terminal of the reset switch 114 is connected to a first terminal of the second capacitor 113, and a second terminal of the reset switch is connected to a second terminalA second terminal of the capacitor 113, a control terminal of the reset switch 114 is connected to the control circuit 230 (not shown); the control circuit 230 is further configured to control the reset switch 114 to be turned on during the reset phase. Specifically, in the embodiment of the present application, the charge converting circuit 110 is configured to receive the charge C output by the touch output terminal, and output the charge C according to the excitation voltage signal V EX Is converted into a first voltage signal V CA1 And a second voltage signal V CA2 。
Specifically, the capacitance of the touch detection is mainly the capacitance from the touch node to the ground, as shown in fig. 2 and fig. 3, that is, the capacitance of the touch detection is mainly the touch capacitance C1, which is not large enough, and if the parasitic capacitance C2 is added, the total amount of the finally detected charge C becomes large, thereby causing a touch detection error. In the embodiment of the present application, the second terminal of the first capacitor 111 is connected to the first input terminal of the charge amplifier 112, and the first terminal is connected to the driving voltage signal V EX Terminal, excitation voltage signal V EX Also called as a protection signal, it can effectively eliminate the influence of the parasitic capacitance C2 on the size of the touch capacitance C1, thereby reducing the touch detection error.
In the embodiment of the present application, the charge converting circuit 110 outputs the high-level reference signal V CA1 And a low level reference signal V CA2 Thereafter, a sample and hold is required. As shown in fig. 1-4, the first sample-and-hold stage includes a first sample stage S1 and a first hold stage H1, and the second sample-and-hold stage includes a second sample stage S2 and a second hold stage H2; the first switch circuit 210 is specifically configured to, under the control of the control circuit 230, conduct the input terminal of the forward sample-and-hold circuit 120 and the output terminal of the charge conversion circuit 110 in the first sampling phase S1, conduct the input terminal of the forward sample-and-hold circuit 120 and the high-level reference signal REFH terminal in the first hold phase H1, and conduct the output terminal of the forward sample-and-hold circuit 120 and the input terminal of the analog-to-digital converter 140; and the second switch circuit 220 is specifically configured to hold the negative-going sample in the second sampling phase S2 under the control of the control circuit 230The input terminal of the circuit 130 is connected to the output terminal of the charge converting circuit 110, and in the second holding phase H2, the input terminal of the negative-direction sample-and-hold circuit 130 is connected to the low-level reference signal REFL terminal, and the output terminal of the negative-direction sample-and-hold circuit 130 is connected to the input terminal of the analog-to-digital converter 140.
In the first sampling stage S1, the input terminal of the forward sample-and-hold circuit 120 receives a first voltage signal V CA1 And according to V CA1 Sampling is carried out, in a first holding stage H1, the input end of the forward sample-and-hold circuit 120 is switched to receive a high-level reference signal REFH, and a first group of differential signals are output to the analog-to-digital converter 140 according to the sampling result of the first sampling stage S1, and the analog-to-digital converter 140 generates a first group of data signals; similarly, during the second sampling phase S2, the negative sample-and-hold circuit 130 receives the second voltage signal V at the input terminal CA2 And according to V CA2 Sampling is carried out, in a second holding stage H2, the input end of the negative-going sample-and-hold circuit 130 is switched to receive the low-level reference signal REFL, and a second group of differential signals are output to the analog-to-digital converter 140 according to the sampling result of the second sampling stage S2, the analog-to-digital converter 140 generates a second group of data signals, the first sampling stage S1 and the first holding stage H1 correspond to the first half period of the excitation voltage signal, and the second sampling stage S2 and the second holding stage H2 correspond to the second half period of the excitation voltage signal, so that one excitation voltage signal V is obtained EX And completing two times of sampling in the period, and obtaining two groups of data signals after the analog-to-digital converter.
In one embodiment, referring to fig. 4, the first switching circuit 210 includes a first positive input switch 211, a second positive input switch 212, a first positive output switch 213, and a second positive output switch 214.
The first forward input switch 211 is respectively connected to the output terminal of the charge conversion circuit 110, the control circuit 230 (not shown in the figure) and the input terminal of the forward sample-and-hold circuit 120, and configured to turn on the input terminal of the forward sample-and-hold circuit 120 and the output terminal of the charge conversion circuit 110 in the first sampling phase S1.
The second forward input switch 212 is respectively connected to the high-level reference signal terminal REFH, the control circuit 230 (not shown in the figure) and the input terminal of the forward sample-and-hold circuit 120, and is configured to conduct the input terminal of the forward sample-and-hold circuit 120 and the high-level reference signal REFH terminal in the first hold phase H1.
The first forward output switches 213 are respectively connected to the first output terminals (shown as V) of the forward sample-and-hold circuit 120 ONH An output), a control circuit 230 (not shown) and a first input (shown as V) of the analog-to-digital converter 140 INP An input) configured to conduct a first output of the forward sample-and-hold circuit 120 with a first input of the analog-to-digital converter 140 during a first hold phase H1.
The second positive output switches 214 are respectively connected to the second output terminals (shown as V) of the positive sample-and-hold circuit 120 OPH An output), a control circuit 230 (not shown) and a second input (shown as V) of the analog-to-digital converter 140 INN An input) configured to conduct a second output of the forward sample-and-hold circuit 120 with a second input of the analog-to-digital converter 140 during the first hold phase H1.
In a first sampling phase S1: the first forward input switch 211 is turned on and the second forward input switch 212, the first forward output switch 213 and the second forward output switch 214 are turned off, so that the first voltage signal V is generated CA1 Is input to the forward sample-and-hold circuit 120; in the first holding phase H1: the second forward input switch 212 is turned on, the first forward input switch 211 is turned off, so that the high-level reference signal REFH is connected to the forward holding circuit 120, and the first forward output switch 213 and the second forward output switch 214 are both turned on, so that the first set of differential signals generated by the forward sample-and-hold circuit 120 is input to the analog-to-digital converter 140.
In another embodiment, with continued reference to fig. 4, the second switching circuit 220 includes a first negative-going input switch 221, a second negative-going input switch 222, a first negative-going output switch 223, and a second negative-going output switch 224.
The first negative-going input switch 221 is respectively connected to the output terminal of the charge conversion circuit 110, the control circuit 230 (not shown in the figure), and the input terminal of the negative-going sample-and-hold circuit 130, and is configured to connect the input terminal of the negative-going sample-and-hold circuit 130 and the output terminal of the charge conversion circuit 110 in the second sampling phase S2.
The second negative-going input switch 222 is respectively connected to the low-level reference signal terminal REFL, the control circuit 230 and the input terminal of the negative-going sample-and-hold circuit 130, and is configured to turn on the input terminal of the negative-going sample-and-hold circuit 130 and the low-level reference signal terminal REFL during the second hold period H2.
The first negative output switches 223 are respectively connected to the first output terminals (shown as V in the figure) of the negative sample-and-hold circuits 130 OPL An output), a control circuit 230 (not shown) and a second input (shown as V) of the analog-to-digital converter 140 INN An input) configured to conduct the first output of the negative sample-and-hold circuit 130 with the second input of the analog-to-digital converter 140 during the second hold phase H2.
The second negative output switches 224 are respectively connected to the second output terminals (shown as V) of the negative sample-and-hold circuits 130 ONL An output), a control circuit 230 (not shown) and a first input (shown as V) of the analog-to-digital converter 140 INP An input) configured to conduct a second output of the negative sample-and-hold circuit 130 with a first input of the analog-to-digital converter 140 during a second hold phase H2.
In a second sampling phase S2: the first negative-direction input switch 221 is turned on, and the second negative-direction input switch 222, the first negative-direction output switch 223 and the second negative-direction output switch 224 are turned off, so that the second voltage signal V is generated CA2 To the negative sample-and-hold circuit 130; in the second holding phase H2: the second negative-direction input switch 222 is turned on, the first negative-direction input switch 221 is turned off, so that the low-level reference signal REFL is connected to the negative-direction holding circuit 130, and both the first negative-direction output switch 223 and the second negative-direction output switch 224 are turned on, so that the second set of differential signals generated by the negative-direction sample-and-hold circuit 130 are input to the analog-to-digital converter 140.
Optionally, the voltage value of the high-level reference signal REFH is set as the excitation voltage signal V EX The voltage value of the high level stage and the voltage value of the low level reference signal REFL are the excitation voltage signal V EX Voltage value of low level stage. Selecting the excitation voltage signal V EX Is highThe level stage signal is used as a high-level reference signal to select the excitation voltage signal V EX The low-level phase signal is used as a low-level reference signal, so that the influence of other voltages on the touch sampling circuit can be avoided, such as reducing parasitic capacitance, improving sensitivity and stability of the touch sampling circuit, and the like.
The positive sample-and-hold circuit and the negative sample-and-hold circuit respectively perform sampling and holding at different stages, and in a specific embodiment, referring to fig. 4, the positive sample-and-hold circuit 120 includes a positive sample-and-hold circuit 123 (SHAH in fig. 4), a first positive sampling capacitor 121, a second positive sampling capacitor 124, a first positive hold capacitor 122, and a second positive hold capacitor 125, and the positive sample-and-hold circuit 123 includes a first input terminal (a positive input terminal shown in the figure), a second input terminal (a negative input terminal shown in the figure), and a first output terminal (V shown in the figure) ONH Output terminal), a second output terminal (shown as V in the figure) OPH An output).
A first input end of the forward sample holder 123 is connected to a second end of the first forward sampling capacitor 121 and a first end of the first forward holding capacitor 122, a second input end of the forward sample holder 123 is connected to a second end of the second forward sampling capacitor 124 and a first end of the second forward holding capacitor 125, respectively, a first output end of the forward sample holder 123 is connected to the first forward output switch 213, and a second output end of the forward sample holder 123 is connected to the second forward output switch 214.
A first end of the first forward sampling capacitor 121 is connected to the first forward input switch 211 and the second forward input switch 212, respectively, and a first end of the second forward sampling capacitor 124 is connected to the high-level reference electrical signal REFH end and the second forward input switch 212, respectively;
a second terminal of the first forward holding capacitor 122 is connected to a first output terminal of the forward sample holder 123, and a second terminal of the second forward holding capacitor 125 is connected to a second output terminal of the forward sample holder 123.
Similarly, with continued reference to the sample-and-hold circuit of fig. 4, in one particular embodiment, the negative sample-and-hold circuit 130 includes a negative sample-and-hold stage 133 (SHAL in fig. 4), a first negative sample capacitor 131,the second negative-direction sampling capacitor 134, the first negative-direction holding capacitor 132, the second negative-direction holding capacitor 135, and the negative-direction sample holder 133 include a first input terminal (a negative-direction input terminal shown in the figure), a second input terminal (a positive-direction input terminal shown in the figure), and a first output terminal (a positive-direction input terminal shown in the figure) OPL Output terminal), a second output terminal (shown as V in the figure) ONL An input).
A first input terminal of the negative sample holder 133 is connected to the second terminal of the first negative sample capacitor 131 and the first terminal of the first negative hold capacitor 132, respectively, a second input terminal of the negative sample holder 133 is connected to the second terminal of the second negative sample capacitor 134 and the first terminal of the second negative hold capacitor 135, respectively, a first output terminal of the negative sample holder 133 is connected to the first negative output switch 223, and a second output terminal of the positive sample holder 133 is connected to the second negative output switch 224.
A first end of the first negative-direction sampling capacitor 131 is connected to the first negative-direction input switch 221 and the second negative-direction input switch 222, respectively, and a first end of the second negative-direction sampling capacitor 134 is connected to the low-level reference electrical signal REFL end and the second negative-direction input switch 222, respectively;
a second terminal of the first negative-going holding capacitor 132 is connected to the first output terminal of the negative-going sample-and-hold circuit 133, and a second terminal of the second negative-going holding capacitor 135 is connected to the second output terminal of the negative-going sample-and-hold circuit 133.
It should be noted that, referring to fig. 4, the dc operating points of the sampling capacitor Cs, the holding capacitor Ch and the sample holder in the positive sample-and-hold circuit 120 and the negative sample-and-hold circuit 130 are all adjustable; the second capacitor 113 (Cfb shown in the figure) in the charge conversion circuit 110 is also adjustable; excitation voltage signal V in touch sampling circuit EX The voltage amplitude of the high level reference signal REFH and the low level reference signal REFL are also adjustable. Those skilled in the art can change the dc level potential and the amplitude of the output voltage by adjusting the above component parameters and the amplitude of the above loading voltage according to actual needs, and the specific adjustment relationship refers to the following formula:
for the charge conversion circuit 110, the output first voltage signal V CA1 And a second voltage signalNumber V CA2 And an excitation voltage signal V EX The second capacitor 113 (Cfb) has the following relationship:
V CA ＝C1/Cfb*(V EX -V I )
for the forward sample-and-hold circuit 120, the voltage at the output of the forward sample-and-hold circuit 123 has the following relationship with the sampling capacitance Cs and the holding capacitance Ch:
(V OPH -V ONH )＝Cs/Ch*(V CA -REFH)
for the negative sample-and-hold circuit 130, the voltage at the output of the negative sample-and-hold circuit 133 has the following relationship with the sampling capacitance Cs and the holding capacitance Ch:
(V OPL -V ONL )＝Cs/Ch*(V CA -REFL)
optionally, in a specific embodiment, referring to fig. 4 and 5, the switches are transmission gates, the transmission gates TG1 to TG9 in fig. 5 are in one-to-one correspondence with the switches 211 to 214, 221 to 224, and 114 in fig. 4, and the control circuit 230 receives the excitation voltage signal V EX And a sampling signal SHA, and according to the excitation voltage signal V EX And the control signal for controlling the conduction of the transmission gate is output by the SHA sampling signal
Figure GDA0003744250180000161
SHA-pos、
Figure GDA0003744250180000162
SHA-neg、
Figure GDA0003744250180000163
CA-reset。
Taking the transmission gate TG1 as an example, the device connected with the control signal SHA-pos is an NMOS tube and the control signal
Figure GDA0003744250180000171
The connected devices are PMOS tubes, and control signal ends of a transmission gate TG1 are respectively loaded
Figure GDA0003744250180000172
And a SHA-pos control signal, during a first sampling phase S1: excitation voltage signal V EX For high level, the sampling signal SHA is high level, the control circuit 230 is based on the excitation voltage signal V EX The sum sampling signal SHA outputs a high-level SHA-pos signal and a low-level SHA-pos signal
Figure GDA0003744250180000173
When the transmission gate TG1 is conducted, the voltage loaded by the control signal ends of the transmission gates TG2, TG3 and TG4 is opposite to that of the transmission gate TG1, and the transmission gates TG2, TG3 and TG4 are turned off; in the first holding phase H1: excitation voltage signal V EX The control circuit 230 is based on the excitation voltage signal V for high level and the sampling signal SHA for low level EX The sum-sampling signal SHA outputs a low-level SHA-pos signal and a high-level SHA-pos signal
Figure GDA0003744250180000174
The transmission gates TG2, TG3, and TG4 are turned on, and the transmission gate TG1 is turned off.
SHA-neg and SHA-neg are respectively loaded at a control signal end of a transmission gate TG5
Figure GDA0003744250180000175
Control signal, in a second sampling phase S2: excitation voltage signal V EX The control circuit 230 is based on the excitation voltage signal V for low level and the sampling signal SHA for high level EX The sum-sampling signal SHA outputting a high-level SHA-neg signal and a low-level
Figure GDA0003744250180000176
The signal, transmission gate TG5 is turned on at this moment, the voltage loaded by the control signal ends of transmission gates TG6, TG7 and TG8 is opposite to TG5, and transmission gates TG6, TG7 and TG8 are turned off; in the first holding phase H1: excitation voltage signal V EX The control circuit 230 is based on the excitation voltage signal V for high level and the sampling signal SHA for low level EX The sum sampling signal SHA outputs a low-level SHA-neg signal and a high-level
Figure GDA0003744250180000177
When the transmission gates TG6, TG7 and TG8 are conducted, the transmission gate TG5 is turned off; the transmission gate TG9 control signal ends are respectively loaded
Figure GDA0003744250180000178
And a CA-reset control signal, refer to the timing diagram of FIG. 6, at the activation voltage signal V EX Before the high-low level is converted, namely at the end of each holding phase, the high-low level is conducted for a period of time for resetting.
It can be understood by those skilled in the art that the above-mentioned setting of the switch circuit as a transmission gate and controlling the transmission gate by the control circuit is not a limitation to the present application, and those skilled in the art can set the switch circuit as a single MOS transistor, a single transistor, or the like according to the actual application requirement.
Further, after the positive sample-and-hold circuit and the negative sample-and-hold circuit output differential signals, the analog-to-digital converter 140 outputs digital signals according to the received differential signals. Referring to fig. 5, after the charge conversion circuit 110, the positive sample-and-hold circuit 120, the negative sample-and-hold circuit 130, and the analog-to-digital converter 140, a digital front-end module 150 is further included, and an output end of the analog-to-digital converter 140 is connected to the digital front-end module 150.
Referring to fig. 7, the analog-to-digital converter 140 includes a comparator 141 and a conversion module 142, where the comparator 141 is configured to compare the differential signals received by the analog-to-digital converter 140 and output digital signals according to the comparison result, and the conversion module 142 is configured to convert the digital signals output by the comparator 141 into bit numbers, and in this embodiment, the digital signals output by the comparator are converted by the conversion module and then output to the digital front-end module 150; digital filtering in this way has the problem of more interaction ends between digital and analog circuits.
In order to solve the problem of a large number of total interactive signals, in the specific embodiment of the present application, the output of each analog-to-digital converter in the digital filtering manner is converted into serial data, the serial data is directly input to the digital front-end module, and the serial data is converted into parallel data with a specific bit number in the digital front-end module. Specifically, referring to fig. 8 and 9, the analog-to-digital converter 140 includes only the comparator 141, and the conversion module 142 is located in the digital front-end module 150. The digital signal output from the comparator is directly output to the digital front-end module 150, and the digital front-end module 150 performs bit conversion.
Specifically, as shown in fig. 9, since the touch sampling circuit of the present application does not perform the integration process, n Analog-to-Digital converters (ADCs) are used for n touch nodes, if the ADCs are configured as shown in fig. 7, each ADC outputs 10 bits of data, and the total number of interaction signals is 10 × n, which may cause too many interaction ports between the Digital and Analog circuits. If the analog-to-digital converters are arranged as in 8, the output of each analog-to-digital converter is changed into serial data, that is, each analog-to-digital converter has only 1 output signal. The comparator output (i.e. serial data) of the analog-to-Digital converter can be directly input into a Digital Front End module (DFE), and the serial data is converted into parallel data with 10 bit digits in the Digital module, so that the Digital signals of n D [9:0] can be reduced into the Digital signals of n D [0], and the number of the interaction signals is reduced by 10 times.
Referring to the waveform diagram of the signal shown in fig. 10, in the digital front end module of the digital data generated by the analog-to-digital converter according to the embodiment of the present invention, a digital filtering manner, such as integration in the diagram, or averaging, weighted re-integration, etc., can be freely selected, and the digital data generated by the analog-to-digital converter can be very easily processed by an algorithm through digital filtering, so that the obtained data has higher flexibility in application, and errors in data fault tolerance and error correction, that is, errors in data deviation can be significantly reduced.
Based on the same inventive concept, the application provides a display device, which comprises a touch display panel and the touch sampling circuit, wherein the touch display panel comprises a plurality of touch electrodes, the touch electrodes are connected with a touch output end, and specifically, each touch electrode is connected with the touch output end through a touch lead. The display device has the same beneficial effects as the touch sampling circuit because the display device comprises the touch sampling circuit, and the description is omitted here.
Based on the same inventive concept, the present application provides a touch sampling method based on the display device, as shown in fig. 11, including:
s100: the charge conversion circuit receives the charge and the excitation voltage signal output by the touch output end and converts the charge into a first voltage signal and a second voltage signal;
s200: in a first sampling and holding stage, the first switch circuit receives a first control signal output by the control circuit, so that the forward sampling and holding circuit receives a first voltage signal and outputs a first group of differential signals to the analog-to-digital converter based on the first voltage signal;
s300: in a second sample-and-hold stage, the second switch circuit receives a second control signal output by the control circuit, so that the negative sample-and-hold circuit receives a second voltage signal and outputs a second set of differential signals to the analog-to-digital converter based on the second voltage signal.
According to the touch sampling method, the correlation double sampling method is used in the sampling stage of the touch method, sampling is performed twice in one excitation voltage period, and two groups of differential signals are output to the analog-to-digital converter, so that two groups of data signals are generated in one excitation voltage period, subsequent digital filtering processing is facilitated, noise influence can be effectively reduced, and the signal-to-noise ratio is improved.
Specifically, referring to fig. 2 and 3, when a finger touches the touch panel, a touch capacitance C1 from a touch node to ground is generated, and a parasitic capacitance C2 is excited by an excitation voltage signal V EX Shielded by the first capacitor 111 to make the touch output end output signal V I The voltage V output by the touch output end can be completely reflected by the size of the touch capacitor C1 I As the charge C due to touch.
Referring to fig. 4, 5 and 6, the first input terminal (negative input terminal) of the charge amplifier 112 in the charge conversion circuit 110 receives the charge C after the influence of the parasitic capacitance is removed by the first capacitor 111; referring to fig. 6, at the end of the previous sample-and-hold period, the next sample is reset, i.e. the charge of the second capacitor 113 is cleared, the reset switch 114 is turned on, and during this period, V I And V CA The signals are all equal to the excitation voltage V EX . The reset switch 114 is then turned off, and the voltage V is activated when the reset switch 114 is turned off EX Entering a high level stage, exciting a voltage V EX Gradually changing from a low potential to a high potential.
In the embodiment of the application, in the first sample-and-hold stage (corresponding to the S1 and H1 stages in FIG. 6), V I The signal is always equal to the stimulus voltage signal V due to the principle of the virtual short at the inputs of the charge amplifier 112 ("virtual short" means that in an ideal situation the potentials of the two inputs are equal, as if they were shorted together, but in fact there is no short, the requirement for virtual short is that the op-amp introduces negative feedback) EX And is combined with the excitation voltage signal V EX Change synchronously. V CA Then V is added to the charge amplifier 112 EX Generating a voltage difference, V CA Changing to a low level as charge is continuously accumulated. Then the sampling signal SHA changes to high level and enters the first sampling phase S1, the first forward input switch 211 is turned on, the forward sample holder 123 is turned on, and V is obtained due to the virtual short principle at the input of the amplifier CA The high reference level signal REFH at the other end of the forward sample and hold unit 123 changes to eventually reach a stable operating voltage point, at which point V is CA Is a DC high-potential first voltage signal V CA1 (ii) a After the first sampling is finished, the sampling signal SHA changes to low level, enters a first holding stage H1, the first forward input switch 211 is not turned on, the second forward input switch 212, the first forward output switch 213 and the second forward output switch 214 are turned on, and the first output end and the second output end of the forward sample holder 123 respectively output a differential signal V ONH And V OPH To an analog to digital converter 140.
The end of the first hold period H1 is a second sample-and-hold period for resetting the charge of the second capacitor 113 when the excitation voltage signal V is zero EX Enter a low level stage of a cycle, V I The signal is always equal to the driving voltage signal V due to the virtual short principle at the input of the charge amplifier 112 EX And with the excitation voltage signal V EX Change synchronously. V CA Then V is added due to the action of the charge amplifier 112 EX Generating a voltage difference, V CA It changes to a high level due to the constant accumulation of charge. Then the sampling signal SHA changes to high level, enters a second sampling stage S2, and is output in a first negative directionThe input switch 221 is turned on and the negative sample holder 133 is turned on, then V due to the virtual short principle at the amplifier input CA The low reference level signal REFL at the other end of the forward sample-and-hold unit 133 changes to finally reach a stable operating voltage point, where V is CA Is a DC low potential first voltage signal V CA2 After the second sampling, the sampling signal SHA changes to a low level, and enters a second holding stage H2, the first negative input switch 221 is turned off, the second negative input switch 222, the first negative output switch 223, and the second negative output switch 224 are turned on, and the first output end and the second output end of the negative sample holder 133 respectively output the differential signal V OPL And V ONL To analog to digital converter 140.
Further, referring to FIGS. 1, 4, 5 and 6, the voltage signal V is applied to the excitation voltage EX In the high level stage of one cycle, the output terminal of the charge conversion circuit 110 outputs the first voltage signal V with high DC level CA1 In the first sample-and-hold phase, i.e. the excitation voltage V EX When the voltage level is high, the first switch circuit 210 receives the first control signal outputted from the control circuit 230 (refer to fig. 5)
Figure GDA0003744250180000211
SHA-pos signal) so that the forward sample-and-hold circuit 120 receives the first voltage signal V CA1 And according to the first voltage signal V CA1 Outputting the first set of differential signals to the analog-to-digital converter 140, comprising the steps of:
s210: in the first sampling phase S1, i.e. the excitation voltage V EX When the sampling signal SHA is high, the first positive input switch 211 receives the first control signal output by the control circuit (refer to fig. 5)
Figure GDA0003744250180000212
SHA-pos signal) to make the input terminal of the forward sample-and-hold circuit 120 and the output terminal of the charge conversion circuit 110 conductive, the forward sample-and-hold circuit 120 receives the first voltage signal V CA1 ；
S220: in the first holding phase H1, i.e. the excitation voltage V EX When the sampling signal SHA is at a high level and at a low level, the second forward input switch 212, the first forward output switch 213, and the second forward output switch 214 receive the first control signal output by the control circuit (refer to fig. 5)
Figure GDA0003744250180000213
SHA-pos signal) so that the input terminal of the forward sample-and-hold circuit 120 is conducted with the high-level reference signal terminal REFH, the output terminal of the forward sample-and-hold circuit 120 is conducted with the input terminal of the analog-to-digital converter 140, and the forward sample-and-hold circuit 120 outputs a first set of differential signals to the analog-to-digital converter 140.
In specific implementation, referring to fig. 4, 5 and 6, the charge conversion circuit 110 is based on the high-level excitation voltage signal V EX Generating a first voltage signal V of high level CA1 In the first sampling phase S1, i.e. the excitation voltage V EX When the sampling signal SHA is at a high level, the first positive input switch 211 is turned on, the second positive input switch 212, the first positive output switch 213, the second positive output switch 214, the first negative output switch 223, and the second negative output switch 224 are turned off, and the first voltage signal V at a high level is turned on CA1 Is inputted to one end of the first forward sampling capacitor 121, and the first forward sampling capacitor 121 and the first forward holding capacitor 122 are connected to each other according to a first voltage signal V CA1 The stored charge is varied to produce a voltage V at the positive input of the positive sample-and-hold stage 123 (SHAH in FIG. 4) IPH The forward sample and hold circuit 120 is in the sample state.
In a first holding phase H1, i.e. the excitation voltage V EX When the sampling signal SHA is at a high level, the second positive input switch 212, the first positive output switch 213, and the second positive output switch 214 are turned on, the first positive input switch 211, the first negative output switch 223, and the second negative output switch 224 are turned off, the two input terminals of the positive sample holder 123 are connected to the first positive sampling capacitor 121 and the second positive sampling capacitor 124, and the same high-level reference signal REFH is input to the first positive sampling capacitor 121 and the first end of the second positive sampling capacitor 124, because the first positive sampling capacitor S1 is at the first sampling stage S1The capacitor 121 and the first forward holding capacitor 122 are driven by a first voltage signal V CA1 The change is stored and sampled, and the charges at the second ends of the first forward sampling capacitor 121 and the second forward sampling capacitor 124 are different, so that the forward sampling holder 123 can output the amplified differential signal V according to the charges stored in the first forward sampling capacitor 121 and the first forward holding capacitor 122 ONH And V OPH (ii) a The first forward output switch 213 and the second forward output switch 214 are turned on, and the holding time is short, generally in the order of microseconds or nanoseconds, and the charges on the capacitors are not easily lost in a short time, so the charges accumulated on the first forward sampling capacitor 121 can be held without sudden change, and at this stage, the forward sampling holding circuit 120 is in a holding state, and thus the amplified differential signal V is output to the analog-to-digital converter 140 ONH And V OPH 。
Similarly, referring to FIGS. 4, 5 and 6, the excitation voltage V EX In the low level stage of one period, the output end of the charge conversion circuit outputs a second voltage signal V with low DC level CA2 (ii) a In the second sample-and-hold phase, i.e. the excitation voltage V EX When the voltage level is low, the second switch circuit 220 receives the second control signal outputted from the control circuit 230 (refer to fig. 5)
Figure GDA0003744250180000221
SHA-neg signal) so that the negative sample-and-hold circuit 130 receives the second voltage signal V CA2 And according to the second voltage signal V CA2 Outputting the second set of differential signals to the analog-to-digital converter 140, comprising the steps of:
s310: in the second sampling phase S2, i.e. the excitation voltage V EX When the sampling signal SHA is at a low level and the first negative input switch 221 receives the second control signal output by the control circuit (refer to fig. 5)
Figure GDA0003744250180000222
SHA-neg signal) to make the input terminal of the negative-going sample-and-hold circuit 130 and the output terminal of the charge conversion circuit 110 conductive, the negative-going sample-and-hold circuit 130 receives the second voltage signal V CA2 ；
S320: in the second holding phase H2, i.e. the excitation voltage V EX When the sampling signal SHA is low, the second negative input switch 222, the first negative output switch 223, and the second negative output switch 224 receive the second control signal output by the control circuit (refer to fig. 5)
Figure GDA0003744250180000223
SHA-neg signal) such that the input terminal of the negative sample-and-hold circuit 130 is conducted with the low-level reference signal terminal REFL, the output terminal of the negative sample-and-hold circuit 130 is conducted with the input terminal of the analog-to-digital converter 140, and the negative sample-and-hold circuit 130 outputs the second set of differential signals to the analog-to-digital converter 140.
In specific implementation, referring to fig. 4, 5 and 6, the charge conversion circuit 110 is based on the low level of the excitation voltage signal V EX Generating a low-level first voltage signal V CA2 In the second sampling phase S2, i.e. the excitation voltage V EX When the sampling signal SHA is at a low level, the first negative-direction input switch 221 is turned on, the second negative-direction input switch 222, the first negative-direction output switch 223, the second negative-direction output switch 224, the first negative-direction output switch 223, and the second negative-direction output switch 224 are turned off, and the second voltage signal V at a low level is turned on CA2 The first negative-direction sampling capacitor 131 and the first negative-direction holding capacitor 132 are respectively connected to one end of the first negative-direction sampling capacitor 131 according to the second voltage signal V CA2 The stored charge is changed and the negative sample and hold circuit 130 is in a sampling state.
In the second holding phase H2, i.e. the excitation voltage V EX When the sampling signal SHA is at a low level, the second negative-direction input switch 222, the first negative-direction output switch 223, and the second negative-direction output switch 224 are turned on, the first negative-direction input switch 221, the first negative-direction output switch 223, and the second negative-direction output switch 224 are turned off, the two input terminals of the amplifier are connected to the first negative-direction sampling capacitor 131 and the second negative-direction sampling capacitor 134, and the same low-level reference signal REFL is input to the first terminals of the first negative-direction sampling capacitor 131 and the second negative-direction sampling capacitor 134 because the first negative-direction sampling capacitor 131, the second negative-direction sampling capacitor 134, and the low-level reference signal REFL are input during the second sampling period S2,The first negative holding capacitor 132 is driven by the second voltage signal V CA2 The change is charge storage sampled, and the charges at the second ends of the first negative-direction sampling capacitor 131 and the second negative-direction sampling capacitor 134 are different, so that the negative-direction sample holder 133 can output the amplified differential signal V according to the charges stored in the first negative-direction sampling capacitor 131 and the first negative-direction holding capacitor 132 OPL And V ONL (ii) a The first negative output switch 223 and the second negative output switch 224 are turned on, and because the holding time is short, generally in the order of microseconds or nanoseconds, and the charge on the capacitor is not easily lost in a short time, the charge accumulated on the first negative sampling capacitor 131 can be held without sudden change, at this stage, the negative sampling holding circuit 130 is in a holding state, and thus the amplified differential signal V is output to the analog-to-digital converter 140 OPL And V ONL 。
After either the positive-going sample-and-hold circuit 120 or the negative-going sample-and-hold circuit 130 outputs the differential signal,
referring to fig. 8, if the adc 140 includes the comparator 141, the conversion module 142 is located in the digital front end module 150; the flow of the output data signal is as follows:
the comparator 141 receives the first set of differential signals, the comparator 141 outputs the first set of digital signals to the digital front-end module 150 directly according to the first set of differential signals, and the digital front-end module 150 performs bit number conversion through the conversion module 142; the comparator 140 receives the second set of differential signals, and the comparator 140 outputs a digital signal to the digital front end module 150 according to the second set of differential signals, and the digital front end module 150 performs bit number conversion through the conversion module 142.
Specifically, referring to fig. 8, the output of each analog-to-digital converter is changed into serial data, that is, each analog-to-digital converter has only 1 output signal. The comparator output (i.e. serial data) of the analog-to-Digital converter can be directly input into a Digital Front End module (DFE), and the serial data is converted into parallel data with 10 bit digits in the Digital module, so that the Digital signals of n D [9:0] can be reduced into the Digital signals of n D [0], and the number of the interaction signals is reduced by 10 times.
Those skilled in the art will understand that: the embodiment of the application can realize sampling twice in one period, so that two groups of data signals are obtained behind the analog-to-digital converter, and the digital noise filtering mode which can be used can be very flexible. If an integral algorithm is adopted, averaging, weighted averaging, integration after weighting and the like are adopted, and methods such as high-pass filtering, low-pass filtering and the like can be adopted according to actual requirements, the embodiment of the application can effectively reduce noise influence and improve the signal-to-noise ratio.
By applying the embodiment of the application, the following beneficial effects can be at least realized:
the touch-control sampling circuit that this application embodiment provided includes: the charge conversion circuit, the analog-to-digital converter, the positive sampling and holding circuit, the negative sampling and holding circuit, the control circuit, the first switch circuit and the second switch circuit; the charge conversion circuit is respectively connected with the touch output end, the first switch circuit and the second switch circuit, charges output by the touch output end are converted into a first voltage signal and a second voltage signal based on an excitation voltage signal, the control circuit is respectively connected with the first switch circuit and the second switch circuit, the connection and disconnection of the first switch circuit are controlled, the connection and disconnection of the second switch circuit are controlled, and then a positive sampling circuit is selected to be used for sampling and holding or a negative sampling circuit is selected to be used for sampling and holding.
1. According to the method, the correlation double-sampling method is used in the sampling stage of the touch method, sampling is performed twice in one excitation voltage period, and two sets of differential signals are output to the analog-to-digital converter, so that two sets of data signals are generated in one excitation voltage period, subsequent digital filtering processing is facilitated, noise influence can be effectively reduced, and the signal-to-noise ratio is improved.
2. The excitation voltage V is connected to one end of the first capacitor 111 EX One end of the charge amplifier 112 is connected to the first input end of the charge amplifier, so that the influence of the parasitic capacitance C2 can be significantly reduced, and the touch accuracy can be improved.
3. Sampling capacitor Cs, holding capacitor Ch, second capacitor 113, and excitation voltage signal V EX Voltage amplitude of (1), high level reference signal REFH amplitude, low level reference signal REFL amplitude andthe direct current working point of the sample holder can be freely adjusted; the second capacitance 113 is adjustable; those skilled in the art can make relevant adjustments according to actual conditions to further realize dynamic adjustment of the output signal of the touch sampling circuit.
Those of skill in the art will understand that various operations, methods, steps in the flow, measures, schemes discussed in this application can be alternated, modified, combined, or deleted. Further, other steps, measures, or schemes in various operations, methods, or flows that have been discussed in this application can be alternated, altered, rearranged, broken down, combined, or deleted. Further, the steps, measures, and schemes in the various operations, methods, and flows disclosed in the present application in the prior art can also be alternated, modified, rearranged, decomposed, combined, or deleted.
In the description of the present application, it is to be understood that the terms "center", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like indicate orientations or positional relationships based on those shown in the drawings, merely for convenience of description and simplicity of description, and do not indicate or imply that the devices or elements referred to must have a particular orientation, be constructed in a particular orientation, and be operated, and thus, are not to be construed as limiting the present application.
The terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present application, "a plurality" means two or more unless otherwise specified.
The particular features, structures, materials, or characteristics may be combined in any suitable manner in any one or more embodiments or examples.
It should be understood that, although the steps in the flowcharts of the figures are shown in order as indicated by the arrows, the steps are not necessarily performed in order as indicated by the arrows. The steps are not performed in the exact order shown and may be performed in other orders unless explicitly stated herein. Moreover, at least a portion of the steps in the flow chart of the figure may include multiple sub-steps or multiple stages, which are not necessarily performed at the same time, but may be performed at different times, and the order of execution is not necessarily sequential, but may be performed alternately or alternately with other steps or at least a portion of the sub-steps or stages of other steps.
The foregoing is only a partial embodiment of the present application, and it should be noted that, for those skilled in the art, several modifications and decorations can be made without departing from the principle of the present application, and these modifications and decorations should also be regarded as the protection scope of the present application.

Claims (12)

1. A touch sampling circuit, comprising:
the charge conversion circuit is connected with the excitation voltage signal end and used for converting the charge output by the touch control output end into a first voltage signal and a second voltage signal based on the excitation voltage signal and outputting the first voltage signal and the second voltage signal, wherein the first voltage signal is a high level signal, and the second voltage signal is a low level signal;
the circuit comprises a first switch circuit, a second switch circuit, a control circuit, a positive sampling and holding circuit, a negative sampling and holding circuit and an analog-to-digital converter;
the control circuit is used for controlling the first switch circuit to be switched on and off and controlling the second switch circuit to be switched on and off based on the excitation voltage signal and the sampling signal;
the first switch circuit is respectively connected with the output end of the charge conversion circuit, the control circuit, the input end of the forward sampling and holding circuit, a high-level reference signal end, the first output end of the forward sampling and holding circuit, the first input end of the analog-to-digital converter, the second output end of the forward sampling and holding circuit and the second input end of the analog-to-digital converter, and is used for enabling the forward sampling and holding circuit to receive the first voltage signal and output a first group of differential signals to the analog-to-digital converter based on the first voltage signal in a first sampling and holding stage under the control of the control circuit;
the second switch circuit is respectively connected to the output end of the charge conversion circuit, the control circuit, the input end of the negative sample-and-hold circuit, the low-level reference signal end, the first output end of the negative sample-and-hold circuit, the first input end of the analog-to-digital converter, the second output end of the negative sample-and-hold circuit, and the second input end of the analog-to-digital converter, and is configured to, in a second sample-and-hold stage, under the control of the control circuit, enable the negative sample-and-hold circuit to receive the second voltage signal and output a second set of differential signals to the analog-to-digital converter based on the second voltage signal;
the first sampling and holding phase corresponds to the first half period of the excitation voltage signal, and the second sampling and holding phase corresponds to the second half period of the excitation voltage signal.
2. The touch sampling circuit of claim 1, wherein the first sample-and-hold phase comprises a first sample phase and a first hold phase, and the second sample-and-hold phase comprises a second sample phase and a second hold phase;
the first switch circuit is specifically configured to, under the control of the control circuit, conduct an input terminal of the forward sample-and-hold circuit with an output terminal of the charge conversion circuit in a first sampling phase, conduct an input terminal of the forward sample-and-hold circuit with the high-level reference signal terminal in a first holding phase, and conduct an output terminal of the forward sample-and-hold circuit with an input terminal of the analog-to-digital converter;
the second switch circuit is specifically configured to, under the control of the control circuit, conduct the input terminal of the negative-direction sample-and-hold circuit with the output terminal of the charge conversion circuit in a second sampling stage, conduct the input terminal of the negative-direction sample-and-hold circuit with the low-level reference signal terminal in a second holding stage, and conduct the output terminal of the negative-direction sample-and-hold circuit with the input terminal of the analog-to-digital converter.
3. The touch sampling circuit of claim 1, wherein the first switching circuit comprises a first forward input switch, a second forward input switch, a first forward output switch, and a second forward output switch;
the first forward input switch is respectively connected with the output end of the charge conversion circuit, the control circuit and the input end of the forward sampling and holding circuit and is configured to conduct the input end of the forward sampling and holding circuit and the output end of the charge conversion circuit in a first sampling stage;
the second forward input switch is respectively connected with the high-level reference signal end, the control circuit and the input end of the forward sample-and-hold circuit, and is configured to conduct the input end of the forward sample-and-hold circuit with the high-level reference signal end in a first hold stage;
the first forward output switch is respectively connected with the first output end of the forward sample-and-hold circuit, the control circuit and the first input end of the analog-to-digital converter, and is configured to conduct the first output end of the forward sample-and-hold circuit and the first input end of the analog-to-digital converter in a first hold stage;
the second forward output switch is respectively connected with the second output end of the forward sample-and-hold circuit, the control circuit and the second input end of the analog-to-digital converter, and is configured to conduct the second output end of the forward sample-and-hold circuit and the second input end of the analog-to-digital converter in a first hold stage.
4. The touch sampling circuit of claim 1, wherein the second switch circuit comprises a first negative-going input switch, a second negative-going input switch, a first negative-going output switch, and a second negative-going output switch;
the first negative input switch is respectively connected with the output end of the charge conversion circuit, the control circuit and the input end of the negative sample-and-hold circuit, and is configured to conduct the input end of the negative sample-and-hold circuit with the output end of the charge conversion circuit in a first sampling stage;
the second negative-direction input switch is respectively connected with the low-level reference signal end, the control circuit and the input end of the negative-direction sampling and holding circuit, and is configured to connect the input end of the negative-direction sampling and holding circuit with the low-level reference signal end in a first holding stage;
the first negative output switch is respectively connected to the first output end of the negative sample-and-hold circuit, the control circuit and the first input end of the analog-to-digital converter, and is configured to connect the first output end of the negative sample-and-hold circuit and the second input end of the analog-to-digital converter in a first hold stage;
the second negative output switch is respectively connected to the second output end of the negative sample-and-hold circuit, the control circuit, and the second input end of the analog-to-digital converter, and is configured to connect the second output end of the negative sample-and-hold circuit to the first input end of the analog-to-digital converter in a first hold stage.
5. The touch sampling circuit of claim 1, wherein the charge conversion circuit comprises a charge amplifier, a first capacitor, a second capacitor, and a reset switch;
the first end of the first capacitor is connected with an excitation voltage signal end, the second end of the first capacitor is connected with the first input end of the charge amplifier, and the second input end of the charge amplifier is connected with the excitation voltage signal end;
a first end of the second capacitor is respectively connected with a first input end of the charge amplifier and a second end of the first capacitor, and a second end of the second capacitor is connected with an output end of the charge amplifier;
the first end of the reset switch is connected with the first end of the second capacitor, the second end of the reset switch is connected with the second end of the second capacitor, and the control end of the reset switch is connected with the control circuit;
the control circuit is further configured to control the reset switch to conduct during a reset phase.
6. The touch sampling circuit of claim 3, wherein the forward sample-and-hold circuit comprises a forward sample-and-hold circuit, a first forward sampling capacitor, a second forward sampling capacitor, a first forward hold capacitor, a second forward hold capacitor;
the first input end of the forward sample and hold device is respectively connected with the second end of the first forward sampling capacitor and the first end of the first forward hold capacitor, the second input end of the forward sample and hold device is respectively connected with the second end of the second forward sampling capacitor and the first end of the second forward hold capacitor, the first output end of the forward sample and hold device is connected with the first forward output switch, and the second output end of the forward sample and hold device is connected with the second forward output switch;
the first end of the first forward sampling capacitor is respectively connected with the first forward input switch and the second forward input switch; the first end of the second forward sampling capacitor is respectively connected with the high-level reference signal end and the second forward input switch;
the second end of the first forward holding capacitor is connected to the first output end of the forward sample holder, and the second end of the second forward holding capacitor is connected to the second output end of the forward sample holder.
7. The touch sampling circuit of claim 4, wherein the negative sample-and-hold circuit comprises a negative sample-and-hold circuit, a first negative sample capacitor, a second negative sample capacitor, a first negative hold capacitor, and a second negative hold capacitor;
a first input end of the negative sample holder is connected to a second end of the first negative sample capacitor and a first end of the first negative hold capacitor, respectively, a second input end of the negative sample holder is connected to a second end of the second negative sample capacitor and a first end of the second negative hold capacitor, respectively, a first output end of the negative sample holder is connected to the first negative output switch, and a second output end of the negative sample holder is connected to the second negative output switch;
a first end of the first negative sampling capacitor is connected with the first negative input switch and the second negative input switch respectively, and a first end of the second negative sampling capacitor is connected with the second negative input switch and the low-level reference signal end;
a second end of the first negative holding capacitor is connected to a first output end of the negative sample-and-hold device, and a second end of the second negative holding capacitor is connected to a second output end of the negative sample-and-hold device.
8. A display device comprising a touch display panel and the touch sampling circuit of any one of claims 1-7;
the touch display panel comprises a plurality of touch electrodes, and the touch electrodes are connected with the touch output ends.
9. A touch sampling method for a display device according to claim 8, comprising:
the charge conversion circuit receives the charge output by the touch control output end and the excitation voltage signal, and converts the charge into a first voltage signal and a second voltage signal;
in a first sampling and holding stage, the first switch circuit receives a first control signal output by the control circuit, so that the forward sampling and holding circuit receives the first voltage signal and outputs a first group of differential signals to the analog-to-digital converter based on the first voltage signal;
in a second sample-and-hold phase, the second switch circuit receives a second control signal output by the control circuit, so that the negative sample-and-hold circuit receives the second voltage signal and outputs a second set of differential signals to the analog-to-digital converter based on the second voltage signal.
10. The touch sampling method of claim 9, wherein the first switch circuit comprises a first forward input switch, a second forward input switch, a first forward output switch, and a second forward output switch;
the first switch circuit receives the first control signal output by the control circuit in the first sample-and-hold stage, so that the forward sample-and-hold circuit receives the first voltage signal and outputs a first set of differential signals to the analog-to-digital converter, including:
in a first sampling phase, the first forward input switch receives a first control signal output by the control circuit and is turned on, the input end of the forward sample-and-hold circuit is turned on with the output end of the charge conversion circuit, and the forward sample-and-hold circuit receives a voltage value of the first voltage signal;
in a first holding stage, the second forward input switch, the first forward output switch and the second forward output switch receive a first control signal output by the control circuit and are switched on, the input end of the forward sample-and-hold circuit is switched on with the high-level reference signal end, the output end of the forward sample-and-hold circuit is switched on with the input end of the analog-to-digital converter, and the forward sample-and-hold circuit outputs a first set of differential signals to the analog-to-digital converter.
11. The touch sampling method of claim 9, wherein the second switch circuit comprises a first negative-sense input switch, a second negative-sense input switch, a first negative-sense output switch, and a second negative-sense output switch;
in the second sample-and-hold stage, the second switch circuit receives the second control signal output by the control circuit, and the negative sample-and-hold circuit receives the second voltage signal and outputs a second set of differential signals to the analog-to-digital converter, including:
in a second sampling phase, the first negative input switch receives a second control signal output by the control circuit and is conducted, the input end of the negative sample-and-hold circuit is conducted with the output end of the charge conversion circuit, and the negative sample-and-hold circuit receives the voltage value of the first voltage signal;
in a second hold stage, the second negative-direction input switch, the first negative-direction output switch, and the second negative-direction output switch receive a second control signal output by the control circuit, the input end of the negative-direction sample-and-hold circuit is connected to the low-level reference signal end, the output end of the negative-direction sample-and-hold circuit is connected to the input end of the analog-to-digital converter, and the negative-direction sample-and-hold circuit outputs a second set of differential signals to the analog-to-digital converter.
12. The touch sampling method of any one of claims 9-11, wherein the touch sampling method further comprises:
in a first sampling and holding stage, the analog-to-digital converter receives the first group of differential signals, converts the first group of differential signals into digital signals and outputs the digital signals to a digital front-end module;
and in a second sampling and holding stage, the analog-to-digital converter receives the second group of differential signals, converts the second group of differential signals into digital signals and outputs the digital signals to the digital front-end module.
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