JP2015121732A - Drive circuit for display device, pixel circuit, and display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize the partial drive of an area defined by a desired gate line and a desired data line.SOLUTION: A drive circuit for a display device according to the present invention includes: a vertical direction drive unit (10), provided corresponding to each gate line and having a vertical direction shift register operating in synchronism with a vertical direction clock, for outputting, for each gate line, a V gate signal for activating the gate lines in accordance with the logical AND of a vertical control signal for switching whether or not to activate the gate lines and the output of the vertical shift register; and a horizontal direction drive unit (20), provided corresponding to each data line and having a horizontal direction shift register operating in synchronism with a horizontal direction clock, for outputting, for each data line, a H gate signal for activating the data lines in accordance with the logical AND of a horizontal control signal for switching whether or not to activate the data lines and the output of the horizontal shift register, with which partial drive is made possible.

Description

  The present invention relates to a drive circuit for a liquid crystal display device or an organic EL display device, and more particularly to a circuit technique for realizing partial drive of both desired gate lines and data lines.

  In recent years, TVs and mobile / smartphones using oxide semiconductors for backplane TFTs have been commercialized. An oxide semiconductor has favorable off-leakage characteristics, and can reduce power consumption by reducing the refresh rate. There are two low refresh rate (LRR) technologies as follows.

(1) Full screen LRR
In this method, the video data writing rate (refresh rate) is reduced by detecting the case where the video data of the previous screen and the screen to be displayed next are the same. This technique is effective in the case of still image display, and normally reduces from 60 Hz operation to a rate of 10 Hz or less. In this case, it is necessary to change the panel driving algorithm, but it is not necessary to change the circuit inside the panel.

(2) Partial LRR
In this method, the difference from the previous screen data is detected for each gate line, and video data is written only when the difference is detected. This is effective for images that are almost still images but need to be partially refreshed. In this case, it is necessary to change the panel driving algorithm and the circuit inside the panel (gate line driving circuit). Products equipped with partial LRR circuits are not yet on the market, and it is considered that reliable circuit technologies are being developed by each company.

  In addition, by using the LRR drive, touch detection can be performed during a time when video data is not written. As a result, it is possible to detect a smaller point (Pen destination recognition, etc.) or to detect a point where the S / N ratio has not been obtained so far, and to provide a more comfortable user interface function.

  As a conventional technique for the purpose of displaying an image only in a desired area, there is a liquid crystal display device that displays black in areas other than the display area. FIG. 7 is a block diagram showing an example of a drive circuit used in a conventional liquid crystal display device (see, for example, Patent Document 1).

  As shown in FIG. 7, the gate driver 104 is connected to each of the shift register stages S / R1 to S / R5 and the shift register stages S / R1 to S / R5 that are cascade-connected to the input line of the gate start pulse GSP. It includes a plurality of output switching units 104A to 104E connected. The plurality of shift register stages S / R1 to S / R5 receive one of the first clock CLK1 and the second clock CLK2.

  The first clock CLK1 and the second clock CLK2 are alternately input to the shift register stages S / R1 to S / R5. That is, the first clock CLK1 is input to the odd-numbered shift register stages S / R1, S / R3, and S / R5, but the second shift register stages S / R2 and S / R4 receive the second clock register CLK. The clock CLK2 is input.

  The first clock CLK1 and the second clock CLK2 have opposite phases and a frequency corresponding to ½ of the horizontal synchronization signal (that is, a period corresponding to twice). The plurality of shift register stages S / R1 to S / R5 are responsive to the first clock CLK1 or the second clock CLK2, and the gate start pulse GSP or the gate signal (Vg1) from the previous shift register stage S / R1 to S / R4. Any one of -Vg4) is latched, and gate signals Vg1-Vg5 supplied to the corresponding gate lines GL1-GL5 are generated.

  In response to the first clock CLK1, the first shift register stage S / R1 latches the gate start pulse GSP to generate the first gate signal Vg1. The first gate signal Vg1 is supplied to the first output switching unit 104A and the second shift register stage S / R2. The second shift register stage S / R2 latches the first gate signal Vg1 from the first shift register stage S / R1, which is the previous stage, by the second clock CLK2, and generates the second gate signal Vg2. The second gate signal Vg2 is supplied to the second output switching unit 104B and the third shift register stage S / R3, which is the next stage.

  The third shift register stage S / R3 responding to the first clock CLK1 also shifts the second gate signal Vg2 from the second shift register stage S / R2, which is the previous stage, to generate the third gate signal Vg3. . The third gate signal Vg3 is supplied to the third output switching unit 104C and the fourth shift register stage S / R4, which is the next stage.

  Accordingly, the remaining shift register stages S / R4 and S / R5 also respond to the first clock CLK1 or the second clock CLK2 and the third gate signal Vg3 from the previous shift register stages S / R3 and S / R4. Alternatively, the fourth gate signal Vg4 is latched and the corresponding gate signal Vg4 (or Vg5) is generated. The plurality of gate signals Vg1 to Vg5 generated from the plurality of shift register stages S / R1 to S / R5 are sequentially enabled in a specific logic (for example, high logic) state for each period of one horizontal synchronization signal.

  The plurality of output switching units 104A to 104E are electrically connected to the plurality of gate lines GL1 to GL5 on the display area of the liquid crystal panel, respectively. Further, the plurality of output switching units 104A to 104E commonly input the vertical window control signal VWS or the delayed vertical window control signal DVWS. The plurality of output switching units 104A to 104E responding in common to the vertical window control signal VWS or the delayed window control signal DVWS from the corresponding shift register stages S / R1 to S / R5 to the corresponding gate lines GL1 to GL5. The supplied gate signals Vg1 to Vg5 are switched.

  In the vertical window pulse period (base logic period) of the vertical window control signal VWS or the delayed vertical window control signal DVWS, the output switching units 104A to 104E correspond to the corresponding shift register stages S / R1 to S / R5. The corresponding gate signals Vg1 to Vg5 supplied to the gate lines GL1 to GL5 are cut off. On the other hand, in the specific logic enable period of the vertical window control signal VWS or the delayed vertical window control signal DVWS, each output switching unit 104A to 104A receives the gate from the corresponding shift register stage S / R1 to S / R5. Signals Vg1 to Vg5 are supplied to corresponding gate lines GL1 to GL5. The CLK signal is introduced only into the shift registers S / R1 to S / R5 and is not introduced into the output switching units Vg1 to Vg5.

  FIG. 8 is a circuit diagram of an output switching unit of the conventional liquid crystal display device shown in FIG. 7 and an example of a drive waveform. The n-th output switching unit Vgn controls whether the output Vgn of the n-th shift register S / Rn is passed or not by the vertical window control signal VWS. Here, when the vertical window control signal VWS is “H”, GLn (Vgn) is output, and when it is “L”, GLn (Vgn) is cut off.

  The transistor Tdrv in the nth shift register S / Rn drives the gate line through the transistor TGn in the nth output switching unit Vgn, and requires a large driving capability. The transistor TGn itself is also set to a large gate width in order to reduce the output resistance of the transistor Tdrv.

  The drive waveform of the vertical window control signal VWS is as follows. As shown in FIG. 8B, a case where the output to the first gate line GL1 and the second gate line GL2 and the output of the third gate line GL3 are cut off will be described. In this case, the vertical window control signal VWS maintains “H” until the second gate line GL2 becomes sufficiently “L”, and then is set to “L” before the third gate line GL3 rises.

JP 2008-003548 A

However, the prior art has the following problems.
In the prior art as disclosed in Patent Document 1, partial display is realized by partially selecting a gate line from among a number of gate lines and performing partial driving. However, there are the following problems. . First, when the display device is rotated 90 degrees, the row and the column are inverted, so that there is a problem that partial driving cannot be performed.

  For example, when only the upper part of the screen is partially displayed, in the conventional technique, a gate line to be activated is selected, and video data is output to all the Data lines. In this state, when the display device is rotated 90 degrees, after displaying the data for one screen, only the data on the upper part of the screen when the display device is rotated by 90 ° may be rewritten. However, since the portion corresponding to the upper portion of the screen corresponds to the data line, not the gate line, partial display cannot be performed, and the entire screen (all gate lines, all data lines) needs to be refreshed. Therefore, there is a problem that partial driving cannot be performed in a place rotated 90 degrees, and power consumption cannot be reduced.

  Further, when the gate line is activated in Patent Document 1, it is necessary to write data to all the data lines, and unnecessary power is consumed. Therefore, if data can be written only in an area required for rewriting, which is defined by a desired gate line and data line, refresh can be performed with a minimum power consumption.

  The present invention has been made in order to solve the above-described problems, and includes a driving circuit for a display device, a pixel circuit, and a pixel circuit that realize partial driving of a region defined by a desired gate line and a desired data line. And to obtain a display device.

  The drive circuit for a display device according to the present invention includes a vertical shift register provided corresponding to each gate line and operating in synchronization with a vertical clock, and activates the gate line for each gate line. A vertical driving unit that outputs a V gate signal that activates a gate line according to a logical product of a vertical control signal that switches whether or not to generate and a vertical shift register output, and a horizontal driving unit that is provided corresponding to each data line. A horizontal shift register that operates in synchronization with the direction clock, and for each data line, a data line according to the logical product of a horizontal control signal for switching whether to activate the data line and the output of the horizontal shift register And a horizontal direction drive unit that outputs an H gate signal for activating the gate line, and each of the gate line and the data line can be partially driven.

  The pixel circuit according to the present invention is a pixel circuit driven by the driving circuit for a display device according to the present invention, and performs on / off control of a plurality of subpixels constituting one pixel and a plurality of subpixels. The plurality of sub-pixels display data line data by turning on the respective gates connected in common to the output of one transistor. One transistor outputs a V gate signal to a gate of a subpixel when a gate connected to an H gate signal is turned on, and a pixel corresponding to partial drive by the V gate signal and the H gate signal. Display.

  According to the present invention, for a display device that realizes partial drive of a region defined by a desired gate line and a desired data line by providing a circuit configuration that enables partial drive of both the gate line and the data line. A driver circuit, a pixel circuit, and a display device can be obtained.

It is explanatory drawing regarding a structure and operation | movement of the partial drive circuit in Embodiment 1 of this invention. It is explanatory drawing regarding the structure of the partial drive circuit in Embodiment 1 of this invention, and a pixel circuit. It is the figure which showed the contrast of the drive waveform at the time of the normal drive and the partial drive in Embodiment 1 of this invention. 6 is a timing chart when an area display mode is selected in the first embodiment of the present invention. It is the figure which showed the activation area | region of the gate line at the time of rotating the display apparatus in Embodiment 1 of this invention, and a data line. It is the figure which showed the activation area | region of the gate line at the time of performing the area part display in Embodiment 1 of this invention, and a data line. It is the block diagram which showed an example of the drive circuit used for the conventional liquid crystal display device. FIG. 8 is a circuit diagram of an output switching unit of the conventional liquid crystal display device shown in FIG. 7 and a diagram illustrating an example of a drive waveform.

  Hereinafter, preferred embodiments of a driver circuit, a pixel circuit, and a display device for a display device of the present invention will be described with reference to the drawings.

Embodiment 1 FIG.
FIG. 1 is an explanatory diagram relating to the configuration and operation of the partial drive circuit according to Embodiment 1 of the present invention. The panel shown in FIG. 1 includes a vertical driving unit 10 including a vertical shift register and a vertical driving circuit, a horizontal driving unit 20 including a horizontal shift register and a horizontal driving circuit, and video data. A partial drive circuit including the driver 30 is provided, and a desired pixel of the display unit 100 is partially driven.

  In addition, as an internal configuration of the display unit 100, a state in which one pixel in units of RGB sub-pixels Pix R, Pix G, and Pix B is driven by the transistor T1 is illustrated.

The signal lines used in FIG. 1 are as follows.
VCLK: Clock signal in the vertical direction VOE: Gate activation signal in the vertical direction (= Vertical Output Enable signal)
Vgate: vertical gate signal generated by the vertical driving unit 10 based on VCLK and VOE HCLK: horizontal clock signal HOE: horizontal gate activation signal (= Horizontal Output Enable signal)
HSET: A signal for setting the data line to be partially driven, and a signal for switching between a normal display mode in which partial drive is not performed and an area display mode in which partial drive is performed. Hgate: Based on HCLK, HOE, and HSET Horizontal direction gate signal generated by the horizontal direction drive unit Npg: a signal line (Node-Pixel Gate) for supplying the output of the transistor T1 to each sub-pixel

Although not shown, the following signals are also used for partial driving.
VSR: signal output from the vertical shift register in the vertical direction drive unit 10 HSR: signal output from the horizontal direction shift register in the horizontal direction drive unit 20 VST: start signal in the vertical direction (for each line)

  The transistor T1 has a gate connected to the Hgate signal, an input connected to Vgate, and an output connected to Npg. Each subpixel is connected to a data line (R, G, B) that is an output of the video data driver 30 and Npg.

The vertical driving unit 10 activates Vgate when the logical product (VOE * VSR) of the activation signal VOE and the VSR signal is “1”.
In the normal drive mode, the horizontal direction drive unit 20 always activates Hgate as “H”, and in the partial drive mode, the logical product (HOE * HSR) of the activation signal HOE and the HSR signal is “1”. In some cases, Hgate is activated. The horizontal driving unit 20 performs switching between the normal driving mode and the partial driving mode by reading the HSET signal.

  FIG. 2 is an explanatory diagram relating to the configuration of the partial drive circuit and the pixel circuit according to the first embodiment of the present invention. The basic configuration is the same as in FIG. 1, but the sub-pixel portion is represented by three transistors T2R, T2G, and T2B. The transistor T2R has a configuration in which the display and non-display of the data R are switched by Npg connected to the gate. Similarly, the transistor T2G has a configuration in which the display and non-display of the data G are switched by Npg connected to the gate, and the transistor T2B is the display and non-display of the data B by Npg connected to the gate. Can be switched.

  In FIG. 2, the horizontal driving unit 20 and the HCLK signal are illustrated as being disposed at positions facing the video data driver 30, but are disposed at positions facing the vertical driving unit 10. It doesn't matter.

  FIG. 3 is a diagram showing a comparison of drive waveforms during normal driving and partial driving in the first embodiment of the present invention. FIG. 3A shows the case of normal driving, in which the gate of the transistor T1 is always “H” and is in a conductive state. That is, in this case, HCLK, HSR and the horizontal direction drive unit 20 are stopped, and all Hgate = “H”.

  The generation of the VST signal starts the operation of the VSR, but the Vgate signal is output when the VOE signal is “H”. Display data to the pixel is input from the data line by toggling Vgate from “H → L” in accordance with the VSR output timing (VCLK1, 2). Thus, the H system signal is in a stopped state and is driven only by the V system signal.

  On the other hand, FIG. 3B shows a partial drive time corresponding to an area display or a 90 degree rotation (R = “Low”) display, and the gate of the transistor T1 is in a control state by HSR and HOE. Shows the case. That is, in this case, HCLK, HSR, and the horizontal driving unit 20 start to operate, and a desired Hgate line is selected. When the Hgate line is selected, the state becomes Hgate = “High”, and as a result, the gate of the transistor T1 becomes “High” and becomes conductive.

  Generation of the Vgate signal is controlled by the VSR and VOE signals. The display data on the pixel is toggled from “H → L” according to the VSR output timing (VCLK1, 2) in the same manner as in the normal driving described with reference to FIG. And input from the data line.

  FIG. 4 is a timing chart when the area display mode is selected in the first embodiment of the present invention. More specifically, FIG. 4A shows a partial display of an area defined by Hgate = 301 to 800 in the horizontal direction and VGate = 1001 to 1500 in the vertical direction. A timing chart is shown in FIG.

When the area display mode is selected (or the same when 90-degree rotation is detected), the following processing is performed.
-The V system drive circuit is reset and the H system operation is started.
When the HCLK starts to operate and operates stably, although not shown, the HST signal is generated and the HSR starts operating.
When the HSR reaches the desired H Address (Hgate 300 in FIG. 4A), VSR * HOE = 1, and the Hgate line is activated accordingly.

The activation of Vgate is controlled by the XOE signal. When VOE = “H”, Xgate is output.
Display data to the pixel is input from the data line by toggling to Vgate “H → L” in accordance with the VSR output timing (VCLK1, 2), as in normal driving.

When the final Vgate selected by VOE is activated and the writing of video data is completed, the next Y-CLK toggles and the next writing starts.
The video data writing from the source driver IC to the data line is performed only for the pixels connected to the selected Hgate.

The effects of the present invention will be described with reference to FIGS.
(Effect 1) Effect by Partial Driving of Data Line when Display Device is Rotated 90 Degrees FIG. 5 shows gate line and data line activation regions when the display device according to Embodiment 1 of the present invention is rotated. Specifically, the following states are shown in FIGS. 5A to 5C.

Fig. 5 (a): Normal use (when not rotated 90 degrees)
When only the upper part of the display part is driven partially, only the upper part of the gate lines and all the data lines are driven.
FIG. 5 (b): 90 degree rotation according to the prior art Since it does not have a data line partial drive function, all gate lines and all data lines are driven despite the display only on the upper part of the display section. Useless power is consumed.
FIG. 5 (c): When rotating 90 degrees according to the present invention Since the data line has a partial drive function, all the gate lines are driven and the data lines of the display portion are partially driven, and when rotated 90 degrees. Even in this case, low power consumption can be realized.

(Effect 2) Effect by Partial Driving of Data Line when Performing Area Partial Display FIG. 6 shows an activation region of a gate line and a data line when performing area partial display in Embodiment 1 of the present invention. Specifically, FIG. 6A to FIG. 6D show the following states. The upper part shows a display area, and the lower part shows an activation area for data writing when the partial drive function of the present invention is used.
6A: When displaying battery status, time, etc. in the upper right of the screen FIG. 6B: When displaying moving images partially FIG. 6C: When inserting pictures partially d): When displaying the right edge of the screen

  In the case of the prior art, all gate lines + all data lines should be driven and refreshed. However, by using the partial drive function of the present invention, the activation region is narrowed, and power consumption can be reduced.

  As described above, according to the first embodiment, the partial drive of the data line can be performed while the conventional partial drive is performed only for the gate line. As a result, power consumption can be further reduced by performing partial driving of both the gate line and the data line in accordance with the display area, compared to partial driving of only the gate line. This is particularly effective when rotated 90 degrees from normal use and when an area is displayed.

Also, by having such a partial drive function, the following four drive modes can be realized with reduced power consumption.
(Mode 1) Normal drive (Mode 2) Partial drive of the gate line (Mode 3) Partial drive at 90 degrees rotation (Mode 4) Area display drive

  10 vertical direction drive unit, 20 horizontal direction drive unit, 30 video data driver, 100 display unit.

Claims (4)

A vertical control signal provided corresponding to each gate line and operating in synchronization with a vertical clock, and switching the gate line to be activated or not for each gate line; A vertical driving unit for outputting a V gate signal for activating the gate line according to a logical product with an output of the vertical shift register;
A horizontal control signal provided corresponding to each data line and having a horizontal shift register that operates in synchronization with a horizontal clock, and for switching whether or not to activate the data line for each data line; And a horizontal driving unit that outputs an H gate signal that activates the data line in accordance with a logical product with the output of the horizontal shift register, and a drive circuit for a display device that enables partial driving of each of the gate line and the data line. A drive circuit for a display device according to claim 1,
The horizontal driving unit is:
Reads the mode switching signal between the normal drive mode for driving the entire surface of the display device and the area display mode for partial display,
When the area display mode is selected, the H gate signal is output according to the logical product of the horizontal control signal and the output of the horizontal shift register,
When the normal drive mode is selected, the drive circuit for the display device outputs the H gate signal as “High” all the time. A pixel circuit driven by the drive circuit for a display device according to claim 1 or 2,
A plurality of sub-pixels constituting one pixel;
A transistor for displaying data on a data line by performing on / off control of the plurality of subpixels, and
The plurality of subpixels display data on the data line by turning on the gates connected in common to the output of the one transistor,
The one transistor outputs the V gate signal to the gate of the subpixel by turning on a gate connected to the H gate signal.
A pixel circuit that performs pixel display corresponding to partial driving by the V gate signal and the H gate signal.   A display device, wherein the sub-pixel according to claim 3 is composed of either liquid crystal or organic EL.

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