JP2015109010A5 - - Google Patents
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- JP2015109010A5 JP2015109010A5 JP2013252039A JP2013252039A JP2015109010A5 JP 2015109010 A5 JP2015109010 A5 JP 2015109010A5 JP 2013252039 A JP2013252039 A JP 2013252039A JP 2013252039 A JP2013252039 A JP 2013252039A JP 2015109010 A5 JP2015109010 A5 JP 2015109010A5
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- Japan
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Description
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2013252039A JP6381899B2 (ja) | 2013-12-05 | 2013-12-05 | 半導体装置の設計方法、設計支援プログラム、設計装置、及び、半導体装置 |
| US14/560,826 US20150161307A1 (en) | 2013-12-05 | 2014-12-04 | Method of Designing Semiconductor Device, Designing Assistance Program, Designing Apparatus, and Semiconductor Device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2013252039A JP6381899B2 (ja) | 2013-12-05 | 2013-12-05 | 半導体装置の設計方法、設計支援プログラム、設計装置、及び、半導体装置 |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2015109010A JP2015109010A (ja) | 2015-06-11 |
| JP2015109010A5 true JP2015109010A5 (ja) | 2017-01-05 |
| JP6381899B2 JP6381899B2 (ja) | 2018-08-29 |
Family
ID=53271430
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2013252039A Active JP6381899B2 (ja) | 2013-12-05 | 2013-12-05 | 半導体装置の設計方法、設計支援プログラム、設計装置、及び、半導体装置 |
Country Status (2)
| Country | Link |
|---|---|
| US (1) | US20150161307A1 (ja) |
| JP (1) | JP6381899B2 (ja) |
Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10783294B2 (en) | 2016-08-04 | 2020-09-22 | Tohoku University | System, method, and non-transitory computer readable recording medium storing a program recorded thereon for supporting a design of a circuit including a stochastic operation element |
| KR102661491B1 (ko) | 2016-12-26 | 2024-04-29 | 삼성전자주식회사 | 동적 전압 주파수 스케일링을 사용하는 시스템 온 칩 및 그것의 동작 방법 |
| US11409560B2 (en) * | 2019-03-28 | 2022-08-09 | Intel Corporation | System, apparatus and method for power license control of a processor |
| KR20210032213A (ko) | 2019-09-16 | 2021-03-24 | 삼성전자주식회사 | 전력 스텝에 기초한 동적 다이내믹 전압 주파주 스케일링(dvfs) 수행 방법 |
| CN113448718A (zh) * | 2020-03-26 | 2021-09-28 | 安徽寒武纪信息科技有限公司 | 用于对芯片进行调频的方法、设备及计算机可读存储介质 |
| WO2021190343A1 (zh) * | 2020-03-26 | 2021-09-30 | 安徽寒武纪信息科技有限公司 | 用于对芯片进行调频的方法、设备及计算机可读存储介质 |
| JP2022109141A (ja) * | 2021-01-14 | 2022-07-27 | 株式会社東芝 | 設計支援装置、設計支援システム、電気装置、設計支援方法、プログラム、及び記憶媒体 |
Family Cites Families (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6735744B2 (en) * | 2001-02-07 | 2004-05-11 | Nec Corporation | Power mode based macro-models for power estimation of electronic circuits |
| AU2002331774A1 (en) * | 2001-08-29 | 2003-03-18 | Analog Devices, Inc. | Methods and apparatus utilizing flash burst mode to improve processor performance |
| US7622979B2 (en) * | 2007-10-31 | 2009-11-24 | Sun Microsytems, Inc. | Dynamic voltage scaling for self-timed or racing paths |
| JP5524568B2 (ja) * | 2009-10-23 | 2014-06-18 | ルネサスエレクトロニクス株式会社 | 半導体装置、及び半導体装置の設計方法 |
| US8924902B2 (en) * | 2010-01-06 | 2014-12-30 | Qualcomm Incorporated | Methods and circuits for optimizing performance and power consumption in a design and circuit employing lower threshold voltage (LVT) devices |
| JP5510258B2 (ja) * | 2010-10-06 | 2014-06-04 | 富士通株式会社 | シミュレーション装置 |
| JP2013088892A (ja) * | 2011-10-14 | 2013-05-13 | Renesas Electronics Corp | 半導体装置および半導体装置の制御方法並びに半導体装置の設計支援方法 |
| US20150261898A1 (en) * | 2012-07-23 | 2015-09-17 | Arizona Board Of Regents, For And On Behalf Of, Arizona State University | Systems, methods, and media for energy usage simulators |
| US9825638B2 (en) * | 2014-03-05 | 2017-11-21 | Sandisk Technologies Llc | Virtual critical path (VCP) system and associated methods |
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2013
- 2013-12-05 JP JP2013252039A patent/JP6381899B2/ja active Active
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2014
- 2014-12-04 US US14/560,826 patent/US20150161307A1/en not_active Abandoned