WO2021190343A1 - 用于对芯片进行调频的方法、设备及计算机可读存储介质 - Google Patents

用于对芯片进行调频的方法、设备及计算机可读存储介质 Download PDF

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WO2021190343A1
WO2021190343A1 PCT/CN2021/080891 CN2021080891W WO2021190343A1 WO 2021190343 A1 WO2021190343 A1 WO 2021190343A1 CN 2021080891 W CN2021080891 W CN 2021080891W WO 2021190343 A1 WO2021190343 A1 WO 2021190343A1
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power consumption
chip
value
real
pid control
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PCT/CN2021/080891
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English (en)
French (fr)
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顾敬梓
项浩哲
翟柏松
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安徽寒武纪信息科技有限公司
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Priority claimed from CN202010225223.3A external-priority patent/CN113448379A/zh
Priority claimed from CN202010225213.XA external-priority patent/CN113448718B/zh
Application filed by 安徽寒武纪信息科技有限公司 filed Critical 安徽寒武纪信息科技有限公司
Publication of WO2021190343A1 publication Critical patent/WO2021190343A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power

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  • This application relates to the field of chip control.
  • it relates to a method, a device and a computer-readable storage medium for frequency modulation of a chip.
  • the present disclosure discloses a method for frequency modulation of a chip.
  • the method includes obtaining at least one real-time power consumption sampling value during operation of the chip; according to the real-time power consumption sampling value and the power consumption target value, Determine an error value between the two; and based on the error value, use a PID control module to determine an adjustment amount for adjusting the clock frequency of the at least one chip.
  • the present disclosure also discloses a method for frequency modulation of a chip.
  • the method includes obtaining at least one real-time power consumption sampling value during operation of the chip; and determining whether the real-time power consumption sampling value is greater than or equal to Fast frequency reduction threshold; when the real-time power consumption sampling value is greater than or equal to the fast frequency reduction threshold, perform a fast frequency reduction operation on the at least one chip; when the real-time power consumption sampling value is less than the fast frequency reduction Frequency threshold, it is executed to determine the error value between the real-time power consumption sampling value and the power consumption target value; and based on the error value, the PID control module is used to determine the value used to adjust the at least one chip The amount of clock frequency adjustment.
  • the present disclosure further discloses a device for frequency modulation of a chip.
  • the device includes: an acquisition module configured to acquire at least one real-time power consumption sampling value during operation of the chip; and a PID control module, It is configured to determine an error value between the real-time power consumption sample value and the power consumption target value; and based on the error value, determine an adjustment amount for adjusting the clock frequency of the at least one chip.
  • the present disclosure discloses a device for frequency modulation of a chip.
  • the device includes: an acquisition module configured to acquire at least one real-time power consumption sampling value during operation of the chip; and a determination module configured to To determine whether the real-time power consumption sampling value is greater than or equal to the fast frequency reduction threshold; a fast frequency reduction module is configured to perform the A fast frequency reduction operation of at least one chip; and a PID control module configured to execute when the real-time power consumption sampling value is less than the fast frequency reduction threshold: according to the real-time power consumption sampling value and the power consumption target value , Determining an error value between the two; and determining an adjustment amount for adjusting the clock frequency of the at least one chip based on the error value.
  • the present disclosure also discloses a device for frequency modulation of a chip.
  • the device includes: at least one processor; at least one memory for storing program instructions. When the processor is executed, the device is caused to execute the aforementioned method for frequency modulation of the chip.
  • the present disclosure discloses a board for frequency modulation of a chip, and the board includes any of the aforementioned devices for frequency modulation of a chip.
  • the present disclosure discloses an integrated circuit chip that includes a core for frequency modulation of the chip, and when the integrated circuit chip is working, the core can be configured to perform the aforementioned method for frequency modulation of the chip .
  • the improved PID control technology can be used to perform frequency modulation control on related chips.
  • the solution of performing frequency modulation control on related chips through an external MCU ("Microcontroller Unit") in the present disclosure can be directly applied to a chip with a frequency modification interface, thereby realizing dynamic frequency modulation.
  • the local data can be directly managed and applied locally after being collected, so that the frequency modulation speed is faster.
  • the technical solution of the present disclosure can also be flexibly adjusted, such as adjusting the proportional coefficient, adjusting the timing clearing time, and removing the integral term, to adapt to different application requirements.
  • the present disclosure discloses a method for frequency modulation of a chip.
  • the method includes obtaining at least one real-time power consumption sample value during chip operation and an average power consumption value in N-1 predetermined execution cycles, Where N is a positive integer greater than or equal to 2; and based on the real-time power consumption sampling value, the average power consumption value, and the average power consumption reference value, N PID control modules connected in series are used to determine the The amount of adjustment of the clock frequency of at least one chip.
  • the present disclosure also discloses a method for frequency modulation of a chip.
  • the method includes obtaining at least one real-time power consumption sampling value during operation of the chip; and determining whether the real-time power consumption sampling value is greater than or equal to Fast frequency reduction threshold; when the real-time power consumption sampling value is greater than or equal to the fast frequency reduction threshold, perform a fast frequency reduction operation on the at least one chip; when the real-time power consumption sampling value is less than the fast frequency reduction Frequency threshold, perform the following operations: obtain the average power consumption value in N-1 predetermined execution cycles, where N is a positive integer greater than or equal to 2; and based on the real-time power consumption sampling value and the average power consumption value And the average power consumption reference value, and the N PID control modules connected in series are used to determine the adjustment amount used to adjust the clock frequency of the at least one chip.
  • the present disclosure further discloses a device for frequency modulation of a chip.
  • the device includes: an acquisition module configured to acquire at least one real-time power consumption sample value during chip operation and N-1 The average power consumption value within a predetermined execution period, where N is a positive integer greater than or equal to 2; and N PID control modules connected in series in stages, configured to be based on the real-time power consumption sampling value and the average power consumption The value and the average power consumption reference value determine the adjustment amount used to adjust the clock frequency of the at least one chip.
  • the present disclosure discloses a device for frequency modulation of a chip.
  • the device includes: an acquisition module configured to acquire at least one real-time power consumption sampling value during operation of the chip; and a determination module configured to To determine whether the real-time power consumption sampling value is greater than or equal to the fast frequency reduction threshold; a fast frequency reduction module is configured to perform the Fast frequency reduction operation of at least one chip; N PID control modules connected in series in stages, configured to perform the following operations when the real-time power consumption sampling value is less than the fast frequency reduction threshold: Obtain N-1 predetermined The average power consumption value in the execution period, where N is a positive integer greater than or equal to 2; and based on the real-time power consumption sampling value, the average power consumption value, and the average power consumption reference value, it is determined to adjust the at least The amount of adjustment of the clock frequency of a chip.
  • the present disclosure also discloses a device for frequency modulation of a chip.
  • the device includes: at least one processor; at least one memory for storing program instructions. When the processor is executed, the device is caused to execute the aforementioned method for controlling the processor.
  • the present disclosure discloses a board for frequency modulation of a chip, and the board includes any of the aforementioned devices.
  • the present disclosure discloses an integrated circuit chip that includes a core for frequency modulation of the chip.
  • the core can be configured to perform any one of the aforementioned control processes. Method.
  • the present disclosure discloses a computer-readable storage medium that stores program instructions for frequency modulation of a chip, and when the program instructions are run by a processor, the method described in any one of the foregoing is executed.
  • the improved PID control technology can be used to perform frequency modulation control on related chips.
  • the solution of performing frequency modulation control on related chips through an external MCU ("Microcontroller Unit") in the present disclosure can be directly applied to a chip with a frequency modification interface, thereby realizing dynamic frequency modulation.
  • the local data can be directly managed and applied locally after being collected, so that the frequency modulation speed is faster.
  • the technical solution of the present disclosure can also be flexibly adjusted, such as adjusting the proportional coefficient, adjusting the timing clearing time, and removing the integral term, to adapt to different application requirements. [14]202010225213.X
  • FIG. 1 is a block diagram showing the operation flow of an example system for frequency modulation of a chip according to an embodiment of the present disclosure.
  • Fig. 2 is an overall flowchart showing a method for frequency modulation of a chip according to an embodiment of the present disclosure.
  • Fig. 3 is a detailed flowchart showing a method for frequency modulation of a chip according to an embodiment of the present disclosure.
  • Fig. 4 is a flowchart showing a frequency modulation method for fast frequency reduction according to an embodiment of the present disclosure.
  • Fig. 5 is an overall flowchart showing a multi-stage dynamic frequency modulation method according to an embodiment of the present disclosure.
  • Fig. 6 is a flowchart showing a two-stage dynamic frequency modulation method according to an embodiment of the present disclosure.
  • Fig. 7 is a flow chart showing a three-level dynamic frequency modulation method according to an embodiment of the present disclosure.
  • Fig. 8 is a flow chart showing a multi-stage dynamic frequency modulation method according to an embodiment of the present disclosure.
  • Fig. 9 is a flowchart illustrating a frequency modulation method with multiple stages and fast frequency reduction according to an embodiment of the present disclosure.
  • Fig. 10 is a schematic block diagram showing frequency modulation of a chip by using the device of an embodiment of the present disclosure.
  • FIG. 11 is another schematic block diagram showing frequency modulation of a chip by using the device of an embodiment of the present disclosure.
  • Fig. 12 is a block diagram showing a structure of a combined processing device according to an embodiment of the present disclosure.
  • Fig. 13 is a block diagram showing the structure of a board for frequency modulation of a chip according to an embodiment of the disclosure.
  • the technical solution of the present disclosure provides a method, device and computer-readable storage medium for frequency modulation of a chip. Collect data such as the power consumption of the chip in real time, and use the PID control module to incrementally adjust the working frequency of the chip, thereby controlling the overall working performance of the system.
  • the solution of the present disclosure uses a single or single-stage PID control module to incrementally adjust the operating frequency of a single or multiple chips.
  • the solution of the present disclosure uses a PID control module connected in multiple stages to adjust the frequency of the chip more finely. Using the technical solution of the present disclosure, the incremental adjustment of the operating frequency of one or more chips in the combined processing device can be realized.
  • the frequency modulation scheme of the present disclosure is stable and reliable.
  • the average power consumption of the actual board can be controlled within ⁇ 1W of the target power consumption.
  • FIG. 1 is a block diagram showing an operation flow 100 of an example system for frequency modulation of a chip according to an embodiment of the present disclosure. It should be noted that the system and its operating procedures here are only exemplary and not restrictive. In addition to the frequency modulation operation, the system can also perform other operations, and these operations will not be described in detail here in order to unnecessarily confuse the solution of the present disclosure.
  • the system operation process of the present disclosure includes performing an initialization operation on the system at step 101.
  • the initialization operation you can set the corresponding parameters for the system according to the actual application situation, and you can also load the initial data to prepare for the execution of the subsequent program.
  • the frequency modulation system of the present disclosure can execute the main loop operation and the dynamic frequency modulation operation in parallel or serially, respectively.
  • the main loop operation may be various operations or tasks that the system needs to perform in addition to the dynamic frequency modulation operation, such as machine learning related operations in the field of artificial intelligence.
  • the PID control module can be used to adjust the operating frequency of the chip.
  • the MCU including the PID control module of the present disclosure can obtain real-time power consumption samples during at least one chip operation at a fixed time interval (for example, 1 millisecond) Value, and by combining the target value of power consumption to determine the amount of adjustment used to adjust the clock frequency of the chip. Thereafter, the adjustment amount can be used to implement a frequency modulation action on the clock frequency of one or more chips in accordance with the relevant situation in step 104, thereby further controlling the power consumption of the entire device or system.
  • the relevant situation here can be, for example, that the operating frequency of the chip is too high or too low, or other scenarios that require dynamic frequency modulation.
  • FIG. 2 is an overall flowchart showing a method 200 for frequency modulation of a chip according to an embodiment of the present disclosure. It is understandable that the frequency modulation method discussed here can be implemented in conjunction with the operation flow of the system in FIG. 1.
  • the method 200 may obtain real-time power consumption sampling values during at least one chip operation.
  • the method 200 determines the error between the real-time power consumption sampling value (for example, the chip power consumption taken within 1 millisecond) and the power consumption target value (for example, the expected power consumption value of the chip). value.
  • the error value between the aforementioned real-time power consumption sample value and the power consumption target value can be obtained by calculating the difference between the two.
  • the method 200 uses the PID control module to determine an adjustment amount for adjusting the clock frequency of at least one chip based on the error value.
  • the adjustment amount here may be a relative increment based on the previous adjustment frequency. Therefore, by adding the adjustment amount to the current clock frequency of the chip, the clock frequency of the chip adjusted for this operation can be obtained.
  • PID control algorithm is a control algorithm that combines proportional (P), integral (I) and derivative (D). The essence of its control is to perform calculations in accordance with the functional relationship of proportional, integral, and derivative according to the input deviation value, and The result of the operation is used to control the output.
  • the PID control algorithm of the present disclosure improves the existing PID control algorithm.
  • the output value is an adjustment value, and can be an increase relative to the previous adjustment value, which is different from the existing PID control algorithm.
  • the output value is an absolute value. Numerical situation.
  • the PID control algorithm of the present disclosure can use the following formula (1) to obtain the adjustment ⁇ u(t):
  • k p is the proportional coefficient
  • k i is the integral coefficient
  • k d is the differential coefficient
  • e(t) is the error value
  • ⁇ e(t) is the cumulative sum of the error value
  • e(t-1) is the previous error value
  • k p *e(t) is a proportional term
  • k i * ⁇ e(t) is an integral term
  • k d *(e(t)-e(t-1)) is a differential term.
  • the solution of the present disclosure can either obtain the adjustment amount through a proportional term, or obtain the adjustment amount by combining a proportional term with any one of an integral term and a derivative term. Furthermore, the aforementioned three can be used in combination to obtain the adjustment amount, and then the frequency modulation scheme for the chip can be implemented. In addition, by improving on the basis of continuous actual measurement, the PID control algorithm of the present disclosure extends the traditional PID algorithm that is only applicable to linear systems to nonlinear systems, and the actual measurement results are good.
  • the PID control module of the present disclosure may have a proportional control unit for determining a proportional term in terms of implementation.
  • it may further include at least one of an integral control unit for determining an integral term and a differential control unit for determining a derivative term.
  • the adjustment amount is determined by a proportional term or a combination of a proportional term and at least one of an integral term and a differential term.
  • the present disclosure provides a variety of flexible ways to perform frequency modulation operations on the chip.
  • FIG. 3 is a detailed flowchart showing a method 300 for frequency modulation of a chip according to an embodiment of the present disclosure.
  • FIG. 3 is a further refinement of the method for frequency modulation of the chip shown in FIG. 2, and the description about FIG. 2 is also applicable to the content shown in FIG. 3.
  • the method 300 obtains real-time power consumption sampling values.
  • acquiring the real-time power consumption sample value includes periodically (for example, 1 millisecond) acquiring a plurality of the real-time power consumption sample value.
  • the method 300 proceeds to step 302 to calculate the error value between the current real-time power consumption and the target power consumption.
  • determining the error value between each of the real-time power consumption sampled value and the power consumption target value can be based on the real-time power consumption sampled value and the power consumption target value (for example, a user-defined chip or board The expected power consumption) to find the difference, and regard the difference as the error value.
  • the method 300 proceeds to step 303, where a proportional term can be obtained according to the error value.
  • the proportional control unit in the PID control module may be used to obtain the proportional term based on the error value.
  • obtaining the proportional term may include obtaining according to the error value, the selected proportional coefficient (for example, a parameter adjusted according to the actual measurement result), and the dimension (for example, Hertz/Watt).
  • the first adjustment amount for adjusting the clock frequency may be determined based on the proportional term.
  • the method 300 may directly proceed to step 310 to perform a frequency modulation operation. Specifically, the frequency modulation action may be performed on the clock frequency of one or more chips according to the obtained first adjustment value in combination with the previous adjustment of the clock frequency.
  • the method 300 determines whether a predetermined time period (for example, a time period of 1 second) is reached, which can be implemented by the timer shown in FIG. 1, for example.
  • a predetermined time period for example, a time period of 1 second
  • the method 300 executes step 305, which is to perform a zeroing operation on the accumulation and zeroing, so as to restart the accumulation operation of the error value in the next predetermined time period.
  • the zeroing operation of the cumulative sum can clear the cumulative effect that may be caused by power consumption adjustment.
  • the target power consumption value (the expected power consumption value set by the user) is 75 watts, and the chip has been in no load for a predetermined period of time.
  • the real-time power consumption sampling value obtained in the period of time is always 30 watts. In this case, when the accumulation operation is performed, the accumulated sum of the error value within the predetermined period of time will be relatively large.
  • the solution of the present disclosure therefore proposes to accumulate the error value and perform a zero-clearing operation within a predetermined period of time to avoid accumulation effects.
  • the method 300 can determine whether the predetermined time period is reached in another way.
  • the time period for obtaining one real-time power consumption sampling value may be referred to as a sampling period, and thus the predetermined time period may be set to include a certain number of sampling periods.
  • the error value obtained in the earliest sampling period can be removed from the accumulation sum, and the error value obtained in the most recent sampling period can be included in the accumulation sum.
  • the method 300 can clear the error value of the earliest sampling period (that is, the first sampling period) among the predetermined number of sampling periods in the accumulated sum, so that the most recent sampling period ( That is, the error value of the 101st sampling period) is accumulated to obtain the accumulated sum. That is, the updated accumulation and accumulation calculation is the error value from the second sampling period to the 101st sampling period. It can be seen that by setting the predetermined time period differently, the present disclosure provides multiple solutions on how to determine the cumulative sum, thereby further enhancing the application flexibility of the present disclosure.
  • the method 300 executes step 306, that is, the current error value is added to the cumulative sum.
  • the method 300 obtains the integral term according to the cumulative sum.
  • obtaining the integral term may include obtaining the integral term according to the cumulative sum, the selected integral coefficient and the dimension (for example, Hertz/Watt).
  • the range of the integral term is limited.
  • the integral term can be limited within the selected range in order to eliminate the effect of static error and avoid the effect of overshoot.
  • the range may be, for example, an empirical statistical value or an adjustment amount determined after multiple actual measurements.
  • step 309 where the frequency adjustment parameter, such as the adjustment amount referred to in the present disclosure, can be obtained according to the proportional term and the integral term after the limit range.
  • step 310 where the method 300 performs a frequency modulation action on the clock frequency of at least one chip according to the obtained adjustment value.
  • the frequency adjustment parameter may be selected in combination with the derivative term according to actual application scenarios.
  • the method 300 performs a subtraction operation based on the error value determined this time and the error value determined last time to obtain the differential difference.
  • the derivative control unit in the PID control module is used to obtain a derivative term.
  • obtaining the differential term may include obtaining the differential term according to the differential difference, the selected differential coefficient, and the dimension (for example, Hertz/Watt).
  • the method 300 may perform a frequency modulation action on the clock frequency of the chip according to the adjustment amount obtained through at least one of the proportional term and the integral term and the derivative term.
  • the differential term When the differential term is used in the process of determining the adjustment value, it can play a certain role in the advance adjustment of the frequency modulation, and can also make the frequency modulation response faster.
  • a plurality of real-time power consumption sample values are acquired periodically (for example, 1 millisecond), and in a predetermined time period (for example, 1 millisecond). Sec) for each real-time power consumption sample value, determine the error value between each real-time power consumption sample value and the power consumption target value, and perform an accumulation operation on each determined error value To get the cumulative sum. Further, based on the cumulative sum, the integral control unit in the PID control module is used to obtain the integral term. Then, a second adjustment amount (relative to the aforementioned first adjustment amount) for adjusting the clock frequency of the at least one chip may be determined based on the obtained proportional term and the integral term obtained by the integral control unit.
  • the present disclosure may also determine the amount used for adjusting the proportional term based on the obtained proportional term and the derivative term obtained by the differential control unit.
  • the fourth adjustment amount for adjusting the clock frequency of the at least one chip may also be determined based on the proportional term, the integral term, and the derivative term obtained above.
  • each of the second adjustment amount, the third adjustment amount, and the fourth adjustment amount is an increment relative to the previous adjustment of the clock frequency.
  • those skilled in the art can make real-time adjustments according to the actual frequency modulation effect monitored, so as to realize the real-time frequency modulation operation of the chip.
  • FIG. 4 is a flowchart illustrating a frequency modulation method 400 for fast frequency reduction according to an embodiment of the present disclosure.
  • the method 400 obtains a real-time power consumption sample value during at least one chip operation.
  • the real-time power consumption sampling value of at least one chip may be collected periodically (for example, 1 millisecond).
  • the fast frequency reduction threshold can be determined according to product specifications, and its calculation formula can be, for example, the following formula:
  • U represents the operating voltage
  • I max represents the maximum allowable current
  • P th represents the fast frequency reduction threshold
  • * represents the product relationship.
  • the rapid frequency reduction threshold may also be adjusted within a certain range based on the calculation result of the foregoing formula and the actual measurement result, and the adjustment range may be determined, for example, based on an empirical value.
  • the method 400 proceeds to step 403, at which time the method 400 performs a fast frequency reduction operation on at least one chip.
  • the target frequency value adjusted this time by the chip may be determined.
  • the target frequency value can be determined by the following formula:
  • F aim is the target frequency
  • F now is the current frequency
  • P aim is the target power consumption
  • P idle is the idle power consumption
  • P now is the current power consumption
  • * represents the product relationship.
  • the method 400 performs a normal frequency modulation operation at step 404.
  • the method 400 may determine the error value between the real-time power consumption sampling value and the power consumption target value.
  • the method 400 may use a PID control module to determine an adjustment amount for adjusting the clock frequency of the at least one chip based on the aforementioned error value.
  • a normal frequency modulation operation can be performed on the clock frequency of one or more chips according to the obtained adjustment amount in combination with the previous adjustment of the clock frequency.
  • the normal frequency modulation operation here may be the frequency modulation operation previously performed in conjunction with FIG. 3, so the operation of performing frequency modulation on the chip described in conjunction with FIG. 3 is also applicable to the normal frequency modulation operation here. , So the same or similar content will not be repeated here.
  • the present disclosure describes the frequency modulation operation of performing a single-stage PID (for example, the second stage shown in FIG. 6, which will be described in detail later) on the chip in conjunction with FIGS.
  • a single-stage PID for example, the second stage shown in FIG. 6, which will be described in detail later
  • FIGS The multi-stage PID frequency modulation operation of this disclosure is further explained.
  • FIG. 5 is an overall flowchart showing a multi-stage dynamic frequency modulation method 500 according to an embodiment of the present disclosure.
  • method 500 to perform multi-level serial PID dynamic frequency modulation on the chip, the frequency adjustment can be made more precise, and to a certain extent, the power consumption in a short period of time is allowed to exceed the TDP ("Thermal Design Power") power consumption. Thereby improving system performance.
  • TDP Thermal Design Power
  • the method 500 obtains at least one real-time power consumption sample value during chip operation and the average power consumption value in N-1 predetermined execution cycles, where N is a positive integer greater than or equal to 2.
  • N is a positive integer greater than or equal to 2.
  • the N-1 predetermined execution periods T 1 , ... T N-1 and the sampling period T N of the real-time power consumption sample value satisfy the relationship T 1 (for example, 1 second)>T 2 (for example, 500 milliseconds) ...T N-1 (for example, 50 milliseconds)>T N (for example, 1 millisecond).
  • the method 500 uses N PID control modules connected in series to determine the value for adjusting the at least one power consumption based on the real-time power consumption sampling value, the average power consumption value, and the average power consumption reference value.
  • the average power consumption reference value of the present disclosure can be flexibly set according to actual conditions. For example, it can be set through the "Power Capping" function of the host computer, which allows the user to limit the average power consumption reference value within its specified range. Furthermore, after modifying the average power consumption reference value, the user does not need to adjust other parameters. All parameters related to the previous average power consumption reference value will be automatically performed according to the new average power consumption reference value given by the user. Adjustment.
  • FIG. 6 is a flowchart of a two-stage dynamic frequency modulation method 600 according to an embodiment of the present disclosure.
  • the method 600 is the situation when N is equal to 2 in the N-level dynamic frequency modulation method described in FIG.
  • the adjustment value is output from the final stage PID control module.
  • the method 600 can respectively obtain the first average power consumption value 601 and the average power consumption associated with the primary PID control module of the primary PID control module of at least one chip within the predetermined execution period T 1 (for example, 1 second). Reference value 602. Next, the method 600 may input the first average power consumption value and the average power consumption reference value into the primary PID control module 603. Further, the method 600 may input the output value of the primary PID control module 603, that is, the current adjustment amount and the real-time power consumption target value of the previous adjustment operation into a processing module for calculation, and the output of the processing module is the original value. The real-time power consumption target value 604 for this adjustment operation. Thereafter, the method 600 can input it to the final PID control module 606.
  • the final stage PID control module 606 is used to output the adjustment amount.
  • the workflow of inputting real-time power consumption target value and real-time power consumption sampling value to the final PID control module is the same as or similar to the method for single-stage frequency modulation of the chip described above in conjunction with FIG. 3, and will not be repeated here.
  • the method 600 can obtain the clock frequency of the current adjustment operation of the chip based on the output value of the final PID control module 606 and the clock frequency of the previous adjustment operation of the chip, and perform corresponding frequency adjustment actions according to the clock frequency.
  • the adjustment amount may be an increment relative to the previous adjustment of the clock frequency.
  • the predetermined execution period T 1 (for example, 1 second) of the primary PID control module is greater than the sampling period T N (for example, 1 millisecond) of the real-time power consumption sampling value.
  • FIG. 7 is a flowchart of a three-level dynamic frequency modulation method 700 according to an embodiment of the present disclosure.
  • the solution of the present disclosure is further described in detail. Therefore, the description of the multi-level dynamic frequency modulation made in FIGS. 5 to 6 is also applicable to the operation of FIG. 7.
  • Figure 7 here is the situation when N is equal to 3 in the N-level dynamic frequency modulation method, that is, the primary PID control module, the secondary PID control module and the final PID control module in series are used to determine the adjustment And output the adjusted value from the last-stage PID control module.
  • the method 700 respectively obtains the first average power consumption value 701 and the average power consumption reference value associated with the primary PID control module in the predetermined execution period T 1 (for example, 1 second) of the primary PID control module of the at least one chip. 702. Input to the primary PID control module 703, so that it outputs an adjustment value of the second average power consumption target value associated with the secondary PID control module 706.
  • the method 700 obtains the second average power consumption value 705 in the predetermined execution period T 2 of the second-level PID control module, and inputs it to the second-level PID control module 706. Further, the second average power consumption target value is adjusted by using the adjustment value to obtain the adjusted second average power consumption target value 704, which is input to the second-stage PID control module 706.
  • the real-time power consumption target value 707 of this adjustment operation is obtained based on the output value of the second-stage PID control module 706 and the real-time power consumption target value of the previous adjustment operation, and it is input to the last-stage PID control module 709 . Then, based on the real-time power consumption sample value 708 and the real-time power consumption target value 707 of this adjustment operation, the final stage PID control module 709 is used to output the adjustment amount.
  • the sampling period of the real-time power consumption sampling value is T N
  • the predetermined execution period T 2 of the second-level PID control module satisfies the relationship T 1 (for example, 1 second)>T 2 (for example, 200 milliseconds) >T N (for example, 1 millisecond).
  • the average power consumption reference value as the input value of the primary PID control module is TDP power consumption (for example, 75 watts)
  • the input value of the next-level PID control module can be increased to reduce the average power consumption target value to suppress power consumption;
  • the average power consumption target value of the next-stage PID control module can be reduced to increase the suppression of power consumption.
  • the method 700 can obtain the output value of the last-stage PID control module 709 and the clock frequency of the previous adjustment operation of the chip.
  • the chip adjusts the clock frequency of the operation this time, and executes the corresponding frequency modulation action according to the clock frequency.
  • FIG. 8 is a flowchart of a multi-stage dynamic frequency modulation method 800 according to an embodiment of the present disclosure.
  • the solution of the present disclosure is further described in detail. Therefore, the description of the multi-level dynamic frequency modulation in FIG. 5 to FIG. 7 is also applicable to the operation of FIG. 8.
  • FIG 8 it shows the situation when N is greater than or equal to 4 in the N-level dynamic frequency modulation method, that is, the primary PID control module, the second-level PID control module,..., the N-1th-level PID control module are used in series And the final stage PID control module to determine the adjustment amount, and output the adjustment amount from the final stage PID control module.
  • the method 800 obtains the first average power consumption value 801 and the second average power consumption value 801 and the second average power consumption of the primary PID control module 803 to the N-1th stage PID control module 809 in their respective predetermined execution periods T 1 ,...T N-1
  • the value 805 to the N-1th average power consumption value 808 is input into the primary PID control module 803, the second stage PID control module 806, ... to the N-1th stage PID control module 809, respectively.
  • the respective predetermined execution periods T 1 from the primary PID control module to the N-1th PID control module, ... T N-1 and the sampling period T N of the real-time power consumption sample value satisfy the relationship T 1 (for example 1 second)>T 2 (e.g.
  • the first average power consumption value 801 and the average power consumption reference value 802 associated with the primary PID control module are input to the primary PID control module 803, and the output from the primary PID control module to the N-2th stage PID control module is directed to Input from the respective next-stage PID control module, where each output from the primary PID control module to the N-2th stage PID control module is an adjustment value to the average power consumption target value associated with the corresponding subsequent-stage PID control module .
  • use each adjustment value to adjust the average power consumption target value of the corresponding subsequent stage to obtain the adjusted second average power consumption target value 804, ... and the N-1th average power consumption target value 807, respectively, and They are respectively input to the corresponding second-stage PID control module 806, ... to the N-1th-stage PID control module 809.
  • the real-time power consumption target value 810 of this adjustment operation is obtained based on the output value of the N-1th stage PID control module 809 and the real-time power consumption target value of the previous adjustment operation, and it is input to the final stage PID control Module 812. And, based on the real-time power consumption sample value 811 and the real-time power consumption target value 810 of this adjustment operation, the final stage PID control module 812 is used to output the adjustment amount.
  • the work flow of inputting the real-time power consumption sampling value and real-time power consumption target value to the final PID control module is the same or similar to the single-stage frequency modulation method of the chip described above in conjunction with FIG. 3, and will not be repeated here.
  • the method 800 can obtain the clock frequency of the current adjustment operation of the chip based on the output value of the final PID control module 812 and the clock frequency of the previous adjustment operation of the chip, and perform corresponding frequency adjustment actions according to the clock frequency.
  • the foregoing description of this disclosure combines at least one chip to describe the acquisition power consumption and its frequency modulation scheme.
  • the solution of the present disclosure is also suitable for collecting the power consumption of a board including one or more chips.
  • the object of the present disclosure to collect power consumption can be either a chip or a board including a chip.
  • the method of frequency modulation will be further described with reference to Figure 9 taking the entire board power consumption of the acquisition board as an example.
  • FIG. 9 is a flowchart illustrating a frequency modulation method 900 with multiple stages and fast frequency reduction according to an embodiment of the present disclosure.
  • FIG. 9 is a frequency modulation method after the combination of fast frequency reduction and multi-stage PID frequency modulation shown in FIGS. 4 to 8. Therefore, the technical details described in FIG. 4 to FIG. 8 are also applicable to FIG. 9.
  • step 901 waiting for the end of the last frequency modulation action, that is, during the process of using the output of the last stage PID to perform frequency modulation on the chip. Since the frequency modulation action takes a certain time from the beginning to the completion of the execution, after the frequency modulation starts, to the time period of waiting for the completion of the frequency modulation, the solution of the present disclosure also allows other tasks to be executed in parallel (for example, the main loop 102 shown in FIG. 1 executes Task), which can improve the efficiency of dynamic frequency modulation. Until the previous frequency modulation action is completed, the method 900 proceeds to step 902, where the power consumption of the entire board can be obtained, and the entire board may be a board including one or more chips to be tuned.
  • the power consumption of the entire board can be collected in real time through the sensors on the board to obtain real-time power consumption sampling values during the operation of the entire board, or the power consumption of the chip can be collected in real time through the sensors on the board. Acquire real-time power consumption sampling values during at least one chip operation, and then acquire real-time power consumption sampling values of the entire board.
  • the method 900 determines whether the real-time power consumption sample value of the entire board is greater than or equal to the fast frequency reduction threshold of the entire board.
  • the fast frequency reduction threshold may be calculated according to the aforementioned formula (2).
  • the threshold value can also be adjusted in a certain range based on the calculated value of the aforementioned formula (2) according to the actual measurement result, and the adjustment range can be determined according to an empirical value.
  • the method 900 proceeds to step 904, where the average power consumption value within a predetermined time period (for example, 1 second) is calculated.
  • the method 900 performs a multi-level dynamic frequency modulation operation, that is, the multi-level PID frequency modulation operation described above in conjunction with FIGS. 6-8.
  • the method 900 obtains the frequency modulation parameter (that is, the clock frequency) adjusted for the current operation of the chip according to the determined adjustment amount and the clock frequency of the previous adjustment operation of the chip.
  • the method 900 calculates the target frequency value of the entire board rapid frequency reduction at step 908.
  • This situation can occur, for example, when the instantaneous power consumption of the entire board is detected to be large (for example, more than 1.2 times TDP), in order to reduce the chip frequency in a short time to meet the power consumption of the board, a fast frequency reduction is performed at this time operate. Before performing the fast frequency reduction operation, it is necessary to determine the target frequency value of the chip to be adjusted. In one or more embodiments, the target frequency value can be calculated according to the aforementioned formula (3).
  • the method 900 performs a corresponding frequency adjustment operation according to the clock frequency.
  • the method for chip frequency adjustment shown in Figures 1 to 9 can also be implemented in one or more devices in various forms. . These implementation forms can include but are not limited to the following four forms: 1) The chip hardware itself has or supports a certain dynamic frequency modulation capability, and the PID module of the disclosure is constructed through hardware analog circuits and/or digital circuits to achieve frequency modulation.
  • FIG. 10 shows a schematic block diagram of frequency modulation of a chip using the device of an embodiment of the disclosure
  • FIG. 11 shows another schematic block diagram of frequency modulation of a chip using the device of an embodiment of the disclosure. It can be seen from the two figures that the device of the present disclosure can be placed outside or inside the chip for frequency modulation operation on at least one chip.
  • the device 1001 performs a frequency modulation operation on the chip outside the chip 1004.
  • the device 1001 includes an obtaining module 1003, which is configured to obtain a real-time power consumption sample value during at least one chip operation and an average power consumption value in N-1 predetermined execution cycles, where N is a positive integer greater than or equal to 2.
  • the acquisition module may be a sensor.
  • the device 1001 may further include a PID control module 1002, for example, it may be a single-stage or N-stage PID control module connected in series to perform a dynamic frequency modulation operation on the chip 1004.
  • the PID control module 1002 may be implemented on an MCU ("Microcontroller Unit").
  • the device 1001 may be an MCU.
  • the chip that accepts dynamic frequency modulation can be configured to have an interface for modifying the frequency, and the aforementioned external equipment can realize dynamic frequency modulation of the chip only by modifying or upgrading its firmware.
  • the operation is convenient and flexible.
  • the local data is collected and managed directly locally (for example, at the board), so the data processing speed is faster than the processing by the upper driver or the operating system kernel.
  • the device for frequency modulation of the present disclosure can also be placed inside the chip to implement the frequency modulation operation of the chip, that is, the chip 1102 contains the device 1101 inside, which is used to perform the frequency modulation operation on the chip.
  • the device 1101 may be embodied as software code (for example, instructions in various situations) residing inside the chip.
  • the description of the single-stage, multi-stage and fast frequency reduction of the chip in Figs. 2-9 is also applicable to the device of Fig. 11, it will not be repeated here.
  • the solution of the present disclosure may also be implemented in an integrated circuit chip, which includes a device 1101 for frequency modulation of the chip.
  • the aforementioned device 1101 may be the core of the chip.
  • the core may be configured to execute the above-mentioned method for frequency modulation of the chip.
  • the integrated circuit chip can, for example, adopt CPLD ("Complex Programmable Logic Device"), FPGA ("Field Programmable Gate Array”), and ASIC (Application Specific Integrated Circuit) for integration for special applications. Circuit), MPU (Microprocessor Unit), CPU (Central Processing Unit) and other hardware.
  • the device includes at least one processor; at least one memory is used to store program instructions, and when the program instructions are executed by the at least one processor, the device executes the above-mentioned method for frequency modulation of a chip .
  • the board includes the above-mentioned device for frequency modulation of the chip.
  • the present disclosure when the frequency modulation operation of the present disclosure is implemented by program instructions, the present disclosure also discloses a computer-readable storage medium, which stores program instructions for frequency modulation of the chip, when the program instructions When run by the processor, the above-mentioned frequency modulation operation is performed.
  • FIG. 12 is a structural block diagram of a combined processing device 1200 according to an embodiment of the present disclosure.
  • the combined processing device 1200 includes a frequency modulation device 1201 having the aforementioned architecture, which can be configured to perform the aforementioned frequency modulation method described in conjunction with the accompanying drawings.
  • the combined processing device also includes a universal interconnection interface 1202 and other processing devices 1203.
  • the frequency modulation device 1201 according to the present disclosure can interact with other processing devices 1203 through the universal interconnection interface 1202 to jointly complete related operations specified by the user.
  • the other processing device may include one or more types of general-purpose and/or special-purpose processors such as a central processing unit (“CPU"), a graphics processing unit (“GPU”), and a neural network processor.
  • CPU central processing unit
  • GPU graphics processing unit
  • the number of processors can not be limited but determined according to actual needs.
  • the other processing device can be used as the interface between the frequency modulation device of the present disclosure and external data and control, performing basic control including but not limited to data transfer, and completing the basic control of the frequency modulation device on and off; others; The processing device can also cooperate with the frequency modulation device to complete computing tasks.
  • the universal interconnection interface can be used to transmit data and control commands between the frequency modulation device and other processing devices.
  • the frequency modulation device can obtain required input data from other processing devices via the universal interconnection interface, and write the required input data into the on-chip storage device (or memory) of the frequency modulation device.
  • the frequency modulation device can obtain control instructions from other processing devices via the universal interconnection interface, and write them into the on-chip control buffer of the frequency modulation device.
  • the universal interconnection interface can also read the data in the storage module of the frequency modulation device and transmit it to other processing devices.
  • the combined processing device may further include a storage device 1204, which may be connected to the frequency modulation device and the other processing device respectively.
  • the storage device may be used to store the data of the frequency modulation device and the other processing device, especially those that cannot be fully stored in the internal or on-chip storage device of the frequency modulation device or other processing devices. data.
  • the combined processing device of this disclosure can be used as an SOC system on chip for mobile phones, robots, drones, video surveillance equipment and other equipment, effectively reducing the core area of the control part, increasing the processing speed, and adjusting the frequency of the chip to reduce Overall power consumption.
  • the universal interconnection interface of the combined processing device is connected to some parts of the equipment. Some of these components can be, for example, a camera, a display, a mouse, a keyboard, a network card, or a Wifi interface.
  • the present disclosure also discloses a chip, which includes the above-mentioned frequency modulation device or combined processing device. In other embodiments, the present disclosure also discloses a chip packaging structure, which includes the above-mentioned chip.
  • the present disclosure also discloses a board card, which includes the above-mentioned chip packaging structure.
  • a board card which includes the above-mentioned chip packaging structure.
  • the board may also include other supporting components.
  • the supporting components include, but are not limited to: a storage device 1302, an interface device 1303, and a control device. 1304.
  • the storage device is connected to the chip in the chip packaging structure through a bus for storing data.
  • the storage device may include multiple groups of storage units 1305 and 1306. Each group of the storage unit and the chip are connected by a bus. It can be understood that each group of the storage units may be DDR SDRAM ("Double Data Rate SDRAM, Double Rate Synchronous Dynamic Random Access Memory", referred to as DDR for short).
  • DDR SDRAM Double Data Rate SDRAM, Double Rate Synchronous Dynamic Random Access Memory
  • the storage device may include 4 groups of the storage unit. Each group of the storage unit may include a plurality of DDR4 particles (chips). In an embodiment, the chip may include four 72-bit DDR4 controllers. In the 72-bit DDR4 controller, 64 bits are used for data transmission and 8 bits are used for ECC verification. It can be understood that when DDR4-3200 particles are used in each group of the storage units, the theoretical bandwidth of a single storage unit to transmit data can reach 25600MB/s.
  • each group of the storage unit includes a plurality of double-rate synchronous dynamic random access memories arranged in parallel.
  • DDR can transmit data twice in one clock cycle.
  • a controller for controlling the DDR is provided in the chip for controlling the data transmission and data storage of each storage unit.
  • the interface device is electrically connected with the chip in the chip packaging structure.
  • the interface device is used to implement data transmission between the chip and an external device 1307 (for example, a server or a computer).
  • the interface device may be a standard PCIE interface.
  • the data to be processed is transferred from the server to the chip through a standard PCIE interface to realize data transfer.
  • the interface device may also be other interfaces.
  • the present disclosure does not limit the specific manifestations of the other interfaces mentioned above, and the interface unit only needs to be able to realize the switching function.
  • the calculation result of the chip is still transmitted by the interface device back to an external device (such as a server).
  • the control device is electrically connected with the chip.
  • the control device is used to monitor the state of the chip.
  • the chip and the control device may be electrically connected through an SPI interface.
  • the control device may include a CPU or a single-chip microcomputer.
  • the chip may include multiple processing chips, multiple processing cores, or multiple processing circuits, which can drive multiple loads. Therefore, the chip can be in different working states such as multi-load and light-load.
  • the control device can realize the regulation and control of the working states of multiple processing chips, multiple processing cores and/or multiple processing circuits in the chip.
  • the present disclosure also discloses an electronic device or device, which includes the above-mentioned board.
  • electronic equipment or devices can include data processing devices, robots, computers, printers, scanners, tablets, smart terminals, mobile phones, driving recorders, navigators, sensors, cameras, servers, cloud servers, and cameras , Cameras, projectors, watches, earphones, mobile storage, wearable devices, vehicles, household appliances, and/or medical equipment.
  • the transportation means include airplanes, ships, and/or vehicles;
  • the household appliances include TVs, air conditioners, microwave ovens, refrigerators, rice cookers, humidifiers, washing machines, electric lights, gas stoves, and range hoods;
  • the medical equipment includes nuclear magnetic resonance, B-ultrasound and/or electrocardiograph.
  • the disclosed device may be implemented in other ways.
  • the device embodiments described above are merely illustrative, for example, the division of the units is only a logical function division, and there may be other divisions in actual implementation, for example, multiple units or components may be combined or may be Integrate into another system, or some features can be ignored or not implemented.
  • the displayed or discussed mutual coupling or direct coupling or communication connection may be indirect coupling or communication connection through some interfaces, devices or units, or through electrical, optical, acoustic, magnetic or other form.
  • the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the units may be selected according to actual needs to implement the solution of this embodiment.
  • the functional units in the various embodiments of the present disclosure may be integrated into one processing unit, or each unit may exist alone physically, or two or more units may be integrated into one unit.
  • the above-mentioned integrated unit can be implemented in the form of hardware or in the form of software program modules.
  • the integrated unit is implemented in the form of a software program module and sold or used as an independent product, it can be stored in a computer readable memory.
  • the computer software product is stored in a memory and includes several instructions to enable a computer device (which can be a personal computer, a server, or a network device) Etc.) Perform all or part of the steps of the methods described in the various embodiments of the present disclosure.
  • the aforementioned memory includes: U disk, read-only memory ("ROM, Read-Only Memory”), random access memory (“RAM, Random Access Memory”), mobile hard drives, magnetic disks or optical disks, etc., which can store programs The medium of the code.
  • a method for frequency modulation of the chip including:
  • a PID control module is used to determine an adjustment amount for adjusting the clock frequency of the at least one chip.
  • a first adjustment amount for adjusting the clock frequency is determined based on the proportional term.
  • Clause A4 The method according to clause A2 or A3, wherein the first adjustment amount is a first increment relative to the previous adjustment of the clock frequency.
  • a fourth adjustment amount for adjusting the clock frequency of the at least one chip is determined based on the proportional term, the integral term, and the derivative term.
  • each of the second adjustment amount, the third adjustment amount, and the fourth adjustment amount is an increment relative to the previous adjustment of the clock frequency.
  • obtaining the real-time power consumption sample value includes periodically obtaining a plurality of the real-time power consumption sample value, wherein determining the integral item includes for each The real-time power consumption sampling value executes:
  • the integral control unit is used to obtain an integral term.
  • Clause A9 The method according to Clause A8, further comprising limiting the integral term to a selected range in order to eliminate static effects and avoid overshooting operations.
  • a clearing operation is performed on the accumulation sum, so as to perform the accumulation operation in the next predetermined period of time.
  • the error value of the earliest sampling period among the number of the predetermined sampling periods in the accumulation sum is cleared, so as to perform the accumulation operation on the error value of the latest sampling period.
  • the derivative control unit Based on the differential difference value, the derivative control unit is used to obtain a derivative term.
  • a method for frequency modulation of the chip including:
  • a PID control module is used to determine an adjustment amount for adjusting the clock frequency of the at least one chip.
  • a device for frequency modulation of the chip including:
  • An obtaining module configured to obtain at least one real-time power consumption sampling value during chip operation
  • PID control module its configuration is used for:
  • an adjustment amount for adjusting the clock frequency of the at least one chip is determined.
  • a device for frequency modulation of the chip including:
  • An obtaining module configured to obtain at least one real-time power consumption sampling value during chip operation
  • a determining module configured to determine whether the real-time power consumption sampling value is greater than or equal to a fast frequency reduction threshold
  • a fast frequency reduction module configured to perform a fast frequency reduction operation on the at least one chip when the real-time power consumption sampling value is greater than or equal to the fast frequency reduction threshold
  • the PID control module is configured to execute when the real-time power consumption sampling value is less than the fast frequency reduction threshold:
  • An adjustment amount for adjusting the clock frequency of the at least one chip is determined based on the error value.
  • a device for frequency modulation of the chip including:
  • At least one processor At least one processor
  • At least one memory is used to store program instructions, when the program instructions are executed by the at least one processor, cause the device to execute the method according to any one of claims 1-14.
  • a board for frequency modulation of a chip comprising the device according to any one of claims 15-17.
  • An integrated circuit chip including a core for frequency modulation of the chip.
  • the core can be configured to execute the method according to any one of claims 1-14. 202010225223.3
  • an adjustment amount for adjusting the clock frequency of the at least one chip is determined by using N PID control modules connected in series.
  • Clause B2 the method according to clause B1, wherein when N is equal to 2, the primary PID control module and the final PID control module connected in series are used to determine the adjustment, and the adjustment is controlled from the final PID Module output, the method further includes:
  • the final stage PID control module is used to output the adjustment amount
  • the predetermined execution period T1 of the primary PID control module is greater than the sampling period TN of the real-time power consumption sampling value.
  • Clause B3 The method according to clause B1 or clause B2, wherein when N is equal to 3, the primary PID control module, the secondary PID control module, and the final PID control module in series are used to determine the adjustment amount, and The adjustment value is output from the last-stage PID control module, and the method further includes:
  • the first average power consumption value and the average power consumption reference value associated with the primary PID control module are input to the primary PID control module, so that it outputs the second average power consumption target associated with the secondary PID control module Adjusted value of value;
  • the final stage PID control module is used to output the adjustment amount
  • the sampling period of the real-time power consumption sampling value is TN, and the predetermined execution period T2 of the second-level PID control module satisfies the relationship T1>T2>TN.
  • Clause B4 The method according to any one of clauses B1-B3, wherein when N is greater than or equal to 4, a series-connected primary PID control module, second-stage PID control module, ..., N-1th stage PID control Module and the last-stage PID control module to determine the adjustment amount, and output the adjustment amount from the last-stage PID control module, the method further includes:
  • each output of the primary PID control module to the N-2th stage PID control module be input to the respective next stage PID control module, wherein each output of the primary PID control module to the N-2th stage PID control module is The adjustment value of the average power consumption target value associated with the corresponding downstream PID control module;
  • the final stage PID control module is used to output the adjustment amount
  • the respective predetermined execution periods T1,...TN-1 and the sampling period TN of the real-time power consumption sampling value from the primary PID control module to the N-1th level PID control module satisfy the relationship T1>T2...TN-1 >TN.
  • a method for frequency modulation of the chip including:
  • N is a positive integer greater than or equal to 2
  • an adjustment amount for adjusting the clock frequency of the at least one chip is determined by using N PID control modules connected in series.
  • a device for frequency modulation of the chip including:
  • An acquiring module configured to acquire at least one real-time power consumption sample value during chip operation and an average power consumption value in N-1 predetermined execution cycles, where N is a positive integer greater than or equal to 2;
  • N PID control modules connected in series step by step, which are configured to determine the adjustment for adjusting the clock frequency of the at least one chip based on the real-time power consumption sampling value, the average power consumption value, and the average power consumption reference value quantity.
  • a device for frequency modulation of the chip including:
  • An acquiring module configured to acquire at least one real-time power consumption sampling value during chip operation
  • a determining module configured to determine whether the real-time power consumption sampling value is greater than or equal to a fast frequency reduction threshold
  • a fast frequency reduction module configured to perform a fast frequency reduction operation on the at least one chip when the real-time power consumption sampling value is greater than or equal to the fast frequency reduction threshold
  • N PID control modules connected in series in stages are configured to perform the following operations when the real-time power consumption sampling value is less than the fast frequency reduction threshold:
  • N is a positive integer greater than or equal to 2
  • an adjustment amount for adjusting the clock frequency of the at least one chip is determined.
  • a device for frequency modulation of the chip including:
  • At least one processor At least one processor
  • At least one memory is used to store program instructions, when the program instructions are executed by the at least one processor, cause the device to execute the method according to any one of clauses B1-B6.
  • Clause B10 A board for frequency modulation of the chip, including the device according to any one of clauses B7-B9.
  • Clause B11 An integrated circuit chip including a core for frequency modulation of the chip.
  • the core can be configured to execute the method according to any one of clauses B1-B6.
  • Clause B12 A computer-readable storage medium that stores program instructions for frequency modulation of the chip. When the program instructions are executed by the processor, the method according to any one of clauses B1-B6 is executed.
  • the term “if” can be interpreted as “when” or “once” or “in response to determination” or “in response to detection” depending on the context.
  • the phrase “if determined” or “if judged [described condition or event]” can be construed to mean “once determined” or “in response to determination” or “once detected [described condition or event]” depending on the context ]” or “in response to detection of [condition or event described]”.

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Abstract

本披露公开了一种用于对芯片进行调频的方法、设备及计算机可读存储介质。其中该调频设备可以包括在组合处理装置中，该组合处理装置还可以包括通用互联接口和其他处理装置。所述设备与其他处理装置进行交互，共同完成用户指定的计算操作。组合处理装置还可以包括存储装置，该存储装置分别与所述设备和其他处理装置连接，用于存储所述设备和其他处理装置的数据。本披露的方案可以通过实时测量系统的功耗以便动态调整芯片工作的频率，进而提高运算芯片及组合处理装置的运算性能。该方案具有方便灵活、频率调节速度快等优点。

Description

用于对芯片进行调频的方法、设备及计算机可读存储介质
相关申请的交叉引用
本申请要求如下优先权：于2020年03月26日申请，申请号为202010225223.3，名称为“用于对芯片进行调频的方法、设备及计算机可读存储介质”的中国专利申请；于2020年03月26日申请，申请号为202010225213.X，名称为“用于对芯片进行调频的方法、设备及计算机可读存储介质”的中国专利申请，在此将其全文引入作为参考。
技术领域
本申请涉及芯片控制领域。特别是涉及一种用于对芯片进行调频的方法、设备及计算机可读存储介质。
背景技术
近年来，随着数据量的增多，计算能力的增强，用于数据运算的计算设备及测试设备中，通常集成了大量的芯片。由于各种芯片的工作性能和制造工艺差别较大，会直接影响整个系统的功耗和运算性能，尤其是运算芯片的工作频率可以决定整个组合处理装置的功耗和工作性能。因此，如何动态调节芯片实际所需频率，已成为亟待解决的问题。
发明内容
202010225223.3为了至少解决在上述背景技术部分所描述的一个或多个问题，以便通过调整一个或多个组合处理装置中的所述芯片的工作频率，进而提高整个组合处理装置的工作性能，本披露提出如下的技术方案及其多个实施例。
在一个方面中，本披露公开了一种用于对芯片进行调频的方法，该方法包括获取至少一个芯片操作时的实时功耗采样值；根据所述实时功耗采样值和功耗目标值，确定二者之间的误差值；以及基于所述误差值，利用PID控制模块来确定用于调整所述至少一个芯片的时钟频率的调整量。
在另一个方面中，本披露还公开了一种用于对芯片进行调频的方法，该方法包括获取至少一个芯片操作时的实时功耗采样值；确定所述实时功耗采样值是否大于或等于快速降频阈值；当所述实时功耗采样值大于或等于所述快速降频阈值时，执行对所述至少一个芯片的快速降频操作；当所述实时功耗采样值小于所述快速降频阈值时，执行根据所述实时功耗采样值和功耗目标值，确定二者之间的误差值；以及基于所述误差值，利用PID控制模块来确定用于调整所述至少一个芯片的时钟频率的调整量。
在又一个方面中，本披露进一步公开了一种用于对芯片进行调频的设备，该设备包括：获取模块，其配置用于获取至少一个芯片操作时的实时功耗采样值；PID控制模块，其配置用于根据所述实时功耗采样值和功耗目标值，确定二者之间的误差值；以及基于所述误差值，确定用于调整所述至少一个芯片的时钟频率的调整量。
在一个方面中，本披露公开了一种用于对芯片进行调频的设备，该设备包括：获取模块，其配置用于获取至少一个芯片操作时的实时功耗采样值；确定模块，其配置用于确定所述实时功耗采样值是否大于或等于快速降频阈值；快速降频模块，其配置用于当所述实时功耗采样值大于或等于所述快速降频阈值时，执行对所述至少一个芯片的快速降频操作；以及PID控制模块，其配置用于当所述实时功耗采样值小于所述快速降频阈值时，执行：根据所述实时功耗采样值和功耗目标值，确定二者之间的误差值；以及基于所述误差值来确定用于调整所述至少一个芯片的时钟频率的调整量。
在另一个方面中，本披露还公开了一种用于对芯片进行调频的设备，该设备包括：至少一个处理器；至少一个存储器，用于存储程序指令，当该程序指令由所述至少一个处理器执行时，使得所述设备执行前述对芯片进行调频的方法。
在又一个方面中，本披露公开了一种用于对芯片进行调频的板卡，该板卡包括前述的任一对芯片进行调频的设备。
在一个方面中，本披露公开了一种集成电路芯片，该芯片包括用于对芯片进行调频的内核，当所述集成电路芯片工作时，所述内核可配置成执行前述对芯片进行调频的方法。
根据本披露所提出的方法、设备和计算机可读存储介质，可以利用改进的PID控制技术对相关芯片进行调频控制。在一些应用场景中，本披露通过外部MCU(“Microcontroller Unit微控制单元”)对相关芯片进行调频控制的方案可以直接应用于具有修改频率接口的芯片，从而实现动态调频。同时，在频率控制过程中，本地数据被采集后可以直接进行本地管理和应用，从而调频速度更快。另外，本披露的技术方案也可以进行灵活地调整，比如调整比例系数、调整定时清空时间以及去掉积分项等，以适应不同的应用需求。
通过权要中的技术特征进行推导，能够达到对应背景技术中的技术问题的有益效果。202010225223.3
202010225213.X为了至少解决在上述背景技术部分所描述的一个或多个问题，以便通过调整一个或多个组合处理装置中的所述芯片的工作频率，进而提高整个组合处理装置的工作性能，本披露提出如下的技术方案及其多个实施例。
在一个方面中，本披露公开了一种用于对芯片进行调频的方法，该方法包括获取至少一个芯片操作时的实时功耗采样值和N-1个预定执行周期内的平均功耗值，其中N是大于或等于2的正整数；以及基于所述实时功耗采样值、所述平均功耗值和平均功耗参考值，利用N个逐级串联的PID控制模块来确定用于调整所述至少一个芯片的时钟频率的调整量。
在另一个方面中，本披露还公开了一种用于对芯片进行调频的方法，该方法包括获取至少一个芯片操作时的实时功耗采样值；确定所述实时功耗采样值是否大于或等于快速降频阈值；当所述实时功耗采样值大于或等于所述快速降频阈值时，执行对所述至少一个芯片的快速降频操作；当所述实时功耗采样值小于所述快速降频阈值时，执行以下操作：获取N-1个预定执行周期内的平均功耗值，其中N是大于或等于2的正整数；以及基于所述实时功耗采样值、所述平均功耗值和平均功耗参考值，利用N个逐级串联的PID控制模块来确定用于调整所述至少一个芯片的时钟频率的调整量。
在又一个方面中，本披露进一步公开了一种用于对芯片进行调频的设备，该设备包括：获取模块，其配置用于获取至少一个芯片操作时的实时功耗采样值和N-1个预定执行周期内的平均功耗值，其中N是大于或等于2的正整数；以及N个逐级串联的PID控制模块，其配置用于基于所述实时功耗采样值、所述平均 功耗值和平均功耗参考值，确定用于调整所述至少一个芯片的时钟频率的调整量。
在一个方面中，本披露公开了一种用于对芯片进行调频的设备，该设备包括：获取模块，其配置用于获取至少一个芯片操作时的实时功耗采样值；确定模块，其配置用于确定所述实时功耗采样值是否大于或等于快速降频阈值；快速降频模块，其配置用于当所述实时功耗采样值大于或等于所述快速降频阈值时，执行对所述至少一个芯片的快速降频操作；N个逐级串联的PID控制模块，其配置用于当所述实时功耗采样值小于所述快速降频阈值时，执行以下操作：获取N-1个预定执行周期内的平均功耗值，其中N是大于或等于2的正整数；以及基于所述实时功耗采样值、所述平均功耗值和平均功耗参考值，确定用于调整所述至少一个芯片的时钟频率的调整量。
在另一个方面中，本披露还公开了一种用于对芯片进行调频的设备，该设备包括：至少一个处理器；至少一个存储器，用于存储程序指令，当该程序指令由所述至少一个处理器执行时，使得所述设备执行前述的控制处理器的方法。
在又一个方面中，本披露公开了一种用于对芯片进行调频的板卡，该板卡包括前述的任一设备。
在一个方面中，本披露公开了一种集成电路芯片，该芯片包括用于对芯片进行调频的内核，当所述集成电路芯片工作时，所述内核可配置成执行前述的任意一项控制处理器的方法。
在又一个方面中，本披露公开了一种计算机可读存储介质，其存储有用于对芯片进行调频的程序指令，当该程序指令由处理器运行时，执行前述任意一项所述的方法。
根据本披露所提出的方法、设备和计算机可读存储介质，可以利用改进的PID控制技术对相关芯片进行调频控制。在一些应用场景中，本披露通过外部MCU(“Microcontroller Unit微控制单元”)对相关芯片进行调频控制的方案可以直接应用于具有修改频率接口的芯片，从而实现动态调频。同时，在频率控制过程中，本地数据被采集后可以直接进行本地管理和应用，从而调频速度更快。另外，本披露的技术方案也可以进行灵活地调整，比如调整比例系数、调整定时清空时间以及去掉积分项等，以适应不同的应用需求。[14]202010225213.X
附图说明
通过结合附图，可以更好地理解本披露的上述特征，并且其众多目的、特征和优点对于本领域技术人员而言是显而易见的。下面描述中的附图仅仅是本披露的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可根据这些附图获得其他的附图，其中：
图1是示出根据本披露实施例的用于对芯片进行调频的示例系统的操作流程的框图。
图2是示出根据本披露实施例的用于对芯片进行调频的方法的总体流程图。
图3是示出根据本披露实施例的用于对芯片进行调频的方法的详细流程图。
图4是示出根据本披露实施例的快速降频的调频方法的流程图。
图5是示出根据本披露实施例的多级动态调频方法的总体流程图。
图6是示出根据本披露实施例的二级动态调频方法的流程框图。
图7是示出根据本披露实施例的三级动态调频方法的流程框图。
图8是示出根据本披露实施例的多级动态调频方法的流程框图。
图9是示出根据本披露实施例的具有多级和快速降频的调频方法的流程框图。
图10是示出利用本披露实施例的设备对芯片进行调频的示意框图。
图11是示出利用本披露实施例的设备对芯片进行调频的另一示意框图。
图12是示出根据本披露实施例的一种组合处理装置的结构框图。
图13是示出根据本披露实施例的对芯片进行调频的板卡的结构框图。
具体实施方式
本披露的技术方案提供了一种用于对芯片进行调频的方法、设备及计算机可读存储介质。通过实时采集芯片的功耗等数据，并使用PID控制模块来对芯片的工作频率进行增量调整，进而控制系统整体的工作性能。在一些实施例中，本披露的方案使用单个或单级的PID控制模块对单个或多个芯片的工作频率进行增量调整。在另一些实施例中，本公开的方案使用多级串联的PID控制模块来对芯片的频率进行更加精细的调整。利用本披露的技术方案，可以实现组合处理装置中的一个或多个芯片的工作频率的增量调整。在频率调 整过程中可以消除静差作用的同时，还可以削弱超调的影响。同时，本披露的调频方案稳定可靠，在业务可以达到设定目标功耗的情况下，可以将实际板卡平均功耗控制在目标功耗的±1W范围内。
应当理解，本披露关于上述的芯片调频的方案阐述了许多具体细节以便提供对本披露所述多个实施例的透彻理解。然而，本领域普通技术人员在本披露公开内容的教导下可以在没有这些具体细节的情况下实践本披露描述的多个实施例。在其他情况下，本披露公开的内容并没有详细描述公知的方法、过程和组件，以避免不必要地模糊本披露描述的实施例。进一步，该描述也不应被视为限制本披露的多个实施例的范围。
下面将结合附图，对本披露的多个实施例中的技术方案进行清楚和完整地描述。
图1是示出根据本披露实施例的用于对芯片进行调频的示例系统的操作流程100的框图。需要注意的是，这里的系统及其操作流程仅仅是示例性的而非限制性的。本系统除调频操作以外，还可以执行其他的操作，而这些操作将不在此处做详细的描述，以便不必要地混淆本披露的方案。
如图1所示，本披露的系统操作流程包括在步骤101处对系统执行初始化操作。例如，在初始化操作中，可以根据实际应用情况针对系统来进行相应的参数设置，并且还可以调入初始数据，以便准备后续程序的执行。
在经过上述的初始化操作后，在步骤102和103处，本披露的调频系统可以并行地或串行地分别执行主循环操作和动态调频操作。这里，主循环操作可以是除动态调频操作以外系统所需执行各类操作或任务，例如针对于人工智能领域的机器学习相关的操作。在动态调频操作中，如前所述，可以使用PID控制模块来对芯片的工作频率进行调整。
在一个应用场景中，在如图所示的定时器的控制下，包括本披露的PID控制模块的MCU可以按照固定的时间间隔(例如1毫秒)来获取至少一个芯片操作时的实时功耗采样值，并且通过结合功耗目标值，从而确定用于调整芯片的时钟频率的调整量。此后，可以利用该调整量在步骤104中针对相关情形来对一个或多个芯片的时钟频率实施调频动作，由此进一步管控整个设备或系统的功耗。此处的相关情形可以例如是芯片的操作频率过高或过低，或者是需要动态调频的 其他场景。
上面结合图1对本披露用于对芯片进行调频的系统的操作流程进行了简要的描述，下面将结合图2-图13对芯片进行调频的流程方法、及其设备和装置做出进一步描述。
图2是示出根据本披露实施例的用于对芯片进行调频的方法200的总体流程图。可以理解的是，这里所讨论的调频方法可以结合图1系统的操作流程来执行。
如图2所示，在步骤201处，方法200可以获取至少一个芯片操作时的实时功耗采样值。接着，在步骤202处，方法200根据所述实时功耗采样值(例如1毫秒内采到的芯片功耗)和功耗目标值(例如芯片的功耗期望值)，确定二者之间的误差值。在一个实施例中，可以通过对前述的实时功耗采样值和功耗目标值求取差值来获得二者之间的误差值。接着，在步骤203处，方法200基于所述误差值，利用PID控制模块来确定用于调整至少一个芯片的时钟频率的调整量。在一个实施例中，这里的调整量可以是基于前次调整频率的一个相对增量。由此，可以通过将所述调整量与芯片当前的时钟频率相加，以获得本次操作调整后的芯片的时钟频率。
为了更好的理解本披露的技术方案，下面将对本披露使用到的PID控制算法进行介绍。
PID控制算法是结合比例(P)、积分(I)和微分(D)的一种控制算法，其控制的实质就是根据输入的偏差值，按照比例、积分、微分的函数关系进行运算，并且将运算结果用以控制输出。本披露的PID控制算法对现有PID控制算法进行改进，输出值是一个调整量，并且可以是一个相对于前一次调整量的增量，从而有别于现有PID控制算法输出值是一个绝对数值的情形。在一个实施例中，本披露的PID控制算法可以采用如下的公式(1)来获得调整量△u(t)：
u(t)＝k p*e(t)+k i*Σe(t)+k d*(e(t)-e(t-1))    (1)
其中k p为比例系数，k i为积分系数，k d为微分系数。e(t)为误差值，Σe(t)为误差值累加和，e(t-1)为前一次误差值。k p*e(t)为比例项，k i*Σe(t)为积分项，k d*(e(t)-e(t-1))为微分项。
根据不同的应用场景，本披露的方案既可以通过比例项来获得调整量， 也可以通过将比例项与积分项和微分项中的任意一项进行组合来获得调整量。进一步，还可以将前述的三者组合使用来获得调整量，进而执行对芯片的调频方案。另外，通过在不断实测的基础上进行改进，本披露的PID控制算法将仅适用于类线性系统的传统PID算法拓展到了非线性系统中，并且实测效果良好。
上文结合图2对本披露的方案以及所使用到的PID控制模块进行了描述。基于上述描述，本领域技术人员可以理解本披露的PID控制模块在实现方面可以具有用于确定比例项的比例控制单元。可选地，其还可以进一步包括用于确定积分项的积分控制单元和用于确定微分项的微分控制单元中的至少一个。通过比例项或者将比例项与积分项和微分项二者中的至少一个来组合以确定调整量，本披露提供了多种灵活的方式来对芯片进行调频操作。
图3是示出根据本披露实施例的用于对芯片进行调频的方法300的详细流程图。通过下文的描述，本领域技术人员可以理解图3是图2所示的用于对芯片进行调频的方法的进一步细化，并且关于图2的描述同样也适用于图3所示出的内容。
如图3所示，在步骤301处，方法300获取实时功耗采样值。在一个实施例中，获取所述实时功耗采样值包括周期性地(例如1毫秒)获取多个所述实时功耗采样值。接着，方法300进入步骤302处，计算当前实时功耗与目标功耗之间的误差值。在一个实施例中，确定每个所述实时功耗采样值与所述功耗目标值之间的误差值可以对该实时功耗采样值与功耗目标值(例如用户定义的芯片或者板卡的期望功耗)求取差值，并将该差值视为误差值。
在获得误差值之后，方法300前进到步骤303，此处可以根据误差值得到比例项。在利用前述PID控制模块来确定调整量的一个实施例中，可以基于所述误差值，利用PID控制模块中的比例控制单元来获得比例项。在一种具体实现中，获得比例项可以包括根据所述误差值、选择的比例系数(例如根据实测结果调整的参量)和量纲(例如赫兹/瓦)来获得。在一个实施例中，可以基于所述比例项来确定用于调整所述时钟频率的第一调整量。接着，如图3中所示，方法300可以直接前进到步骤310处执行调频操作。具体地，可以依据获得的前述第一调整量结合前一次调整所述时钟频率对一个或多 个芯片的时钟频率实施调频动作。
作为上述的替代方案，在步骤304处，方法300判断是否到达预定时间段(例如1秒的时间段)，这例如可以通过图1中所示出的定时器来实现。当预定时间段到达时，方法300执行步骤305，即对累加和执行清零操作，以便重新开始下一所述预定时间段内的对误差值的累加操作。根据本披露的方案，该累加和的清零操作可以清除功耗调节可能引起的累积效应。为了便于说明该累积效应，假设在一个实现的场景中，目标功耗值(用户设定的预期功耗值)是75瓦，并且芯片在预定的时间段内一直处于空载，从而在该预定的时间段内获取的实时功耗采样值一直是30瓦。在该情况下，当进行累加操作时，在该预定的时间段内的误差值累加和相对会很大。若此时出现芯片的功耗采样值超过目标功耗值(即75瓦)的情形，则会因为累加和已经过大而导致此次功耗的误差值被中和(即前述的累积效应)，从而导致系统功耗长时间超标，既而影响系统性能。鉴于此，本披露的方案因此提出在预定的时间段内对误差值累加和执行清零操作，以避免累积效应。
作为步骤304和305的替代方案，方法300可以另一种方式来判断是否到达预定时间段。具体地，可以将获取一个所述实时功耗采样值的时间段称为一个采样周期，由此可以将预定时间段设定为包括一定数目的采样周期。当该数目的采样周期到达时，可以从累加和中清除最早的采样周期所获得的误差值，并且将最近的采样周期所获得的误差值计入到累加和中。例如，以预定时间段包括100个采样周期为例，从第1个采样周期开始，确定该采样周期获取的实时功耗采样值与目标功耗值之间的误差值，并且依次与下一个周期的所述误差值执行累加操作，以获得累加和。当第100个采样周期到达时，方法300可以对累加和中预定采样周期个数中的最早一个采样周期(即第1个采样周期)的所述误差值进行清除，以便对最近一个采样周期(即第101个采样周期)的所述误差值执行累加操作，以获得累加和。即，该更新的累加和累计计算的是第2个采样周期至第101个采样周期的所述误差值。可以看出，通过对预定时间段进行不同的设置，本披露对如何确定累加和给出了多种方案，由此进一步提升了本披露的应用灵活性。
相反地，在预定时间段还未到达时，则方法300执行步骤306，即将本次 误差值加入至累加和中。在获得更新后的累加和后，在步骤307处，方法300根据累加和得到积分项。如前所述，获得积分项可以包括根据所述累加和、选择的积分系数和量纲(例如赫兹/瓦)来获得积分项。接着，在步骤308处，限制积分项范围。在一个实施例中，可以将积分项限制在选择的范围内，以便消除静差作用和避免超调作用。该范围例如可以是经验统计值或多次实测后确定的调整量。此后，方法300进入步骤309，此处可以根据比例项与限制范围后的积分项来获得频率调节参数，例如本披露所称的调整量。此后，方法300前进到步骤310，此处方法300根据获得的调整量来对至少一个芯片的时钟频率执行调频动作。
替代地或可选地，在步骤303处获得比例项或步骤309处获得比例项与限制后的积分项后，可以根据实际应用场景选择与微分项组合来获得频率调节参数。在此种情况下，方法300根据本次确定的误差值与前一次确定的误差值执行减法操作以获得微分差值。接着，基于所述微分差值，利用所述PID控制模块中的微分控制单元来获得微分项。如前所述，获得微分项可以包括根据所述微分差值、选择的微分系数和量纲(例如赫兹/瓦)来获得微分项。最后，在步骤310处，方法300可以根据通过比例项以及积分项和微分项二者中的至少一项所获得的调整量来对芯片的时钟频率执行调频动作。当在确定调整量的过程中使用微分项时，可以对调频起到一定的超前调节作用，也可以使调频反应速度变得更快。
通过上述结合步骤304-310的描述，本领域技术人员可以理解本披露在一个实施例中周期性地(例如1毫秒)获取多个所述实时功耗采样值，并且在预定时间段(例如1秒)内针对每个所述实时功耗采样值执行确定每个所述实时功耗采样值与所述功耗目标值之间的误差值，并且对每次确定的所述误差值执行累加操作以获得累加和。进一步，基于该累加和，利用所述PID控制模块中的积分控制单元来获得积分项。接着，可以基于获得的比例项和利用积分控制单元所获得的积分项来确定用于调整所述至少一个芯片的时钟频率的第二调整量(相对于前述的第一调整量而言)。
如前所述，除了可以获得上述的第二调整量，在一个或多个实施例中，本披露还可以基于获得的比例项和利用微分控制单元所获得的微分项来确 定用于调整所述至少一个芯片的时钟频率的第三调整量。类似地，还可以基于前述获得的比例项、积分项和微分项来确定用于调整所述至少一个芯片的时钟频率的第四调整量。在一个应用场景中，该第二调整量、第三调整量和第四调整量中的每个是相对于前次调整所述时钟频率的增量。对于这四种示例性的调整量，本领域技术人员可以根据监测到的实际调频效果来进行实时的调整，从而实现对芯片的实时调频操作。
上文结合图2和图3描述了本披露在芯片功耗位于合理范围内时，对芯片执行的调频操作。下文将结合图4详细描述了芯片功耗波动瞬时变大到超过常规范围的情况下，对芯片执行快速降频的操作。
图4是示出根据本披露实施例的快速降频的调频方法400的流程图。如图4所示，在步骤401处，方法400获取至少一个芯片操作时的实时功耗采样值。例如，可以周期性地(例如1毫秒)采集至少一个芯片的实时功耗采样值。接着，在步骤402处，确定实时功耗采样值是否大于或等于快速降频阈值。在一个应用场景中，该快速降频阈值可以根据产品规格要求来确定，其计算公式例如可以为下式：
P th＝U*I max      (2)
其中U表示工作电压，I max表示允许的最大电流，P th表示快速降频阈值，*表示乘积关系。
在另一个实施例中，该快速降频阈值也可以在前述公式计算结果的基础上，根据实测结果进行一定范围内的调整，该调整范围可以例如根据经验值来确定。
当实时功耗采样值大于或等于上述的快速降频阈值时，方法400前进到步骤403处，此时方法400执行对至少一个芯片的快速降频操作。在执行快速降频操作前，在一个或多个实施例中，可以确定芯片本次调整的目标频率值。在一个实施例中，该目标频率值可以由如下公式确定：
F aim＝F now*(P aim-P idle)/(P now-P idle)      (3)
其中F aim为目标频率，F now为当前频率，P aim为目标功耗，P idle为空闲功耗，P now为当前功耗，*表示乘积关系。需要注意的是，在执行快速降频的瞬时，可以近似认为功耗与频率二者间是线性关系。本披露的方案可以借助于这样的线性关系来获得目标频率值，该目标频率值可以作为本次调整的时钟频率，从而对至 少一个芯片执行相应的调频动作。
相反地，当实时功耗采样值小于快速降频阈值时，方法400在步骤404处执行正常调频操作。例如，方法400可以根据实时功耗采样值和功耗目标值，确定二者之间的误差值。接着，方法400可以基于前述误差值，利用PID控制模块来确定用于调整所述至少一个芯片的时钟频率的调整量。由此，可以依据获得的调整量结合前一次调整所述时钟频率对一个或多个芯片的时钟频率执行正常调频操作。本领域技术人员可以理解的是，这里的正常调频操作可以是前面结合图3所执行的调频操作，因此前面结合图3所描述的对芯片进行调频的操作也同样适用于此处的正常调频操作，故相同或类似的内容在此处将不再赘述。
在上文中，本披露结合图1-图4描述了对芯片执行单级PID(例如图6中所示出的第二级，稍后详细描述)的调频操作，下文将结合图5-图9对本披露的多级PID调频操作做出进一步地说明。
图5是示出根据本披露实施例的多级动态调频方法500的总体流程图。通过利用方法500对芯片进行多级串行PID动态调频，可以使频率调节更加精细，并且在一定程度上允许短时间内功耗超过TDP(“Thermal Design Power，散热设计功耗”)功耗，从而提高系统性能。
如图5所示，在步骤501处，方法500获取至少一个芯片操作时的实时功耗采样值和N-1个预定执行周期内的平均功耗值，其中N是大于或等于2的正整数。在一个实施例中，N-1个预定执行周期T 1，……T N-1和实时功耗采样值的采样周期T N满足关系T 1(例如1秒)>T 2(例如500毫秒)……T N-1(例如50毫秒)>T N(例如1毫秒)。接着，在步骤502处，方法500基于所述实时功耗采样值、所述平均功耗值和平均功耗参考值，利用N个逐级串联的PID控制模块来确定用于调整所述至少一个芯片的时钟频率的调整量。在一个实施场景中，本披露的平均功耗参考值可根据实际情况进行灵活设定。例如，可以通过上位机的“Power Capping”功能进行设定，该功能允许用户将平均功耗参考值限定在其指定的范围内。进一步，在修改该平均功耗参考值后，用户无须再调整其他参数，所有涉及到前一次的平均功耗参考值的参数将自动按照用户给出的新的平均功耗参考值来进行相应地调整。
以上结合图5对多级动态调频方法500的总体流程进行了简要说明，为了便于进一步地理解本披露的多级调频方案，下文将结合图6以二级PID控制模块串联的方式对多级动态调频方法进行详细的描述。
图6是示出根据本披露实施例的二级动态调频方法600的流程框图。正如将理解到的，方法600是前述图5描述的N级动态调频方法中当N等于2时的情形，即利用串联的初级PID控制模块和末级PID控制模块来确定所述调整量，并将该调整量从所述末级PID控制模块输出。
如图6所示，方法600可以分别获取至少一个芯片的初级PID控制模块的预定执行周期T 1(例如1秒)内的第一平均功耗值601和与初级PID控制模块关联的平均功耗参考值602。接着，方法600可以将所述第一平均功耗值和所述平均功耗参考值输入至初级PID控制模块603中。进一步，方法600可以将初级PID控制模块603的输出值，即本次的调整量和前次调整操作的实时功耗目标值输入至一个处理模块中进行计算，而该处理模块的输出即是本次调整操作的实时功耗目标值604。此后，方法600可以将其输入至末级PID控制模块606。接着，基于实时功耗采样值605和本次调整操作的实时功耗目标值604，利用末级PID控制模块606来输出调整量。实时功耗目标值与实时功耗采样值输入至末级PID控制模块的工作流程与上文结合图3描述的对芯片进行单级调频的方法相同或类似，此处将不再赘述。
最后，在步骤607处，方法600基于末级PID控制模块606输出值和芯片前次调整操作的时钟频率，可以获得芯片本次调整操作的时钟频率，依据该时钟频率执行相应的调频动作。如前所述，所述调整量可以是相对于前次调整时钟频率的增量。在一个实施例中，初级PID控制模块的预定执行周期T 1(例如1秒)大于所述实时功耗采样值的采样周期T N(例如1毫秒)。
图7是示出根据本披露实施例的三级动态调频方法700的流程框图。这里在图5-图6的基础上，对本披露的方案做出进一步细化描述，因此关于图5-图6所做的多级动态调频的描述也同样适用于图7的操作。如图7所示，这里绘出了N级动态调频方法中当N等于3时的情形，即利用串联的初级PID控制模块、第二级PID控制模块和末级PID控制模块来确定所述调整量，并且将该调整量从所述末级PID控制模块输出。
具体地，方法700分别获取所述至少一个芯片的初级PID控制模块的预定执行周期T 1(例如1秒)内的第一平均功耗值701和与初级PID控制模块关联的平均功耗参考值702，输入至初级PID控制模块703，以令其输出与第二级PID控制模块706关联的第二平均功耗目标值的调整值。接着，方法700获取第二级PID控制模块的预定执行周期T 2内的第二平均功耗值705，并且将其输入至第二级PID控制模块706。进一步，利用调整值对第二平均功耗目标值进行调整来获得调整后的第二平均功耗目标值704，并将其输入至所述第二级PID控制模块706。
更进一步，基于第二级PID控制模块706的输出值和前次调整操作的实时功耗目标值来获得本次调整操作的实时功耗目标值707，并且将其输入至末级PID控制模块709。接着，基于实时功耗采样值708和本次调整操作的实时功耗目标值707，利用末级PID控制模块709输出所述调整量。在一个实施例中，实时功耗采样值的采样周期为T N，并且所述第二级PID控制模块的预定执行周期T 2满足关系T 1(例如1秒)>T 2(例如200毫秒)>T N(例如1毫秒)。在一个示例性实施场景中，当作为初级PID控制模块输入值的平均功耗参考值是TDP功耗(例如75瓦)时，如果预定执行周期(例如1秒)内第一平均功耗值低于平均功耗参考值(即TDP功耗)，则可以升高下一级PID控制模块(例如第二级PID控制模块)的输入值，使该平均功耗目标值减少抑制功耗的力度；反之，当第一平均功耗值高于平均功耗参考值(即TDP功耗)时，则可以降低下一级PID控制模块的平均功耗目标值，以加大对功耗的抑制力度。
类似图6中所示出的，在获得上述至少一个芯片的时钟频率调整量后，在步骤710处，方法700基于末级PID控制模块709输出值和芯片前次调整操作的时钟频率，可以获得芯片本次调整操作的时钟频率，并依据该时钟频率执行相应的调频动作。
图8是示出根据本披露实施例的多级动态调频方法800的流程框图。这里在图5-图7的基础上，对本披露的方案做出进一步细化描述，因此关于图5-图7所做的多级动态调频的描述也同样适用于图8的操作。
如图8所示，其示出N级动态调频方法中N大于等于4时的情形，即利 用串联的初级PID控制模块、第二级PID控制模块，……，第N-1级PID控制模块和末级PID控制模块来确定所述调整量，并且将该调整量从所述末级PID控制模块输出。
首先，方法800获取初级PID控制模块803至第N-1级PID控制模块809在其各自预定执行周期T 1，……T N-1内的第一平均功耗值801、第二平均功耗值805至第N-1平均功耗值808，并将其分别输入到所述初级PID控制模块803、第二级PID控制模块806、……至第N-1级PID控制模块809中。在一个实施例中，初级PID控制模块至第N-1级PID控制模块的各自预定执行周期T 1，……T N-1和实时功耗采样值的采样周期T N满足关系T 1(例如1秒)>T 2(例如500毫秒)……T N-1(例如50毫秒)>T N(例如1毫秒)。接着，将第一平均功耗值801和与初级PID控制模块关联的平均功耗参考值802输入至初级PID控制模块803，并且令初级PID控制模块至第N-2级PID控制模块的输出向各自的下一级PID控制模块输入，其中所述初级PID控制模块至第N-2级PID控制模块的每个输出是对与相应后一级PID控制模块关联的平均功耗目标值的调整值。进一步，利用每个调整值对相应后一级的平均功耗目标值进行调整来分别获得调整后的第二平均功耗目标值804，……和第N-1平均功耗目标值807，并且将其分别输入至相应的第二级PID控制模块806，……至第N-1级PID控制模块809。
更进一步，基于第N-1级PID控制模块809的输出值和前次调整操作的实时功耗目标值来获得本次调整操作的实时功耗目标值810，并且将其输入至末级PID控制模块812。以及，基于实时功耗采样值811和本次调整操作的实时功耗目标值810，利用末级PID控制模块812输出所述调整量。实时功耗采样值与实时功耗目标值输入至末级PID控制模块的工作流程与上文结合图3描述的对芯片进行单级调频的方法相同或类似，此处将不再赘述。最后，在步骤813处，方法800基于末级PID控制模块812输出值和芯片前次调整操作的时钟频率，可以获得芯片本次调整操作的时钟频率，并依据该时钟频率执行相应的调频动作。
本披露的前文结合至少一个芯片对采集功耗及其调频方案进行了描述。然而，本披露的方案也适用于对包括一个或多个芯片的板卡的功耗进行采集。 换句话说，本披露采集功耗的对象既可以是芯片，也可以是包括芯片的板卡。下面将结合图9以采集板卡的整板功耗作为示例来进一步描述调频的方法。
图9是示出根据本披露实施例的具有多级和快速降频的调频方法900的流程框图。本领域技术人员可以理解的是，图9的技术方案是在图4-图8所示的快速降频和多级PID调频结合后的调频方法。因此，关于图4-图8中所描述的技术细节在图9中也同样适用。
如图9所示，在步骤901处，等待上一次的调频动作结束，即利用末级PID的输出对芯片进行调频的过程期间。由于调频动作从开始到执行完成需要一定的时间，在调频开始之后，到等待调频完成的时间段内，本披露的方案也允许并行执行其他任务(例如图1中所示出的主循环102执行的任务)，从而可以提高动态调频的效率。直到前次调频动作完成后，方法900进入到步骤902，此处可以获取整板功耗，该整板可以是包括一个或多个待调频的芯片的板卡。在实际场景中，例如可以通过板卡上的传感器来实时采集整板功耗，以获取整板操作时的实时功耗采样值，也可以通过板卡上的传感器来实时采集芯片功耗，以获取至少一个芯片操作时的实时功耗采样值，进而获取整板实时功耗采样值。接着，在步骤903处，每获取一个整板实时功耗采样值后，方法900确定整板实时功耗采样值是否大于或等于整板快速降频阈值。在一个实施例中，该快速降频阈值可以根据前述公式(2)来计算获得。在另一个实施例中，该阈值也可以在前述公式(2)计算数值的基础上，根据实测结果进行一定范围的调整，该调整范围可以根据经验值确定。
当整板实时功耗采样值小于整板快速降频阈值时，方法900前进到步骤904，此处计算预定时间段(例如1秒)内的平均功耗值。接着，在步骤905处，方法900执行多级动态调频的操作，即前面结合图6-图8所描述的多级PID调频操作。最后，在步骤906处，方法900根据确定的调整量和芯片前次调整操作的时钟频率，以获得芯片本次操作调整的调频参数(即时钟频率)。
相反地，当整板实时功耗采样值大于或等于整板快速降频阈值时，则方法900在步骤908处计算整板快速降频的目标频率值。该情形例如可以发生在当检测到整板瞬时功耗较大(例如超过1.2倍TDP)后，为了能在短时间内将芯片频率降低以满足板卡功耗的需求，此时执行快速降频操作。在执行快速降频操作前， 需要确定芯片待调整的目标频率值。在一个或多个实施例中，该目标频率值可以根据前述的公式(3)来计算。
最后，根据在步骤906或908获得的芯片本次调整操作的时钟频率后，在步骤907处，方法900依据该时钟频率执行相应的调频动作。基于上文结合图1-图9的描述，本领域技术人员可以理解图1-图9所示出的一种用于芯片频率调节的方法也可以各种形式实现于一种或多种设备中。这些实现形式可以包括但不限于以下的四种形式：1)芯片硬件自身具有或支持一定的动态调频能力，并且通过硬件模拟电路和/或数字电路构建本披露的PID模块来实现对其的调频操作；2)通过上层驱动或者操作系统内核对本地采集的功耗或与功耗相关的芯片占用率等数据进行类似于本披露的PID模块的处理，以便对芯片进行动态调频控制；3)通过设置于芯片外部的设备对芯片进行调频操作；4)通过设置于芯片内部的设备对芯片进行调频操作。关于此处的第3项和第4项实现形式，下文将结合图10和图11来具体阐述。
图10示出利用本披露实施例的设备对芯片进行调频的示意框图，而图11示出利用本披露实施例的设备对芯片进行调频的另一示意框图。从该两附图中可以看出，本披露的设备可置于芯片的外部或者内部以用于对至少一个芯片进行调频操作。
如图10所示，设备1001在芯片1004外部对芯片进行调频操作。该设备1001包括获取模块1003，其配置用于获取至少一个芯片操作时的实时功耗采样值和N-1个预定执行周期内的平均功耗值，其中N是大于或等于2的正整数。在一个实施例中，该获取模块可以是传感器。该设备1001还可以包括PID控制模块1002，例如可以是单级的或N个逐级串联的PID控制模块，以对芯片1004执行动态调频操作。在一个实施例中，该PID控制模块1002可以实现在MCU(“Microcontroller Unit微控制单元”)上。由此，该设备1001可以是MCU。
尽管在图10中未示出，但本领域技术人员基于前面结合图4-图9的描述，也可以想到为了实现快速降频的方案，上述设备还可以包括：确定模块，其配置用于确定所述实时功耗采样值是否大于或等于快速降频阈值；以及快速降频模块，其配置用于当所述实时功耗采样值大于或等于所述快速降频阈值 时，执行对所述至少一个芯片的快速降频操作。
对于图10所示的通过外部设备进行调频控制的方式来说，接受动态调频的芯片可以配置成具有修改频率的接口并且前述外部设备仅通过修改或升级其固件即可实现对芯片的动态调频，从而操作方便并且灵活。另外，本地数据采集后直接在本地(例如板卡处)管理，因此数据处理速度要比由上层驱动或者操作系统内核处理快。
如图11所示，本披露的用于调频的设备还可以置于芯片内部以实现对该芯片的调频操作，即芯片1102内部包含设备1101，该设备用来对芯片执行调频操作。在一些应用场景中，该设备1101可以具体化为驻留于芯片内部的软件代码(例如各种情形的指令)。鉴于图2-图9中关于对芯片单级、多级以及快速降频的描述也同样适用于图11的设备，因此在此将不再赘述。
除了图10和图11所示出的示例性设备框图，本披露的方案也可以实现于一种集成电路芯片中，该芯片包括用于对芯片进行调频的设备1101。在一些场景中，前述设备1101可以是芯片的内核。当所述集成电路芯片工作时，所述内核可配置成执行上述用于对芯片进行调频的方法。该集成电路芯片例如可以采用CPLD(“Complex Programmable Logic Device复杂可编程逻辑器件”)、FPGA(“Field Programmable Gate Array现场可编程门阵列”)、ASIC(Application Specific Integrated Circuit用于供专门应用的集成电路)、MPU(Microprocessor Unit微处理器)、CPU(Central Processing Unit中央处理器)等硬件来实现。
另外，本领域技术人员也可以想到本披露的方案也可以实现于一种设备或板卡中。具体地，该设备包括至少一个处理器；至少一个存储器，用于存储程序指令，当该程序指令由所述至少一个处理器执行时，使得所述设备执行上述的用于对芯片进行调频的方法。进一步，该板卡包括上述的用于对芯片进行调频的设备。在另一个方面中，当本披露的调频操作由程序指令来实现时，本披露也就同样公开了一种计算机可读存储介质，其存储有用于对芯片进行调频的程序指令，当该程序指令由处理器运行时，执行上述的调频操作。
图12是示出根据本披露实施例的一种组合处理装置1200的结构框图。 如图12所示，该组合处理装置1200包括具有前述架构的调频装置1201，其可以配置用于执行前述结合附图所描述的调频方法。另外，该组合处理装置还包括通用互联接口1202和其他处理装置1203。根据本披露的调频装置1201可以通过通用互联接口1202与其他处理装置1203进行交互，共同完成用户指定的相关操作。
根据本披露的方案，该其他处理装置可以包括中央处理器(“CPU”)、图形处理器(“GPU”)、神经网络处理器等通用和/或专用处理器中的一种或多种类型的处理器，其数目可以不做限制而是根据实际需要来确定。在一个或多个实施例中，该其他处理装置可以作为本披露的调频装置与外部数据和控制的接口，执行包括但不限于数据搬运，完成对调频装置的开启、停止等的基本控制；其他处理装置也可以和调频装置协作共同完成运算任务。
根据本披露的方案，该通用互联接口可以用于在调频装置与其他处理装置间传输数据和控制指令。例如，该调频装置可以经由所述通用互联接口从其他处理装置中获取所需的输入数据，写入该调频装置片上的存储装置(或称存储器)。进一步，该调频装置可以经由所述通用互联接口从其他处理装置中获取控制指令，写入调频装置片上的控制缓存。替代地或可选地，通用互联接口也可以读取调频装置的存储模块中的数据并传输给其他处理装置。
可选的，该组合处理装置还可以包括存储装置1204，其可以分别与所述调频装置和所述其他处理装置连接。在一个或多个实施例中，存储装置可以用于保存所述调频装置和所述其他处理装置的数据，尤其是那些在本调频装置或其他处理装置的内部或片上存储装置中无法全部保存的数据。
根据应用场景的不同，本披露的组合处理装置可以作为手机、机器人、无人机、视频监控设备等设备的SOC片上系统，有效降低控制部分的核心面积，提高处理速度，调节芯片的频率以降低整体功耗。在此情况下，该组合处理装置的通用互联接口与设备的某些部件相连接。其中某些部件例如可以是摄像头、显示器、鼠标、键盘、网卡或Wifi接口。
在一些实施例里，本披露还公开了一种芯片，其包括了上述调频装置或组合处理装置。在另一些实施例里，本披露还公开了一种芯片封装结构，其包括了上述芯片。
在一些实施例里，本披露还公开了板卡，其包括了上述芯片封装结构。参阅图13，其提供了前述的示例性板卡，上述板卡除了包括上述芯片1301以外，还可以包括其他的配套部件，该配套部件包括但不限于：存储器件1302、接口装置1303和控制器件1304。
所述存储器件与所述芯片封装结构内的芯片通过总线连接，用于存储数据。所述存储器件可以包括多组存储单元1305及1306。每一组所述存储单元与所述芯片通过总线连接。可以理解，每一组所述存储单元可以是DDR SDRAM(“Double Data Rate SDRAM，双倍速率同步动态随机存储器”，简称为DDR)。
上述DDR不需要提高时钟频率就能加倍提高SDRAM的传输速度。DDR允许在时钟脉冲的上升沿和下降沿传输数据。DDR的传输速度是标准SDRAM的两倍。在一个实施例中，所述存储器件可以包括4组所述存储单元。每一组所述存储单元可以包括多个DDR4颗粒(芯片)。在一个实施例中，所述芯片内部可以包括4个72位DDR4控制器，上述72位DDR4控制器中64bit用于传输数据，8bit用于ECC校验。可以理解，当每一组所述存储单元中采用DDR4-3200颗粒时，单个所述存储单元传输数据的理论带宽可达到25600MB/s。
在一个实施例中，每一组所述存储单元包括多个并联设置的双倍速率同步动态随机存储器。DDR在一个时钟周期内可以传输两次数据。在所述芯片中设置控制DDR的控制器，用于对每个所述存储单元的数据传输与数据存储的控制。
所述接口装置与所述芯片封装结构内的芯片电连接。所述接口装置用于实现所述芯片与外部设备1307(例如服务器或计算机)之间的数据传输。例如在一个实施例中，所述接口装置可以为标准PCIE接口。比如，待处理的数据由服务器通过标准PCIE接口传递至所述芯片，实现数据转移。优选地，当采用PCIE3.0X16接口传输时，理论带宽可达到16000MB/s。在另一个实施例中，所述接口装置还可以是其他的接口，本披露并不限制上述其他的接口的具体表现形式，所述接口单元能够实现转接功能即可。另外，所述芯片的计算结果仍由所述接口装置传送回外部设备(例如服务器)。
所述控制器件与所述芯片电连接。所述控制器件用于对所述芯片的状态进行监控。具体地，所述芯片与所述控制器件可以通过SPI接口电连接。所述控制器件可以包括CPU或者单片机。在一个或多个实施例中，所述芯片可以包括多个处理芯片、多个处理核或多个处理电路，可以带动多个负载。因此，所述芯片可以处于多负载和轻负载等不同的工作状态。通过所述控制装置可以实现对所述芯片中多个处理芯片、多个处理核和/或多个处理电路的工作状态的调控。
在一些实施例里，本披露还公开了一种电子设备或装置，其包括了上述板卡。根据不同的应用场景，电子设备或装置可以包括数据处理装置、机器人、电脑、打印机、扫描仪、平板电脑、智能终端、手机、行车记录仪、导航仪、传感器、摄像头、服务器、云端服务器、相机、摄像机、投影仪、手表、耳机、移动存储、可穿戴设备、交通工具、家用电器、和/或医疗设备。所述交通工具包括飞机、轮船和/或车辆；所述家用电器包括电视、空调、微波炉、冰箱、电饭煲、加湿器、洗衣机、电灯、燃气灶、油烟机；所述医疗设备包括核磁共振仪、B超仪和/或心电图仪。
需要说明的是，对于前述的各方法实施例，为了简单描述，故将其都表述为一系列的动作组合，但是本领域技术人员应该知悉，本披露并不受所描述的动作顺序的限制，因为依据本披露，某些步骤可以采用其他顺序或者同时进行。其次，本领域技术人员也应该知悉，说明书中所描述的实施例均属于可选实施例，所涉及的动作和模块并不一定是本披露所必须的。
在本披露所提供的几个实施例中，应该理解到，所披露的装置，可通过其它的方式实现。例如，以上所描述的装置实施例仅仅是示意性的，例如所述单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个单元或组件可以结合或者可以集成到另一个系统，或一些特征可以忽略，或不执行。另一点，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口、装置或单元的间接耦合或通信连接，也可以是通过电性、光学、声学、磁性或其它的形式。
所述作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是或者也可以不是物理单元，即可以位于一个地方， 或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部单元来实现本实施例的方案。另外，在本披露各个实施例中的各功能单元可以集成在一个处理单元中，也可以是各个单元单独物理存在，也可以两个或两个以上单元集成在一个单元中。上述集成的单元既可以采用硬件的形式实现，也可以采用软件程序模块的形式实现。
所述集成的单元如果以软件程序模块的形式实现并作为独立的产品销售或使用时，可以存储在一个计算机可读取存储器中。基于这样的理解，当本披露的技术方案可以以软件产品的形式体现出来，该计算机软件产品存储在一个存储器中，包括若干指令用以使得一台计算机设备(可为个人计算机、服务器或者网络设备等)执行本披露各个实施例所述方法的全部或部分步骤。而前述的存储器包括：U盘、只读存储器(“ROM，Read-Only Memory”)、随机存取存储器(“RAM，Random Access Memory”)、移动硬盘、磁碟或者光盘等各种可以存储程序代码的介质。
在本披露的上述实施例中，对各个实施例的描述都各有侧重，某个实施例中没有详述的部分，可以参见其他实施例的相关描述。上述实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例中的各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。
依据以下条款可更好地理解前述内容：
202010225223.3条款A1、一种用于对芯片进行调频的方法，包括：
获取至少一个芯片操作时的实时功耗采样值；
根据所述实时功耗采样值和功耗目标值，确定二者之间的误差值；以及
基于所述误差值，利用PID控制模块来确定用于调整所述至少一个芯片的时钟频率的调整量。
条款A2、根据条款A1所述的方法，其中所述PID控制模块包括比例控制单元，其中利用所述PID控制模块来确定所述调整量包括：
基于所述误差值，利用所述比例控制单元来获得比例项；以及
基于所述比例项来确定用于调整所述时钟频率的第一调整量。
条款A3、根据条款A2所述的方法，其中获得所述比例项包括根据所述 误差值和选择的比例系数来获得所述比例项。
条款A4、根据条款A2或A3所述的方法，其中所述第一调整量是相对于前次调整所述时钟频率的第一增量。
条款A5、根据条款A1所述的方法，其中所述PID控制模块包括比例控制单元以及积分控制单元和微分控制单元二者中的至少一项，其中利用所述PID控制模块来确定所述调整量包括：
基于所述误差值，利用所述比例控制单元来获得比例项；以及
基于所述比例项和利用所述积分控制单元所获得的积分项来确定用于调整所述至少一个芯片的时钟频率的第二调整量；或者
基于所述比例项和利用所述微分控制单元所获得的微分项来确定用于调整所述至少一个芯片的时钟频率的第三调整量；或者
基于所述比例项、积分项和微分项来确定用于调整所述至少一个芯片的时钟频率的第四调整量。
条款A6、根据条款A5所述的方法，其中所述第二调整量、第三调整量、第四调整量中的每个是相对于前次调整所述时钟频率的增量。
条款A7、根据条款A5所述的方法，其中获取所述实时功耗采样值包括周期性地获取多个所述实时功耗采样值，其中确定所述积分项包括在预定时间段内针对每个所述实时功耗采样值执行：
确定每个所述实时功耗采样值与所述功耗目标值之间的误差值；
对每次确定的所述误差值执行累加操作以获得累加和；以及
基于所述累加和，利用所述积分控制单元来获得积分项。
条款A8、根据条款A7所述的方法，其中获得所述积分项包括根据所述累加和以及选择的积分系数来获得所述积分项。
条款A9、根据条款A8所述的方法，进一步包括将所述积分项限制在选择的范围内，以便清除静差作用和避免超调操作。
条款A10、根据条款A7所述的方法，其中当所述预定时间段到达时，所述方法进一步包括：
对所述累加和执行清零操作，以便进行下一所述预定时间段内的所述累加操作。
条款A11、根据条款A7所述的方法，其中当所述预定时间段内的预定采样周期个数到达时，所述方法进一步包括：
对所述累加和中所述预定采样周期个数中的最早一个采样周期的所述误差值进行清除，以便对最近一个采样周期的所述误差值执行所述累加操作。
条款A12、根据条款A5所述的方法，其中利用所述PID控制模块中的所述微分控制单元来确定所述调整量包括：
对本次确定的所述误差值与前一次确定的所述误差值执行减法操作以获得微分差值；以及
基于所述微分差值，利用所述微分控制单元来获得微分项。
条款A13、根据条款A12所述的方法，其中获得所述微分项包括根据所述微分差值以及选择的微分系数来获得所述微分项。
条款A14、一种用于对芯片进行调频的方法，包括：
获取至少一个芯片操作时的实时功耗采样值；
确定所述实时功耗采样值是否大于或等于快速降频阈值；
当所述实时功耗采样值大于或等于所述快速降频阈值时，执行对所述至少一个芯片的快速降频操作；
当所述实时功耗采样值小于所述快速降频阈值时，执行：
根据所述实时功耗采样值和功耗目标值，确定二者之间的误差值；以及
基于所述误差值，利用PID控制模块来确定用于调整所述至少一个芯片的时钟频率的调整量。
条款A15、一种用于对芯片进行调频的设备，包括：
获取模块，其配置用于获取至少一个芯片操作时的实时功耗采样值；
PID控制模块，其配置用于：
根据所述实时功耗采样值和功耗目标值，确定二者之间的误差值；以及
基于所述误差值，确定用于调整所述至少一个芯片的时钟频率的调整量。
条款A16、一种用于对芯片进行调频的设备，包括：
获取模块，其配置用于获取至少一个芯片操作时的实时功耗采样值；
确定模块，其配置用于确定所述实时功耗采样值是否大于或等于快速降频阈值；
快速降频模块，其配置用于当所述实时功耗采样值大于或等于所述快速降频阈值时，执行对所述至少一个芯片的快速降频操作；以及
PID控制模块，其配置用于当所述实时功耗采样值小于所述快速降频阈值时，执行：
根据所述实时功耗采样值和功耗目标值，确定二者之间的误差值；以及
基于所述误差值来确定用于调整所述至少一个芯片的时钟频率的调整量。
条款A17、一种用于对芯片进行调频的设备，包括：
至少一个处理器；
至少一个存储器，用于存储程序指令，当该程序指令由所述至少一个处理器执行时，使得所述设备执行根据权利要求1-14的任意一项所述的方法。
条款A18、一种用于对芯片进行调频的板卡，包括根据权利要求15-17的任意一项所述的设备。
条款A19、一种集成电路芯片，包括用于对芯片进行调频的内核，当所述集成电路芯片工作时，所述内核可配置成执行根据权利要求1-14的任意一项所述的方法。202010225223.3
202010225213.X
条款B1、一种用于对芯片进行调频的方法，包括：
获取至少一个芯片操作时的实时功耗采样值和N-1个预定执行周期内的平均功耗值，其中N是大于或等于2的正整数；以及
基于所述实时功耗采样值、所述平均功耗值和平均功耗参考值，利用N个逐级串联的PID控制模块来确定用于调整所述至少一个芯片的时钟频率的调整量。
条款B2、根据条款B1所述的方法，其中当N等于2时，利用串联的初级PID控制模块和末级PID控制模块来确定所述调整量，并将该调整量从所述末级PID控制模块输出，所述方法进一步包括：
获取初级PID控制模块的预定执行周期T1内的第一平均功耗值；
将所述第一平均功耗值和与初级PID控制模块关联的平均功耗参考值输入至所述初级PID控制模块；
基于所述初级PID控制模块的输出值和前次调整操作的实时功耗目标值来获得本次调整操作的实时功耗目标值，并且将其输入至所述末级PID控制模块；以及
基于所述实时功耗采样值和本次调整操作的实时功耗目标值，利用所述末级PID控制模块输出所述调整量，
其中所述初级PID控制模块的预定执行周期T1大于所述实时功耗采样值的采样周期TN。
条款B3、根据条款B1或条款B2所述的方法，其中当N等于3时，利用串联的初级PID控制模块、第二级PID控制模块和末级PID控制模块来确定所述调整量，并且将该调整量从所述末级PID控制模块输出，所述方法进一步包括：
获取初级PID控制模块的预定执行周期T1内的第一平均功耗值；
将所述第一平均功耗值和与初级PID控制模块关联的平均功耗参考值输入至所述初级PID控制模块，以令其输出与第二级PID控制模块关联的第二平均功耗目标值的调整值；
获取第二级PID控制模块的预定执行周期T2内的第二平均功耗值，并将其输入至所述第二级PID控制模块；
利用调整值对第二平均功耗目标值进行调整来获得调整后的第二平均功耗目标值，并且将其输入至所述第二级PID控制模块；
基于所述第二级PID控制模块的输出值和前次调整操作的实时功耗目标值来获得本次调整操作的实时功耗目标值，并且将其输入至所述末级PID控制模块；以及
基于所述实时功耗采样值和本次调整操作的实时功耗目标值，利用所述末级PID控制模块输出所述调整量，
其中所述实时功耗采样值的采样周期为TN，并且所述第二级PID控制模块的预定执行周期T2满足关系T1>T2>TN。
条款B4、根据条款B1-B3任一项所述的方法，其中当N大于或等于4时，利用串联的初级PID控制模块、第二级PID控制模块，……，第N-1级PID控制模块和末级PID控制模块来确定所述调整量，并且将该调整量从 所述末级PID控制模块输出，所述方法进一步包括：
获取所述初级PID控制模块至第N-1级PID控制模块在其各自预定执行周期T1，……TN-1内的第一至第N-1平均功耗值，并将其分别输入到所述初级PID控制模块至第N-1级PID控制模块中；
将所述第一平均功耗值和与初级PID控制模块关联的平均功耗参考值输入至所述初级PID控制模块；
令所述初级PID控制模块至第N-2级PID控制模块的输出向各自的下一级PID控制模块输入，其中所述初级PID控制模块至第N-2级PID控制模块的每个输出是对与相应后一级PID控制模块关联的平均功耗目标值的调整值；
利用每个调整值对相应后一级的平均功耗目标值进行调整来分别获得调整后的平均功耗目标值，并且将其分别输入至相应的第二级PID控制模块至第N-1级PID控制模块；
基于所述第N-1级PID控制模块的输出值和前次调整操作的实时功耗目标值来获得本次调整操作的实时功耗目标值，并且将其输入至所述末级PID控制模块；以及
基于所述实时功耗采样值和本次调整操作的实时功耗目标值，利用所述末级PID控制模块输出所述调整量，
其中所述初级PID控制模块至所述第N-1级PID控制模块的各自预定执行周期T1，……TN-1和实时功耗采样值的采样周期TN满足关系T1>T2……TN-1>TN。
条款B5、根据条款B1-B4任一项所述的方法，其中所述调整量是相对于前次调整所述时钟频率的增量。
条款B6、一种用于对芯片进行调频的方法，包括：
获取至少一个芯片操作时的实时功耗采样值；
确定所述实时功耗采样值是否大于或等于快速降频阈值；
当所述实时功耗采样值大于或等于所述快速降频阈值时，执行对所述至少一个芯片的快速降频操作；
当所述实时功耗采样值小于所述快速降频阈值时，执行以下操作：
获取N-1个预定执行周期内的平均功耗值，其中N是大于或等于2的正整数；以及
基于所述实时功耗采样值、所述平均功耗值和平均功耗参考值，利用N个逐级串联的PID控制模块来确定用于调整所述至少一个芯片的时钟频率的调整量。
条款B7、一种用于对芯片进行调频的设备，包括：
获取模块，其配置用于获取至少一个芯片操作时的实时功耗采样值和N-1个预定执行周期内的平均功耗值，其中N是大于或等于2的正整数；以及
N个逐级串联的PID控制模块，其配置用于基于所述实时功耗采样值、所述平均功耗值和平均功耗参考值，确定用于调整所述至少一个芯片的时钟频率的调整量。
条款B8、一种用于对芯片进行调频的设备，包括：
获取模块，其配置用于获取至少一个芯片操作时的实时功耗采样值；
确定模块，其配置用于确定所述实时功耗采样值是否大于或等于快速降频阈值；
快速降频模块，其配置用于当所述实时功耗采样值大于或等于所述快速降频阈值时，执行对所述至少一个芯片的快速降频操作；
N个逐级串联的PID控制模块，其配置用于当所述实时功耗采样值小于所述快速降频阈值时，执行以下操作：
获取N-1个预定执行周期内的平均功耗值，其中N是大于或等于2的正整数；以及
基于所述实时功耗采样值、所述平均功耗值和平均功耗参考值，确定用于调整所述至少一个芯片的时钟频率的调整量。
条款B9、一种用于对芯片进行调频的设备，包括：
至少一个处理器；
至少一个存储器，用于存储程序指令，当该程序指令由所述至少一个处理器执行时，使得所述设备执行根据条款B1-B6的任意一项所述的方法。
条款B10、一种用于对芯片进行调频的板卡，包括根据条款B7-B9的任 意一项所述的设备。
条款B11、一种集成电路芯片，包括用于对芯片进行调频的内核，当所述集成电路芯片工作时，所述内核可配置成执行根据条款B1-B6的任意一项所述的方法。
条款B12、一种计算机可读存储介质，其存储有用于对芯片进行调频的程序指令，当该程序指令由处理器运行时，执行根据条款B1-B6的任意一项所述的方法。
应当理解，本披露的权利要求、说明书及附图中的术语“第一”、“第二”、“第三”和“第四”等是用于区别不同对象，而不是用于描述特定顺序。本披露的说明书和权利要求书中使用的术语“包括”和“包含”指示所描述特征、整体、步骤、操作、元素和/或组件的存在，但并不排除一个或多个其它特征、整体、步骤、操作、元素、组件和/或其集合的存在或添加。
还应当理解，在此本披露说明书中所使用的术语仅仅是出于描述特定实施例的目的，而并不意在限定本披露。如在本披露说明书和权利要求书中所使用的那样，除非上下文清楚地指明其它情况，否则单数形式的“一”、“一个”及“该”意在包括复数形式。还应当进一步理解，在本披露说明书和权利要求书中使用的术语“和/或”是指相关联列出的项中的一个或多个的任何组合以及所有可能组合，并且包括这些组合。
如在本说明书和权利要求书中所使用的那样，术语“如果”可以依据上下文被解释为“当...时”或“一旦”或“响应于确定”或“响应于检测到”。类似地，短语“如果确定”或“如果经过判断[所描述条件或事件]”可以依据上下文被解释为意指“一旦确定”或“响应于确定”或“一旦检测到[所描述条件或事件]”或“响应于检测到[所描述条件或事件]”。
以上对本披露实施例进行了详细介绍，本文中应用了具体个例对本披露的原理及实施方式进行了阐述，以上实施例的说明仅用于帮助理解本披露的方法及其核心思想。同时，本领域技术人员依据本披露的思想，基于本披露的具体实施方式及应用范围上做出的改变或变形之处，都属于本披露保护的范围。综上所述，本说明书内容不应理解为对本披露的限制。

Claims (19)

  1. 一种用于对芯片进行调频的方法，包括：
    获取至少一个芯片操作时的实时功耗采样值；
    根据所述实时功耗采样值和功耗目标值，确定二者之间的误差值；以及
    基于所述误差值，利用PID控制模块来确定用于调整所述至少一个芯片的时钟频率的调整量。
  2. 根据权利要求1所述的方法，其中所述PID控制模块包括比例控制单元，其中利用所述PID控制模块来确定所述调整量包括：
    基于所述误差值，利用所述比例控制单元来获得比例项；以及
    基于所述比例项来确定用于调整所述时钟频率的第一调整量。
  3. 根据权利要求2所述的方法，其中获得所述比例项包括根据所述误差值和选择的比例系数来获得所述比例项。
  4. 根据权利要求2或3所述的方法，其中所述第一调整量是相对于前次调整所述时钟频率的第一增量。
  5. 根据权利要求1所述的方法，其中所述PID控制模块包括比例控制单元以及积分控制单元和微分控制单元二者中的至少一项，其中利用所述PID控制模块来确定所述调整量包括：
    基于所述误差值，利用所述比例控制单元来获得比例项；以及
    基于所述比例项和利用所述积分控制单元所获得的积分项来确定用于调整所述至少一个芯片的时钟频率的第二调整量；或者
    基于所述比例项和利用所述微分控制单元所获得的微分项来确定用于调整所述至少一个芯片的时钟频率的第三调整量；或者
    基于所述比例项、积分项和微分项来确定用于调整所述至少一个芯片的时钟频率的第四调整量。
  6. 根据权利要求5所述的方法，其中所述第二调整量、第三调整量、第四调整量中的每个是相对于前次调整所述时钟频率的增量。
  7. 根据权利要求5所述的方法，其中获取所述实时功耗采样值包括周期性地获取多个所述实时功耗采样值，并且其中确定所述积分项包括在预定时间段内针对每个所述实时功耗采样值执行：
    确定每个所述实时功耗采样值与所述功耗目标值之间的误差值；
    对每次确定的所述误差值执行累加操作以获得累加和；以及
    基于所述累加和，利用所述积分控制单元来获得积分项。
  8. 根据权利要求7所述的方法，其中获得所述积分项包括根据所述累加和以及选择的积分系数来获得所述积分项。
  9. 根据权利要求8所述的方法，进一步包括将所述积分项限制在选择的范围内，以便清除静差作用和避免超调操作。
  10. 根据权利要求7所述的方法，其中当所述预定时间段到达时，所述方法进一步包括：
    对所述累加和执行清零操作，以便进行下一所述预定时间段内的所述累加操作。
  11. 根据权利要求7所述的方法，其中当所述预定时间段内的预定采样周期个数到达时，所述方法进一步包括：
    对所述累加和中所述预定采样周期个数中的最早一个采样周期的所述误差值进行清除，以便对最近一个采样周期的所述误差值执行所述累加操作。
  12. 根据权利要求5所述的方法，其中利用所述PID控制模块中的所述微分控制单元来确定所述调整量包括：
    对本次确定的所述误差值与前一次确定的所述误差值执行减法操作以获得微分差值；以及
    基于所述微分差值，利用所述微分控制单元来获得微分项。
  13. 根据权利要求12所述的方法，其中获得所述微分项包括根据所述微分差值以及选择的微分系数来获得所述微分项。
  14. 一种用于对芯片进行调频的方法，包括：
    获取至少一个芯片操作时的实时功耗采样值；
    确定所述实时功耗采样值是否大于或等于快速降频阈值；
    当所述实时功耗采样值大于或等于所述快速降频阈值时，执行对所述至少一个芯片的快速降频操作；
    当所述实时功耗采样值小于所述快速降频阈值时，执行：
    根据所述实时功耗采样值和功耗目标值，确定二者之间的误差值；以及
    基于所述误差值，利用PID控制模块来确定用于调整所述至少一个芯片的时钟频率的调整量。
  15. 一种用于对芯片进行调频的设备，包括：
    获取模块，其配置用于获取至少一个芯片操作时的实时功耗采样值；
    PID控制模块，其配置用于：
    根据所述实时功耗采样值和功耗目标值，确定二者之间的误差值；以及
    基于所述误差值，确定用于调整所述至少一个芯片的时钟频率的调整量。
  16. 一种用于对芯片进行调频的设备，包括：
    获取模块，其配置用于获取至少一个芯片操作时的实时功耗采样值；
    确定模块，其配置用于确定所述实时功耗采样值是否大于或等于快速降频阈值；
    快速降频模块，其配置用于当所述实时功耗采样值大于或等于所述快速降频阈值时，执行对所述至少一个芯片的快速降频操作；以及
    PID控制模块，其配置用于当所述实时功耗采样值小于所述快速降频阈值时，执行：
    根据所述实时功耗采样值和功耗目标值，确定二者之间的误差值；以及
    基于所述误差值来确定用于调整所述至少一个芯片的时钟频率的调整量。
  17. 一种用于对芯片进行调频的设备，包括：
    至少一个处理器；
    至少一个存储器，用于存储程序指令，当该程序指令由所述至少一个处理器执行时，使得所述设备执行根据权利要求1-14的任意一项所述的方法。
  18. 一种用于对芯片进行调频的板卡，包括根据权利要求15-17的任意一项所述的设备。
  19. 一种集成电路芯片，包括用于对芯片进行调频的内核，当所述集成电路芯片工作时，所述内核可配置成执行根据权利要求1-14的任意一项所述的方法。
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