JP2015075609A - Liquid crystal display device and control method of liquid crystal display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the capacity of charging means for charging power for an operation to turn off the power of a liquid crystal display device.SOLUTION: In turning off the power of a liquid crystal display device, the order to select gate bus lines to be writing objects is set such that the order becomes different from that during the display of an image according to image data and gate bus lines having a larger value of resistance of a power supply path from a power supply source are selected in descending order, and a predetermined voltage for processing to turn off the power is applied to source bath lines.

Description

  The present invention relates to a technique for suppressing a voltage from being continuously applied to a pixel when a power source is turned off in a liquid crystal display device.

  Conventionally, in a liquid crystal display device, it is known that if an electric field of the same polarity is continuously applied to a pixel, the liquid crystal molecules are polarized, causing problems such as changes in pixel characteristics and image burn-in. In addition, when the power of the liquid crystal display device is turned off while displaying an image, the applied voltage immediately before the power is turned off remains applied to each pixel, and the same image is continuously drawn. Also in this case, it is known that a seizure phenomenon occurs.

  For this reason, in the conventional liquid crystal display device, when the power is turned off, a predetermined power-off operation for discharging the charge applied to each pixel of the liquid crystal display panel is performed.

  For example, in Patent Document 1, an electrolytic capacitor is provided in a power supply circuit, and when the power of the liquid crystal display device is turned off, a predetermined amount is applied to the entire screen of the liquid crystal display panel using charges stored in the electrolytic capacitor. A technique for performing a process of drawing a fixed pattern is described.

JP 2000-131671 (May 12, 2000)

  However, in the technique of Patent Document 1, it is necessary to provide a large-capacity electrolytic capacitor in order to charge all the pixels with sufficient power for performing a fixed pattern drawing process during the power-off operation. The manufacturing cost will increase.

  The present invention has been made in view of the above problems, and an object of the present invention is to reduce the capacity of charging means for charging power for power-off operation of a liquid crystal display device.

  A liquid crystal display device according to one aspect of the present invention periodically switches a gate bus line to be written and a source connected to each pixel connected to the gate bus line selected as the write target A liquid crystal display device including a control unit that performs a writing process of applying a voltage according to image data to each picture element by controlling a voltage applied to a bus line according to image data, wherein the control unit includes: When the power of the liquid crystal display device is turned off, the selection order of the gate bus lines to be written is different from the order of displaying the image according to the image data, and the power supply path from the power supply source is selected. It is set so that the resistance bus value is selected in order from the gate bus line in descending order, and power off processing is performed to apply a predetermined voltage for power off processing to each source bus line. We are a symptom.

  According to the above configuration, when the charging voltage of the charging means at the time of starting the power-off operation is relatively high, writing is performed on the gate bus line having a large resistance value of the power supply path (gate bus line having a large voltage drop amount), and the power source Writing to a gate bus line having a small resistance value in the power supply path (a gate bus line having a relatively small amount of voltage drop) when the charging voltage of the charging unit has relatively decreased with the passage of time since the start of the off operation. Can do. As a result, since the power charged in the charging means can be efficiently used, the power consumption during the power-off process can be reduced, and the capacity of the charging means can be reduced to reduce the cost. Can do.

It is explanatory drawing which shows the structure of the liquid crystal display device concerning Embodiment 1 of this invention. FIG. 2 is an explanatory diagram illustrating a configuration of a voltage drop detection circuit provided in the liquid crystal display device illustrated in FIG. 1. It is explanatory drawing which shows the structure of the liquid crystal panel with which the liquid crystal display device shown in FIG. 1 is equipped. It is explanatory drawing which shows the structure of the TFT substrate with which the liquid crystal panel shown in FIG. 3 is equipped. It is explanatory drawing which shows the structure of the picture element with which the liquid crystal panel shown in FIG. 3 is equipped. FIG. 6 is an equivalent circuit diagram of the picture element shown in FIG. 5. FIG. 2 is an explanatory diagram showing input / output signals of a gate driver provided in the liquid crystal display device shown in FIG. 1. FIG. 2 is an explanatory diagram illustrating a configuration of a gate driver provided in the liquid crystal display device illustrated in FIG. 1 and a power supply path to the gate driver. 6 is a graph showing characteristics of a TFT included in the picture element shown in FIG. 5 and a TFT according to a comparative example. It is explanatory drawing which showed schematically the circuit structure for switching the selection order of the gate bus line of the writing object in the liquid crystal display device shown in FIG. 1, (a) is the flow of the control signal at the normal time, (B) shows the flow of the control signal during the power-off process. 2A and 2B are explanatory diagrams illustrating waveforms of input signals of a gate driver 3 in the liquid crystal display device illustrated in FIG. 1, in which FIG. 1A illustrates a signal waveform at a normal time, and FIG. It is explanatory drawing which shows the structure of the liquid crystal display device concerning one Embodiment 2 of this invention. FIG. 13 is an explanatory diagram showing a configuration of a gate driver provided in the liquid crystal display device shown in FIG. 12 and a power supply path to the gate driver. It is explanatory drawing which shows the structure of the liquid crystal display device concerning one Embodiment 3 of this invention.

Embodiment 1
An embodiment of the present invention will be described.

(1-1. Configuration of the liquid crystal display device 100)
FIG. 1 is an explanatory diagram showing a schematic configuration of a liquid crystal display device 100 according to the present embodiment. As shown in the figure, the liquid crystal display device 100 includes a power supply circuit 1, a control circuit (control unit) 2, a gate driver 3, a source driver 4, and a liquid crystal panel 5.

  The power supply circuit 1 receives power supplied from outside the power supply circuit 1 (for example, commercial power supply, private power generation power supply, charging device, etc.) and supplies power to each block (each unit) of the liquid crystal display device 100. A voltage drop detection circuit 11, a main power supply circuit 12, and an auxiliary power supply circuit 13.

  The voltage drop detection circuit (voltage drop detection unit) 11 detects the power-off of the liquid crystal display device 100 (power-off by user operation, power-off due to power failure, disconnection, etc.) by monitoring the input voltage from the outside. Then, a control signal corresponding to the detection result is output to the main power supply circuit 12, the auxiliary power supply circuit 13, and the control circuit 2.

  FIG. 2 is an explanatory diagram illustrating a configuration example of the voltage drop detection circuit 11. As shown in this figure, the voltage drop detection circuit 11 includes a detection IC 11a and resistors R1 to R3.

  One end of the resistor R1 is connected to the input power supply, and the other end is connected to the input side of the detection IC 11a and one end of the resistor R2. The other end side of the resistor R2 is grounded. In the present embodiment, the voltage of the input power supply during normal operation is set to 12V.

  One end of the resistor R3 is connected to a pull-up power supply circuit (5 V in this embodiment), and the other end is connected to the output side of the detection IC 11a. Note that the pull-up power supply circuit is provided in the main power supply circuit 12, converts the input power supply voltage into a voltage for the pull-up power supply (5 V in this embodiment), and outputs it to the voltage drop detection circuit 11.

  Thus, when the input voltage to the detection IC 11a is equal to or higher than a predetermined threshold, the output (control signal) of the detection IC 11a becomes high level (5V) by the pull-up resistor. Further, when the input voltage to the detection IC 11a falls below the threshold, the output (control signal) of the detection IC 11a becomes a low level (0 V).

  The main power supply circuit 12 distributes power supplied from the outside to each block of the liquid crystal display device 100 during normal display (during the period when the power supply of the liquid crystal display device 100 is turned on). Specifically, the main power supply circuit 12 supplies the logic voltage Vlogic to the image data input unit 21, the image processing unit 22, the synchronization processing unit 23, the gate control signal generation unit 24, and the source control signal generation unit 25, and the gate A logic voltage VL, an analog high level voltage VGH, and a low level voltage VGL are supplied to the driver 3, an opposing reference potential VCOM of the liquid crystal panel 5 and a CS reference potential (reference potential of the liquid crystal auxiliary capacitor) VCS are supplied, and a source driver 4, the logic voltage VCC / LRVDD, the analog voltage VLS, the gradation reference voltages VL0 to VL1023, and VH0 to VH1023 are supplied, and the pull-up power supply voltage described above is supplied to the voltage drop detection circuit 11.

  The auxiliary power supply circuit 13 includes a charging means (not shown) such as an electrolytic capacitor, for example, and charges the charging means with electric power supplied from the outside, and also supplies the charging means when the liquid crystal display device 100 is powered off. The charged power is supplied to each block that performs a power-off process in the liquid crystal display device 100. The power-off process is a process for releasing charges accumulated in each picture element of the liquid crystal panel 5 when the liquid crystal display device 100 is powered off. Details of the power-off process will be described later.

  The power for charging the charging means provided in the auxiliary power supply circuit 13 may be directly input from the outside to the auxiliary power supply circuit 13 or may be input from the main power supply circuit 12.

  The control circuit 2 generates a control signal for causing the liquid crystal panel 5 to display an image corresponding to an input signal input from the outside of the control circuit 2, and outputs the control signal to the gate driver 3 and the source driver 4. An image data input unit 21, an image processing unit 22, a synchronization processing unit 23, a gate control signal generation unit 24, and a source control signal generation unit 25 are provided. The image data input unit 21, the image processing unit 22, the synchronization processing unit 23, the gate control signal generation unit 24, and the source control signal generation unit 25 may be configured by one chip, and a plurality of It may be composed of a chip.

  The image data input unit 21 receives an input signal input from the outside of the control circuit 2, outputs an image signal included in the input signal to the image processing unit 22, and outputs a synchronization signal included in the input signal to the synchronization processing unit 23. Output.

  The image processing unit 22 converts the image signal input from the image data input unit 21 into a signal corresponding to the input format of the source driver 4 and outputs the signal to the source driver 4.

  The synchronization processing unit 23 generates horizontal position information and vertical position information of each picture element based on the synchronization signal input from the image data input unit 21, and generates vertical position information as a gate control signal. The position information in the horizontal direction is output to the source control signal generator 25.

  The gate control signal generation unit 24 controls the gate driver 3 based on the vertical position information input from the synchronization processing unit 23 (gate start pulses GSP1, GSP2, gate switching signal GLBR, gate clock). Signal GCK, gate output enable GOE, etc.) are generated and sent to the gate driver 3. Further, the gate control signal generation unit 24 generates a control signal for selecting each gate bus line in a predetermined order for the power-off process when performing a power-off process described later, and sends the control signal to the gate driver 3. .

  The source control signal generation unit 25 is configured to control the source driver 4 based on the horizontal position information input from the synchronization processing unit 23 (latch pulse, polarity inversion signal for AC driving of liquid crystal, etc.) ) And output to the source driver 4. Further, the source control signal generation unit 25 generates a control signal for applying a predetermined voltage for power-off processing to each pixel and sends it to the source driver 4 when performing power-off processing described later.

  FIG. 3 is an explanatory diagram showing a schematic configuration of the liquid crystal panel 5. As shown in this figure, the liquid crystal panel 5 includes a TFT substrate 51 and a counter substrate 52 which are arranged to face each other via a spacer 53, and a liquid crystal layer made of a liquid crystal material sealed between the TFT substrate 51 and the counter substrate 52. 54, the first polarizing plate 55 disposed on the back surface side of the TFT substrate 51 (the surface opposite to the surface facing the counter substrate 52), and the surface side of the counter substrate 52 (the surface facing the TFT substrate 51). And a second polarizing plate 56 disposed on the opposite surface side). A backlight 57 is disposed on the back side of the liquid crystal panel 5.

  The first polarizing plate 55 transmits only light according to the polarization axis direction of the first polarizing plate 55 among the light emitted from the backlight 57. In addition, a voltage corresponding to the image data is applied to the liquid crystal layer 54 of each picture element, whereby the birefringence of the liquid crystal in each picture element changes according to the image data, The polarization direction of the light passing through changes according to the image data. The second polarizing plate 56 transmits only light according to the polarization axis direction of the second polarizing plate 56 out of the light that has passed through the liquid crystal layer 54. Thereby, the image display is performed by controlling the amount of light transmitted through the liquid crystal panel 5 for each picture element according to the image data.

  In the region corresponding to each picture element (subpixel) in the counter substrate 52, any one of R (red), G (green), and B (blue) color filters is formed. One pixel is formed by a combination of the three B picture elements. As a result, the R, G, and B transmitted light amounts of each pixel are controlled for each pixel according to the image data, and an image according to the image data is displayed. In the present embodiment, R, G, and B picture elements are provided. However, the present invention is not limited to this, and other color picture elements may be provided.

  In the present embodiment, the case where the liquid crystal display device 100 is a transmissive liquid crystal display device 100 that performs display using light emitted from a backlight will be described. It may be a reflective liquid crystal display device that reflects incident light to be used as display light, and is a transflective liquid crystal display device that combines the functions of a transmissive liquid crystal display device and the reflective liquid crystal display device. It may be.

  In this embodiment, a liquid crystal display device in which a pixel electrode is provided on the TFT substrate 51 and a counter electrode is provided on the counter substrate 52 will be described. However, the present invention is not limited to this, and both the pixel electrode and the counter electrode are provided. The structure provided in the same board | substrate may be sufficient.

  FIG. 4 is an explanatory diagram showing a schematic configuration of the TFT substrate 51. As shown in this figure, on the TFT substrate 51, a large number of gate bus lines 31, a large number of source bus lines 41 arranged so as to cross the gate bus lines 31 in a grid pattern, and the gate bus lines 31 are shown. And the source bus line 41, and a picture element 50 provided at each intersection and a CS wiring 34 arranged substantially parallel to the gate bus line 31.

  FIG. 5 is an explanatory diagram showing the picture element structure of the picture element 50 provided in the liquid crystal panel 5.

  As shown in FIG. 5, each picture element 50 includes a TFT (Thin Film Transistor) 61 as a switching element, a picture element electrode 62, and a counter electrode 63. The gate terminal of the TFT 61 is connected to the gate bus line 31, the source terminal is connected to the source bus line 41, and the drain terminal is connected to the pixel electrode 62. Further, the CS wiring 34 is disposed at a position facing the pixel electrode 62 through an insulating film (not shown). In the present embodiment, a TFT having a channel layer made of an indium gallium zinc oxide semiconductor (oxide semiconductor) is used as the TFT 61.

  Each gate bus line 31 is connected to the gate driver 3, and each source bus line 41 is connected to the source driver 4. The counter electrode 63 is connected to a reference potential (counter potential) through a counter wiring (not shown) disposed on the counter substrate 52. The CS wiring 34 is connected to a CS potential supply source (not shown).

  As a result, the gate driver 3 periodically switches the gate bus line 31 to be written, and the source driver 4 is synchronized with the gate driver 3 and connected to the gate bus line selected as the write target. By controlling the voltage applied to the source bus line connected to the picture element according to the image data, the voltage according to the image data is applied to the liquid crystal layer 54 of each picture element 50 to control the alignment direction of the liquid crystal molecules. And display.

  FIG. 6 is an equivalent circuit diagram of the picture element 50. When the voltage of the gate terminal of the TFT 61 becomes higher than the voltage of the source terminal of the TFT 61 by a predetermined value or more, the TFT 61 is turned on, a current flows between the source terminal and the drain terminal, and the potential of the source bus line 41 changes to the liquid crystal capacitance ( Applied to the liquid crystal layer 54). In the equivalent circuit diagram, the pixel electrode 62, the liquid crystal layer 54, and the counter electrode 63 are represented as capacitors (liquid crystal capacitance). In addition, each pixel arranged in parallel to the liquid crystal capacitance (the pixel electrode 62, the liquid crystal layer 54, and the counter electrode 63) by the pixel electrode 62, the insulating layer (not shown), and the CS wiring 34. A liquid crystal storage capacitor (CS capacitor) 64 is formed to maintain the potential. The liquid crystal storage capacitor 64 is not an essential component and may be omitted.

  The gate driver 3 controls the voltage applied to each gate bus line 31 provided in the liquid crystal panel 5 based on the control signal input from the gate control signal generation unit 24, thereby setting the gate bus line 31 to be written to Switch periodically.

  FIG. 7 is an explanatory diagram showing input / output signals of the gate driver 3. As shown in this figure, the gate driver 3 includes a high level voltage VGH applied to the gate bus line 31, a low level voltage VGL applied to the gate bus line 31, a logic voltage VL, and a logic ground potential (reference potential) GND. Is entered. These signals are supplied from the power supply circuit 1 (or another power supply circuit of the liquid crystal display device 100). The gate driver 3 receives gate start pulses GSP1 and GSP2, a gate switching signal GLBR, a gate clock signal GCK, and a gate enable signal GOE from the gate control signal generator 24. G2160 are connected to the first, second,..., 2160th gate bus lines 31 of the gate bus lines 31 of the liquid crystal panel 5, respectively. The gate switching signal GLBR is a signal that defines whether the selection order of the gate bus lines to be written is in the order of G1 → G2160 (forward direction) or in the order of G2160 → G1 (reverse direction).

  FIG. 8 is an explanatory diagram showing the configuration of the gate driver 3 and the power supply path to the gate driver 3.

  As shown in FIG. 8, the gate driver 3 includes processing blocks 35 a to 35 h, and these processing blocks 35 a to 35 h are in-panel wirings (inter-block wiring portions) 37 a to 37 g formed in the liquid crystal panel 5. Are connected in series with each other. Further, the processing block 35 a disposed at the end on the source driver 4 side is connected to the power supply circuit 1 via a wiring 36 that passes through a part of the liquid crystal panel 5 and the source driver 4. As a result, the power supplied from the power supply circuit 1 to the gate driver 3 is input to the processing block 35a via the wiring 36, and to the processing blocks 35b, 35c,..., 35h via the in-panel wirings 37a to 37g. It is transmitted sequentially.

  270 gate bus lines 31 are assigned to each of the processing blocks 35a to 35h, and each of the processing blocks 35a to 35h is assigned to the processing block based on a control signal input from the gate control signal generator 24. The output potential for the gate bus line 31 is switched between a high level and a low level. The number of processing blocks provided in the gate driver 3 and the number of gate bus lines assigned to each processing block are not particularly limited, and may be changed as appropriate.

  Although details will be described later, in this embodiment, during normal image display, a gate bus line (in the power supply path) close to the power input portion for the gate driver 3 (in this embodiment, the connection portion of the wiring 36 to the gate driver 3). When selecting the gate bus line to be written in order from the resistance bus (gate bus line with the smallest voltage drop) and turning off the power, the gate bus line far from the power input section (resistance value (voltage drop) in the power supply path) The gate bus lines to be written are selected in order from the largest gate bus line).

  Based on the control signal input from the source control signal generator 25, the source driver 4 applies a voltage to each source bus line 41 at a timing synchronized with the switching cycle of the gate bus line 31 to be written by the gate driver 3. To control.

  Specifically, the potential applied to each source bus line 41 according to the signal input from the image processing unit 22 and the polarity inversion signal input from the source control signal generation unit 25 (in each source bus line 41). Among the connected picture elements, a potential to be applied to the picture element connected to the gate bus line 31 to be written), and the generated potential is a latch pulse input from the source control signal generation unit 25 It is applied to each source bus line 41 at a timing according to LS.

  When the power of the liquid crystal display device 100 is turned off, the source driver 4 outputs a predetermined potential for power-off processing (for example, a potential for displaying black on each pixel) to each source bus line 41. To do.

(1-2. Characteristics of TFT61)
FIG. 9 shows a TFT made of indium gallium zinc oxide semiconductor (oxide semiconductor) (Example), a TFT made of low-temperature polysilicon (LTPS) (Comparative Example 1), and a TFT made of amorphous silicon (a-Si) ( It is the graph which compared the characteristic of the comparative example 2). The horizontal axis in FIG. 9 indicates the potential difference (Vg−Vs) between the gate and source of the TFT, and the vertical axis indicates the current flowing between the source and drain.

  As shown in FIG. 9, a TFT made of an indium gallium zinc oxide semiconductor has an off-leakage current (current flowing between the source and drain when the TFT is off) of 1 / TFT that is made of amorphous silicon (a-Si). It has a characteristic that it is 1000 or less and 1 / 10,000 or less of TFT made of low temperature polysilicon (LPTS).

  The above-described characteristics of TFTs made of an indium gallium zinc oxide semiconductor with low off-leakage current lead to improved driving characteristics (reduction of low power consumption, etc.), while the power supply of the liquid crystal display device is turned off. When this is done, there is a problem that the charges charged in the pixel electrodes are difficult to escape. If charges remain in the pixel electrode, an electric field in a certain direction is applied to the liquid crystal layer due to the potential difference between the pixel electrode and the counter electrode, and polarization occurs in the liquid crystal molecules composed of polar molecules, resulting in characteristic deviation and image Problems such as burn-in may occur.

  For this reason, in the liquid crystal display device 100 according to the present embodiment, a predetermined power-off process is performed to remove the charges charged in the pixel electrodes when the power is turned off.

(1-3. Power off processing)
Next, power off processing performed on the liquid crystal panel 5 when the liquid crystal display device 100 is powered off will be described.

  As described above, if a state in which a voltage is applied to each pixel is continued for a long time during the power-off period, a problem such as burn-in may occur.

  Therefore, in the present embodiment, when the voltage drop detection circuit 11 monitors the input voltage to the power supply circuit 1 to detect the power-off of the liquid crystal display device 100 and detect the power-off of the liquid crystal display device 100, each picture A power-off process is performed to write a predetermined potential for the power-off process to the element. Note that the power-off process may be started when the power button of the liquid crystal display device 100 is operated or when a power-off instruction is input via the remote control.

  FIG. 10 is an explanatory diagram schematically showing a circuit configuration for switching the selection order (drawing order) of the gate bus lines to be written, and (a) is a control during normal time (during power-on period). Signal flow (b) shows the flow of control signals during the power-off process. FIG. 11 is an explanatory diagram showing the waveform of the input signal of the gate driver 3. FIG. 11A shows the signal waveform during normal operation (during the power-on period), and FIG. 11B shows the signal waveform during power-off processing. Yes.

  In addition, G1-G2160 shown in FIG. 11 is a code | symbol attached | subjected with respect to each gate bus line 31 in order according to the arrangement position from the source bus line 41 side (connection part side with the wiring 36). The gate bus line 31 closest to the power input unit for the gate driver 3 is shown, and G2160 shows the gate bus line 31 farthest from the power input unit for the gate driver 3.

  As shown in FIG. 10, the output terminal of the gate start pulse GSP1 in the gate control signal generator 24 is connected to the processing block 35a of the gate driver 3 via a resistor (protective resistor) R4. The output terminal of the gate start pulse GSP2 in the gate control signal generator 24 is connected to the processing block 35h of the gate driver 3 and is connected to the pull-up power supply via the resistor R5. That is, the gate start pulse GSP1 is set to high impedance (HiZ), and the gate start pulse GSP2 is set to WeakPullUp. The output terminal of the gate switching signal GLBR in the gate control signal generator 24 is connected to each processing block 35 a to 35 h of the gate driver 3.

  Note that the circuit configuration for switching the selection order of the gate bus lines is not limited to the circuit configuration example shown in FIG.

  For example, even if the gate start pulse GSP2 is not set to WeakPullUp and the gate start pulse GSP2 is controlled to output a high level signal during the end processing, substantially the same operation as in the circuit configuration example of FIG. 10 is realized. it can.

  In addition, the gate start pulse GSP1 is not limited to the high impedance (HiZ) setting in the termination process, and may be set to open or set to pulse signal output, for example. Note that the gate start pulse GSP1 and the processing block 35a are set when the gate start pulse GSP1 is set as the pulse signal output in the same manner as in the normal process and the gate bus line selection order is switched in the reverse order to the normal process in the final process. In this embodiment, the protective resistance R4 is provided between the output terminal of the gate start pulse GSP1 in the gate control signal generator 24 and the processing block 35a. Can be prevented.

  At normal times, as shown in FIGS. 10A and 11A, the gate control signal generator 24 outputs a low-level gate switching signal GLBR to the processing blocks 35a to 35h. Thereby, the gate start pulse GSP1 is transmitted to each processing block in the order from the processing block 35a to the processing block 35h, and the gate bus lines corresponding to each processing block are sequentially selected in this order. That is, the gate bus lines 31 are sequentially selected in the order from G1 to G2160.

  As a result, after the gate start pulse GSP1 becomes high level, the potential of the gate bus line 31 to be selected is switched to high level at the timing when the gate clock signal GCK switches from high level to low level, and then the gate clock signal When GCK is switched from the low level to the high level, the potential of the gate bus line 31 is switched to the low level. That is, a high level voltage is applied to one gate bus line 31 from the fall of the gate clock signal GCK (switch from high level to low level) until the next rise (switch from low level to high level). Applied.

  Thereafter, when the gate clock signal GCK is switched from the high level to the low level again, the potential of the next gate bus line 31 is switched to the high level. Thereafter, when the gate clock signal GCK is switched from the low level to the high level, The potential of the gate bus line 31 is switched to a low level. This process is repeated until selection of all the gate bus lines 31 is completed.

  Note that during the period in which the gate clock signal GCK is at a high level, no gate bus line 31 is selected (a high-level voltage is not applied to any gate bus line 31), which is a non-write period. . As a result, it is possible to prevent an appropriate image display from becoming impossible due to a delay in transmission of the applied voltage in the gate bus line 31. That is, when the length of the gate bus line 31 is long, the timing of turning on the pixel TFT 61 between the portion close to the gate driver 3 and the portion far from the gate driver 3 occurs due to the delay in transmission of the applied voltage in the gate bus line 31. As a result, there is a case where a shift between the ON timing of the TFT 61 and the switching timing of the applied voltage to each source bus line 41 by the source driver 4 occurs, making it impossible to display an appropriate image.

  On the other hand, according to the above configuration, the gate bus line is provided by providing a non-write period in which no high level is applied to any gate bus line 31 every time the gate bus line 31 to which a high level is applied is switched. Inappropriate image display can be prevented due to a difference between the drive timing of 31 and the voltage application timing to the source bus line 41.

  The gate enable signal GOE (not shown) is a signal for stopping all outputs from the gate driver 3 when the signal is at a high level (a signal for setting all the gate bus lines 31 to a low level). In the present embodiment, the gate enable signal GOE is fixed at a low level.

  Further, as shown in FIG. 11A, the cycle of the gate clock signal GCK during normal display (selection switching in which the gate bus line 31 to be written is switched by switching between the low level and the high level of the gate clock signal GCK. The period) is set so that selection of all the gate bus lines 31 is completed within one frame period.

  On the other hand, during the power-off process, as shown in FIGS. 10B and 11B, the gate control signal generator 24 switches the gate switching signal GLBR to the high level simultaneously with the rise of the gate start pulse GSP1. As a result, the gate start pulse GSP2 is transmitted to each processing block in the order from the processing block 35h to the processing block 35a, and the gate bus lines corresponding to each processing block pass through the gate bus lines 31 to be written in the order corresponding thereto. Increase it. That is, each gate bus line 31 is sequentially added to the gate bus line to be written in the order from G2160 to G1.

(1-4. Summary of Embodiment 1)
As described above, in the liquid crystal display device 100 according to the present embodiment, during the power-off process, the selection order of the gate bus lines 31 to be written is different from the normal order, and power is supplied to the gate driver 3. The gate bus lines 31 are set so that the resistance value of the power supply path from the source is selected in descending order, and a predetermined voltage for power-off processing is applied to each source bus line 41.

  As a result, when the charging voltage of the charging means at the start of the power-off operation is relatively high, writing to the gate bus line having a large resistance value of the power supply path is performed. When the voltage drops relatively, writing to the gate bus line having a small resistance value of the power supply path can be performed. Therefore, since the power charged in the charging means can be used efficiently, the power consumption during the power-off process can be reduced, and the capacity of the charging means can be reduced to reduce the cost. it can.

  Specifically, the potential of the power supply path for each of the processing blocks 35a to 35h in the gate driver 3 decreases due to a voltage drop as the distance from the power supply source to the gate driver 3 increases.

  In particular, in the present embodiment, the processing blocks 35a to 35h are connected by the in-panel wirings 37a to 37g. However, since the in-panel wiring passes through the liquid crystal panel 5, the wiring is formed thin and thin. The resistance value is higher than that of wiring provided in a normal general circuit. For this reason, the wiring in the panel becomes a kind of resistance, and due to the influence of this resistance, the voltage drop in the power supply path is more likely to occur in the processing block far from the power supply source for the gate driver 3.

For example, the wiring resistance Rtab of the wiring 36 is 34.3Ω, the wiring resistance Rp of each of the intra-panel wirings 37a to 37g is 30.5Ω, the supply voltage Vgh to the wiring 36 is 35V, and necessary for driving each gate bus line 31. If the current amount i is 10 mA, the supply voltage Vghx for the final gate bus line 31 and the number x of processing blocks are 8,
Vghx = Vgh-Rtab.i- (x-1) .R.i
= 35-34.3 × 0.01-7 × 30.5 × 0.01
= 32.522
Thus, the maximum voltage drop ΔV is ΔV = 35−32.522 = 2.478V.

  In addition, when the power is turned off, the power supply from the outside is cut off and power is supplied from the charging means provided in the auxiliary power supply circuit 13, so that the charging power of the charging means gradually decreases during the power off process. Go. That is, the voltage supplied from the charging means to the gate driver 3 when the final write gate bus line is selected in the power-off process is lower than the voltage supplied to the gate driver 3 at the start of the power-off process.

  For this reason, when the power-off process is performed as in the prior art, the gate bus line 31 is selected in order from the power supply source for the gate driver 3 in the same manner as in the normal state. The gate bus line 31 having the largest voltage drop is selected. Therefore, the amount of power that should be charged in the charging means in order to appropriately select all the gate bus lines 31 increases.

  On the other hand, in the present embodiment, when the charging power of the charging unit immediately after the start of the power-off process is large, the gate bus line 31 (gate bus line 31 having a large voltage drop) that is far from the power supply source for the gate driver 3 is used. When the charging power of the charging means at the end of the power-off process is reduced, the gate bus line 31 (gate bus line 31 having a large voltage drop amount) close to the power supply source for the gate driver 3 is selected.

  As a result, the total amount of power to be charged in the charging means in order to properly select all the gate bus lines 31 can be reduced, so that the capacity of the charging means can be reduced to reduce the cost. it can.

  In the present embodiment, the configuration in which the in-panel wirings 37a to 37g are included in the power supply path for the processing blocks 35a to 35h in the gate driver 3 is described, but the present invention is not limited to this.

  In the present embodiment, the configuration using a TFT made of an indium gallium zinc oxide semiconductor as the switching element of each pixel has been described. However, the present invention is not limited to this. For example, a channel layer made of an oxide semiconductor other than an indium gallium zinc oxide semiconductor may be used, or a channel layer made of a material other than an oxide semiconductor may be used.

[Embodiment 2]
Another embodiment of the present invention will be described. For convenience of explanation, members having the same functions as those of the above-described embodiment are denoted by the same reference numerals as those of the embodiment, and description thereof is omitted.

  FIG. 12 is an explanatory diagram showing a schematic configuration of the liquid crystal display device 100b according to the present embodiment. In addition to the configuration of the liquid crystal display device 100 of the first embodiment, the liquid crystal display device 100b according to the present embodiment is on the side opposite to the side on which the gate driver (first gate driver) 3 is disposed with respect to the liquid crystal panel 5. Is provided with a gate driver (second gate driver) 3b. That is, the gate driver 3 is provided on one end side of each gate bus line 31 in the extending direction, and the gate driver 3b is provided on the other end side.

  FIG. 13 is an explanatory diagram showing the configuration of the gate drivers 3 and 3b. As shown in this figure, the gate driver 3 b has a configuration substantially similar to that of the gate driver 3.

  That is, the gate driver 3b is provided with processing blocks 35a to 35h, similar to the gate driver 3, and these processing blocks 35a to 35h are connected in series to each other by in-panel wirings 37a to 37g formed in the liquid crystal panel 5. Has been. Further, the processing block 35 a disposed at the end on the source driver 4 side is connected to the power supply circuit 1 via a wiring 36 that passes through a part of the liquid crystal panel 5 and the source driver 4. As a result, the power supplied from the power supply circuit 1 to the gate driver 3b is input to the processing block 35a via the wiring 36, and to the processing blocks 35b, 35c,..., 35h via the in-panel wirings 37a to 37g. It is transmitted sequentially.

  270 gate bus lines 31 are allocated to the processing blocks 35a to 35h of the gate driver 3 and the processing blocks 35a to 35h of the gate driver 3b, respectively, and one end side of each gate bus line 31 is the gate driver 3. The other end side is connected to one of the processing blocks of the gate driver 3b.

  In addition, each processing block 35 a to 35 h of the gate driver 3 switches the output potential to one end side of the gate bus line 31 assigned to the processing block based on the control signal input from the gate control signal generation unit 24. The processing blocks 35a to 35h of the gate driver 3b are synchronized with the switching of the output potential from the gate driver 3 to each gate bus line 31 based on the control signal input from the gate control signal generator 24. The output potential to each gate bus line 31 is switched. Therefore, an output voltage having the same potential is simultaneously applied to each gate bus line 31 from both ends of the gate bus line 31.

  Thereby, even when the size of the liquid crystal panel 5 is large (when the length of the gate bus line 31 is long), it is possible to prevent an appropriate image display from being performed due to a delay in transmission of the applied voltage in the gate bus line 31. it can. That is, it is possible to prevent a shift in the timing at which the TFT 61 of the picture element is turned on between the portion close to one end side and the portion close to the other end side of the gate bus line 31 due to the transmission delay of the applied voltage in the gate bus line 31. It is possible to prevent an inappropriate image display from being performed due to a difference between the drive timing of the gate bus line 31 and the voltage application timing to the source bus line 41.

  The number of processing blocks provided in the gate driver 3 and the gate driver 3b and the number of gate bus lines assigned to each processing block are not particularly limited, and may be changed as appropriate.

  Further, in the present embodiment, as shown in FIG. 13, as in the first embodiment, the power input unit for the gate drivers 3 and 3b during normal image display (in this embodiment, the connection part of the wiring 37 to the gate driver 3). The gate bus lines to be written are selected in order from the gate bus line closer to the gate (the gate bus line having a small resistance value (voltage drop) in the power supply path), and when performing power-off processing, the gate bus line far from the power input unit ( A gate bus line to be written is selected in order from a gate bus line having a large resistance value (voltage drop) in the power supply path.

  As a result, since the power charged in the charging means can be efficiently used during the power-off process, the power consumption during the power-off process can be reduced, and the capacity of the charging means can be reduced. Cost can be reduced.

[Embodiment 3]
Still another embodiment of the present invention will be described. For convenience of explanation, members having the same functions as those of the above-described embodiment are denoted by the same reference numerals as those of the embodiment, and description thereof is omitted.

  FIG. 14 is an explanatory diagram showing a schematic configuration of the liquid crystal display device 100c according to the present embodiment. The liquid crystal display device 100c according to the present embodiment has the same configuration as the liquid crystal display device 100 according to the first embodiment except that the power supply circuit 1c is provided instead of the power supply circuit 1 in the liquid crystal display device 100 according to the first embodiment.

  The power supply circuit 1 c includes a voltage drop detection circuit 11, a main power supply circuit 12, and an auxiliary power supply circuit 13, similar to the power supply circuit 1 in the first embodiment. However, in the first embodiment, the voltage drop detection circuit 11 is provided in the front stage of the main power supply circuit 12, and the input voltage to the power supply circuit 1 is monitored from the outside, whereas in this embodiment, the voltage drop detection circuit 11 is provided. It is provided in the subsequent stage of the main power supply circuit 12 and monitors the output voltage of the main power supply circuit 12.

  The main power supply circuit 12 distributes power supplied from the outside to each block of the liquid crystal display device 100c during normal display (during the period when the power supply of the liquid crystal display device 100c is turned on). Specifically, the main power supply circuit 12 supplies the logic voltage Vlogic to the image data input unit 21, the image processing unit 22, the synchronization processing unit 23, the gate control signal generation unit 24, and the source control signal generation unit 25, and the gate A logic voltage VL, an analog high level voltage VGH, and a low level voltage VGL are supplied to the driver 3, an opposing reference potential VCOM of the liquid crystal panel 5 and a CS reference potential (reference potential of the liquid crystal auxiliary capacitor) VCS are supplied, and a source driver 4 are supplied with a logic voltage VCC / LRVDD, an analog voltage VLS, gradation reference voltages VL0 to VL1023, and VH0 to VH1023.

  The voltage drop detection circuit (voltage drop detection unit) 11 monitors at least a part of the output voltage from the main power supply circuit 12 to each block, thereby turning off the power of the liquid crystal display device 100c (user operation). Power off due to power failure, power off due to power failure, disconnection, etc.).

  The auxiliary power supply circuit 13 is provided with charging means (not shown) such as a capacitor, for example, and charges the charging means with electric power supplied from the outside, and charges the charging means when the liquid crystal display device 100c is powered off. The supplied power is supplied to each block that performs power-off processing in the liquid crystal display device 100c. The processing contents of the power-off processing are the same as those in the first embodiment. The power for charging the charging means provided in the auxiliary power supply circuit 13 may be directly input from the outside to the auxiliary power supply circuit 13 or may be input from the main power supply circuit 12.

  According to the configuration of the present embodiment, substantially the same effect as that of the first embodiment can be obtained.

[Embodiment 4]
The control blocks (particularly the control circuit 2, the gate control signal generation unit 24, the source control signal generation unit 25, and the image processing unit 22) of the liquid crystal display devices 100, 100b, and 100c are formed in an integrated circuit (IC chip) or the like. It may be realized by a logic circuit (hardware), or may be realized by software using a CPU (Central Processing Unit).

  In the latter case, the liquid crystal display devices 100, 100b, and 100c include a CPU that executes instructions of a program that is software that realizes each function, and a ROM (in which the program and various data are recorded so as to be readable by a computer (or CPU)). A Read Only Memory) or a storage device (these are referred to as “recording media”), a RAM (Random Access Memory) for expanding the program, and the like are provided. And the objective of this invention is achieved when a computer (or CPU) reads the said program from the said recording medium and runs it. As the recording medium, a “non-temporary tangible medium” such as a tape, a disk, a card, a semiconductor memory, a programmable logic circuit, or the like can be used. The program may be supplied to the computer via an arbitrary transmission medium (such as a communication network or a broadcast wave) that can transmit the program. The present invention can also be realized in the form of a data signal embedded in a carrier wave in which the program is embodied by electronic transmission.

[Summary]
In the liquid crystal display device according to the first aspect of the present invention, the gate bus line to be written is periodically switched, and the source connected to each pixel connected to the gate bus line selected as the writing target A liquid crystal display device including a control unit that performs a writing process of applying a voltage according to image data to each picture element by controlling a voltage applied to a bus line according to image data, wherein the control unit includes: When the power of the liquid crystal display device is turned off, the selection order of the gate bus lines to be written is different from the order of displaying the image according to the image data, and the power supply path from the power supply source is selected. It is set so that the resistance bus value is selected in order from the gate bus line in descending order, and power off processing is performed to apply a predetermined voltage for power off processing to each source bus line. It is a symptom.

  According to the above configuration, the selection order of the gate bus lines when performing a process of applying a predetermined voltage for the power-off process to each pixel during the power-off operation, the resistance value of the power supply path from the power supply source Set so that the gate bus lines are selected in descending order. As a result, when the charging voltage of the charging means at the time of starting the power-off operation is relatively high, writing to the gate bus line having a large resistance value of the power supply path (a gate bus line having a large voltage drop amount) is performed. When the charging voltage of the charging unit is relatively lowered with time, writing to a gate bus line having a small resistance value in the power supply path (a gate bus line having a relatively small voltage drop amount) can be performed. Therefore, since the power charged in the charging means can be used efficiently, the power consumption during the power-off process can be reduced, and the capacity of the charging means can be reduced to reduce the cost. it can.

  The liquid crystal display device according to aspect 2 of the present invention is the liquid crystal display device according to aspect 1, further comprising a voltage drop detection unit that detects a decrease in the power supply voltage of the liquid crystal display device, and the control unit has a power supply voltage predetermined by the voltage drop detection unit. In this configuration, the power-off process is performed when it is detected that the value has fallen below the value.

  According to said structure, it can detect that the power supply of a liquid crystal display device is turned off by a voltage detection part, and can perform a power-off process automatically.

  A liquid crystal display device according to aspect 3 of the present invention is the liquid crystal display device according to aspect 1 or 2, which is disposed on one end side in the extending direction of each gate bus line and applied to each gate bus line in accordance with an instruction from the control unit. A first gate driver that switches between the gate bus lines, and a second gate driver that is arranged on the other end side in the extending direction of the gate bus lines and switches the voltage applied to the gate bus lines according to an instruction from the control unit. When the power supply of the liquid crystal display device is turned off, the control unit determines the selection order of the gate bus lines to be written for both the first gate driver and the second gate driver from the power supply source. In this configuration, the supply path is set so that the resistance value of the supply path is selected in order from the gate bus line.

  According to the above configuration, even in a configuration including a plurality of gate drivers, the power charged in the charging means can be used efficiently, so the power consumption when performing the power-off process is reduced. Therefore, the capacity of the charging means can be reduced and the cost can be reduced.

  A liquid crystal display device according to aspect 4 of the present invention is the liquid crystal display device according to aspects 1 to 3, wherein the gate bus line, the source bus line, the liquid crystal panel on which each of the pixels is formed, and an instruction from the control unit. A gate driver that switches an applied voltage to each of the gate bus lines, and the gate driver includes a plurality of processing blocks that switch an applied voltage to one or more gate bus lines, and the power supply path includes the processing An inter-block wiring section that connects the blocks is included, and at least a part of the inter-block wiring section is an intra-panel wiring provided in the liquid crystal panel.

  Since the intra-panel wiring is generally formed to be thin and thin, it has a higher resistance value than the wiring provided in a normal circuit. Therefore, when the inter-block wiring portion includes the intra-panel wiring, the amount of voltage drop is greatly different between the gate bus line having the maximum resistance value and the minimum gate bus line in the power supply path. For this reason, in the configuration in which the selection order of the gate bus lines is set without considering the difference in the resistance value of the power supply path as in the prior art, in order to perform a fixed pattern drawing process on all the pixels during the power-off operation. The required charging capacity was very large.

  On the other hand, according to the above configuration, since the power charged in the charging means can be efficiently used during the power-off process, power consumption when performing the power-off process can be reduced. The capacity of the charging means can be greatly reduced as compared with the prior art.

  A liquid crystal display device according to aspect 5 of the present invention is the liquid crystal display device according to aspects 1 to 4, wherein each of the picture elements includes a picture element electrode, a counter electrode, and a liquid crystal layer disposed between the picture element electrode and the counter electrode. A switching element having a gate terminal connected to the gate bus line, a source terminal connected to the source bus line, and a drain terminal connected to the pixel electrode, wherein the switching element is a channel layer made of an oxide semiconductor. It is the structure which is a thin-film transistor provided with.

  A thin film transistor including a channel layer made of an oxide semiconductor has a characteristic of extremely low off-leakage current, and a potential difference remains between a pixel electrode and a counter electrode when the power supply of the liquid crystal display device is turned off. In this case, the potential difference continues to be applied during the period when the power is turned off, so that problems such as burn-in are likely to occur. On the other hand, according to the above configuration, the potential difference between the pixel electrode and the counter electrode can be reduced by the power-off process, which is a case where a thin film transistor including a channel layer made of an oxide semiconductor is used. However, it is possible to prevent problems such as image sticking due to a potential difference between the pixel electrode and the counter electrode.

  The liquid crystal display device control method according to one aspect of the present invention periodically switches the gate bus line to be written, and is connected to each pixel connected to the gate bus line selected as the writing target. A method for controlling a liquid crystal display device that performs a writing process of applying a voltage corresponding to image data to each of the picture elements by controlling an applied voltage to a source bus line according to image data, the liquid crystal display When turning off the power of the apparatus, the selection order of the gate bus lines to be written is different from the order of displaying the image according to the image data, and the resistance value of the power supply path from the power supply source is large. It is set so that the order is selected in order from the gate bus line, and power off processing is performed to apply a predetermined voltage for power off processing to each source bus line. There.

  According to the above method, the selection order of the gate bus lines when performing a process of applying a predetermined voltage for the power-off process to each pixel during the power-off operation, the resistance value of the power supply path from the power supply source Set so that the gate bus lines are selected in descending order. As a result, when the charging voltage of the charging means at the time of starting the power-off operation is relatively high, writing to the gate bus line having a large resistance value of the power supply path (a gate bus line having a large voltage drop amount) is performed. When the charging voltage of the charging unit is relatively lowered with time, writing to a gate bus line having a small resistance value in the power supply path (a gate bus line having a relatively small voltage drop amount) can be performed. As a result, since the power charged in the charging means can be efficiently used, the power consumption during the power-off process can be reduced, and the capacity of the charging means can be reduced to reduce the cost. Can do.

  The present invention is not limited to the above-described embodiments, and various modifications can be made within the scope shown in the claims. That is, embodiments obtained by combining technical means appropriately modified within the scope of the claims are also included in the technical scope of the present invention.

  The present invention can be applied to a liquid crystal display device. Further, the present invention can be particularly preferably applied to a liquid crystal display device using a thin film transistor made of an oxide semiconductor or the like with a small off-leakage current as a switching element.

1, 1c Power supply circuit 2 Control circuit (control unit)
3 Gate driver (first gate driver)
3b Gate driver (second gate driver)
4 Source driver 5 Liquid crystal panel 11 Voltage drop detection circuit (Voltage drop detection unit)
11a IC for detection
12 Main power supply circuit 13 Auxiliary power supply circuit 21 Image data input unit 22 Image processing unit 23 Synchronization processing unit 24 Gate control signal generation unit 25 Source control signal generation unit 31 Gate bus lines 35a to 35h Processing block 36 Wiring 37a to 37g In-panel wiring (Inter-block wiring section)
41 Source bus line 50 Picture element 100, 100b, 100c Liquid crystal display device

Claims (6)

The gate bus line to be written is periodically switched, and the voltage applied to the source bus line connected to each pixel connected to the gate bus line selected as the write target is controlled according to the image data. A liquid crystal display device including a control unit that performs a writing process of applying a voltage according to image data to each of the picture elements,
When the power of the liquid crystal display device is turned off, the control unit selects a gate bus line to be written in an order different from that for displaying an image according to image data, and from the power supply source. The power supply path is set so that the resistance value of the power supply path is selected in descending order from the gate bus line, and the power off process is performed to apply a predetermined voltage for the power off process to each source bus line. A liquid crystal display device. A voltage drop detection unit that detects a drop in the power supply voltage of the liquid crystal display device,
The liquid crystal display device according to claim 1, wherein the control unit performs the power-off process when the voltage drop detection unit detects that the power supply voltage has decreased to a predetermined value or less. A first gate driver that is disposed on one end side in the extending direction of each gate bus line, and switches an applied voltage to each gate bus line in accordance with an instruction from the control unit;
A second gate driver that is arranged on the other end side in the extending direction of each gate bus line, and switches an applied voltage to each gate bus line in accordance with an instruction from the control unit;
When the power of the liquid crystal display device is turned off, the control unit determines the selection order of the gate bus lines to be written for both the first gate driver and the second gate driver, and supplies power from a power supply source. 3. The liquid crystal display device according to claim 1, wherein the liquid crystal display device is set so as to be selected in order from a gate bus line having a larger resistance value of the path. A liquid crystal panel on which the gate bus line, the source bus line, and the picture elements are formed;
A gate driver that switches an applied voltage to each of the gate bus lines according to an instruction from the control unit;
The gate driver includes a plurality of processing blocks for switching applied voltages to one or more gate bus lines,
The power supply path includes an inter-block wiring unit that connects the processing blocks,
4. The liquid crystal display device according to claim 1, wherein at least a part of the inter-block wiring portion is an intra-panel wiring provided in the liquid crystal panel. 5. Each of the above picture elements has a picture element electrode, a counter electrode, a liquid crystal layer disposed between the picture element electrode and the counter electrode, a gate terminal connected to the gate bus line, and a source terminal connected to the source bus line. And a switching element having a drain terminal connected to the pixel electrode,
5. The liquid crystal display device according to claim 1, wherein the switching element is a thin film transistor including a channel layer made of an oxide semiconductor. The gate bus line to be written is periodically switched, and the voltage applied to the source bus line connected to each pixel connected to the gate bus line selected as the write target is controlled according to the image data. A control method of a liquid crystal display device that performs a writing process of applying a voltage according to image data to each of the picture elements,
When the power supply of the liquid crystal display device is turned off, the selection order of the gate bus lines to be written is different from the order in which the image is displayed according to the image data, and the resistance of the power supply path from the power supply source A liquid crystal display device that performs power-off processing in which a predetermined voltage for power-off processing is applied to each source bus line, and the order is selected so that gate bus lines with larger values are sequentially selected. Control method.

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