JP2015049568A - Noise removal device, communication device, and noise removal method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a noise removal device capable of automatically setting an appropriate noise removal period according to a communication environment.SOLUTION: A noise removal circuit 1 comprises a removal circuit 3, a register 5, and a CPU interface 7. The register 5 holds a setting value P for setting a noise removal period. The removal circuit 3 receives a data signal IN in synchronization with a clock signal CLK and removes noise of a time width equal to or shorter than the noise removal period included in the data signal IN according to the setting value P. The CPU interface 7 rewrites the setting value P so that the noise removal period becomes longer every time when a communication error occurs.

Description

  The present invention relates to a noise removing device, a communication device, and a noise removing method for removing noise contained in a data signal.

  The noise removal circuit disclosed in Patent Literature 1 includes a plurality of stages of shift registers, a coincidence circuit, and a plurality of switches provided corresponding to the plurality of stages of shift registers. The multistage shift register sequentially shifts the input signal. The coincidence circuit outputs a coincidence signal only when the levels of the output signals of the plurality of shift registers all coincide. The coincidence signal is a signal obtained by removing noise from the input signal.

  The switch is provided to change the number of stages of the shift register, that is, the noise removal period. The switch is switched by a trigger or a register.

Japanese Patent Laid-Open No. 5-120162

  However, Patent Document 1 does not disclose specific control of the noise removal period by switching the switch. Therefore, the noise removal period may not be set appropriately depending on the communication environment.

  The present invention has been made in view of the above problems, and an object thereof is to provide a noise removing device, a communication device, and a noise removing method capable of automatically setting an appropriate noise removing period according to a communication environment. is there.

  According to a first aspect of the present invention, a noise removing device includes a holding circuit, a removing circuit, and a rewriting circuit. The holding circuit holds a setting value for setting the noise removal period. The removal circuit receives the data signal in synchronization with the clock signal, and removes noise having a time width equal to or shorter than the noise removal period included in the data signal according to the set value. The rewrite circuit rewrites the set value so that the noise removal period becomes longer each time a communication error occurs.

  According to a second aspect of the present invention, a communication device includes a transmission device and a reception device. The receiving device receives a data signal and a clock signal from the transmitting device. The receiving device includes a holding circuit, a removing circuit, and a rewriting circuit. The holding circuit holds a setting value for setting the noise removal period. The removal circuit receives the data signal in synchronization with the clock signal, and removes noise having a time width equal to or shorter than the noise removal period included in the data signal according to the set value. The rewrite circuit rewrites the set value so that the noise removal period becomes longer each time a communication error occurs. In the noise removal period, an upper limit is provided corresponding to the frequency of the clock signal. The transmission device changes the frequency of the clock signal to a value lower than that before the occurrence of the communication error in response to the occurrence of a communication error after the upper limit noise elimination period is set.

  According to a third aspect of the present invention, a noise removal method includes a step of holding a setting value for setting a noise removal period, a step of receiving a data signal in synchronization with a clock signal, and the setting value. A step of removing noise having a time width equal to or shorter than the noise removal period included in the received data signal, and a step of rewriting the set value so that the noise removal period becomes longer each time a communication error occurs. .

  According to the present invention, the set value is rewritten so that the noise removal period becomes longer each time a communication error occurs. Therefore, the noise removal period is changed until communication is normally performed. As a result, an appropriate noise removal period can be automatically set according to the communication environment.

It is a block diagram which shows the noise removal circuit which concerns on Embodiment 1 of this invention. It is a figure which shows the circuit structure of the removal circuit shown in FIG. 3 is a time chart illustrating a majority operation of the determination circuit illustrated in FIG. 2. FIG. 3 is a diagram for explaining the majority operation of the determination circuit shown in FIG. 2. It is a block diagram of the communication apparatus which concerns on Embodiment 2 of this invention. It is a flowchart which shows the noise removal method which concerns on Embodiment 3 of this invention.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same reference numerals and description thereof is not repeated.

(Embodiment 1)
[Basic principle]
With reference to FIG. 1, the noise removal circuit 1 in Embodiment 1 of this invention is demonstrated. The noise removal circuit 1 includes a removal circuit 3, a register 5, and a CPU (Central Processing Unit) interface 7. The noise removal circuit 1 functions as a noise removal device. The register 5 functions as a holding circuit. The CPU interface 7 functions as a rewrite circuit.

  The register 5 holds a setting value (hereinafter referred to as “setting value P”) for setting the noise removal period. The removal circuit 3 receives the data signal IN in synchronization with the clock signal CLK. The removal circuit 3 removes noise having a time width equal to or shorter than the noise removal period included in the data signal IN according to the set value P. The CPU interface 7 rewrites the set value P so that the noise removal period becomes longer each time a communication error occurs.

  According to the first embodiment, every time a communication error occurs, the set value P is rewritten so that the noise removal period becomes longer. Therefore, the noise removal period is changed until communication is normally performed. As a result, an appropriate noise removal period can be automatically set according to the communication environment.

[Circuit configuration of the noise removal circuit 1]
With reference to FIG.1 and FIG.2, the circuit structure of the noise removal circuit 1 is illustrated. FIG. 2 is a diagram illustrating a circuit configuration of the removal circuit 3 included in the noise removal circuit 1. The removal circuit 3 generates an output signal OUT. The output signal OUT is a signal obtained by removing noise having a time width equal to or shorter than the noise removal period from the data signal IN.

  The removal circuit 3 includes a shift register 9, a selection circuit 11, and a determination circuit 13. The shift register 9 includes N-stage (N is an integer of 2 or more) flip-flops FF (1) to FF (N) (hereinafter, the term “flip-flop” is omitted, and reference numerals “FF (1) ˜ Only FF (N) "is described. FF (1) to FF (N) are connected in series.

  A clock signal CLK having a period T is input to FF (1) to FF (N) from a CPU (not shown) via a clock line L1. The CPU corresponds to a CPU 200 described later (see FIG. 5). FF (1) to FF (N) delay the input signal by a predetermined time (for example, one cycle of the clock signal CLK), and generate delayed signals S (1) to S (N), respectively.

  The input signal to the first stage FF (1) is the data signal IN. The data signal IN is input from the CPU via the data line L2. For example, the data signal IN is a serial data signal including an H (high) level signal (first level signal) and an L (low) level signal (second level signal). Input signals to FF (2) to FF (N) are delay signals S (1) to S (N-1) output from FF (1) to FF (N-1), respectively.

  The delay signal S (1) to the delay signal S (N) are input to the selection circuit 11. According to the set value P set in the register 5, the selection circuit 11 selects two or more delay signals S (1) to S (n) (n is 2) from the delay signals S (1) to S (N). The integer N or less is selected, and the delay signal S (1) to the delay signal S (n) are output to the determination circuit 13 as the delay signal s (1) to the delay signal s (n). The larger the selection number n, the longer the noise removal period, and the smaller the selection number n, the shorter the noise removal period. Details of the noise removal period will be described later.

  The determination circuit 13 counts the number of H level signals included in the data signal IN in a period (for example, the selected number n × period T) corresponding to the set value P, and generates an output signal OUT corresponding to the counting result. . As a result, the output signal OUT from which noise is removed can be generated with a simple circuit configuration.

  For example, the determination circuit 13 determines the level corresponding to the H level in response to the number of H level signals included in the data signal IN being greater than the number of L level signals in the period corresponding to the set value P. Output signal OUT is generated (majority processing). Alternatively, for example, the determination circuit 13 responds to detecting that a predetermined number (for example, the selection number n) of H level signals are continuously included in the data signal IN in a period corresponding to the set value P. Thus, an output signal OUT having a level corresponding to the H level is generated (match determination processing).

  Specifically, it is as follows. Based on the delay signal s (1) to the delay signal s (n), the determination circuit 13 generates the output signal OUT from which noise having a time width equal to or shorter than the noise removal period is removed. In the first embodiment, a majority circuit and a coincidence circuit will be described as examples of the determination circuit 13. The output signal OUT when the determination circuit 13 is a majority circuit is referred to as an output signal OUTM. The output signal OUT when the determination circuit 13 is a coincidence circuit is referred to as an output signal OUTS.

  The decision circuit 13 as a majority circuit counts the number Nh of the H level and the number Nl (= n−Nh) of the L level of the delay signal s (1) to the delay signal s (n) at the rising edge of the clock signal CLK. . When the number Nh exceeds n / 2, the determination circuit 13 outputs an H level output signal OUTM. The number Nh exceeding n / 2 corresponds to the number of H level signals included in the data signal IN being greater than the number of L level signals in the period corresponding to the set value P. .

  On the other hand, the determination circuit 13 outputs an L level output signal OUTM when the number Nl exceeds n / 2. The fact that the number Nl exceeds n / 2 corresponds to the number of L level signals included in the data signal IN being larger than the number of H level signals in the period corresponding to the set value P. .

  The determination circuit 13 as a coincidence circuit determines whether or not all levels of the delay signal s (1) to the delay signal s (n) coincide at the rising edge of the clock signal CLK. The determination circuit 13 outputs an H level output signal OUTS when all the levels of the delay signals s (1) to s (n) are H levels. Note that the fact that all levels are H levels corresponds to the fact that a predetermined number of H level signals are continuously included in the data signal IN in the period corresponding to the set value P.

  On the other hand, the determination circuit 13 outputs the output signal OUTS of L level when all the levels of the delay signals s (1) to s (n) are L level. Note that the fact that all levels are L levels corresponds to the fact that a predetermined number of L level signals are continuously included in the data signal IN in the period corresponding to the set value P.

[Specific example of noise elimination period]
A specific example of the noise removal period will be described with reference to FIGS. Since the decision circuit 13 as a majority circuit determines the level of the output signal OUTM by majority vote, the noise removal period is described as (n / 2) × T according to the selection number n and the period T of the clock signal CLK. . However, when the selection number n is an odd number, the decimal part of (n / 2) is rounded down. On the other hand, since the determination circuit 13 as the coincidence circuit determines the level of the output signal OUTS by the coincidence determination, the noise removal period is described as (n−1) × T.

[Change of noise removal period, change of frequency f of clock signal CLK]
With reference to FIG. 1 and FIG. 2, the change of the noise removal period and the change of the frequency f (= 1 / T) of the clock signal CLK will be described. Since the noise removal period is defined by the selection number n, in the first embodiment, the selection number n is written in the register 5 as the set value P. The selection number n is provided with a lower limit value and an upper limit value. The lower limit value of the selection number n can be selected from an integer of 2 or more and smaller than the upper limit value. The upper limit value of the selection number n can be selected from an integer that is less than the number of stages N and greater than the lower limit value.

  The lower limit and the upper limit of the noise removal period are set by the lower limit value and the upper limit value of the selection number n, respectively. Further, since the noise removal period is defined by the period T (frequency f), the noise removal period is different if the period T is different even if the selection number n is the same. Accordingly, the lower limit and the upper limit of the noise removal period are provided corresponding to the cycle T (frequency f) of the clock signal CLK.

  In the first embodiment, an example will be described in which the lower limit value and the upper limit value of the stage number N and the selection number n are “16”, “2”, and “16”, respectively. Therefore, the initial value and the final value of the set value P are set to the lower limit value “2” and the upper limit value “16”, respectively. The set value P is incremented by 2 from the initial value as follows.

  At the start of communication (for example, when the power is turned on), the CPU interface 7 writes the initial value of the setting value P into the register 5. Then, the CPU interface 7 rewrites or does not rewrite the set value P of the register 5 in accordance with the enable signal EN. Specifically, it is as follows. The enable signal EN is input from the CPU to the CPU interface 7 via the control line L3. The L level enable signal EN indicates that the communication has been executed normally. On the other hand, the H level enable signal EN indicates that a communication error has occurred.

  Therefore, when the enable signal EN is at the L level, the CPU interface 7 does not rewrite the set value P of the register 5 because an appropriate noise removal period is set. As a result, the set value P of the register 5 is maintained, and communication is executed under an appropriate noise removal period.

  On the other hand, when the enable signal EN is at the H level, noise has not been removed, so the CPU interface 7 rewrites the set value P of the register 5. Specifically, the CPU interface 7 updates the setting value P held by the register 5 with a value obtained by adding “2” to the setting value P at the time of receiving the H level enable signal EN (P ← P + 2). ). As a result, communication is performed under a noise removal period that is longer than before the update.

  The CPU interface 7 updates the setting value P held by the register 5 by adding “2” to the setting value P until the enable signal EN becomes L level. As a result, the noise removal period becomes longer stepwise until the enable signal EN becomes L level.

  However, even after the final value of the set value P is written to the register 5, if the enable signal EN is at the H level, the CPU interface 7 writes the initial value of the set value P to the register 5 while the CPU The frequency f of CLK is changed. Specifically, the CPU changes the frequency f of the clock signal CLK from the first value f1 (for example, 100 MHz) to the second value f2 (for example, 50 MHz) (for example, f2 = f1 / 2). The second value f2 indicates a frequency lower than the first value f1.

  Even if the setting value P is the same when the frequency f is the first value f1 and when the frequency f is the second value f2, if the frequency f is changed to the second value f2, the frequency f is the first value during the noise removal period. It becomes longer than when 1 value f1 is set. As a result, after the change of the frequency f, communication is executed under a longer noise removal period.

  Further, the CPU interface 7 adds the setting value P held by the register 5 by adding “2” to the setting value P until the enable signal EN becomes L level as before the frequency f is changed. Update. As a result, even after the frequency f is changed, the noise removal period is increased stepwise until the enable signal EN becomes L level. However, the noise removal period at each stage is longer than the noise removal period at each stage before the frequency f is changed. Therefore, communication is performed under a longer noise removal period than before the change of the frequency f, and an appropriate noise removal period is set.

[Operation of majority circuit]
The operation of the determination circuit 13 as a majority circuit will be described with reference to FIGS. FIG. 3 is a time chart showing the majority operation of the determination circuit 13. FIG. 4 is a diagram for explaining the majority operation of the determination circuit 13. 3 and 4 show an example in which the number of stages N is “16” and the set value P (number of selections n) is “8”. Therefore, the noise removal period is 4T (= (n / 2) × T).

  FIG. 3 shows a rising edge of the clock signal CLK, original data D, data signal IN, delay signal s (1) to delay signal s (8), output signal OUTM, and output signal OUTS. In the description of the majority circuit, the output signal OUTS is ignored. This is because the output signal OUTS is the output signal OUT of the determination circuit 13 as a matching circuit described later.

  The original data D is transmitted from the CPU to the removal circuit 3 in synchronization with the clock signal CLK. However, noise Z0 to noise Z3 are superimposed on the original data D according to the environment where the CPU, the data line L2, and the removal circuit 3 are arranged. Accordingly, the original data D on which the noise Z0 to the noise Z3 are superimposed, that is, the data signal IN is input to the removal circuit 3.

  The data signal IN is sequentially delayed by the shift register 9. As a result, the delay signal S (1) to the delay signal S (16) are generated. The delay time per one of FF (1) to FF (16) is the same time as the cycle T of the clock signal CLK. The selection circuit 11 selects the delay signal S (1) to the delay signal S (8) from the delay signal S (1) to the delay signal S (16) according to the set value P, and the delay signal s (1) to the delay signal. Output as s (8).

  As shown in FIGS. 3 and 4, in the delay signal s (1) to the delay signal s (8) in the sixth cycle, the number of H levels is “5” (> n / 2). Accordingly, in the next seventh cycle, the determination circuit 13 generates an H-level output signal OUTM. The determination circuit 13 generates the H level output signal OUTM until the number of L levels becomes “5” (> n / 2).

  In the delay signal s (1) to the delay signal s (8) in the fifteenth cycle, the number of L levels is “5”. Accordingly, in the next sixteenth cycle, the determination circuit 13 generates the L-level output signal OUTM. The determination circuit 13 generates the L level output signal OUTM until the number of H levels becomes “5”. As a result, the noise Z0 is removed.

  In the delayed signal s (1) to delayed signal s (8) in the 23rd cycle, the number of H levels is “5”. Accordingly, in the next twenty-fourth cycle, the determination circuit 13 generates the H-level output signal OUTM. The determination circuit 13 generates the H level output signal OUTM until the number of L levels becomes “5”. As a result, the noise Z1 is removed.

  Thereafter, similarly, the determination circuit 13 removes noise having a time width equal to or shorter than the noise removal period from the data signal IN, and generates an output signal OUTM corresponding to the original data D.

[Matching circuit operation]
With reference to FIGS. 1 to 3, the operation of the determination circuit 13 as a coincidence circuit will be described. An example in which the number of stages N is “16” and the setting value P (number of selections n) is “5” will be described. Therefore, in the description of the coincidence circuit, the delay signal s (6) to the delay signal s (8) are ignored in FIG. The noise removal period is 4T (= (n−1) × T).

  As shown in FIG. 3, in the sixth cycle, the levels of all the delayed signals s (1) to delayed signals s (5) become the H level. Accordingly, in the next seventh cycle, the determination circuit 13 generates the H-level output signal OUTS. The determination circuit 13 generates the output signal OUTM at the H level until all the delay signals s (1) to s (5) have the L level.

  In the sixteenth cycle, the levels of all the delayed signals s (1) to delayed signals s (5) become L level. Accordingly, in the next seventeenth cycle, the determination circuit 13 generates the L level output signal OUTS. The determination circuit 13 generates the L level output signal OUTM until all the delay signals s (1) to s (5) have the H level.

  In the example of FIG. 3 as the coincidence circuit, the levels of all the delayed signals s (1) to delayed signals s (5) do not become the H level in the 17th and subsequent cycles. Therefore, after the 17th cycle, noise is also removed, but H level data included in the original data D is also lost. On the other hand, in the output signal OUTM of the determination circuit 13 as a majority circuit, noise is removed without losing data. Accordingly, it is preferable to employ a majority circuit rather than a coincidence circuit as the determination circuit 13. In the majority circuit, the data determination position after noise removal is more stable than the coincidence circuit.

  As described above with reference to FIGS. 1 and 2, in the first embodiment, the CPU interface 7 increments the set value P every time a communication error occurs, and lengthens the noise removal period stepwise. To do. As a result, an appropriate noise removal period can be automatically set according to the communication environment. Generally, a sufficiently long noise removal period is set so that noise having an unexpected time width can be removed. Therefore, since the number of samplings increases, the processing speed is reduced. On the other hand, in the first embodiment, since an appropriate noise removal period is set according to the communication environment, the number of samplings can be made appropriate.

  In the first embodiment, an upper limit is provided in the noise removal period corresponding to the frequency f of the clock signal CLK. Then, the frequency f of the clock signal CLK is changed to a value lower than that before the occurrence of the communication error according to the occurrence of the communication error after the upper limit noise removal period is set. When the frequency f of the clock signal CLK is lowered, the noise removal period is lengthened even if the set value P is the same.

  That is, the noise removal period is set to be longer stepwise, and when noise cannot be removed even in the upper limit noise removal period, the noise removal period is further lengthened by setting the frequency f low. Therefore, an appropriate noise removal period and frequency f can be automatically set according to the communication environment. As a result, communication can be performed at an appropriate speed. In general, a sufficiently low frequency f is set in a range satisfying the communication specifications so that noise having an unexpected time width can be removed. Therefore, even when the communication environment is good, communication is executed at a low speed.

  Further, in the first embodiment, the CPU interface 7 rewrites the set value P in response to the occurrence of a communication error after the upper limit noise removal period is set. In this case, in the first embodiment, the initial value of the setting value P is written in the register 5. Therefore, even after the frequency f is changed, the CPU interface 7 can increment the set value P every time a communication error occurs, and lengthen the noise removal period stepwise. As a result, an appropriate noise removal period can be automatically set according to the communication environment even after the frequency f is changed.

(Embodiment 2)
With reference to FIG. 5, the communication apparatus 100 in Embodiment 2 of this invention is demonstrated. FIG. 5 is a block diagram of the communication device 100. The communication device 100 includes a CPU 200 and an ASIC (Application Specific Integrated Circuit) 300. The CPU 200 functions as a transmission device. The ASIC 300 functions as a receiving device. The ASIC 300 receives the data signal IN and the clock signal CLK from the CPU 200. For example, serial communication is performed between the CPU 200 and the ASIC 300.

  The ASIC 300 includes a noise removal circuit 1 and a functional block 15. The noise removal circuit 1 includes a removal circuit 3, a register 5, and a CPU interface 7. The circuit configuration and operation of the noise removal circuit 1 are the same as the circuit configuration and operation of the noise removal circuit 1 according to the first embodiment described with reference to FIGS. The functional block 15 is a circuit that realizes a function corresponding to the application of the ASIC 300. An output signal (a signal from which noise having a duration less than or equal to the noise removal period is removed) OUT generated by the removal circuit 3 is input to the functional block 15 via the CPU interface 7.

  The CPU 200 supplies (transmits) the clock signal CLK to the ASIC 300 via the clock line L1. The CPU 200 transmits the data signal IN to the ASIC 300 via the data line L2 in synchronization with the clock signal CLK. The CPU 200 transmits an enable signal EN to the ASIC 300 via the control line L3.

  The CPU 200 changes the frequency f of the clock signal CLK to a value lower than that before the occurrence of the communication error in response to the occurrence of the communication error after the upper limit noise removal period is set.

  The CPU 200 detects whether or not a communication error has occurred, for example, as follows. The CPU 200 transmits a data signal IN to the ASIC 300. The ASIC 300 receives the data signal IN. The ASIC 300 transmits an output signal OUT generated from the data signal IN to the CPU 200 via the data line L2.

  The CPU 200 compares the transmitted data signal IN with the received output signal OUT. Then, when the contents indicated by the data signal IN and the output signal OUT match (that is, when communication is normally executed), the CPU 200 sets the enable signal EN to the L level and transmits it to the ASIC 300. On the other hand, when the contents indicated by the data signal IN and the output signal OUT do not match (that is, when a communication error occurs), the CPU 200 sets the enable signal EN to the H level and transmits it to the ASIC 300.

  As described above with reference to FIG. 5, according to the second embodiment, the communication device 100 includes the same noise removal circuit 1 as that of the first embodiment. Therefore, the second embodiment has the same effect as the first embodiment. In addition, the CPU 200 can execute communication at an appropriate speed according to the communication environment by changing the frequency f of the clock signal CLK according to the communication environment (installation environment of the communication device 100).

(Embodiment 3)
With reference to FIG.5 and FIG.6, the noise removal method in Embodiment 3 of this invention is demonstrated. FIG. 6 is a flowchart showing the noise removal method. The noise removal method is executed by the communication device 100 described with reference to FIG.

  In step S <b> 1, the CPU interface 7 of the ASIC 300 writes a set value P (lower limit value of the selection number n) indicating the lower limit of the noise removal period in the register 5. Step S1 corresponds to a step of holding a set value P for setting the noise removal period.

  In step S <b> 3, the CPU 200 transmits a data signal IN to the ASIC 300. Then, the ASIC 300 receives the data signal IN. Step S3 corresponds to a step of receiving the data signal IN in synchronization with the clock signal CLK. In step S5, the removal circuit 3 of the ASIC 300 removes noise having a time width equal to or shorter than the noise removal period corresponding to the set value P from the data signal IN. Step S5 corresponds to a step of removing noise having a time width equal to or shorter than the noise removal period included in the received data signal IN according to the set value P.

  In step S7, the CPU 200 determines whether a communication error has occurred. If an affirmative determination (Yes) is made in step S7, the process proceeds to step S11. On the other hand, if a negative determination (No) is made in step S7, the process proceeds to step S9.

  In step S9, the CPU 200 determines whether or not communication is completed. If a positive determination (Yes) is made in step S9, the process ends. On the other hand, if a negative determination (No) is made in step S9, the process proceeds to step S3.

  After an affirmative determination is made in step S7, in step S11, the CPU interface 7 determines whether or not the register 5 holds a set value P (an upper limit value of the selection number n) indicating the upper limit of the noise removal period. To do. If an affirmative determination (Yes) is made in step S11, the process proceeds to step S15. On the other hand, if a negative determination (No) is made in step S11, the process proceeds to step S13.

  In step S13, the CPU interface 7 rewrites the set value P so that the noise removal period becomes longer. Step S13 corresponds to a step of rewriting the set value P so that the noise removal period becomes longer each time a communication error occurs. For example, the CPU interface 7 writes a value obtained by adding “2” to the setting value P to the register 5 as a new setting value P (P ← P + 2). Thereafter, the process proceeds to step S3.

  After an affirmative determination is made in step S11, in step S15, the CPU 200 changes the frequency f of the clock signal CLK to a value lower than that before the occurrence of the communication error. Then, the process proceeds to step S1. Step S15 corresponds to a step of changing the frequency f of the clock signal CLK to a value lower than that before the occurrence of the communication error in response to the occurrence of the communication error after the upper limit noise elimination period is set.

  As described above with reference to FIGS. 5 and 6, according to the third embodiment, the communication apparatus 100 includes the same noise removal circuit 1 as that of the first embodiment, thereby executing the noise removal method. Therefore, the third embodiment has the same effect as the first embodiment. In addition, the CPU 200 can execute communication at an appropriate speed according to the communication environment by changing the frequency f of the clock signal CLK according to the communication environment (installation environment of the communication device 100).

  The present invention is not limited to the above-described embodiment, and can be implemented in various modes without departing from the gist thereof. For example, the following modifications are possible.

  (1) The noise removal circuit 1 according to Embodiment 1 shown in FIG. 1, the communication device 100 according to Embodiment 2 shown in FIG. 5, and the noise removal method according to Embodiment 3 shown in FIG. It can be mounted on an image forming apparatus (not shown). The image forming apparatus is, for example, a copying machine, a printer, or a facsimile. The image forming apparatus is, for example, a multifunction machine having two or more functions of a copying machine, a printer, and a facsimile machine.

  (2) The circuit configuration of the removal circuit 3 is not limited to the circuit configuration shown in FIG. Further, the majority process and the coincidence determination process described with reference to FIGS. 2 to 4 are examples, and the majority process and the coincidence determination process can be realized by other methods.

  The present invention can be installed in various environments and can be used in the field of an apparatus (for example, an image forming apparatus) in which the time width of noise superimposed on a data signal cannot be predicted.

DESCRIPTION OF SYMBOLS 1 Noise removal circuit 3 Removal circuit 5 Register 7 CPU interface 100 Communication apparatus 200 CPU
300 ASIC

Claims (8)

A holding circuit for holding a setting value for setting a noise removal period;
A removal circuit that receives a data signal in synchronization with a clock signal and removes noise having a time width equal to or less than the noise removal period included in the data signal according to the set value;
And a rewriting circuit that rewrites the set value so that the noise removal period becomes longer each time a communication error occurs. In the noise removal period, an upper limit is provided corresponding to the frequency of the clock signal,
2. The noise according to claim 1, wherein the frequency of the clock signal is changed to a lower value than before the occurrence of the communication error in response to the occurrence of a communication error after the upper limit noise elimination period is set. Removal device.   3. The noise removal device according to claim 2, wherein the rewriting circuit rewrites the set value in response to the occurrence of the communication error after the upper limit noise removal period is set. The data signal includes a first level signal and a second level signal;
The said removal circuit counts the number of the said 1st level signal in the period corresponding to the said setting value, and produces | generates the output signal corresponding to a count result. Noise removal device.   In the period corresponding to the set value, the removal circuit has the level corresponding to the first level in response to the number of the first level signals being greater than the number of the second level signals. The noise removal circuit according to claim 4, which generates an output signal. A transmitting device;
A receiver for receiving a data signal and a clock signal from the transmitter;
The receiving device is:
A holding circuit for holding a setting value for setting a noise removal period;
A removal circuit that receives the data signal in synchronization with the clock signal and removes noise having a time width equal to or less than the noise removal period included in the data signal according to the set value;
A rewriting circuit that rewrites the set value so that the noise removal period becomes longer each time a communication error occurs, and
In the noise removal period, an upper limit is provided corresponding to the frequency of the clock signal,
The transmission device changes the frequency of the clock signal to a value lower than that before the occurrence of the communication error in response to a communication error occurring after the upper limit noise elimination period is set. Holding a set value for setting a noise removal period;
Receiving a data signal in synchronization with a clock signal;
Removing noise having a time width equal to or shorter than the noise removal period included in the received data signal according to the set value;
Rewriting the set value so that the noise removal period becomes longer each time a communication error occurs. In the noise removal period, an upper limit is provided corresponding to the frequency of the clock signal,
The method according to claim 7, further comprising: changing a frequency of the clock signal to a lower value than before the occurrence of the communication error in response to a communication error occurring after the upper limit noise elimination period is set. Noise removal method.

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