JP2015032684A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce capacitance fluctuation due to rising of a die bond material during mounting.SOLUTION: A semiconductor device comprises: a semiconductor substrate 1; an insulating layer 2 formed on a first surface 11 of the semiconductor substrate 1; and a semiconductor layer 3 formed on the first surface 11 side of the semiconductor substrate 1 via the insulating layer 2. The semiconductor layer 3 includes: a drain region 33 of a first conductivity type; a well region 34 of a second conductivity type formed in a position different from the drain region 33; and a source region 35 exposed on the first surface 31 side opposite to a second surface 32 facing the insulating layer 2 and formed surrounded by the well region. A closed space 6 surrounded by the semiconductor substrate 1 and the insulating layer 2 is formed on the second surface 32 side of the semiconductor layer 3.

Description

  The present invention relates to a semiconductor device.

  Conventionally, in a semiconductor device having a drift region in which carriers in a semiconductor in which a p layer and an n layer are formed on the surface of a silicon substrate move due to an electric field, parasitic capacitance is generated via the back surface of the silicon substrate. For this reason, it has been pointed out that when a voltage is applied to the semiconductor device, the withstand voltage is lower than the theoretical value due to the influence of the depletion layer in the silicon substrate. As a method for solving such a problem, it is effective to remove silicon on the back side of the portion where the drift region is formed (see, for example, Patent Document 1).

JP-T-2004-510329

  However, in the conventional semiconductor device described in Patent Document 1, the die bond material (silver paste or the like) rises in a region where silicon is removed during mounting, and thus there is a possibility that the capacitance may fluctuate. In other words, in the conventional semiconductor device described in Patent Document 1, since the die bond material penetrates into the region from which the silicon has been removed, the capacitance between the insulating layer and the die bond material may fluctuate. It was.

  The present invention has been made in view of the above points, and an object of the present invention is to provide a semiconductor device that can reduce capacitance variation due to a die bond material during mounting.

  The semiconductor device of the present invention comprises a semiconductor substrate, an insulating layer formed on one surface of the semiconductor substrate, and a semiconductor layer formed on the one surface side of the semiconductor substrate via the insulating layer, The semiconductor layer includes a first conductivity type drain region, a second conductivity type well region formed away from the drain region, and a first surface opposite to the second surface facing the insulating layer. A closed region surrounded by the semiconductor substrate and the insulating layer on the second surface side of the semiconductor layer. The source region of the first conductivity type is exposed to the side and is surrounded by the well region. Is formed.

  In this semiconductor device, the closed space is preferably filled with a sealing material having a relative dielectric constant lower than that of the semiconductor substrate.

  The semiconductor device preferably further includes a second insulating layer that insulates the closed space from the semiconductor substrate.

  In this semiconductor device, the drain electrode formed on the first surface of the semiconductor layer and electrically connected to the drain region, the well region and the source region formed on the first surface of the semiconductor layer And a source electrode electrically connected to the semiconductor layer, a gate insulating layer formed on the first surface of the semiconductor layer, and a gate electrode formed on the gate insulating layer.

  In the present invention, it is possible to reduce the capacity fluctuation due to the rise of the die bond material during mounting, compared to the case where the open space is formed.

1 is a cross-sectional view of a semiconductor device according to a first embodiment. FIG. 6 is a cross-sectional view of a semiconductor device according to a second embodiment. FIG. 6 is a cross-sectional view of a semiconductor device according to a third embodiment.

  In the semiconductor devices according to the following first to third embodiments, a closed space surrounded by a semiconductor substrate and an insulating layer is formed.

  In the first to third embodiments, a case where a semiconductor device is used as a semiconductor switching element in a semiconductor relay will be described. Specifically, a case where the semiconductor device is a photo MOS relay (registered trademark) MOSFET (Metal Oxide Semiconductor Field Effect Transistor) will be described. That is, each of the semiconductor devices of Embodiments 1 to 3 constitutes the relay together with a light emitting element and a light receiving element.

  When a semiconductor device is used for the relay, it is preferable to reduce the figure of merit expressed by the product of the capacitance between the output terminals of the relay and the resistance. That is, it is preferable to reduce the capacity between the output terminals of the relay.

  In the relay, the output terminal capacitance Cout of the relay is the sum of 1/2 of the output capacitance Coss of the MOSFET (semiconductor device) and the package capacitance Cp. Expressed by the equation, Cout = Coss / 2 + Cp. The output capacitance Coss of the MOSFET is the sum of the drain-source capacitance Cds, the drain-gate capacitance Cgd, and the drain-substrate capacitance Cdsub. Expressed as an equation, Coss = Cds + Cgd + Cdsub.

  Hereinafter, the semiconductor device according to the first to third embodiments will be described in detail with reference to the drawings.

(Embodiment 1)
As shown in FIG. 1, the semiconductor device according to the first embodiment includes a semiconductor substrate 1, an insulating layer 2, an N-type (first conductivity type) semiconductor layer 3, a gate insulating layer 4, a gate electrode 51, and the like. , A drain electrode 52 and a source electrode 53 are provided. In the semiconductor device according to this embodiment, the semiconductor substrate 1, the insulating layer 2, and the semiconductor layer 3 have an SOI (Silicon On Insulator) structure.

  The semiconductor substrate 1 is made of, for example, single crystal silicon.

  The insulating layer 2 is formed on the first surface (one surface) 11 of the semiconductor substrate 1. The insulating layer 2 is an oxide film, for example. Examples of the oxide film include a silicon oxide film.

  The semiconductor layer 3 is formed on the first surface 11 side of the semiconductor substrate 1 via the insulating layer 2. The semiconductor layer 3 is an N-type semiconductor layer such as an N-type silicon layer, for example.

  The semiconductor layer 3 includes a drain region 33, a well region 34, a source region 35, and a drift region 36. The drain region 33 is an N + type (first conductivity type) drain region. The drain region 33 is exposed on the first surface 31. The well region 34 is a P-type (second conductivity type) well region formed away from the drain region 33. The well region 34 is formed so as to reach the second surface 32 from the first surface 31 at a position different from the drain region 33. The source region 35 is an N + type (first conductivity type) source region formed on the first surface (one surface) 31 side surrounded by the well region 34. The source region 35 is formed so as to be exposed on the first surface 31 in the well region 34. The drift region 36 is interposed between the end of the drain region 33 and the end of the well region 34.

  The gate insulating layer 4 is formed on the first surface 31 of the semiconductor layer 3. The gate insulating layer 4 is formed on a portion of the semiconductor layer 3 between the source region 35 and the drift region 36. For example, an oxide film is used as the gate insulating layer 4.

  The gate electrode 51 is formed on the gate insulating layer 4. The gate electrode 51 is electrically connected to a gate electrode pad (not shown).

  The drain electrode 52 is formed on the drain region 33 of the semiconductor layer 3. The drain electrode 52 is electrically connected to the drain region 33. The drain electrode 52 is electrically connected to a drain electrode pad (not shown).

  The source electrode 53 is formed on the first surface 31 of the semiconductor layer 3 so as to straddle the well region 34 and the source region 35. The source electrode 53 is electrically connected to the well region 34 and the source region 35. The source electrode 53 is electrically connected to a source electrode pad (not shown).

  In such a semiconductor device, a closed space 6 is formed on the second surface 32 side of the semiconductor layer 3, that is, on the insulating layer 2 side. The closed space 6 is surrounded by the semiconductor substrate 1 and the insulating layer 2. That is, silicon on the second surface 32 side of the drain region 33 and the well region 34 in the semiconductor substrate 1 is removed to form the closed space 6. Since the relative dielectric constant of silicon is 12, whereas the relative dielectric constant of air is 1.0006, when the semiconductor substrate 1 is a silicon substrate, the region having a lower relative dielectric constant than the semiconductor substrate 1 is defined as a semiconductor. A closed space 6 that does not penetrate to the second surface 12 of the substrate 1 is formed.

  Here, the drain-substrate capacitance Cdsub is obtained by the capacitance C1 of the semiconductor substrate 1, the capacitance C2 of the closed space 6, and the capacitance C3 of the insulating layer 2. Specifically, 1 / Cdsub = 1 / C1 + 1 / C2 + 1 / C3. The capacitance C1 of the semiconductor substrate 1 is determined by the relative dielectric constant ε1 of the semiconductor substrate 1, the dielectric constant ε0 of vacuum, the thickness t1 of the semiconductor substrate 1, and the area A1. Expressed as an equation, C1 = ε1 · ε0 · A1 / t1. The capacity C2 of the closed space 6 is obtained from the relative dielectric constant ε2 of the closed space 6, the dielectric constant ε0 of vacuum, the distance t2 of the closed space 6, and the area A2. Expressed by the equation, C2 = ε2 · ε0 · A2 / t2. The capacitance C3 of the insulating layer 2 is obtained from the relative dielectric constant ε3 of the insulating layer 2, the dielectric constant ε0 of vacuum, the thickness t3 of the insulating layer 2, and the area A3. Expressed by the equation, C3 = ε3 · ε0 · A3 / t3.

  As described above, since the relative dielectric constant ε2 (= 1.0006) of the closed space 6 is smaller than the relative dielectric constant ε1 (= 12) of the semiconductor substrate 1, 1 / C1 + 1 / C2 of this embodiment is the closed space. 6 is larger than the reciprocal of the capacity of the semiconductor substrate in the semiconductor device in which 6 is not formed.

  Therefore, the drain-substrate capacitance Cdsub of the semiconductor device according to the present embodiment is smaller than the drain-substrate capacitance of the semiconductor device in which the closed space 6 is not formed.

  Although not shown, the semiconductor device of this embodiment is mounted on a frame using a die bond material. As the die bond material, for example, a silver paste is used. The semiconductor device is mounted on the frame such that the second surface 12 of the semiconductor substrate 1 faces the frame. At this time, a die bond material is provided around the second surface 12 and the second surface 12 side of the semiconductor substrate 1.

  In the semiconductor device of this embodiment, since the closed space 6 that does not penetrate the second surface 12 side of the semiconductor substrate 1 is formed, the die bonding material does not enter the closed space 6 during mounting. That is, the die bond material does not rise to the insulating layer 2 side.

  Therefore, even if the semiconductor device is mounted on the frame, the drain-substrate capacitance Cdsub does not change. On the other hand, when a space opened on the second surface side of the semiconductor substrate is formed, the die bond material penetrates into the space from the second surface side of the semiconductor substrate during mounting, and the die bond material becomes an insulating layer in the space. Raise to the 2nd side. For this reason, there exists a possibility that a capacity | capacitance may fluctuate.

  In the semiconductor device according to the present embodiment described above, the closed space 6 is formed on the second surface 32 side of the semiconductor layer 3 with the insulating layer 2 interposed therebetween, so that the closed space 6 is not formed. Thus, the facing area between the drain region and the semiconductor substrate can be reduced. Thereby, the semiconductor device according to the present embodiment can reduce the drain-substrate capacitance Cdsub as compared to the case where the closed space 6 is not formed. As a result, according to the semiconductor device of the present embodiment, the output capacity of the semiconductor device can be reduced, and further, the capacity between the output terminals of the semiconductor relay can be reduced.

  Further, in the semiconductor device according to the present embodiment, a closed space 6 that does not penetrate the semiconductor substrate 1 is formed on the second surface 12 side. As a result, the semiconductor device according to the present embodiment prevents the die bond material (such as silver paste) from rising during mounting, unlike the case where a space opened on the second surface side of the semiconductor substrate is formed. can do. As a result, the semiconductor device according to the present embodiment can reduce capacitance variation due to the rise of the die bond material during mounting, as compared with the case where an open space is formed.

(Embodiment 2)
The semiconductor device according to the second embodiment is different from the semiconductor device according to the first embodiment (see FIG. 1) in that the closed space 6 is filled with a sealing material 7 as shown in FIG. Note that the same components as those of the semiconductor device according to the first embodiment are denoted by the same reference numerals, and description thereof is omitted.

  The closed space 6 is filled with a sealing material 7 having a dielectric constant lower than that of the semiconductor substrate 1. The sealing material 7 is, for example, quartz, polyimide, glass or the like. The relative dielectric constant of silicon is 12, whereas the relative dielectric constant of quartz and polyimide is 3.5, and the relative dielectric constant of glass (epoxy glass) is 5.0. Therefore, when the semiconductor substrate 1 is a silicon substrate, the capacity can be reduced even when the closed space 6 is filled with the sealing material 7 as compared with the case where the closed space 6 is not formed.

  In the semiconductor device according to the present embodiment described above, the mechanical strength in the thickness direction of the semiconductor substrate 1 can be increased by filling the closed space 6 with the sealing material 7. That is, in the semiconductor device according to the present embodiment, the strength against external force and thermal stress can be increased by the sealing material 7 in the closed space 6. For example, when a semiconductor device that has been diced into a chip is packaged, the strength can be increased with respect to an impact when picking up the chip and a force applied when bonding a wire to a drain electrode pad or the like.

(Embodiment 3)
As shown in FIG. 3, the semiconductor device according to the third embodiment is different from the semiconductor device according to the second embodiment (see FIG. 2) in that it further includes a second insulating layer 8. Note that the same components as those of the semiconductor device according to the second embodiment are denoted by the same reference numerals, and description thereof is omitted.

  The semiconductor device according to this embodiment further includes a second insulating layer 8 that insulates the closed space 6 from the semiconductor substrate 1.

  The second insulating layer 8 is formed on the first surface 11 of the semiconductor substrate and the peripheral surface of the closed space 6. That is, the second insulating layer 8 is formed so as to surround the closed space 6 together with the insulating layer 2. The second insulating layer 8 is an oxide film, for example. Examples of the oxide film include a silicon oxide film. In the present embodiment, the closed space 6 is electrically insulated from the surrounding semiconductor substrate 1 by the second insulating layer 8.

  The drain-substrate capacitance Cdsub of the semiconductor device according to the present embodiment is obtained by the capacitance C1 of the semiconductor substrate 1, the capacitance C2 of the closed space 6, the capacitance C3 of the insulating layer 2, and the capacitance C4 of the second insulating layer 8. . Specifically, 1 / Cdsub = 1 / C1 + 1 / C2 + 1 / C3 + 1 / C4. The capacitance C4 of the second insulating layer 8 is determined by the relative dielectric constant ε4 of the second insulating layer 8, the dielectric constant ε0 of the vacuum, the thickness t4 of the second insulating layer 8, and the area A4. Expressed by the equation, C4 = ε4 · ε0 · A4 / t4.

  Therefore, the drain-substrate capacitance Cdsub of the semiconductor device according to the present embodiment is smaller than the drain-substrate capacitance of the semiconductor device that does not include the second insulating layer 8.

  The semiconductor device according to the present embodiment described above includes the second insulating layer 8 so as to insulate the closed space 6 from the semiconductor substrate 1. Thereby, the semiconductor device according to the present embodiment can reduce the drain-substrate capacitance Cdsub and improve the insulating property as compared with the semiconductor device that does not include the second insulating layer 8.

  Note that the second insulating layer 8 according to the present embodiment may be applied to the semiconductor device according to the first embodiment (see FIG. 1). In other words, the closed space 6 that is not filled with the sealing material 7 may be insulated from the surrounding semiconductor substrate 1 by the second insulating layer 8. Even in such a case, the drain-substrate capacitance can be reduced and the insulation can be improved as compared with the semiconductor device not provided with the second insulating layer 8.

  The semiconductor device according to the first to third embodiments has a configuration in which the first conductivity type is N-type and the second conductivity type is P-type. As a modification of the semiconductor device according to the first to third embodiments, the first The conductivity type may be P-type and the second conductivity type may be N-type.

1 Semiconductor substrate 11 First surface (one surface)
DESCRIPTION OF SYMBOLS 2 Insulating layer 3 Semiconductor layer 31 1st surface 32 2nd surface 33 Drain region 34 Well region 35 Source region 4 Gate insulating layer 51 Gate electrode 52 Drain electrode 53 Source electrode 6 Closed space 7 Sealing material 8 Second insulating layer

Claims (4)

A semiconductor substrate;
An insulating layer formed on one surface of the semiconductor substrate;
A semiconductor layer formed on the one surface side of the semiconductor substrate via the insulating layer,
The semiconductor layer is
A drain region of a first conductivity type;
A second conductivity type well region formed apart from the drain region;
A first conductivity type source region exposed on the first surface side opposite to the second surface facing the insulating layer and surrounded by the well region;
In the semiconductor layer, a closed space surrounded by the semiconductor substrate and the insulating layer is formed on the second surface side.   The semiconductor device according to claim 1, wherein the closed space is filled with a sealing material having a relative dielectric constant lower than that of the semiconductor substrate.   The semiconductor device according to claim 1, further comprising a second insulating layer that insulates the closed space from the semiconductor substrate. A drain electrode formed on the first surface of the semiconductor layer and electrically connected to the drain region;
A source electrode formed on the first surface of the semiconductor layer and electrically connected to the well region and the source region;
A gate insulating layer formed on the first surface of the semiconductor layer;
The semiconductor device according to claim 1, further comprising: a gate electrode formed on the gate insulating layer.

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