JP2010062331A - Semiconductor device for electric power - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a capacitor-incorporated semiconductor device for electric power whose manufacturing cost can be reduced. <P>SOLUTION: The semiconductor device for electric power includes: an MOSFET 2 having an n-type drift layer 12; a columnar p-type drift layer 14 cyclically arranged in the n-type drift layer 12, a drain electrode 39 on an upper surface of the n-type drift layer 12; a p-type base layer 15 connected to the p-type drift layer 14 above the n-type drift layer 12; an n-type source layer 17 on a surface of the p-type base layer 15; a source electrode 33 on surfaces of the p-type drift layer 12 and n-type source layer 17, and a gate electrode 31 provided on an upper surface of the n-type drift layer 12 with a gate insulating film 21 interposed; a capacitor 3 having an n-type channel stopper layer 18 on a surface of the n-type semiconductor layer 12a, and a capacitor insulating film 25 on a surface of the n-type channel stopper layer 18 and a capacitor electrode 37 on a surface of the capacitor insulating film 25 apart from the MOSFET 2; and a metal material 55 for connecting the capacitor electrode 37 and source electrode 33 to each other. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a power semiconductor device with a built-in capacitor.

  A power semiconductor device using a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) as a switching element for power control is used. The MOSFET is intermittently turned on and off to perform power control and the like. In particular, a so-called surge voltage is generated due to an abrupt change in drain current during switching at turn-off and wiring inductance of a switching circuit including a MOSFET.

  If the voltage between the drain and source of the MOSFET exceeds the withstand voltage due to the surge voltage, the MOSFET may be destroyed. In order to reduce the surge voltage applied to the drain, a capacitor is connected in parallel between the drain and the source to reduce the surge voltage. Connecting a capacitor to the outside of a MOSFET is widely performed, but an increase in the number of components that are capacitors and an increase in the number of steps for connecting the components occur.

  Thus, a MOSFET in which capacitors are integrally formed is disclosed (for example, see Patent Document 1). That is, the capacitor is provided inside the semiconductor substrate or semiconductor layer constituting the MOSFET, and one electrode of the capacitor is electrically connected to the source electrode, and the other electrode of the capacitor is electrically connected to the drain electrode. This is a MOSFET having a structure.

However, since the disclosed MOSFET does not require an external capacitor, the capacitor does not increase the number of components and increase the number of component connection processes. However, the capacitor has both electrodes at the MOSFET drain and source, respectively. Since the capacitor is internally connected and integrated, a capacitor characteristic defect becomes a characteristic defect of a MOSFET with a built-in capacitor, which causes a problem of a decrease in manufacturing yield. That is, the disclosed MOSFET is manufactured by adding a manufacturing process of a highly difficult capacitor embedded in a semiconductor substrate or a semiconductor layer to a manufacturing process of manufacturing a single MOSFET structure. Each is internally connected to the gate and source of the MOSFET. The manufacturing yield of the MOSFET with a built-in capacitor is a product of these two manufacturing yields, and it is difficult to avoid a decrease in manufacturing yield compared to the manufacturing yield of the MOSFET alone. As a result, the manufacturing cost increases. Further, if the capacitor has poor characteristics, there is a problem that it is difficult to effectively utilize only the MOSFET structure portion even if the MOSFET structure portion operates normally.
JP 2004-22644 A

  The present invention provides a power semiconductor device with a built-in capacitor capable of suppressing the manufacturing cost.

  A power semiconductor device of one embodiment of the present invention includes a first conductive type first semiconductor layer and a plurality of columnar second conductive types that are periodically arranged in the first semiconductor layer in a direction along the film surface. A second semiconductor layer, a first electrode provided on a surface of one side of the first semiconductor layer and electrically connected to the first semiconductor layer, and a surface region on the other side of the first semiconductor layer A plurality of second-conductivity-type third semiconductor layers selectively connected to the second semiconductor layer, and a first-conductivity-type fourth semiconductor layer selectively provided on the surface of the third semiconductor layer A second electrode provided in contact with the surfaces of the third semiconductor layer and the fourth semiconductor layer, and a gate insulating film on the first semiconductor layer between the adjacent third semiconductor layers. A power switching element having a gate electrode and a surface of the first semiconductor layer. A first conductive type fifth semiconductor layer; a capacitor insulating film provided on a surface of the fifth semiconductor layer and spaced apart from the power switching element; and a capacitor electrode provided on the surface of the capacitor insulating film. A capacitor and a conductive material having a separation portion from the power switching element that connects the capacitor electrode and the second electrode are provided.

  ADVANTAGE OF THE INVENTION According to this invention, the power semiconductor device with a built-in capacitor which can suppress manufacturing cost can be provided.

  Embodiments of the present invention will be described below with reference to the drawings. In the figure shown below, the same code | symbol is attached | subjected to the same component.

  A power semiconductor device according to an embodiment of the present invention will be described with reference to FIGS. FIG. 1 is a circuit diagram showing a connection between a MOSFET and a capacitor of a power semiconductor device. 2 is a diagram schematically showing the configuration of a semiconductor chip of a power semiconductor device, FIG. 2 (a) is a plan view, and FIG. 2 (b) is a cross-sectional view taken along line AA in FIG. 2 (a). FIG. 2C is a cross-sectional view taken along the line BB in FIG. In the cross-sectional view, the protective film on the surface is omitted. FIG. 3 is a diagram schematically showing connections outside the semiconductor chip of the power semiconductor device. In the following description, the surface side of the semiconductor chip on which the gate electrode is formed is the top.

  As shown in FIG. 1, the power semiconductor device 101 includes a semiconductor chip 1 having an n-channel MOSFET 2 and a capacitor 3, and the drain of the MOSFET 2 and one electrode terminal of the capacitor 3 are connected inside the semiconductor chip 1. The source of the MOSFET 2 and the other electrode terminal of the capacitor 3 are connected to the outside of the semiconductor chip 1. That is, the capacitor 3 is connected in parallel between the drain and source of the MOSFET 2. The MOSFET 2 has a gate that is a control electrode.

  2 and 3, the first conductivity type is n-type, the second conductivity type is p-type, and the power semiconductor device 101 includes an n-type drift layer 12 which is an n-type first semiconductor layer. A p-type drift layer 14 which is a plurality of columnar p-type second semiconductor layers periodically arranged in the direction along the film surface in the n-type drift layer 12, and one side of the n-type drift layer 12 The drain electrode 39 which is a first electrode electrically connected to the n-type drift layer 12 and the p-type drift layer 14 selectively provided in the surface region on the other side of the n-type drift layer 12. A p-type base layer 15 which is a plurality of p-type third semiconductor layers connected to the n-type source layer 17 and an n + -type source layer 17 which is an n-type fourth semiconductor layer selectively provided on the surface of the p-type base layer 15; , The second power provided so as to be in contact with the surfaces of the p-type base layer 15 and the n-type source layer 17. MOSFET 2 that is a power switching element having a source electrode 33 and a gate electrode 31 provided on the n-type drift layer 12 between adjacent p-type base layers 15 via a gate insulating film 21; An n + type channel stopper layer 18 which is an n type fifth semiconductor layer provided on the surface of the n type semiconductor layer 12 a extending from the n type drift layer 12, and provided on the surface of the n + type channel stopper layer 18 apart from the MOSFET 2. A capacitor 3 having a capacitor insulating film 25 and a capacitor electrode 37 provided on the surface of the capacitor insulating film 25; and a metal material 55 which is a conductive material connecting the capacitor electrode 37 and the source electrode 33. ing.

  As shown in FIG. 2A, the MOSFET 2 and the capacitor 3 are each formed in a substantially rectangular shape on the same semiconductor chip 1. In the semiconductor chip 1, a MOSFET 2 is formed on one side, for example, the left side of the drawing, and a capacitor 3 is formed on the other side, for example, the right side of the drawing.

  The MOSFET 2 has a cell region 5 that constitutes the MOSFET on the inside, with the three peripheral portions at the left end of the semiconductor chip 1 and the cell / termination boundary 7 on the near side reaching the capacitor 3 facing the capacitor 3 as a boundary. And a termination region 9 is disposed outside the cell / termination boundary 7.

  The cell region 5 has a substantially rectangular gate electrode pad 41 and source electrode pad 43 on the upper surface in a state where it can be connected to a metal material or the like from the outside. In the cell region 5, a plurality of cells serving as units constituting a super junction structure MOSFET described later are arranged. A potential for gate control is applied to each cell via a gate main wiring 42 connected to the gate electrode pad 41. The gate main wiring 42 has a rectangular shape with rounded corners along the peripheral portion of the cell region 5, but may have other forms such as a comb-teeth shape.

  The termination region 9 is formed so as to surround the cell region 5 with a substantially constant width except for rounded corners for the purpose of obtaining the breakdown voltage of the MOSFET 2.

  The capacitor 3 has a substantially rectangular capacitor electrode pad 45 on the upper surface in a state where it can be connected to a metal material or the like from the outside. The capacitor electrode 37, part of which forms the capacitor electrode pad 45, has a boundary on the right side of the three sides of the semiconductor chip 1 and the front side of the MOSFET 2 on the side facing the MOSFET 2, and is substantially rectangular.

  As shown in FIG. 2B, the cell shown in the cross section along the line AA in FIG. 2A includes an n-type drift layer 12 and a plurality of columnar shapes formed in the n-type drift layer 12. The p-type drift layer 14 has a super junction structure. An n + -type drain layer 11 having a higher concentration than the n-type drift layer 12 is formed on the lower surface of the n-type drift layer 12, and the n + -type drain layer 11 is on the surface opposite to the n-type drift layer 12. A drain electrode 39 is formed. The drain electrode 39 is connected to the drain terminal (D). The n-type drift layer 12 and the n + -type drain layer 11 may be formed by diffusing impurities on one surface of the n-type drift layer 12 to form the n + -type drain layer 11 or by using the n + -type drain layer 11 as a substrate. As an alternative, the n-type drift layer 12 may be crystal-grown.

  In the upper surface region of the n-type drift layer 12, a p-type base layer 15 corresponding to each p-type drift layer 14 and connected to the p-type drift layer 14 extends in a direction perpendicular to the paper surface. It is formed in a stripe shape. On the surface of each p-type base layer 15, an n + -type source layer 17 is formed in a stripe shape so as to extend in a direction perpendicular to the paper surface. The p-type base layer 15 becomes a channel. Two cells adjacent to each other in the cell region 5 have a relationship formed by juxtaposing and connecting the left end portion of the illustrated cell to the right end portion of the cell having the same structure without any gap.

  For example, in contact with the two p-type base layers 15 that are spaced apart, the n-type drift layer 12 between the two p-type base layers 15, and the n + -type source layer 17 provided in these p-type base layers 15, A gate insulating film 21 made of a silicon oxide film and having a thickness of about 1 μm is formed in a stripe shape so as to extend in a direction perpendicular to the paper surface. On the gate insulating film 21, the gate electrodes 31 are formed in stripes so as to extend in a direction perpendicular to the paper surface. The gate electrode 31 is connected to a common gate terminal (G).

  In two adjacent cells (not shown), two n + -type source layers 17 provided on the p-type base layer 15 in a region sandwiched between adjacent gate electrodes 31, and these n + -type source layers 17 The source electrode 33 is formed in a stripe shape in a direction perpendicular to the paper surface so as to be in contact with the p-type base layer 15 therebetween. The source electrode 33 is connected to a common source terminal (S). The gate electrode 31 and the source electrode 33 are electrically insulated by an insulating film (not shown).

  As shown in FIG. 2 (c), the semiconductor chip 1 has a termination region 9 disposed around the cell region 5 of the MOSFET 2 and a capacitor 3 on the surface side adjacent to the termination region 9. Under the outer peripheral portion and the capacitor 3, an n-type semiconductor layer 12a including a drain electrode 39, an n + -type drain layer 11, and an n-type drift layer 12 extending from the lower surface is provided. In addition, an n + type channel stopper layer 18 having substantially the same impurity concentration and film thickness as the n + type source layer 17 is commonly provided. The n + -type channel stopper layer 18 has a constant potential at the outer periphery of the MOSFET 2 as an equivalent potential ring (EQPR).

  The termination region 9 has a field insulating film 23 made of, for example, a silicon oxide film on the n + type channel stopper layer 18, and a stopper electrode 35 connected to the n + type channel stopper layer 18 at the end of the field insulating film 23. Is formed. The stopper electrode 35 is disposed so as to go around the outer periphery of the surface of the MOSFET 2, and is connected to the drain electrode 39 via a lower n-type semiconductor layer. The distance from the stopper electrode 35 in the termination region 9 to the end of the cell region 5 can be made suitable depending on the required breakdown voltage or the like. It is possible to form a RESURF (Reduced Surface Field) structure, a guard ring structure, or the like at the end of the cell region 5 or the termination region 9 up to the n + -type channel stopper layer 18.

  In the capacitor 3, a capacitor insulating film 25 made of, for example, a silicon oxide film having a film thickness similar to that of the field insulating film 23 is formed on the n + -type channel stopper layer 18 continuously arranged from the termination region 9. A capacitor electrode 37 having a film thickness similar to that of the stopper electrode 35 is formed on the film 25 so as to be separated from the stopper electrode 35.

  The capacitor electrode 37 is made of an Al alloy like the stopper electrode 35, and the capacitor electrode pad 45 is exposed so that the Al alloy can be connected to the outside, like the gate electrode pad 41 and the source electrode pad 43. ing. Here, Si and / or Cu is added to the Al alloy. In place of the Al alloy, Cu or an alloy containing Cu as a main component can be used.

As described above, in the capacitor 3, the capacitor insulating film 25 can be manufactured by the same process as the field insulating film 23, for example, by the CVD method, and the capacitor electrode 37 can be manufactured by the same process as the stopper electrode 35, for example, by the sputtering method. It can be produced. For example, by setting the thickness of the capacitor insulating film 25 made of a silicon oxide film to about 100 nm and the area of the capacitor electrode 37 to about 0.34 mm ² , the capacitance can be set to about 118 pF. The capacitor 3 has a MIS (Metal Insulator Semiconductor) structure, and the capacitance can be easily changed in proportion to the area.

  Further, by forming the capacitor insulating film 25 in a separate process from the field insulating film 23, it is possible to widen the change range of the capacitance. That is, the area occupied by the capacitor 3 can be reduced by using, for example, a silicon nitride film, an aluminum oxide film, a tantalum oxide film, or the like having a relative dielectric constant higher than that of the silicon oxide film. In addition, the occupied area can be reduced by forming the silicon oxide film thin.

  As shown in FIG. 3, the power semiconductor device 101 rotates the semiconductor chip 1 shown in FIG. 2A by 90 degrees on an internal lead 51 made of, for example, Cu, and thereby drain electrodes on the lower surface of the semiconductor chip 1. 39 is connected and fixed. The internal lead 51 has a drain external terminal 53 that is integrally formed in parallel with the other external terminals 53.

  The gate electrode pad 41 on the upper surface of the MOSFET 2 of the semiconductor chip 1 is connected to the gate electrode external terminal 53 by a metal material 55 made of, for example, Al wire. The source electrode pad 43 on the upper surface of the MOSFET 2 is connected to the capacitor electrode pad 45 of the capacitor 3 by a metal material 55, and is connected to the source electrode external terminal 53 by a metal material 55. The metal material 55 can be connected from the capacitor electrode pad 45 to the external terminal 53 via the source electrode pad 43 with a single metal material 55.

  The metal material 55 made of Al wire can be connected by, for example, an ultrasonic pressure bonding method. In addition to Al wires, it is also possible to connect a plate material mainly composed of Al or Cu using, for example, solder. By using the metal material 55 as a plate material, it is possible to increase the cross-sectional area and lower the resistance. Moreover, resistance lower than Al can be realized by using a plate material mainly composed of Cu.

  In the power semiconductor device 101, although not shown, the connection portions of the semiconductor chip 1, the internal leads 51, the metal material 55, and the external terminal 53 with the metal material 55 are sealed with a sealing resin.

  As described above, the power semiconductor device 101 includes the superjunction MOSFET 2 and the capacitor having one electrode terminal connected to the drain outside the termination region 9 of the MOSFET 2 through the semiconductor layer common to the MOSFET 2. The source of MOSFET 2 and the other electrode terminal of the capacitor 3 are connected to each other outside the semiconductor chip 1 through a metal material 55.

  Among the manufactured power semiconductor devices 101, for example, a power semiconductor device 101 having two types of capacitors 3 having a capacitance of about 118 pF and a capacitance of about 235 pF, and a MOSFET with a conventional record for comparison were evaluated. The voltage change rate dV / dt at the time of turn-off is 5.0 V / ns for the power semiconductor device for comparison of the past results and 4.1 V / ns for the power semiconductor device 101 having the capacity 118 pF and for the power having the capacity 235 pF. In the semiconductor device 101, the voltage change rate is reduced as the capacitance of the capacitor 3 increases to 3.4 V / ns. That is, the decrease in the voltage change rate at the time of turn-off makes it possible to reduce the surge voltage generated at the time of turn-off and further reduce the noise.

  The power semiconductor device 101 has a characteristic of lowering the on-resistance without sacrificing the withstand voltage of the MOSFET 2 having a super junction structure, and further has a good surge voltage tolerance and noise tolerance.

  The MOSFET 2 has exactly the same structure as a conventional MOSFET without the capacitor 3 and can be manufactured with almost the same manufacturing yield. On the other hand, the capacitor 3 uses the MOSFET semiconductor layer that has been proven so far on the lower side of one terminal as it is, and a film having the same configuration as the terminal region of the proven MOSFET on the surface on the other terminal side. In addition, each is manufactured by being laminated. As a result, the semiconductor chip 1 having the MOSFET 2 and the capacitor 3 can be manufactured with almost no decrease in the manufacturing yield of the proven MOSFET. Although a semiconductor layer for disposing the capacitor 3 outside the termination region 9 and a material for connecting the capacitor 3 to the source terminal of the MOSFET 2 are required, a MOSFET and an external capacitor component that have been proven in the past are used. Compared to the combination, the manufacturing cost of the power semiconductor device 101 can be reduced.

  Further, by comparing analog manufacturing methods in which a capacitor is embedded in a semiconductor substrate or semiconductor layer of a MOSFET and compared, the semiconductor chip 1 of the present embodiment is determined from the difficulty of the technology and the length of the manufacturing process. It can be speculated that the production yield is higher.

  Further, although one terminal of the capacitor 3 is connected to the drain electrode of the MOSFET 2, the other terminal is connected to the source electrode by the metal material 55 after evaluating the element characteristics on the semiconductor chip. Even if it is determined that the characteristic of the capacitor 3 has not been achieved, it can be used as a MOSFET having a proven track record, which is composed only of the MOSFET 2, without being connected by the metal material 55.

  Further, since the capacitor 3 can be manufactured by being stacked on the semiconductor layer, the capacitance can be changed relatively easily as described above. In addition, the position of the capacitor electrode pad 45 can be changed relatively easily. It is possible to respond quickly to the required specifications.

  In addition, since the power semiconductor device 101 has a built-in capacitor 3 having a capacity suitable for the operating conditions of the MOSFET 2, it is not necessary to prepare an external capacitor in the applied device, and an external capacitor is mounted. Therefore, it is not necessary to secure an area for mounting on the mounting board.

  As mentioned above, this invention is not limited to the said Example, In the range which does not deviate from the summary of this invention, it can change and implement variously.

  For example, in the embodiment, an example is shown in which the capacitor is formed on one side of the semiconductor chip so as to have almost the same length as one side of the MOSFET. However, the capacitor only needs to have a necessary area. You may arrange | position in the area | region shorter than the one side of MOSFET of the one side of a chip | tip, and may arrange | position so that the outer side of the termination | terminus area | region of MOSFET may be enclosed. Further, the capacitor electrode pad can be arranged at a position where the connection is easy in the assembly process, a position where the length of the metal material for connection is suitable, a position according to the form of the package, and the like.

  In the embodiment, the semiconductor chip has a super junction structure MOSFET and a capacitor. However, the super junction structure MOSFET is a power switching device such as a vertical MOSFET other than the super junction structure or an IGBT (Insulated Gate Bipolar Transistor). It can be an element.

The present invention can be configured as described in the following supplementary notes.
(Supplementary Note 1) A first semiconductor layer of a first conductivity type, a plurality of columnar second conductivity type second semiconductor layers periodically disposed in a direction along a film surface in the first semiconductor layer, A first electrode provided on a surface of one side of the first semiconductor layer and electrically connected to the first semiconductor layer; and selectively provided in a surface region on the other side of the first semiconductor layer. A plurality of second conductivity type third semiconductor layers connected to the two semiconductor layers, a first conductivity type fourth semiconductor layer selectively provided on a surface of the third semiconductor layer, the third semiconductor layer, A second electrode provided in contact with the surface of the fourth semiconductor layer; and a gate electrode provided on the first semiconductor layer between the adjacent third semiconductor layers via a gate insulating film. A switching element and a fifth semiconductor layer of a first conductivity type provided on a surface of the first semiconductor layer A capacitor insulating film provided on the surface of the fifth semiconductor layer, spaced apart from the power switching element, a capacitor having a capacitor electrode provided on the surface of the capacitor insulating film, the capacitor electrode, A power semiconductor device comprising: a conductive material having a separation portion from the power switching element that connects to the second electrode.

(Additional remark 2) It has a field insulating film which makes a stopper electrode an end on the 5th semiconductor layer of the switching element for electric power, and the field insulating film is the material and film thickness equivalent to the capacitor insulating film The power semiconductor device according to appendix 1, wherein:

The circuit diagram which shows the connection of MOSFET and the capacitor of the semiconductor device for electric power which concerns on the Example of this invention. 2A and 2B are diagrams schematically illustrating a configuration of a semiconductor chip of a power semiconductor device according to an embodiment of the present invention, in which FIG. 2A is a plan view and FIG. 2B is a line AA in FIG. Sectional drawing along, FIG.2 (c) is sectional drawing along the BB line of Fig.2 (a). The figure which shows typically the connection in the exterior of the semiconductor chip of the semiconductor device for electric power which concerns on the Example of this invention.

Explanation of symbols

1 Semiconductor chip 2 MOSFET
3 Capacitor 5 Cell region 7 Cell / termination boundary 9 Termination region 11 n + type drain layer 12 n type drift layer 12a n type semiconductor layer 14 p type drift layer 15 p type base layer 17 n + type source layer 18 n + type channel stopper layer 21 gate insulating film 23 field insulating film 25 capacitor insulating film 31 gate electrode 33 source electrode 35 stopper electrode 37 capacitor electrode 39 drain electrode 41 gate electrode pad 42 gate main wiring 43 source electrode pad 45 capacitor electrode pad 51 internal lead 53 external terminal 55 Metal material 101 Power semiconductor device

Claims (5)

A first semiconductor layer of a first conductivity type;
A plurality of columnar second conductivity type second semiconductor layers periodically arranged in a direction along the film surface in the first semiconductor layer;
A first electrode provided on a surface of one side of the first semiconductor layer and electrically connected to the first semiconductor layer;
A plurality of second conductivity type third semiconductor layers which are selectively provided in a surface region on the other side of the first semiconductor layer and are connected to the second semiconductor layer;
A fourth semiconductor layer of a first conductivity type selectively provided on a surface of the third semiconductor layer;
A second electrode provided in contact with the surfaces of the third semiconductor layer and the fourth semiconductor layer;
A gate electrode provided on the first semiconductor layer between the adjacent third semiconductor layers via a gate insulating film;
A power switching element comprising:
A fifth semiconductor layer of a first conductivity type provided on a surface of the first semiconductor layer; a capacitor insulating film provided on a surface of the fifth semiconductor layer spaced apart from the power switching element; and the capacitor insulation A capacitor having a capacitor electrode provided on the surface of the film;
A conductive material having a separation portion from the power switching element connecting the capacitor electrode and the second electrode;
A power semiconductor device comprising:   The power switching element has the fifth semiconductor layer on the surface of the periphery of the first semiconductor layer of the power switching element, and has a stopper electrode on the fifth semiconductor layer. The power semiconductor device according to claim 1.   The power semiconductor device according to claim 1, wherein the fifth semiconductor layer has an impurity concentration and a layer thickness equivalent to those of the fourth semiconductor layer.   The power semiconductor device according to claim 1, wherein the conductive material is an aluminum wire.   4. The power semiconductor device according to claim 1, wherein the conductive material is a plate-like metal. 5.

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