JP2015015361A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device which can reduce power loss in a simple composition.SOLUTION: A semiconductor device comprises a semiconductor element which includes: a nitride-based semiconductor layer including a first semiconductor layer which is formed on a substrate and composed of a nitride-based semiconductor, and a second semiconductor layer which is formed on a surface of the first semiconductor layer and has band gap wider than that of the first semiconductor layer; a first electrode and a second electrode which are formed on the second semiconductor layer; an equipotential region formed closer to the substrate than the first semiconductor layer or formed in the substrate; and a passive circuit part which is connected between the first electrode and the equipotential region and includes an electric resistance part and an electrostatic capacitance part. The passive circuit is composed in a manner such that the equipotential region becomes positive potential with respect to the second electrode when a voltage applied to between the first electrode and the second electrode is switched from a backward voltage to a forward voltage.

Description

  The present invention relates to a semiconductor device.

  Wide band gap semiconductors are very attractive as materials for semiconductor devices for high temperature environments, high power, or high frequency because they have high breakdown voltage, good electron transport properties, and good thermal conductivity. Typical wide band gap semiconductors include GaN, AlN, InN, BN, or a nitride semiconductor that is a mixed crystal of two or more of these. For example, in a semiconductor device having an AlGaN / GaN heterojunction structure, two-dimensional electron gas is generated at the heterojunction interface due to piezo polarization and spontaneous polarization. This two-dimensional electron gas has high electron mobility and carrier density. Therefore, a semiconductor device having such an AlGaN / GaN heterojunction structure, such as a Schottky barrier diode or a field effect transistor, has high withstand voltage, low on-resistance, and fast switching speed, and is very suitable for power switching applications. is there.

  It is known that a nitride semiconductor device has a problem of current collapse. Current collapse is a phenomenon in which the on-resistance of the device increases due to a decrease in the electron concentration of the two-dimensional electron gas due to the negative charge of electrons trapped in the semiconductor. Current collapse reduces the operating current of the device, increases power loss, and reduces device efficiency.

  In order to alleviate the decrease in element efficiency due to such current collapse, a semiconductor device including a power supply that applies a positive voltage to the back electrode has been disclosed (for example, see Patent Document 1).

JP 2011-9504 A

  In nitride semiconductor devices, reduction of power loss is required.

  The present invention has been made in view of the above, and an object thereof is to provide a semiconductor device capable of reducing power loss with a simple configuration.

  In order to solve the above-described problems and achieve the object, a semiconductor device according to the present invention is formed on a substrate and formed on a surface of the first semiconductor layer formed of a nitride semiconductor and the first semiconductor layer. A nitride semiconductor layer including a nitride semiconductor having a wider band gap than the first semiconductor layer; a first electrode and a second electrode formed on the second semiconductor layer; An equipotential region formed on the substrate side or in the substrate with respect to the first semiconductor layer, and an electric resistance portion and a capacitance portion connected between the first electrode and the equipotential region. Including a passive circuit, and the passive circuit includes the equipotential when the voltage applied between the first electrode and the second electrode is switched from a reverse voltage to a forward voltage. The region is positive with respect to the second electrode Characterized in that it is configured so that.

第１または第２電極領域とは、前記第１または第２電極および該第１または第２電極に接続する導体が形成された領域または当該領域に対応する前記窒化物系半導体層の表面または内部の領域である。 The semiconductor device according to the present invention is characterized in that, in the above invention, the passive circuit is configured so that the following formula (A) is satisfied.

The first or second electrode region is a region where the first or second electrode and a conductor connected to the first or second electrode are formed, or the surface or inside of the nitride-based semiconductor layer corresponding to the region. It is an area.

  The semiconductor device according to the present invention is characterized in that, in the above invention, the equipotential region is formed in the substrate.

  The semiconductor device according to the present invention is characterized in that, in the above invention, the semiconductor device includes a package in which the semiconductor element is accommodated, and the passive circuit is accommodated in the package.

  In the semiconductor device according to the present invention, in the above invention, the package includes a conductive substrate, and the semiconductor element is mounted on the conductive substrate via a dielectric layer, and the electric resistance unit and the electrostatic device are mounted. The capacitor portion is configured by a resistance component and a capacitance component of the dielectric layer between the equipotential region in the substrate and the conductive substrate.

  The semiconductor device according to the present invention is characterized in that, in the above invention, the semiconductor device includes a package in which the semiconductor element is accommodated, and the passive circuit is disposed outside the package.

  In the semiconductor device according to the present invention, in the above invention, the equipotential region is constituted by an n-type semiconductor layer, a p-type semiconductor layer, or a two-dimensional electron gas layer formed in the nitride-based semiconductor layer. It is characterized by that.

  In the semiconductor device according to the present invention, in the above invention, the electrical resistance portion is configured by a resistance component of the nitride-based semiconductor layer between the equipotential region and the substrate, and an area of the equipotential region. Alternatively, the electrical resistance is adjusted by the thickness or electrical resistivity of the nitride-based semiconductor layer between the equipotential region and the substrate.

  In the semiconductor device according to the present invention, in the above invention, the capacitance section is configured by a capacitance component of the nitride-based semiconductor layer between the equipotential region and the substrate. The capacitance is adjusted by the area of the region or the thickness or dielectric constant of the nitride-based semiconductor layer between the equipotential region and the substrate.

  In the semiconductor device according to the present invention, in the above invention, the electrical resistance between the first or second electrode region and the equipotential region is between the first or second conductive region and the equipotential region. The nitride-based semiconductor layer is configured by a resistance component of the nitride-based semiconductor layer, and the area of the first or second electrode region, or the nitride-based semiconductor layer between the first or second electrode region and the equipotential region The electrical resistance is adjusted by the thickness or the electrical resistivity.

  The semiconductor device according to the present invention is the above invention, wherein the capacitance between the first or second electrode region and the equipotential region is between the first or second conductive region and the equipotential region. Of the nitride-based semiconductor layer, and the area of the first or second electrode region, or the nitride between the first or second electrode region and the equipotential region The electrostatic capacity is adjusted by the thickness or dielectric constant of the semiconductor layer.

  In the semiconductor device according to the present invention, in the above invention, the electrical resistivity of the nitride-based semiconductor layer is the type of the nitride-based semiconductor layer, the impurity concentration in the nitride-based semiconductor layer, and the nitride-based semiconductor layer. It is characterized by being adjusted by any one of the few crystal defect densities.

  The semiconductor device according to the present invention is characterized in that, in the above invention, the substrate is made of conductive silicon.

  In the semiconductor device according to the present invention, in the above invention, the first electrode is an anode electrode, the second electrode is a cathode electrode, and the area of the first electrode region and the area of the second electrode region are The ratio is characterized by being greater than 0.5.

  In the semiconductor device according to the present invention, in the above invention, the first electrode is a drain electrode region, the second electrode is a source electrode, the area of the first electrode region, the area of the second electrode region, The ratio is less than 0.5.

  According to the present invention, it is possible to realize a semiconductor device capable of reducing power loss with a simple configuration.

FIG. 1 is a schematic cross-sectional view of the semiconductor device according to the first embodiment. FIG. 2 is a diagram showing an equivalent circuit of the semiconductor element shown in FIG. FIG. 3 is a diagram showing a case where a stress voltage is applied to an equivalent circuit obtained by synthesizing a part of the equivalent circuit shown in FIG. FIG. 4 is a diagram showing a transient state before the equilibrium state immediately after releasing the stress voltage applied to the equivalent circuit shown in FIG. FIG. 5 is a schematic cross-sectional view of the semiconductor device according to the second embodiment. FIG. 6 is a schematic cross-sectional view of the semiconductor device according to the third embodiment. FIG. 7 is a diagram showing a change in potential in the equipotential region. FIG. 8 is a diagram showing changes in the electron concentration of the two-dimensional electron gas. FIG. 9 is a diagram showing the relationship between the ratio of the area of the first electrode region to the area of the second electrode region and the potential of the equipotential region. FIG. 10 is a schematic cross-sectional view of the semiconductor device according to the fourth embodiment. FIG. 11 is a diagram showing an equivalent circuit of the semiconductor element shown in FIG. FIG. 12 is a diagram showing an equilibrium state when a stress voltage is applied to an equivalent circuit obtained by synthesizing a part of the equivalent circuit shown in FIG. FIG. 13 is a diagram showing a transient state before the equilibrium state immediately after releasing the stress voltage applied to the equivalent circuit shown in FIG.

  Embodiments of a semiconductor device according to the present invention will be described below in detail with reference to the drawings. Note that the present invention is not limited to the embodiments. Moreover, in each drawing, the same code | symbol is attached | subjected suitably to the same or corresponding element. Furthermore, it should be noted that the drawings are schematic, and dimensional relationships between elements may differ from actual ones. Even between the drawings, there are cases in which portions having different dimensional relationships and ratios are included.

(Embodiment 1)
FIG. 1 is a schematic cross-sectional view of a semiconductor device according to Embodiment 1 of the present invention. The semiconductor device 100 includes a package 10 and a semiconductor element 20 that is housed in the package 10 and is a Schottky barrier diode (SBD). The package 10 includes a metal conductive substrate 10a, and the semiconductor element 20 is mounted on the conductive substrate 10a. The semiconductor element 20 is mounted on the conductive substrate 10a by, for example, die bonding using a conductive material such as solder or silver paste.

  The semiconductor element 20 includes a conductive substrate 21 made of, for example, conductive silicon, and a nitride semiconductor layer formed on the substrate 21. The nitride-based semiconductor layer includes a buffer layer 22, a first semiconductor layer 23, and a second semiconductor layer 24 that are sequentially formed from the substrate 21 side.

  The buffer layer 22 is made of a nitride-based semiconductor, and has a configuration in which, for example, a plurality of AlN layers and a plurality of GaN layers are alternately stacked. However, the thicknesses of the AlN layer and the GaN layer are so thin that no two-dimensional electron gas is generated at the heterojunction interface between the AlN layer and the GaN layer. The first semiconductor layer 23 is made of a nitride semiconductor, for example, GaN. The second semiconductor layer 24 is formed on the surface of the first semiconductor layer 23, and is made of a nitride semiconductor having a wider band gap than the first semiconductor layer 23, for example, AlGaN. The first semiconductor layer 23 and the second semiconductor layer 24 form a heterojunction. As a result, a two-dimensional electron gas layer is formed at the interface between the first semiconductor layer 23 and the second semiconductor layer 24. The first semiconductor layer 23 functions as an electron transit layer, and the second semiconductor layer 24 functions as an electron supply layer.

  The semiconductor element 20 further includes an insulating film 25, a first electrode 26, a first electrode pad 27, and a second electrode 28 formed on the second semiconductor layer 24.

The insulating film 25 is made of, for example, SiO ₂ or SiN _x and covers the surface of the second semiconductor layer 24. The first electrode 26 is formed so as to be in Schottky junction with the second semiconductor layer 24, and functions as an anode electrode. The first electrode 26 has, for example, a Ni / Au structure. The first electrode pad 27 is formed on the second semiconductor layer 24 via the insulating film 25. The first electrode pad 27 is made of, for example, Au, and is electrically connected to the first electrode 26 to realize electrical contact between the first electrode 26 and the outside. The second electrode 28 is formed in ohmic contact with the second semiconductor layer 24 and functions as a cathode electrode. The second electrode 28 has, for example, a Ti / Al structure.

  As shown in FIG. 1, an equipotential region S <b> 1 is formed inside a conductive substrate 21. In the present specification, the first electrode region is defined. The first electrode region is a region where the first electrode and a conductor in contact with the first electrode region are formed on the upper side of the nitride-based semiconductor layer. In some cases, the surface of the nitride-based semiconductor layer corresponding to the region where the first electrode and the conductor in contact therewith are formed or a region inside the nitride-based semiconductor layer is the first electrode region. In the first embodiment, for the reasons described later, the first semiconductor layer 23 and the second semiconductor layer 24 corresponding to the region where the first electrode 26 and the first electrode pad 27 that is a conductor in contact with the first electrode 26 are formed. The region at the interface with the first electrode region S2. The region S <b> 2 a is a region where the first electrode 26 is in contact with the second semiconductor layer 24, and is shown at the interface between the first semiconductor layer 23 and the second semiconductor layer 24. Similarly, in the present specification, a second electrode region is defined. The second electrode region is a region where the second electrode and a conductor in contact therewith are formed on the upper side of the nitride-based semiconductor layer. In addition, the surface of the nitride-based semiconductor layer corresponding to the region where the second electrode and the conductor in contact therewith are formed or a region inside the nitride-based semiconductor layer may be used as the second electrode region. In the first embodiment, for the reason described later, the region at the interface between the first semiconductor layer 23 and the second semiconductor layer 24 corresponding to the region where the second electrode 28 is formed is defined as the second electrode region S3. . When an electrode pad that is a conductor in contact with the second electrode 28 is formed, the interface between the first semiconductor layer 23 and the second semiconductor layer 24 corresponding to the region where the electrode pad is formed is formed. The region is also included in the second electrode region S3. Further, an equipotential region S4 is formed inside the conductive substrate 10a of the package 10.

  The resistance component 20a and the capacitance component 20b are respectively a nitride-based semiconductor layer between the first electrode region S2 and the equipotential region S1, that is, the resistance component or capacitance of the buffer layer 22 and the first semiconductor layer 23. It is an ingredient. The resistance component 20c and the capacitance component 20d are respectively the resistance component or capacitance of the nitride-based semiconductor layer between the second electrode region S3 and the equipotential region S1, that is, the buffer layer 22 and the first semiconductor layer 23. It is an ingredient.

  Furthermore, the semiconductor device 100 includes a passive circuit 30 housed in a package together with the semiconductor element 20. The passive circuit 30 includes an electric resistance unit 30a and a capacitance unit 30b connected in parallel. The passive circuit 30 is connected between the first electrode 26 and the equipotential region S1 via the first electrode pad 27 and the conductive substrate 10a.

  Next, when the semiconductor device 100 is switched from a state in which a large reverse voltage (for example, several hundred volts) is applied to a state in which a small forward voltage (for example, several volts) is applied, as in the case of applying a switching voltage, for example. The operation of the semiconductor device 100 will be described. In the semiconductor device 100, when the voltage applied between the first electrode 26 and the second electrode 28 is switched from the reverse voltage to the forward voltage, the passive circuit 30 causes the equipotential region S <b> 1 to be applied to the second electrode 28. So as to be positive potential. As a result, the semiconductor device 100 is compensated for the decrease in the electron concentration of the two-dimensional electron gas due to the semiconductor trap, and the power loss is reduced.

This will be specifically described below. FIG. 2 is a diagram showing an equivalent circuit of the semiconductor element 20 shown in FIG. Points P1, P2, and P3 correspond to the equipotential region S1, the first electrode 26, and the second electrode 28, respectively. Here, the resistance component 20a, 20c, the electrical resistance value of the electric resistance portion 30a, respectively _{R ab,} R _cb, and _{R bs.} The capacitance values of the capacitance components 20b and 20d and the capacitance portion 30b are C _ab , C _cb , and C _bs , respectively. The second electrode 28 is set to 0V is grounded, first electrode 26 is the voltage _{V in} is applied.

Note that the electric resistance value R _ab of the resistance component 20a and the capacitance value C _ab of the capacitance component 20b can be adjusted by changing the area of the first electrode region. The electric resistance value R _cb of the resistance component 20c and the capacitance C _cb of the capacitance component 20d can be adjusted by changing the area of the second electrode region. Further, the electric resistance value _{R cb} electric resistance value _{R ab} and resistance component 20c of the resistor components 20a, a buffer layer 22, the first semiconductor layer 23 or the second type semiconductor layer 24, at least the impurity concentration and crystal defect density It can be adjusted by either one.

FIG. 3 is a diagram showing a case where a stress voltage is applied to an equivalent circuit obtained by synthesizing a part of the equivalent circuit shown in FIG. The equivalent circuit shown in FIG. 3 includes resistors 20e and 20f whose electric resistance values are R ₁ and R ₂ , respectively, and capacitances 20g and 20h whose capacitance values are C ₁ and C ₂ . Here, R ₁ = R _cb , C ₁ = C _cb , 1 / R ₂ = 1 / R _ab + 1 / R _bs , and C ₂ = C _ab + C _bs . When a reverse voltage (stress voltage) _in which Vin is negative is applied to the equivalent circuit shown in FIG. 3 (for example, V _in = −600 V), charges are accumulated in the capacitances 20g and 20h by the leakage current I1. Is done. When the electric charges accumulated on the point P1 side of the electrostatic capacitances 20g and 20h at the equilibrium state are Q _m1 and Q _m2 , respectively, and the electric potential at the point P1 is V _m , the following equations (1) to (3 ) Holds.

V _m = V _in × R ₁ / (R ₁ + R ₂ ) (1)
Q _m1 = C ₁ × V _m (2)
Q _m2 = C ₂ × (V _m −V _in ) (3)

Next, FIG. 4 is a diagram showing a transient state before the equilibrium state immediately after releasing the stress voltage applied to the equivalent circuit shown in FIG. Immediately after releasing the stress voltage, V _in becomes substantially to 0V. At this time, the electric charge accumulated in the capacitances 20g and 20h flows like a current I2. Assuming that the potential at the point P1 corresponding to the equipotential region S1 at this time is V _m ′, V _m ′ is expressed by the following equation (4).

V _m ′ = (Q _m1 + Q _m2 ) / (C ₁ + C ₂ ) (4)

In the semiconductor device 100, the passive circuit 30 is configured so that V _m ′ has a positive value. Therefore, the following formula (A) is established as derived from the above formulas (1) to (4).

When V _m ′ becomes a positive value, electrons are attracted toward the equipotential region S1 by the back gate effect, and the electron concentration of the two-dimensional electron gas layer of the first semiconductor layer 23 increases. As a result, the decrease in the electron concentration of the two-dimensional electron gas due to current collapse is compensated, and the forward current when the forward voltage is applied increases. As described above, in the semiconductor device 100, the power loss is reduced by the passive circuit 30 having a simple configuration.

At this time, V _m ′ decreases with a time constant τ (time until the value becomes 1 / e) shown in Expression (5).
τ = (C ₁ + C ₂ ) × (R ₁ × R ₂ ) / (R ₁ + R ₂ ) (5)

Therefore, the electric resistance value R _bs of the electric resistance unit 30a of the passive circuit 30 and the capacitance value C _bs of the electrostatic capacitance unit 30b are also taken into consideration such as the relationship between the frequency of the applied switching voltage and the time constant. The semiconductor element 20 is preferably set to a value that can compensate for a decrease in the electron concentration of the two-dimensional electron gas due to current collapse.

  In the first embodiment, the region of the interface between the first semiconductor layer 23 and the second semiconductor layer 24 corresponding to the region where the first electrode 26 and the first electrode pad 27 that is a conductor in contact with the first electrode 26 are formed. Is the first electrode region S2. The reason is that the region where the first electrode 26 and the first electrode pad 27 which is a conductor in contact with the first electrode 26 are formed, and the region of the interface between the first semiconductor layer 23 and the second semiconductor layer 24 corresponding thereto. The resistance component and capacitance component of the second semiconductor layer 24 and the insulating film 25 existing between the resistance region 20a and the capacitance component 20b between the corresponding interface region and the equipotential region S1. This is because the comparison can be omitted. Similarly, in the first embodiment, the region at the interface between the first semiconductor layer 23 and the second semiconductor layer 24 corresponding to the region where the second electrode 28 is formed is defined as a second electrode region S3. The reason is that the resistance component of the second semiconductor layer 24 exists between the region where the second electrode 28 is formed and the region corresponding to the interface between the first semiconductor layer 23 and the second semiconductor layer 24. This is because the capacitance component is a value that can be considered as compared with the resistance component 20c and the capacitance component 20d between the corresponding interface region and the equipotential region S1.

  However, the present invention is not limited to this, and the omitted resistance component and capacitance component may be considered. In that case, each value of the resistance component 20a, the capacitance component 20b, the resistance component 20c, and the capacitance component 20d is replaced with a value including the resistance component and the capacitance component which are omitted, and the above formula ( 1) to (5) and (A) may be used. In this case, the first electrode region and the second electrode region may be defined as, for example, the surface of the second semiconductor layer 24 or a specific position inside the nitride-based semiconductor layer.

(Embodiment 2)
FIG. 5 is a schematic cross-sectional view of a semiconductor device according to Embodiment 2 of the present invention. The semiconductor device 200 has a configuration in which the semiconductor element 20 is replaced with the semiconductor element 20A in the semiconductor device 100 according to the first embodiment, and the passive circuit 30 is deleted.

The semiconductor element 20A is obtained by replacing the substrate 21 in the semiconductor element 20 with the substrate 21A. The substrate 21A is obtained by forming a dielectric layer 21Aa on the back side of a conductive substrate. The substrate 21A is obtained by forming a dielectric layer such as a SiO ₂ film on the surface of a substrate made of conductive silicon, for example, by thermal oxidation or a CVD method. The semiconductor element 20A is mounted on the conductive substrate 10a of the package 10 via a dielectric layer 21Aa. An equipotential region S1A is formed inside the substrate 21A.

  In this semiconductor device 200, a passive circuit 31 including an electric resistance portion 31a and a capacitance portion 31b connected in parallel is formed inside the semiconductor element 20A. That is, the electric resistance portion 31a and the capacitance portion 31b are formed by the resistance component and the capacitance component of the dielectric layer 21Aa between the equipotential region S1A in the substrate 21A and the equipotential region S4 of the conductive substrate 10a. It is comprised by. The passive circuit 31 is connected between the first electrode 26 and the equipotential region S1A via the first electrode pad 27 and the conductive substrate 10a.

  Similarly to the semiconductor device 100 according to the first embodiment, the passive circuit 31 also switches the voltage applied between the first electrode 26 and the second electrode 28 from the reverse voltage to the forward voltage. The equipotential region S1A is sometimes configured to be a positive potential. As a result, the semiconductor device 200 is compensated for the decrease in the electron concentration of the two-dimensional electron gas due to the semiconductor trap, and the power loss is reduced.

  The electric resistance value of the electric resistance portion 31a of the passive circuit 31 and the electrostatic capacitance value of the capacitance portion 31b are determined by considering the relationship between the frequency of the switching voltage to be applied and the time constant, and the like. It is preferable to set a value that can compensate for the decrease in the electron concentration of the two-dimensional electron gas due to collapse. The electric resistance value of the electric resistance portion 31a and the electrostatic capacitance value of the capacitance portion 31b are adjusted by changing the electric resistivity, dielectric constant, or thickness of the dielectric layer 21Aa. be able to.

  Also in the second embodiment, the resistance component and the capacitance component of the second semiconductor layer 24 and the insulating film 25 are omitted as in the case of the first embodiment. And the capacitance component may be taken into account.

(Embodiment 3)
FIG. 6 is a schematic cross-sectional view of a semiconductor device according to Embodiment 3 of the present invention. The semiconductor device 300 has a configuration in which the semiconductor element 20 is replaced with the semiconductor element 20B in the semiconductor device 200 according to the first embodiment, and the passive circuit 30 is omitted.

  The semiconductor element 20B is obtained by replacing the buffer layer 22 in the semiconductor element 20 with the buffer layer 22B. The buffer layer 22B has a configuration in which a first buffer layer 22Ba and a second buffer layer 22Bb are sequentially stacked.

  The first buffer layer 22Ba is made of a nitride-based semiconductor, and has a configuration in which, for example, a plurality of AlN layers and a plurality of GaN layers are alternately stacked. However, the thicknesses of the AlN layer and the GaN layer are so thick that two-dimensional electron gas is generated at the heterojunction interface between the AlN layer and the GaN layer. On the other hand, the second buffer layer 22Bb is made of a nitride-based semiconductor and has a configuration in which, for example, a plurality of AlN layers and a plurality of GaN layers are alternately stacked. However, the thicknesses of the AlN layer and the GaN layer are so thin that no two-dimensional electron gas is generated at the heterojunction interface between the AlN layer and the GaN layer. As a result, an equipotential region S5 of a two-dimensional electron gas layer is formed in the first buffer layer 22Ba. FIG. 6 shows the case where the equipotential region S5 is formed at the interface between the first buffer layer 22Ba and the second buffer layer 22Bb. However, the position where the equipotential region S5 is formed is not limited to this. Absent.

  The resistance component 20Ba and the capacitance component 20Bb are respectively a nitride-based semiconductor layer between the first electrode region S2 and the equipotential region S5, that is, the resistance component or static of the second buffer layer 22Bb and the first semiconductor layer 23. It is a capacitance component. The resistance component 20Bc and the capacitance component 20Bd are respectively a nitride-based semiconductor layer between the second electrode region S3 and the equipotential region S5, that is, the resistance component or static of the second buffer layer 22Bb and the first semiconductor layer 23. It is a capacitance component.

  In this semiconductor device 300, a passive circuit 32 including an electric resistance portion 32a and a capacitance portion 32b connected in parallel is formed inside the semiconductor element 20B. That is, the electric resistance portion 32a and the electrostatic capacitance portion 32b are configured such that the resistance component and electrostatic capacitance of the first buffer layer 22Ba between the equipotential region S5 of the first buffer layer 22Ba and the equipotential region S1 in the substrate 21 are obtained. It is comprised by the capacitive component. The passive circuit 32 is connected between the first electrode 26 and the equipotential region S5 via the first electrode pad 27, the conductive substrate 10a, and the substrate 21.

  Similarly to the semiconductor device 100 according to the first embodiment, the passive circuit 32 switches the voltage applied between the first electrode 26 and the second electrode 28 from the reverse voltage to the forward voltage. The equipotential region S5 is sometimes configured to be a positive potential. As a result, the semiconductor device 300 is compensated for the decrease in the electron concentration of the two-dimensional electron gas due to the semiconductor trap, and the power loss is reduced.

  The electric resistance value of the electric resistance portion 32a of the passive circuit 32 and the capacitance value of the electrostatic capacitance portion 32b are determined in consideration of the relationship between the frequency of the applied switching voltage and the time constant, and the like. It is preferable to set a value that can compensate for the decrease in the electron concentration of the two-dimensional electron gas due to collapse. The electrical resistance value of the electrical resistance portion 32a and the electrostatic capacitance value of the electrostatic capacitance portion 32b change the configuration of the first buffer layer 22Ba, the area of the equipotential region S5, the electrical resistivity, the dielectric constant, and the thickness. By adjusting the value, the value can be adjusted. The electrical resistivity can be adjusted by any one of the type of the first buffer layer 22Ba, the impurity concentration in the first buffer layer 22Ba, and the crystal defect density in the first buffer layer 22Ba.

  Even in the third embodiment, the resistance component and the capacitance component of the second semiconductor layer 24 and the insulating film 25 are omitted as in the case of the first embodiment. And the capacitance component may be taken into account. In that case, each value of the resistance component 20Ba, the capacitance component 20Bb, the resistance component 20Bc, and the capacitance component 20Bd may be replaced with the omitted values including the resistance component and the capacitance component.

Here, in the configuration of the semiconductor device according to the first and third embodiments, the electric resistance values R ₁ and R ₂ of the resistors 20e and 20f and the capacitance values of the capacitances 20g and 20h in the equivalent circuit shown in FIG. The potential of the equipotential region S1 (potential at the point P1) when the anode voltage (V _in ) is switched from −600 V to +2 V by changing C ₁ and C ₂ , and the two-dimensional electrons of the first semiconductor layer 23 The electron concentration in the gas layer was calculated. Here, calculation was performed for three types of combinations (calculation 1, calculation 2, and calculation 3) in which the values of R ₁ , R ₂ , C ₁ , and C ₂ were changed. Calculation 1 is a case where the configuration of the first embodiment is adopted. Calculations 2 and 3 are cases where the configuration of the third embodiment is adopted and the thickness of the second buffer layer 22Bb is set to a different value.

FIG. 7 is a diagram showing a change in potential in the equipotential region. FIG. 8 is a diagram showing the amount of change (ΔNs) in the electron concentration of the two-dimensional electron gas. Note that the vertical axis in FIG. 8 represents the amount of change based on the electron concentration of the two-dimensional electron gas in a state where a DC forward voltage is applied to the semiconductor element. In the vertical axis of FIG. 8, for example, “1.E + 13” means “1 × 10 ¹³ ”. 7 and 8, the anode voltage V (anode) was set to -600 V from 0 second to 10.000 seconds, and then +2 V from 10.000 seconds to 10.100 seconds. Vbuf1, Vbuf2, and Vbuf3 in FIG. 7 indicate potentials obtained by calculation 1, calculation 2, and calculation 3, respectively. ΔNs 1, ΔNs 2, and ΔNs 3 in FIG. 8 indicate changes in electron concentration by calculation 1, calculation 2, and calculation 3, respectively. ΔN (c) indicates a change in electron concentration due to current collapse.

  As shown in FIG. 7, Vbuf1 became negative when the voltage was switched from the reverse voltage to the forward voltage, and then reached 0V with a predetermined time constant. Moreover, Vbuf2 became positive when the voltage was switched, and then reached 0 V with a longer time constant than in the case of Vbuf1. Furthermore, Vbuf3 became positive when the voltage was switched, and then the potential gradually decreased, but did not reach 0 V until 10.100 seconds. Therefore, Vbuf3 has a longer time constant than Vbuf2.

  As shown in FIG. 8, ΔNs1 became negative when the voltage was switched from the reverse voltage to the forward voltage, and then reached 0 with a predetermined time constant. This indicates that when Vbuf1 becomes negative as shown in FIG. 7, ΔNs1 also becomes negative and the electron concentration decreases. On the other hand, ΔNs2 became positive when the voltage was switched, and then reached 0 with a longer time constant than in the case of ΔNs1. This indicates that when Vbuf2 is positive as shown in FIG. 7, ΔNs2 is also positive and the electron concentration increases. Furthermore, ΔNs3 became positive when the voltage was switched, and then gradually decreased, but did not reach 0 until 10.100 seconds. Therefore, ΔNs3 has a longer time constant than ΔNs2.

  As can be seen from FIGS. 7 and 8, by switching the reverse voltage to the forward voltage so that the equipotential region becomes a positive potential, the electron concentration of the two-dimensional electron gas can be increased. The decrease in the two-dimensional electron gas can be compensated. In particular, as shown in FIG. 8, in the case of calculation 2, the curve shape of ΔNs2 over time is such that the decrease in ΔN (c) due to current collapse can be substantially offset. Further, in the case of calculation 3, the value of ΔNs3 is a value that can compensate for the decrease amount of ΔN (c).

  Next, preferable values for the ratio of the area of the first electrode region to the area of the second electrode region will be described. Here, in the condition of calculation 2 of the configuration according to the above-described third embodiment, while fixing the area of the second electrode region and changing the area of the first electrode region by enlarging the area of the electrode pad, The potential in the equipotential region immediately after switching the voltage from the reverse voltage to the forward voltage was calculated.

  FIG. 9 is a diagram showing the relationship between the ratio of the area of the first electrode region to the area of the second electrode region and the potential of the equipotential region. The horizontal axis is logarithmically displayed. As shown in FIG. 9, when the ratio of the area of the first electrode region to the area of the second electrode region was 0.5, the potential was almost 0V. Therefore, the equipotential region can be set to a positive potential by making the ratio larger than 0.5.

(Embodiment 4)
FIG. 10 is a schematic cross-sectional view of a semiconductor device according to Embodiment 4 of the present invention. The semiconductor device 400 has a configuration in which, in the semiconductor device 100 according to the first embodiment, the semiconductor element 20 is replaced with the semiconductor element 40 and the passive circuit 30 is disposed outside the package 10.

  The semiconductor element 40 is mounted on the conductive substrate 10a. The semiconductor element 40 is mounted on the conductive substrate 10a by, for example, die bonding using a conductive material such as solder or silver paste. Similar to the semiconductor element 20, the semiconductor element 40 includes a conductive substrate 21 and a nitride-based semiconductor layer formed on the substrate 21. The nitride-based semiconductor layer includes a buffer layer 22, a first semiconductor layer 23, and a second semiconductor layer 24 that are sequentially formed from the substrate 21 side.

  The semiconductor element 40 further includes an insulating film 25, a gate electrode 46, a first electrode 47 and a second electrode 48 formed on the second semiconductor layer 24.

The insulating film 25 is made of, for example, SiO ₂ or SiN _x and covers the surface of the second semiconductor layer 24. The gate electrode 46 is formed so as to be in Schottky junction with the second semiconductor layer 24 from the opening formed in the insulating film 25. The first electrode 47 is formed so as to be in ohmic contact with the second semiconductor layer 24 and functions as a source electrode. The second electrode 48 is formed so as to be in ohmic contact with the second semiconductor layer 24 and functions as a drain electrode. The gate electrode 46 has, for example, a Ni / Au structure. The first and second electrodes 47 and 48 have, for example, a Ti / Al structure.

  Similar to the semiconductor element 20, an equipotential region S <b> 1 is formed inside the conductive substrate 21. Further, for the same reason as in the case of the semiconductor element 20, a region at the interface between the first semiconductor layer 23 and the second semiconductor layer 24 corresponding to the region where the first electrode 47 is formed is defined as a first electrode region S6. Yes. A region at the interface between the first semiconductor layer 23 and the second semiconductor layer 24 corresponding to the region where the second electrode 48 is formed is defined as a second electrode region S7. In addition, when the electrode pad which is a conductor which contacts the 1st electrode 47 or the 2nd electrode 48 is formed, the area | region of the surface of the 2nd semiconductor layer 24 corresponding to the area | region in which this electrode pad was formed also. , Included in the first or second electrode region. The region S8 is a region where the gate electrode 46 is in contact with the second semiconductor layer 24, and is shown at the interface between the first semiconductor layer 23 and the second semiconductor layer 24. Further, an equipotential region S4 is formed inside the conductive substrate 10a of the package 10.

  The resistance component 40a and the capacitance component 40b are the resistance component or capacitance of the nitride-based semiconductor layer between the first electrode region S6 and the equipotential region S1, that is, the buffer layer 22 and the first semiconductor layer 23, respectively. It is an ingredient. The resistance component 40c and the capacitance component 40d are respectively a nitride-based semiconductor layer between the second electrode region S7 and the equipotential region S1, that is, the resistance component or capacitance of the buffer layer 22 and the first semiconductor layer 23. It is an ingredient. The resistance component 40e and the capacitance component 40f are the resistance component or the capacitance component of the buffer layer 22 and the first semiconductor layer 23, respectively, of the nitride-based semiconductor layer between the region S8 and the equipotential region S1. is there.

  The passive circuit 30 is connected between the first electrode 47 and the equipotential region S1 through the conductive substrate 10a. Thus, the passive circuit 30 may be disposed outside the package 10.

  Next, when the semiconductor device 400 is switched from a state in which a large reverse voltage (for example, several hundred volts) is applied to a state in which a small forward voltage (for example, several volts) is applied, as in the case of applying a switching voltage, for example. The operation of the semiconductor device 400 will be described. In the semiconductor device 400, the passive circuit 30 is configured such that the equipotential region S1 becomes a positive potential when the voltage applied between the first electrode 47 and the second electrode 48 is switched from the reverse voltage to the forward voltage. Has been. As a result, the semiconductor device 400 is compensated for the decrease in the electron concentration of the two-dimensional electron gas due to the semiconductor trap, and the power loss is reduced.

This will be specifically described below. FIG. 11 is a diagram showing an equivalent circuit of the semiconductor element 40 shown in FIG. Points P1, P6, and P7 correspond to the equipotential region S1, the first electrode 47, and the second electrode 48, respectively. Here, the resistance component 40a, 40c, the electrical resistance value of the electric resistance portion 30a, respectively _{R ab,} R _cb, and _{R bs.} The capacitance values of the capacitance components 40b and 40d and the capacitance portion 30b are C _ab , C _cb , and C _bs , respectively. The second electrode 48 is set to 0V is grounded, first electrode 47 has a voltage _{V in} is applied. Further, since the gate potential is smaller than the reverse voltage value, the resistance component 40e and the capacitance component 40f can be ignored.

Incidentally, the capacitance value C _ab of the electric resistance value R _ab and the capacitance component 40b of the resistance component 40a can be adjusted by changing the area of the first electrode region. The electric resistance value R _cb of the resistance component 40c and the capacitance C _cb of the capacitance component 40d can be adjusted by changing the area of the second electrode region. Further, the electric resistance value _{R cb} electric resistance value _{R ab} and resistance component 40c of the resistor components 40a, a buffer layer 22, the first semiconductor layer 23 or the second type semiconductor layer 24, at least the impurity concentration and crystal defect density It can be adjusted by either one.

FIG. 12 is a diagram showing a case where a stress voltage is applied to an equivalent circuit obtained by synthesizing a part of the equivalent circuit shown in FIG. The equivalent circuit shown in FIG. 12 includes resistors 40g and 40h whose electric resistance values are R ₁ and R ₂ , and capacitances 40i and 40j whose capacitance values are C ₁ and C ₂ , respectively. Here, R ₁ = R _cb , C ₁ = C _cb , 1 / R ₂ = 1 / R _ab + 1 / R _bs , and C ₂ = C _ab + C _bs . When a reverse voltage (stress voltage) _in which V _in is a positive value is applied to the equivalent circuit shown in FIG. 12 (for example, V _in = 600 V), charges are accumulated in the capacitances 40i and 40j by the leakage current I3. The As in the case of the first embodiment, assuming that the electric charges accumulated on the point P1 side of the capacitances 40i and 40j when the equilibrium state is reached are Q _m1 and Q _m2 , respectively, and the potential at the point P1 is V _m. The above-described formulas (1) to (3) are established.

Next, FIG. 13 is a diagram showing a transient state before the equilibrium state immediately after releasing the stress voltage applied to the equivalent circuit shown in FIG. Immediately after releasing the stress voltage, V _in becomes substantially to 0V. At this time, the electric charge accumulated in the capacitances 40i and 40j flows like a current I4. Assuming that the potential of the point P1 corresponding to the equipotential region S1 at this time is V _m ′, V _m ′ is expressed by the above-described formula (4) as in the case of the first embodiment.

In the semiconductor device 400, the passive circuit 30 is configured so that V _m ′ has a positive value. Therefore, as in the case of the first embodiment, the above-described formula (A) is established.

When V _m ′ becomes a positive value, electrons are attracted toward the equipotential region S1 and the electron concentration of the two-dimensional electron gas layer of the first semiconductor layer 23 increases. As a result, the decrease in the electron concentration of the two-dimensional electron gas due to current collapse is compensated, and the forward current when the forward voltage is applied increases. As described above, in the semiconductor device 400, the power loss is reduced by the passive circuit 30 having a simple configuration. At this time, V _m ′ decreases with the time constant τ shown in the above equation (5).

Therefore, the electric resistance value R _bs of the electric resistance unit 30a of the passive circuit 30 and the capacitance value C _bs of the electrostatic capacitance unit 30b are also taken into consideration such as the relationship between the frequency of the applied switching voltage and the time constant. The semiconductor element 40 is preferably set to a value that can compensate for the decrease in the electron concentration of the two-dimensional electron gas due to current collapse.

  When the semiconductor element is a field effect transistor such as HEMT as in the fourth embodiment, the sign of the reverse voltage is different from that of the SBD of the first embodiment or the like (see FIGS. 3 and 12). The equipotential region can be set to a positive potential by making the ratio of the area of the first electrode region and the area of the second electrode region smaller than 0.5.

  In the fourth embodiment, as in the case of the first embodiment, the resistance component and the capacitance component of the second semiconductor layer 24 and the insulating film 25 are omitted, but they are omitted. Resistance components and capacitance components may be considered. In that case, the values of the resistance component 40a, the capacitance component 40b, the resistance component 40c, and the capacitance component 40d are replaced with the omitted values including the resistance component and the capacitance component. 1) to (5) and (A) may be used.

  In the third embodiment, the equipotential region S5 is a two-dimensional electron gas layer formed by a heterojunction included in the first buffer layer 22Ba. However, the present invention is not limited to this, and a positive potential is used. The equipotential region may be an n-type semiconductor layer or a p-type semiconductor layer formed in a nitride-based semiconductor layer. Further, the equipotential region to be positive potential is not limited to the inside of the substrate of the semiconductor element as in the first and second embodiments, and may be on the substrate side from the first semiconductor layer as in the third embodiment. .

  In the above embodiment, the nitride-based semiconductor layer includes the buffer layer, the first semiconductor layer, and the second semiconductor layer. However, the nitride-based semiconductor layer may include other semiconductor layers as appropriate.

  In the above embodiment, the semiconductor device is HEMT or SBD. However, the present invention is applicable to other semiconductors such as MOS-type and MIS-type field effect transistors having a heterojunction structure and using a two-dimensional electron gas. The present invention can also be applied to an apparatus.

  Further, the present invention is not limited by the above embodiment. What was comprised combining each component mentioned above suitably is also contained in this invention. For example, the passive circuit according to the first to third embodiments may be replaced with the passive circuit according to the fourth embodiment. Further effects and modifications can be easily derived by those skilled in the art. Therefore, the broader aspect of the present invention is not limited to the above-described embodiment, and various modifications can be made.

10 Package 10a Conductive substrate 20, 20A, 20B, 40 Semiconductor element 20a, 20c, 40a, 40c, 40e Resistance component 20b, 20d, 40b, 40d, 40f Capacitance component 20e, 20f, 40g, 40h Resistance 20g, 20h , 40i, 40j Capacitance 21, 21A Substrate 21Aa Dielectric layer 22, 22B Buffer layer 22Ba First buffer layer 22Bb Second buffer layer 23 First semiconductor layer 24 Second semiconductor layer 25 Insulating film 26, 47 First electrode 27 1st electrode pad 28, 48 2nd electrode 30, 31, 32 Passive circuit 30a, 31a, 32a Electrical resistance part 30b, 31b, 32b Capacitance part 46 Gate electrode 100, 200, 300, 400 Semiconductor device I1, I3 Leakage current I2, I4 Current P1, P2, P3, P6 P7 points S1, S1A, S4, S5 equipotential region S2, S6 first electrode region S2a, S8 region S3, S7 second electrode region

Claims (15)

A first semiconductor layer formed on a substrate and made of a nitride semiconductor; a second semiconductor layer formed on a surface of the first semiconductor layer and made of a nitride semiconductor having a wider band gap than the first semiconductor layer; A nitride-based semiconductor layer containing
A first electrode and a second electrode formed on the second semiconductor layer;
An equipotential region formed on the substrate side or in the substrate with respect to the first semiconductor layer;
A passive circuit including an electric resistance portion and a capacitance portion connected between the first electrode and the equipotential region;
When the voltage applied between the first electrode and the second electrode is switched from a reverse voltage to a forward voltage, the equipotential region becomes the second electrode. The semiconductor device is configured to have a positive potential with respect to. The semiconductor device according to claim 1, wherein the passive circuit is configured to satisfy the following formula (A).

The first or second electrode region is a region where the first or second electrode and a conductor connected to the first or second electrode are formed, or the surface or inside of the nitride-based semiconductor layer corresponding to the region. It is an area.   The semiconductor device according to claim 1, wherein the equipotential region is formed in the substrate.   The semiconductor device according to claim 1, further comprising a package in which the semiconductor element is accommodated, wherein the passive circuit is accommodated in the package.   The package includes a conductive substrate, the semiconductor element is mounted on the conductive substrate via a dielectric layer, and the electric resistance portion and the capacitance portion are connected to an equipotential region in the substrate. The semiconductor device according to claim 4, wherein the semiconductor device includes a resistance component and a capacitance component of the dielectric layer between the conductive substrate and the conductive substrate.   The semiconductor device according to claim 1, further comprising a package in which the semiconductor element is accommodated, wherein the passive circuit is arranged outside the package.   3. The equipotential region is configured by an n-type semiconductor layer, a p-type semiconductor layer, or a two-dimensional electron gas layer formed in the nitride-based semiconductor layer. Semiconductor device.   The electrical resistance portion is configured by a resistance component of the nitride-based semiconductor layer between the equipotential region and the substrate, and an area of the equipotential region or between the equipotential region and the substrate. 8. The semiconductor device according to claim 7, wherein the electrical resistance is adjusted by the thickness or electrical resistivity of the nitride-based semiconductor layer.   The capacitance section is configured by a capacitance component of the nitride-based semiconductor layer between the equipotential region and the substrate, and the area of the equipotential region or the equipotential region and the substrate 9. The semiconductor device according to claim 7, wherein the capacitance is adjusted by a thickness or a dielectric constant of the nitride-based semiconductor layer therebetween.   The electrical resistance between the first or second electrode region and the equipotential region is constituted by a resistance component of the nitride-based semiconductor layer between the first or second conductive region and the equipotential region. The electrical resistance depends on the area of the first or second electrode region, or the thickness or electrical resistivity of the nitride-based semiconductor layer between the first or second electrode region and the equipotential region. The semiconductor device according to claim 3, wherein the semiconductor device is adjusted.   The capacitance between the first or second electrode region and the equipotential region is a capacitance component of the nitride-based semiconductor layer between the first or second conductive region and the equipotential region. Depending on the area of the first or second electrode region or the thickness or dielectric constant of the nitride-based semiconductor layer between the first or second electrode region and the equipotential region. The semiconductor device according to claim 3, wherein the capacitance is adjusted.   The electrical resistivity of the nitride based semiconductor layer depends on at least one of the type of the nitride based semiconductor layer, the impurity concentration in the nitride based semiconductor layer, and the density of crystal defects in the nitride based semiconductor layer. The semiconductor device according to claim 8, wherein the semiconductor device is adjusted.   The semiconductor device according to claim 1, wherein the substrate is made of conductive silicon.   The first electrode is an anode electrode, the second electrode is a cathode electrode, and the ratio of the area of the first electrode region to the area of the second electrode region is greater than 0.5, 14. The semiconductor device according to claim 3, wherein the semiconductor device according to claim 2 is cited.   The first electrode is a drain electrode region, the second electrode is a source electrode, and the ratio of the area of the first electrode region to the area of the second electrode region is smaller than 0.5. 14. The semiconductor device according to claim 3, wherein the semiconductor device according to claim 2 is cited.

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