JP2015012271A - Method for manufacturing wiring board - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for manufacturing a wiring board capable of surely suppressing generation of undercut and manufacturing a wiring board having excellent reliability.SOLUTION: A seed layer forming step forms a first seed layer and a second seed layer. A resist forming step forms a plating resist 21 on the second seed layer. A second seed layer removing step removes the second seed layer by etching which uses a first etchant. A wiring pattern forming step forms a part of a wiring pattern by plating an opening of the plating resist with copper . A resist removing step removes the plating resist 21. After the second seed layer removing step, an alloy layer forming step is performed which forms an alloy layer 24 by alloying copper in the first seed layer and a metallic material in the second seed layer. After the resist removing step, an alloy layer removing step is performed which removes the alloy layer 24 by etching which uses a second etchant.

Description

  The present invention relates to a method for manufacturing a wiring board in which a wiring pattern is formed on a main surface of a substrate body.

  In recent years, with the miniaturization of electrical equipment and electronic equipment, miniaturization and high density are also demanded for wiring boards and the like mounted on these equipment. As an example, a wiring board having a build-up layer formed by alternately laminating resin insulating layers and conductor layers (wiring patterns) on one side or both sides of a core board has been conventionally proposed.

  The wiring pattern can be formed by the following procedure, for example. First, a copper plating layer (seed layer) is formed on the entire surface of the resin insulating layer. Next, after applying a photosensitive dry film on the copper plating layer, exposure and development are performed to form a predetermined pattern of plating resist. Furthermore, after performing the wiring pattern formation process which forms a wiring pattern by performing copper plating in the opening part of a plating resist, the resist removal process which peels (removes) a plating resist using a peeling liquid is performed. Then, a wiring pattern having a desired shape is obtained by performing a plating layer removing step of removing a portion of the copper plating layer covered with the plating resist by etching.

  However, in the removal process, there is a possibility that a phenomenon (so-called undercut) occurs in which the bottom of the wiring pattern is etched along with the removal of the copper plating layer. In this case, the contact area between the wiring pattern and the resin insulating layer is reduced, and the adhesion between the two is reduced. Therefore, the wiring pattern is peeled off or disconnected, resulting in an increased defective product rate and reduced yield. There is a problem.

  Therefore, conventionally, various techniques for solving the problems caused by the occurrence of undercut have been proposed (see, for example, Patent Documents 1 to 3). More specifically, Patent Document 1 proposes a technique for suppressing the occurrence of undercut by improving the etching solution. Patent Document 2 discloses a wiring pattern in which another seed layer (alloy layer) made of an alloy having etching resistance is formed on a seed layer (copper plating layer) exposed in an opening of a plating resist. There has been proposed a technique for suppressing the occurrence of undercut by sequentially performing a formation process, a resist removal process, and a plating layer removal process.

JP 2009-149971 A ([0013] etc.) JP 2006-24902 A (FIG. 1 etc.)

  However, the conventional techniques described in Patent Documents 1 to 3 have the following problems. That is, in the prior art described in Patent Document 1, the etching solution is improved because the region removed by etching in the seed layer and the region constituting the bottom of the wiring pattern in the seed layer are made of the same component (copper). However, there is a problem that the occurrence of undercut cannot be sufficiently suppressed. Moreover, when the prior art described in Patent Document 2 is adopted, the occurrence of undercuts can be suppressed, but the alloy layer may reduce the insulation between adjacent wiring patterns, and thus manufacturing. The reliability of the printed wiring board may be reduced.

  The present invention has been made in view of the above-described problems, and an object of the present invention is to provide a wiring board capable of reliably suppressing the occurrence of undercut and capable of manufacturing a highly reliable wiring board. It is to provide a manufacturing method.

  Means for solving the above problems (Means 1) is a method of manufacturing a wiring board by forming a wiring pattern on the substrate main surface of the substrate body, covering the substrate main surface, A first seed layer made of copper, and a seed layer forming step of covering the first seed layer and forming a second seed layer made of a metal material other than copper; and a plating resist having an opening is formed into the second seed layer. A second seed layer that removes the second seed layer exposed through the opening by a resist forming step formed on the layer and etching using a first etching solution that selectively dissolves the metal material After the removing step and the second seed layer removing step, copper plating is performed in the opening to form a part of the wiring pattern, and after the wiring pattern forming step, the plating layer is formed. And a resist removing step for removing a strike, and after the second seed layer removing step, by performing a heat treatment, the copper in the first seed layer and the metal material in the second seed layer are alloyed. Performing an alloy layer forming step of forming an alloy layer, and after the resist removing step, performing an alloy layer removing step of removing the alloy layer by etching using a second etching solution that selectively dissolves the alloy layer. There is a method of manufacturing a wiring board characterized by the following.

  Therefore, according to the method of manufacturing the wiring substrate of means 1, the first seed layer formed in the seed layer forming step includes a region that becomes the bottom of the wiring pattern and a region that is removed without being a wiring pattern. Exists. Then, the region to be removed in the first seed layer is alloyed with the second seed layer in the alloy layer forming step to become an alloy layer, and then removed by etching using the second etchant in the alloy layer removing step. Is done. Since the second etching solution selectively dissolves only the alloy layer and not the wiring pattern, the occurrence of undercut in the wiring pattern can be reliably suppressed. Further, by performing the alloy layer removing step, the manufactured wiring board does not include an alloy layer that causes a decrease in insulation, so that the reliability of the wiring board can be ensured.

  Hereinafter, a method for manufacturing a wiring board will be described.

  First, a seed layer forming step is performed to cover the substrate main surface of the wiring substrate (substrate body), to cover the first seed layer made of copper, and to cover the first seed layer and to make a second material made of a metal material other than copper. A seed layer is formed.

  Here, as the wiring board, for example, a resin wiring board, a ceramic wiring board, a glass wiring board, a metal wiring board, or the like can be used. However, considering the cost, the resin wiring board is preferable. Preferable examples of such resin wiring boards include wiring boards made of EP resin (epoxy resin), PI resin (polyimide resin), BT resin (bismaleide-triazine resin), PPE resin (polyphenylene ether resin), and the like. Can do. In addition, a wiring board made of a composite material of these resins and organic fibers such as glass fibers (glass woven fabric or glass nonwoven fabric) or polyamide fibers may be used. As a preferred example of the ceramic wiring board, there is a wiring board made of alumina, aluminum nitride, silicon nitride, boron nitride, beryllia, mullite, or the like. Furthermore, when the suitable example of a glass wiring board is given, there exists a wiring board which consists of borosilicate glass, low-temperature baking glass ceramic, glass ceramic, etc. Moreover, as a suitable example of a metal wiring board, the wiring board which consists of copper, the wiring board which consists of a copper alloy, the wiring board which consists of single metals other than copper, the wiring board which consists of alloys other than copper etc. can be mentioned, for example. .

  The metal material constituting the second seed layer is not particularly limited as long as it can be selectively removed leaving copper when coexisting with copper, for example, Sn, Ni, Ti There may be mentioned at least one selected from among, or any one selected from Sn—Pb and Ni—Cr. However, in particular, the metal material may be Sn or Sn—Pb. In this way, in the heat treatment in the alloy layer forming step, alloying with copper can be performed at a low temperature (specifically, 250 ° C. or lower), and thus damage to the substrate body due to heat can be prevented. .

  In the subsequent resist formation step, a plating resist having an opening is formed on the second seed layer. Although it does not specifically limit as a plating resist, For example, it is suitable to form the plating resist of a predetermined pattern by performing exposure and image development, for example using an acryl-type dry film and sticking. The dry film may be either a negative type or a positive type, but it is preferable to select a negative type here. This is because the negative type has a disadvantage that it needs to be peeled off with a predetermined stripping solution since the peelability is lowered when temperature is applied, but has an advantage that it is advantageous for forming a pattern having a good shape.

  In the subsequent second seed layer removal step, the second seed layer exposed through the opening is removed by etching using a first etching solution that hardly dissolves copper and selectively dissolves the metal material. Note that when the second seed layer is made of Sn or Sn—Pb, the first etching solution may be a nitric acid-based etching solution. When the second seed layer is made of Ni or Ti, examples of the first etching solution include a hydrogen peroxide-based etching solution. In the case where the second seed layer is made of Ni—Cr, examples of the first etchant include an remover CH series etchant manufactured by MEC Co., Ltd.

  In the wiring pattern forming step after the second seed layer removing step, copper plating is performed in the opening of the plating resist to form a part of the wiring pattern. In the resist removing step after the wiring pattern forming step, the plating resist is removed (peeled). Although it does not specifically limit as stripping solution used for the removal of a plating resist, For example, it is suitable to use organic amine type stripping solution. Examples of the organic amine contained as a main component in the organic amine-based stripping solution include monoethanolamine, diethanolamine, triethanolamine, monomethylamine, dimethylamine, trimethylamine, ethyleneamine, isopropylamine, isopropanolamine, and 2-amino-2. -Methyl-1-propanol, 2-amino-2-methyl-1,3-propanediol and the like. Note that an additive such as hydrazine or TMH may be added to the organic amine stripping solution used in the resist removing step.

  In the alloy layer forming step after the second seed layer removing step, heat treatment is performed to alloy the copper in the first seed layer and the metal material in the second seed layer to form an alloy layer. The alloy layer forming step may be performed after the second seed layer removing step and before the wiring pattern forming step, may be performed after the wiring pattern forming step and before the resist removing step, or the resist removing step. It may be performed after and before the alloy layer removing step. However, when the alloy layer forming process is performed after the second seed layer removing process and before the wiring pattern forming process, the heat treatment is performed before the wiring pattern is formed. Damage to the pattern can be prevented.

  In the alloy layer removing step after the resist removing step, the alloy layer is removed by etching using a second etching solution that selectively dissolves the alloy layer. At this point, the wiring board is completed. Here, the first etching solution and the second etching solution may be the same etching solution or different etching solutions, but are preferably the same etching solution. In this way, it is not necessary to prepare different etchants for the second seed layer removal step and the alloy layer removal step, and thus the manufacturing cost of the wiring board can be reduced. Moreover, it is preferable that the volume ratio of the metal material contained in the alloy layer is larger than the volume ratio of copper contained in the alloy layer. That is, it is preferable that the alloy layer contains more metal material that is easily dissolved by the second etching solution than copper that is hardly dissolved by the second etching solution. In this way, the entire alloy layer is easily dissolved by the second etching solution, and the removal of the alloy layer in the metal layer removal step is completed in a short time, so that the second etching solution is added to the wiring pattern. The contact time is even shorter. Accordingly, since the wiring pattern is hardly affected by the second etching solution, undercut can be more reliably suppressed.

  Note that the depth from the side surface of the undercut wiring pattern that may occur at the bottom of the wiring pattern after the alloy layer removing step is preferably 3 μm or less. If the depth of the undercut is larger than 3 μm, the occurrence of the undercut cannot be sufficiently suppressed, so that the contact area between the wiring pattern and the substrate body is reduced, and the adhesion between the two is reduced. As a result, the wiring pattern is likely to be peeled off or disconnected, so that the defective product generation rate is increased and the yield is likely to be reduced.

1 is a schematic cross-sectional view showing a wiring board according to an embodiment embodying the present embodiment. The principal part sectional view showing a wiring pattern. Explanatory drawing which shows the process of forming a resin insulating layer on a core main surface and a core back surface. Explanatory drawing which shows a seed layer formation process. Explanatory drawing which shows a resist formation process. Explanatory drawing which shows a 2nd seed layer removal process. Explanatory drawing which shows an alloy layer formation process. Explanatory drawing which shows a wiring pattern formation process. Explanatory drawing which shows a resist removal process. Explanatory drawing which shows an alloy layer removal process. Explanatory drawing which shows the process of laminating | stacking and arrange | positioning the 3rd resin insulation layer so that a wiring pattern may be covered on the 2nd resin insulation layer.

  Hereinafter, an embodiment which embodies the wiring board 1 of the present invention will be described in detail with reference to the drawings.

  As shown in FIG. 1, the wiring board 1 of this embodiment is a wiring board for mounting an IC chip. The substrate body 10 constituting the wiring substrate 1 includes a substantially rectangular plate-shaped core substrate 11, a main surface side buildup layer 31 formed on the core main surface 12 (upper surface in FIG. 1) of the core substrate 11, and a core The back surface side buildup layer 32 is formed on the core back surface 13 (the lower surface in FIG. 1) of the substrate 11.

  The core substrate 11 of the present embodiment has a substantially rectangular plate shape in plan view of 25 mm length × 25 mm width × 0.8 mm thickness. The core substrate 11 is made of a thermosetting resin (epoxy resin), and has a thermal expansion coefficient of about 10 to 30 ppm / ° C. (specifically, 18 ppm / ° C.) in the plane direction (XY direction). In addition, the thermal expansion coefficient of the core board | substrate 11 says the average value of the measured value between 0 degreeC-glass transition temperature (Tg).

  A plurality of through-hole conductors 16 are formed in the core substrate 11 so as to penetrate the core main surface 12 and the core back surface 13. The through-hole conductor 16 connects and connects the core main surface 12 side and the core back surface 13 side of the core substrate 11. Note that the inside of the through-hole conductor 16 is filled with a filling resin 17 such as an epoxy resin. Further, a main surface side conductor layer 14 made of copper is patterned on the core main surface 12 of the core substrate 11, and a back surface side conductor layer 15 also made of copper is patterned on the core back surface 13 of the core substrate 11. ing. Each of the conductor layers 14 and 15 is electrically connected to the through-hole conductor 16.

  As shown in FIG. 1, the main surface side buildup layer 31 includes three resin insulation layers 33, 35, and 37 made of thermosetting resin (epoxy resin), and wiring patterns 41, 42, and 43 made of copper. Are alternately stacked. The thermal expansion coefficient of the resin insulating layers 33, 35, and 37 in a completely cured state is about 10 to 60 ppm / ° C., specifically 46 ppm / ° C. In addition, the thermal expansion coefficient of the resin insulating layers 33, 35, and 37 refers to an average value of measured values between 25 ° C and 150 ° C. Further, via conductors 47 formed by copper plating are provided in the resin insulating layers 33 and 35, respectively. The upper end of the through-hole conductor 16 is electrically connected to a part of the wiring pattern 41 on the upper surface of the first resin insulating layer 33. The surface of the resin insulating layer 37 is almost entirely covered with a solder resist 39. An opening 50 for exposing the wiring pattern 43 is formed at a predetermined position of the solder resist 39. A plurality of solder bumps 51 are arranged on the surface of the wiring pattern 43.

  Each solder bump 51 is electrically connected to a surface connection terminal of an IC chip (semiconductor integrated circuit element). The IC chip of this embodiment is a plate-like object having a rectangular shape in plan view of 12.0 mm long × 12.0 mm wide × 0.9 mm thick, and has a thermal expansion coefficient of about 3 to 4 ppm / ° C. (specifically (About 3.5 ppm / ° C.).

  As shown in FIG. 1, the back surface side buildup layer 32 has substantially the same structure as the main surface side buildup layer 31 described above. That is, the back-side buildup layer 32 has a structure in which three resin insulating layers 34, 36, and 38 made of thermosetting resin (epoxy resin) and wiring patterns 44, 45, and 46 made of copper are alternately laminated. have. The thermal expansion coefficient of the resin insulating layers 34, 36, and 38 in a completely cured state is about 10 to 60 ppm / ° C. (specifically, about 46 ppm / ° C.). In addition, the thermal expansion coefficient of the resin insulating layers 34, 36, and 38 refers to an average value of measured values between 25 ° C and 150 ° C. Further, via conductors 48 each formed by copper plating are provided in the resin insulating layers 34 and 36. The lower end of the through-hole conductor 16 is electrically connected to a part of the wiring pattern 44 on the lower surface of the first resin insulating layer 34. The lower surface of the resin insulating layer 38 is almost entirely covered with the solder resist 40. An opening 52 that exposes the wiring pattern 46 is formed at a predetermined location of the solder resist 40.

  As shown in FIGS. 1 and 2, the wiring patterns 42 and 45 of this embodiment have an electroless copper plating layer 61 as a first seed layer made of copper at the bottom. Further, at the bottom of the wiring patterns 42 and 45 (the portion where the electroless copper plating layer 61 exists), an inversely tapered undercut U1 is formed which becomes thinner toward the core substrate 11 side. The depth U2 from the side surface 49 of the wiring patterns 42 and 45 of the undercut U1 is 3 μm or less (1.2 μm in this embodiment).

  Next, the manufacturing method of the wiring board 1 of this embodiment is demonstrated.

  First, an intermediate product of the core substrate 11 is prepared by a conventionally known method and prepared in advance. The intermediate product of the core substrate 11 is manufactured as follows. First, a copper clad laminate (not shown) in which a copper foil is pasted on both sides of a base having a length of 400 mm, a width of 400 mm, and a thickness of 0.8 mm is prepared. Next, the copper foils on both sides of the copper clad laminate are etched to pattern the conductor layers 14 and 15 by, for example, a subtractive method. Specifically, after the electroless copper plating, electrolytic copper plating is performed using the electroless copper plating layer as a common electrode. Further, the dry film is laminated, and the dry film is exposed and developed to form a dry film in a predetermined pattern. In this state, unnecessary electrolytic copper plating layer, electroless copper plating layer and copper foil are removed by etching. Thereafter, the dry film is peeled off to obtain an intermediate product of the core substrate 11. The intermediate product of the core substrate 11 is a multi-piece core substrate having a structure in which a plurality of regions to be the core substrate 11 are arranged vertically and horizontally along the plane direction.

  Next, the main surface side buildup layer 31 is formed on the core main surface 12 and the back surface side buildup layer 32 is formed on the core back surface 13 based on a conventionally known technique. Specifically, first, a resin insulating layer 33 is formed by depositing (attaching) a thermosetting epoxy resin on the core main surface 12 (see FIG. 3). Moreover, the resin insulating layer 34 is formed by depositing (attaching) a thermosetting epoxy resin on the core back surface 13 (see FIG. 3). Instead of depositing a thermosetting epoxy resin, a photosensitive epoxy resin, an insulating resin, or a liquid crystal polymer (LCP) may be deposited.

  Further, laser drilling is performed using a YAG laser or a carbon dioxide gas laser to form via holes at positions where via conductors 47 and 48 are to be formed. Further, drilling is performed using a drill machine, and through holes that penetrate the core substrate 11 and the resin insulating layers 33 and 34 are formed in advance at predetermined positions. Next, after performing electroless copper plating on the inner surfaces of the via holes and the through holes on the surfaces of the resin insulating layers 33 and 34, electrolytic copper plating is performed. As a result, the first copper plating layer 71 is formed on the entire surface of the resin insulating layers 33, 34, the through-hole conductor 16 is formed in the through hole, and the via conductors 47, 48 are formed in each via hole. Is done. Thereafter, the hollow portion of the through-hole conductor 16 is filled with an insulating resin material (epoxy resin) to form a filling resin 17 (see FIG. 3).

  Next, the second copper plating layer 72 (see FIG. 3) is formed on the surface of the first copper plating layer 71 by performing electrolytic copper plating according to a conventionally known method. Further, the second copper plating layer 72 is etched to pattern the second copper plating layer 72 by, for example, a subtractive method. Specifically, a dry film is laminated on the second copper plating layer 72 on the resin insulation layer 33 and the second copper plating layer 72 on the resin insulation layer 34, and the dry film is exposed and developed. Thus, the dry film is formed into a predetermined pattern. In this state, unnecessary copper plating layers 71 and 72 are removed by etching, and then the dry film is peeled off. As a result, the wiring pattern 41 including the first copper plating layer 71 and the second copper plating layer 72 is formed on the resin insulating layer 33, and the first copper plating layer 71 and the second copper plating layer 71 are also formed on the resin insulating layer 34. A wiring pattern 44 composed of the two copper plating layers 72 is formed (see FIG. 3). At this time, a part of the second copper plating layer 72 on the resin insulating layer 33 becomes a lid plating layer that covers the end surface of the through-hole conductor 16 on the core main surface 12 side, and the second copper plating layer on the resin insulating layer 34 A part of 72 becomes a lid plating layer that covers the end surface of the through-hole conductor 16 on the core back surface 13 side.

  Next, a thermosetting epoxy resin is deposited on the resin insulation layers 33 and 34 to form resin insulation layers 35 and 36 having via holes at positions where the via conductors 47 and 48 are to be formed (FIG. 4). reference). Instead of depositing the thermosetting epoxy resin, a photosensitive epoxy resin, an insulating resin, or a liquid crystal polymer may be deposited. In this case, via holes are formed at positions where the via conductors 47 and 48 are to be formed by a laser processing machine or the like.

  Next, after performing a seed layer formation process and forming the electroless copper plating layer 61 as the first seed layer, electrolytic tin plating as the second seed layer made of a metal material other than copper (Sn in this embodiment) Layer 62 is formed (see FIG. 4). More specifically, a thickness of 0 covering the substrate main surface 60 by performing electroless copper plating on the entire surface (substrate main surface 60) of the resin insulating layers 35 and 36 including the inner surface of the via hole. An electroless copper plating layer 61 having a thickness of 7 μm is formed. Furthermore, by performing electrolytic tin plating on the entire surface of the electroless copper plating layer 61, an electrolytic tin plating layer 62 having a thickness of 1.5 μm that covers the electroless copper plating layer 61 is formed.

  In the subsequent resist formation step, a plating resist 21 having openings 22 and 23 is formed on the electrolytic tin plating layer 62 (see FIG. 5). Specifically, by laminating a dry film having a thickness of 20 μm on the surface of the electrolytic tin plating layer 62 and exposing and developing the dry film, the first opening 22 having a width of 30 μm and a width of 150 μm. The plating resist 21 having the second opening 23 is formed.

  In the subsequent second seed layer removing step, etching using the first etching solution is performed for 30 seconds to remove the electrolytic tin plating layer 62 exposed through the openings 22 and 23 (see FIG. 6). The first etching solution (Meltex TL3400 manufactured by Meltex Co., Ltd.) of the present embodiment is a nitric acid-based etching solution that hardly dissolves copper and selectively dissolves a metal material (tin).

  In the alloy layer forming step performed after the second seed layer removing step and before the wiring pattern forming step described later, heat treatment is performed at 120 ° C. for 3 hours. As a result, in the region covered with the plating resist 21, the copper in the electroless copper plating layer 61 and the metal material (Sn) in the electrolytic tin plating layer 62 are alloyed to form the alloy layer 24 (FIG. 7). reference). The volume ratio of tin (Sn) contained in the alloy layer 24 is about 68%, and the volume ratio of copper (Cu) contained in the alloy layer 24 is about 32%. Therefore, the volume ratio of tin contained in the alloy layer 24 is larger than the volume ratio of copper contained in the alloy layer 24.

  In the wiring pattern forming step after the alloy layer forming step, electrolytic copper plating is performed after performing electroless copper plating on the inner surfaces of the openings 22 and 23. As a result, a part of the wiring patterns 42 and 45 (specifically, a part excluding the electroless copper plating layer 61 in the wiring patterns 42 and 45) is formed in the openings 22 and 23 (see FIG. 8).

  In the resist removing step after the wiring pattern forming step, the plating resist 21 is removed (see FIG. 9). Specifically, the plating resist 21 is stripped using an organic amine stripping solution (0.5 wt% or more, 50 ° C. or more) containing monoethanolamine as a main component.

  In the alloy layer removing step after the resist removing step, etching using a second etching solution that selectively dissolves the alloy layer 24 is performed for 4 minutes to remove the alloy layer 24 (see FIG. 10). By this processing, the interconnected wiring patterns 42 are independent from each other, and the interconnected wiring patterns 45 are also independent from each other. Note that the second etching solution of the present embodiment is the same etching solution as the first etching solution. After the alloy layer removing step, an undercut U1 (see FIG. 2) can occur at the bottom of the wiring patterns 42 and 45.

  Thereafter, the resin insulating layers 37 and 38 are formed by depositing a thermosetting epoxy resin on the resin insulating layers 35 and 36 (see FIG. 11). At this time, the resin insulating layer 37 is laminated on the resin insulating layer 35 so as to cover the wiring pattern 42. Similarly, a resin insulating layer 38 is laminated on the resin insulating layer 36 so as to cover the wiring pattern 45. Instead of depositing the thermosetting epoxy resin, a photosensitive epoxy resin, an insulating resin, or a liquid crystal polymer may be deposited. Next, electrolytic copper plating is performed according to a conventionally known method to form a wiring pattern 43 on the resin insulating layer 37 and a wiring pattern 46 on the resin insulating layer 38.

  Next, solder resists 39 and 40 are formed by applying and curing a photosensitive epoxy resin on the resin insulating layers 37 and 38. Next, exposure and development are performed with a predetermined mask placed, and the openings 50 and 52 are patterned in the solder resists 39 and 40. Further, solder bumps 51 are formed on the wiring pattern 43, and solder bumps (not shown) are formed on the wiring pattern 46. It can be understood that the product in this state is a multi-cavity wiring board in which a plurality of product regions to be the wiring board 1 are arranged vertically and horizontally along the plane direction. Furthermore, when the multi-piece wiring board is divided, a large number of wiring boards 1 as individual products can be obtained simultaneously.

  Next, an IC chip is placed on the surface of the main surface side buildup layer 31 constituting the wiring board 1. At this time, the surface connection terminals on the IC chip side and the solder bumps 51 are aligned. Then, the solder bump 51 is reflowed by heating to a temperature of about 220 ° C. to 240 ° C., thereby joining the solder bump 51 and the surface connection terminal, and electrically connecting the wiring substrate 1 side and the IC chip side. . As a result, an IC chip is mounted on the wiring board 1 (see FIG. 1).

  Next, a method for evaluating a wiring board and the result will be described.

First, a measurement sample was prepared as follows. Each step (seed layer forming step, resist forming step, second seed layer removing step, alloy layer forming step, wiring pattern forming step, resist removing step, alloy layer removing step) is performed under the same conditions as in this embodiment. The wiring board obtained by the above was prepared, and this was designated as Example 1. In Example 1, the alloy layer was observed (XRD observation) with an X-ray diffractometer (XRD) after the alloy layer forming step and before the wiring pattern forming step, and as a result, Cu ₆ Sn ₅ and Sn were identified. It was done. Moreover, the wiring board obtained by performing each process in the state which changed the thickness of the electroless copper plating layer (first seed layer) and the electrolytic tin plating layer (second seed layer) to 0.7 μm respectively. This was prepared as Example 2. In Example 2, as a result of XRD observation after the alloy layer forming step and before the wiring pattern forming step, Cu ₆ Sn ₅ and Cu were identified. In Example 2, it took 6 minutes to remove the alloy layer 24 using the second etching solution. On the other hand, the wiring board obtained by forming a wiring pattern in the state which formed the single seed layer by the electroless copper plating layer was prepared, and this was made into the comparative example.

  Next, the cross section of the wiring pattern was observed for each measurement sample (Examples 1 and 2, Comparative Example), and the depth from the side surface of the undercut wiring pattern was measured. Here, in each of Examples 1 and 2 and Comparative Example, the depth of undercut was measured for 10 measurement samples, and the average value of the obtained measurement values was calculated. And if the average value of the depth of undercut was 3 micrometers or less, it judged with "pass", and if larger than 3 micrometers, it judged with "fail".

  As a result, in the comparative example, the average value of the depth of the undercut was 3.6 μm (“failed”), so it was confirmed that the undercut was not sufficiently suppressed. On the other hand, in Example 1, the average value of the depth of undercut was 1.2 μm (“pass”), and in Example 2, the average value of the depth of undercut was 2.5 μm (“pass”). It was confirmed that the undercut was reliably suppressed.

  Therefore, it has been proved that undercutting is reliably suppressed if the wiring pattern is formed through the process of forming the first seed layer and the second seed layer.

  Therefore, according to the present embodiment, the following effects can be obtained.

  (1) In the manufacturing method of the wiring substrate 1 of the present embodiment, the electroless copper plating layer 61 formed in the seed layer forming step includes a region serving as the bottom of the wiring patterns 42 and 45, and the wiring patterns 42 and 45. There is a region that is removed without breaking. The region to be removed in the electroless copper plating layer 61 is alloyed with the electrolytic tin plating layer 62 in the alloy layer forming step to form the alloy layer 24, and then the second etching solution is used in the alloy layer removing step. It is removed by etching. Since the second etching solution selectively dissolves only the alloy layer 24 and does not dissolve the wiring patterns 42 and 45, the occurrence of undercut U1 in the wiring patterns 42 and 45 is ensured. Can be suppressed. Therefore, since the occurrence of undercut U1 in the wiring patterns 42 and 45 is suppressed, the wiring patterns 42 and 45 can be easily miniaturized. Further, by performing the alloy layer removing step, the manufactured wiring board 1 does not include the alloy layer 24 that causes a decrease in insulation, so that the reliability of the wiring board 1 can be ensured.

  (2) In this embodiment, since the alloy layer 24 contains a metal material (tin in this embodiment) that is easily dissolved by the second etching solution, the alloy layer 24 is removed in the metal layer removal step. The process is completed in a short time, and the time for the second etching solution to contact the wiring patterns 42 and 45 is also shortened. Moreover, the volume ratio of tin (about 68%) contained in the alloy layer 24 is larger than the volume ratio (about 32%) of copper contained in the alloy layer 24. That is, the alloy layer 24 contains more tin that is easily dissolved by the second etching solution than copper that is not easily dissolved by the second etching solution. As a result, the alloy layer 24 is more easily dissolved by the second etching solution, and the removal of the alloy layer 24 in the metal layer removing process is completed in a shorter time. The contact time of the etching solution is further shortened. Accordingly, since the wiring patterns 42 and 45 are not easily affected by the second etching solution, the undercut U1 can be more reliably suppressed.

  (3) In the prior art described in Japanese Patent Laid-Open No. 2006-49804, instead of forming a wiring pattern by etching, a groove is formed and then a metal is embedded, and the embedded metal is cut by CMP (Chemical Mechanical Polishing). A technique for suppressing the occurrence of undercut by forming a wiring pattern using a technique (so-called damascene process) is disclosed. However, in this case, since the seed layer must be removed by special polishing called CMP, there is a problem that the manufacturing cost of the wiring board increases. Therefore, in the present embodiment, the alloy layer 24 is selectively removed using the second etching solution after the formation of the wiring patterns 42 and 45 without using special polishing as in JP-A-2006-49804. As a result, the undercut U1 that may occur in the wiring patterns 42 and 45 is suppressed. For this reason, the wiring patterns 42 and 45 can be formed at a lower cost than in the case of using a damascene process.

  In addition, you may change this embodiment as follows.

  In the above embodiment, the alloy layer forming step is performed after the second seed layer removing step and before the wiring pattern forming step. However, the timing of executing the alloy layer forming step may be changed. For example, the alloy layer forming step may be executed after the wiring pattern forming step and before the resist removing step. Moreover, you may perform an alloy layer formation process after a resist removal process and before an alloy layer removal process.

  In the above embodiment, the wiring patterns 42 and 45 are made of copper, but the wiring patterns may be made of nickel (Ni). In this case, in the seed layer forming step, an electroless nickel plating layer which is a first seed layer made of nickel is formed, and in the alloy layer forming step, nickel in the electroless nickel plating layer and tin in the electrolytic tin plating layer are formed. An alloy layer is formed by alloying, and in the wiring pattern forming step, a part of the wiring pattern is formed by performing nickel plating in the opening of the plating resist.

  Next, the technical ideas grasped by the embodiment described above are listed below.

  (1) In the above means 1, the method of manufacturing a wiring board, wherein the second seed layer is made of the metal material that can be removed by etching using an etchant that hardly dissolves the first seed layer.

  (2) The method for manufacturing a wiring board according to the above means 1, wherein the etching rate of the first etching solution and the etching rate of the second etching solution are different from each other.

  (3) A method of manufacturing a wiring board by forming a wiring pattern on a substrate main surface of a substrate body, the first seed layer made of nickel covering the substrate main surface, and the first A seed layer forming step of covering one seed layer and forming a second seed layer made of a metal material other than nickel; a resist forming step of forming a plating resist having an opening on the second seed layer; A second seed layer removing step of removing the second seed layer exposed through the opening by etching using a first etching solution that selectively dissolves a metal material; and after the second seed layer removing step A wiring pattern forming step of performing nickel plating in the opening and forming a part of the wiring pattern; and a resist for removing the plating resist after the wiring pattern forming step Including a leaving step, and after the second seed layer removing step, by performing a heat treatment, the nickel in the first seed layer and the metal material in the second seed layer are alloyed to form an alloy layer. Conducting an alloy layer, and after the resist removing step, performing an alloy layer removing step of removing the alloy layer by etching using a second etching solution that selectively dissolves the alloy layer. A method for manufacturing a substrate.

DESCRIPTION OF SYMBOLS 1 ... Wiring board 10 ... Board | substrate main body 21 ... Plating resist 22 ... 1st opening part 23 as an opening part ... 2nd opening part 24 as an opening part ... Alloy layer 42, 45 ... Wiring pattern 49 ... Side surface 60 of a wiring pattern ... Substrate main surface 61 ... electroless copper plating layer 62 as first seed layer ... electrolytic tin plating layer U1 as second seed layer ... undercut U2 ... depth from side of undercut wiring pattern

Claims (6)

A method of manufacturing a wiring board by forming a wiring pattern on a substrate main surface of a substrate body,
A seed layer forming step of covering the substrate main surface, forming a first seed layer made of copper, and covering the first seed layer and forming a second seed layer made of a metal material other than copper;
A resist forming step of forming a plating resist having an opening on the second seed layer;
A second seed layer removing step of removing the second seed layer exposed through the opening by etching using a first etchant that selectively dissolves the metal material;
After the second seed layer removing step, copper plating is performed in the opening to form a part of the wiring pattern; and
A resist removal step of removing the plating resist after the wiring pattern formation step,
After the second seed layer removing step, an alloy layer forming step is performed in which an alloy layer is formed by alloying the copper in the first seed layer and the metal material in the second seed layer by performing a heat treatment. ,
A method of manufacturing a wiring board, comprising performing an alloy layer removing step of removing the alloy layer by etching using a second etching solution that selectively dissolves the alloy layer after the resist removing step.   The method for manufacturing a wiring board according to claim 1, wherein the alloy layer forming step is performed after the second seed layer removing step and before the wiring pattern forming step.   3. The method for manufacturing a wiring board according to claim 1, wherein the first etching solution and the second etching solution are the same etching solution.   4. The wiring board manufacturing method according to claim 1, wherein a volume ratio of the metal material included in the alloy layer is larger than a volume ratio of the copper included in the alloy layer. 5. Method.   5. The method of manufacturing a wiring board according to claim 1, wherein the metal material is Sn or Sn—Pb. 6.   6. The depth of the undercut from the side surface of the wiring pattern that may occur at the bottom of the wiring pattern after the alloy layer removing step is 3 μm or less. 6. Wiring board manufacturing method.

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