JP2015012065A - Method of manufacturing semiconductor device - Google Patents

Method of manufacturing semiconductor device Download PDF

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JP2015012065A
JP2015012065A JP2013134965A JP2013134965A JP2015012065A JP 2015012065 A JP2015012065 A JP 2015012065A JP 2013134965 A JP2013134965 A JP 2013134965A JP 2013134965 A JP2013134965 A JP 2013134965A JP 2015012065 A JP2015012065 A JP 2015012065A
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semiconductor chip
solder
clip
bonded
bonded portion
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重信 稲葉
Shigenobu Inaba
重信 稲葉
幸宏 前田
Yukihiro Maeda
幸宏 前田
厚司 水谷
Koji Mizutani
厚司 水谷
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Denso Corp
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Denso Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L24/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
    • H01L24/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L24/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L24/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/4005—Shape
    • H01L2224/4009—Loop shape
    • H01L2224/40095—Kinked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/401—Disposition
    • H01L2224/40135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/40137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/401—Disposition
    • H01L2224/40151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/40221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/40245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/83801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
    • H01L2224/848—Bonding techniques
    • H01L2224/84801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Abstract

PROBLEM TO BE SOLVED: To provide a manufacturing method in which void formation in a solder is suppressed.SOLUTION: In a method of manufacturing a semiconductor device in which an island part 21 is jointed to a semiconductor chip 3 by a first solder 5, a load is applied on a position away from the center of gravity of the semiconductor chip 3. Thus, after the first solder 5 is melted and until its soldering completes, a one surface 3a of the semiconductor chip 3 is kept in a condition in which it is inclined against one surface 21a of the island part 21. Thus, the gas (for example, a gas generated when flux is decomposed) present in the first solder 5 being in molten state becomes easy to move in a region where an interval is wide between the one surface of the island part 21 and the one surface 3a of the semiconductor chip 3. Thus, the gas is easy to be released to the outside of the first solder 5 through the wide region, to discourage formation of a void in the first solder 5 after solidification.

Description

本発明は、はんだ接合により、リードフレームや配線基板等に半導体チップ等を実装した半導体装置の製造方法に関する。   The present invention relates to a method for manufacturing a semiconductor device in which a semiconductor chip or the like is mounted on a lead frame, a wiring board, or the like by solder bonding.

従来、はんだ接合により、リードフレーム等に半導体チップ等を接合して構成される半導体装置が知られている。この種の半導体装置の製造方法では、一般に、はんだが加熱により溶融する際に、空気を巻き込むことや、はんだがフラックスを含有する場合にはフラックスが分解ガスを発生させることにより、はんだにこれらの気体が残留してボイドが形成される。はんだにボイドが形成されると、半導体装置の接合強度や放熱性等の性能が不十分となり得るため、好ましくない。   2. Description of the Related Art Conventionally, a semiconductor device configured by bonding a semiconductor chip or the like to a lead frame or the like by solder bonding is known. In this type of semiconductor device manufacturing method, generally, when the solder is melted by heating, air is entrained, or when the solder contains a flux, the flux generates a decomposition gas. Gas remains and voids are formed. If voids are formed in the solder, the performance of the semiconductor device, such as the bonding strength and heat dissipation, may be insufficient.

はんだにおけるボイド形成を抑制する技術として、特許文献１に記載の方法が提案されている。この方法では、はんだ接合によって、リードフレームを基板に接合する際に、この方法では、リードフレームに貫通孔を設け、この貫通孔からはんだ溶融時に生じる気体を放出することにより、はんだにおけるボイド形成を抑制している。   As a technique for suppressing void formation in solder, a method described in Patent Document 1 has been proposed. In this method, when the lead frame is bonded to the substrate by solder bonding, in this method, a lead hole is provided in the lead frame, and a gas generated when the solder melts is released from the through hole, thereby forming a void in the solder. Suppressed.

特開平７−１５３８８９号公報Japanese Patent Laid-Open No. 7-153889

上記の特許文献１の方法では、ボイド抑制効果を高めるためには、リードフレームに設ける貫通孔を大きくしなければならない。しかしながら、リードフレームの強度等の問題から、貫通孔の大きさは制限される。このため、上記の特許文献１の方法では、十分なボイド抑制効果を得ることが難しい。また、上記の特許文献１の方法では、貫通孔を形成することが困難なもの（幅が短いなど孔加工をすることが困難なリードフレームなど）には適用できない。   In the method disclosed in Patent Document 1, in order to increase the void suppression effect, the through hole provided in the lead frame must be enlarged. However, the size of the through hole is limited due to problems such as the strength of the lead frame. For this reason, it is difficult to obtain a sufficient void suppression effect with the method of Patent Document 1 described above. Further, the method disclosed in Patent Document 1 cannot be applied to a device in which it is difficult to form a through hole (such as a lead frame having a short width and difficult to drill).

本発明は上記点に鑑みて、はんだ接合された部分を有する半導体装置の製造方法において、上述した貫通孔を形成することなく、はんだにおけるボイド形成が抑制される製造方法を提供することを目的とする。   In view of the above points, an object of the present invention is to provide a manufacturing method in which void formation in solder is suppressed without forming the above-described through hole in a manufacturing method of a semiconductor device having a soldered portion. To do.

上記目的を達成するため、請求項１に記載の発明では、第１のはんだ（５）により第１の被接合部（２１）と半導体チップ（３）とを接合して構成される半導体装置の製造方法において、半導体チップの重心から離れた位置に荷重を加えることにより、第１のはんだを溶融させてからその固化が完了するまで、半導体チップの一面（３ａ）を、第１の被接合部の一面（２１ａ）に対して傾斜した状態に維持することを特徴とする。   In order to achieve the above object, according to the first aspect of the present invention, there is provided a semiconductor device configured by joining the first joined portion (21) and the semiconductor chip (3) with the first solder (5). In the manufacturing method, by applying a load to a position away from the center of gravity of the semiconductor chip, the first surface (3a) of the semiconductor chip is melted until the solidification is completed after the first solder is melted. It maintains in the state inclined with respect to one surface (21a).

このため、溶融状態の第１のはんだ中に存在する気体（例えば、フラックスが分解して発生するガス）が、第１の被接合部の一面と半導体チップの一面との間隔が広い領域において移動し易くなる。よって、この広い領域を通じて気体が第１のはんだの外部へ放出され易くなり、固化後における第１のはんだ中にボイドが形成され難くなる。これにより、貫通孔を形成しなくても、はんだにおけるボイド形成を抑制することが可能となる。   For this reason, the gas (for example, gas generated when the flux is decomposed) present in the molten first solder moves in a region where the distance between one surface of the first bonded portion and one surface of the semiconductor chip is wide. It becomes easy to do. Therefore, gas is easily released to the outside of the first solder through this wide region, and voids are hardly formed in the first solder after solidification. This makes it possible to suppress void formation in the solder without forming a through hole.

なお、この欄および特許請求の範囲で記載した各手段の括弧内の符号は、後述する実施形態に記載の具体的手段との対応関係を示すものである。   In addition, the code | symbol in the bracket | parenthesis of each means described in this column and the claim shows the correspondence with the specific means as described in embodiment mentioned later.

（ａ）は、本発明の第１実施形態に係る半導体装置１の断面構成を示す図であり、（ｂ）は、図１（ａ）に示す半導体装置１の上面図である。(A) is a figure which shows the cross-sectional structure of the semiconductor device 1 which concerns on 1st Embodiment of this invention, (b) is a top view of the semiconductor device 1 shown to Fig.1 (a). 図１に示す半導体装置１の製造工程中におけるはんだ溶融前のワークの断面構成を示す図である。It is a figure which shows the cross-sectional structure of the workpiece | work before the solder melting in the manufacturing process of the semiconductor device 1 shown in FIG. 図１に示す半導体装置１の製造工程中におけるはんだ溶融後のワークの断面構成を示す図である。It is a figure which shows the cross-sectional structure of the workpiece | work after the solder melting in the manufacturing process of the semiconductor device 1 shown in FIG. 本発明の第２実施形態に係る半導体装置１の製造工程中におけるはんだ溶融前のワークの断面構成を示す図である。It is a figure which shows the cross-sectional structure of the workpiece | work before the solder melting in the manufacturing process of the semiconductor device 1 which concerns on 2nd Embodiment of this invention. 本発明の第２実施形態に係る半導体装置１の製造工程中におけるはんだ溶融後のワークの断面構成を示す図である。It is a figure which shows the cross-sectional structure of the workpiece | work after solder melting in the manufacturing process of the semiconductor device 1 which concerns on 2nd Embodiment of this invention. 本発明の他の実施形態に係る半導体装置１の製造工程中におけるはんだ溶融前のワークの断面構成を示す図である。It is a figure which shows the cross-sectional structure of the workpiece | work before the solder melting in the manufacturing process of the semiconductor device 1 which concerns on other embodiment of this invention. 図６に示す例に係る半導体装置１の製造工程中におけるはんだ溶融後のワークの断面構成を示す図である。It is a figure which shows the cross-sectional structure of the workpiece | work after the solder melting in the manufacturing process of the semiconductor device 1 which concerns on the example shown in FIG. 本発明の別の他の実施形態に係る半導体装置１の製造工程中におけるはんだ溶融前のワークおよび治具１０の断面構成を示す図である。It is a figure which shows the cross-sectional structure of the workpiece | work before the solder melting and the jig | tool 10 in the manufacturing process of the semiconductor device 1 which concerns on another another embodiment of this invention. 図８に示す例に係る半導体装置１の製造工程中におけるはんだ溶融後のワークおよび治具１０の断面構成を示す図である。FIG. 9 is a diagram showing a cross-sectional configuration of a workpiece and a jig 10 after solder melting during the manufacturing process of the semiconductor device 1 according to the example shown in FIG. 8. 本発明の別の他の実施形態に係る半導体装置１の製造工程中におけるはんだ溶融前のワークおよび治具１０の断面構成を示す図である。It is a figure which shows the cross-sectional structure of the workpiece | work before the solder melting and the jig | tool 10 in the manufacturing process of the semiconductor device 1 which concerns on another another embodiment of this invention. 図１０に示す例に係る半導体装置１の製造工程中におけるはんだ溶融後のワークおよび治具１０の断面構成を示す図である。FIG. 11 is a diagram showing a cross-sectional configuration of a workpiece and a jig 10 after solder melting during the manufacturing process of the semiconductor device 1 according to the example shown in FIG. 10.

以下、本発明の実施形態について図に基づいて説明する。なお、以下の各実施形態相互において、互いに同一もしくは均等である部分には、同一符号を付して説明を行う。   Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following embodiments, parts that are the same or equivalent to each other will be described with the same reference numerals.

（第１実施形態）
本発明の第１実施形態に係る半導体装置１について図１を参照して説明する。本実施形態に係る半導体装置１は、例えば自動車などの車両に搭載され、車両用の各種電子装置を駆動するための装置として適用される。 (First embodiment)
A semiconductor device 1 according to a first embodiment of the present invention will be described with reference to FIG. The semiconductor device 1 according to the present embodiment is mounted on a vehicle such as an automobile, and is applied as a device for driving various electronic devices for the vehicle.

図１（ａ）、（ｂ）に示すように、本実施形態に係る半導体装置１は、アイランド部２１およびリード部２２により構成されるリードフレーム２と、半導体チップ３と、半導体チップ３とリード部２２とに接合されたクリップ４と、を備える。本実施形態に係る半導体装置１は、半導体チップ３が、第１のはんだ５を介してアイランド部２１に接合され、クリップ４が、第２のはんだ６を介して半導体チップ３に接合される共に、第３のはんだ７を介してリード部２２に接合された構成とされている。   As shown in FIGS. 1A and 1B, the semiconductor device 1 according to the present embodiment includes a lead frame 2 including an island portion 21 and a lead portion 22, a semiconductor chip 3, a semiconductor chip 3, and a lead. A clip 4 joined to the portion 22. In the semiconductor device 1 according to this embodiment, the semiconductor chip 3 is bonded to the island part 21 via the first solder 5, and the clip 4 is bonded to the semiconductor chip 3 via the second solder 6. In addition, it is configured to be joined to the lead portion 22 via the third solder 7.

リードフレーム２は、導電性金属材料よりなるものであり、上述したように、 アイランド部（第１の被接合部）２１およびリード部（第２の被接合部）２２により構成される。アイランド部２１は、半導体チップ３を積載するための薄板部材である。リード部２２は、アイランド部２１の周囲に配置された薄板部材である。リード部２２は、クリップ４を介して半導体チップ３と電気的に接続されていると共に、図示しない配線により半導体装置１の外部と電気的に接続されている。   The lead frame 2 is made of a conductive metal material, and includes the island part (first joined part) 21 and the lead part (second joined part) 22 as described above. The island portion 21 is a thin plate member on which the semiconductor chip 3 is loaded. The lead portion 22 is a thin plate member disposed around the island portion 21. The lead portion 22 is electrically connected to the semiconductor chip 3 via the clip 4 and is electrically connected to the outside of the semiconductor device 1 by wiring not shown.

半導体チップ３は、平板状に形成された半導体集積回路であり、例えば、マイコンなどのＩＣチップや、トランジスタなどのパワー素子や、その他の各種チップ部品等により構成される。   The semiconductor chip 3 is a semiconductor integrated circuit formed in a flat plate shape, and includes, for example, an IC chip such as a microcomputer, a power element such as a transistor, and other various chip components.

図１（ａ）に示すように、半導体チップ３は、その一面３ａがアイランド部２１の一面２１ａに対向するようにして配置されている。アイランド部２１の一面２１ａと半導体チップ３の一面３ａとの間には、半導体チップ３の一面３ａの略全面に亘って、第１のはんだ５が設けられている。本実施形態に係る半導体装置１では、第１のはんだ５により、アイランド部２１と半導体チップ３とが接合されている。   As shown in FIG. 1A, the semiconductor chip 3 is arranged so that one surface 3 a thereof faces the one surface 21 a of the island portion 21. Between the one surface 21 a of the island portion 21 and the one surface 3 a of the semiconductor chip 3, the first solder 5 is provided over substantially the entire surface 3 a of the semiconductor chip 3. In the semiconductor device 1 according to the present embodiment, the island portion 21 and the semiconductor chip 3 are joined by the first solder 5.

図１（ａ）に示すように、本実施形態に係る半導体装置１は、半導体チップ３の一面３ａが、アイランド部２１の一面２１ａに対して傾斜した傾斜状態とされた構成とされている。   As shown in FIG. 1A, the semiconductor device 1 according to the present embodiment has a configuration in which one surface 3 a of the semiconductor chip 3 is inclined with respect to the one surface 21 a of the island portion 21.

クリップ４は、半導体チップ３とリード部２２に接合されたものであり、金属（例えば、Ｃｕ）よりなる。図１（ａ）、（ｂ）に示すように、クリップ４は、例えば板状部材を４箇所で折り曲げて形成され、両端の間に凸部４１を備えた形状とされている。すなわち、クリップ４は、凸部４１と、凸部４１を挟んだ両端の部分のうちの一方の端部である第１部位４２、および他方の端部である第２部位４３と、を有して構成されている。また、本実施形態に係る半導体装置１は、クリップ４のうち第１部位４２と凸部４１との境界位置が、半導体チップ３の重心よりもリード部２２の側に配置された構成とされている。   The clip 4 is bonded to the semiconductor chip 3 and the lead portion 22 and is made of metal (for example, Cu). As shown in FIGS. 1 (a) and 1 (b), the clip 4 is formed, for example, by bending a plate-like member at four locations and having a convex portion 41 between both ends. That is, the clip 4 has a convex portion 41, a first portion 42 that is one end portion of both end portions sandwiching the convex portion 41, and a second portion 43 that is the other end portion. Configured. Further, the semiconductor device 1 according to the present embodiment has a configuration in which the boundary position between the first portion 42 and the convex portion 41 of the clip 4 is arranged on the lead portion 22 side with respect to the center of gravity of the semiconductor chip 3. Yes.

第１部位４２は一面（第１の面）４２ａを有し、第２部位４３は一面（第２の面）４３ａを有する。図１（ａ）に示すように、クリップ４の第１部位４２の一面４２ａは、半導体チップ３のうち一面３ａとは反対側の他面３ｂと、第２のはんだ６を介して接合されている。第２のはんだ６は、クリップ４の第１部位４２の一面４２ａの略全面に亘って設けられている。   The first portion 42 has one surface (first surface) 42a, and the second portion 43 has one surface (second surface) 43a. As shown in FIG. 1A, one surface 42 a of the first portion 42 of the clip 4 is joined to the other surface 3 b of the semiconductor chip 3 opposite to the one surface 3 a through the second solder 6. Yes. The second solder 6 is provided over substantially the entire surface 42 a of the first portion 42 of the clip 4.

また、図１（ａ）に示すように、クリップ４の第２部位４３の一面４３ａは、第３のはんだ７を介してリード部２２の一面２２ａと接合されている。第３のはんだ７は、クリップ４の第２部位４３の一面４３ａの略全面に亘って設けられている。このような構成により、クリップ４にて、半導体チップ３とリード部２２とが物理的および電気的に接続されている。   Further, as shown in FIG. 1A, the one surface 43 a of the second portion 43 of the clip 4 is joined to the one surface 22 a of the lead portion 22 through the third solder 7. The third solder 7 is provided over substantially the entire surface 43 a of the second portion 43 of the clip 4. With such a configuration, the semiconductor chip 3 and the lead portion 22 are physically and electrically connected by the clip 4.

本実施形態に係る半導体装置１では、クリップ４の第１部位４２の一面４２ａが、半導体チップ３の他面３ｂに対して傾斜した傾斜状態となっている。また、本実施形態に係る半導体装置１では、クリップ４の第２部位４３の一面４３ａが、リード部２２の一面２２ａに対して傾斜した傾斜状態となっている。また、図１（ａ）に示すように、本実施形態に係る半導体装置１では、第１部位４２の一面４２ａを含む平面と、第２部位４３の一面４３ａを含む平面とが交差するように、第１部位４２の一面４２ａおよび第２部位４３の一面４３ａが設けられている。   In the semiconductor device 1 according to the present embodiment, one surface 42 a of the first portion 42 of the clip 4 is in an inclined state inclined with respect to the other surface 3 b of the semiconductor chip 3. Further, in the semiconductor device 1 according to the present embodiment, the one surface 43 a of the second portion 43 of the clip 4 is inclined with respect to the one surface 22 a of the lead portion 22. As shown in FIG. 1A, in the semiconductor device 1 according to the present embodiment, a plane including the one surface 42a of the first part 42 and a plane including the one surface 43a of the second part 43 intersect each other. Further, one surface 42a of the first part 42 and one surface 43a of the second part 43 are provided.

なお、本実施形態に係る半導体装置１では、リード部２２のうち一部（外部と電気的に接続する配線が設けられる部分）を除いた部分、半導体チップ３、およびクリップ４が、図示しない被覆部（モールド樹脂など）により被覆されている。   In the semiconductor device 1 according to the present embodiment, a portion of the lead portion 22 excluding a portion (a portion provided with a wiring that is electrically connected to the outside), the semiconductor chip 3, and the clip 4 are not covered. Part (mold resin etc.).

次に、本実施形態に係る半導体装置１の製造方法について、図２〜３を参照して説明する。   Next, a method for manufacturing the semiconductor device 1 according to this embodiment will be described with reference to FIGS.

まず、用意工程として、リードフレーム２（アイランド部２１、リード部２２）、半導体チップ３、およびクリップ４を用意する。   First, as a preparation process, the lead frame 2 (the island part 21 and the lead part 22), the semiconductor chip 3, and the clip 4 are prepared.

用意工程ののち、積載工程を行う。具体的には、まず最初に、半導体チップ３の一面３ａがアイランド部２１の一面２１ａに対向するように半導体チップ３をアイランド部２１上に積載して、半導体チップ３の一面３ａとアイランド部２１の一面２１ａとを第１のはんだ５を介して接着させる。次に、クリップ４の第１部位４２の一面４２ａが半導体チップ３の他面３ｂに対向すると共に、クリップ４の第２部位４３の一面４３ａがリード部２２の一面２２ａに対向するように、クリップ４を半導体チップ３上およびリード部２２上に積載する。このとき、クリップ４のうち第１部位４２と凸部４１との境界位置が、半導体チップ３の重心よりもリード部２２の側に配置されるように、クリップ４を半導体チップ３上およびリード部２２上に積載する。そして、クリップ４の第１部位４２の一面４２ａと半導体チップ３の他面３ｂとを第２のはんだ６を介して接着させ、第２部位４３の一面４３ａとリード部２２の一面２２ａとを第３のはんだ７を介して接着させる。   After the preparation process, the loading process is performed. Specifically, first, the semiconductor chip 3 is stacked on the island portion 21 so that the one surface 3a of the semiconductor chip 3 faces the one surface 21a of the island portion 21, and the one surface 3a and the island portion 21 of the semiconductor chip 3 are stacked. The one surface 21 a is bonded to the first solder 5 via the first solder 5. Next, the clip 42 is formed so that the one surface 42 a of the first portion 42 of the clip 4 faces the other surface 3 b of the semiconductor chip 3 and the one surface 43 a of the second portion 43 of the clip 4 faces the one surface 22 a of the lead portion 22. 4 is stacked on the semiconductor chip 3 and the lead part 22. At this time, the clip 4 is placed on the semiconductor chip 3 and the lead portion so that the boundary position between the first portion 42 and the convex portion 41 of the clip 4 is arranged on the lead portion 22 side of the center of gravity of the semiconductor chip 3. 22 is loaded. Then, the one surface 42a of the first portion 42 of the clip 4 and the other surface 3b of the semiconductor chip 3 are bonded via the second solder 6, and the one surface 43a of the second portion 43 and the one surface 22a of the lead portion 22 are connected to each other. 3 is bonded through the solder 7.

第１のはんだ５、第２のはんだ６、第３のはんだ７としては、それぞれ、例えばフラックスを含有するはんだが採用され得る。   As the first solder 5, the second solder 6, and the third solder 7, for example, solder containing flux can be employed.

積載工程が完了したとき（はんだ溶融前）のワークは、図２に示すように、半導体チップ３の一面３ａおよび他面３ｂがそれぞれ、アイランド部２１の一面２１ａと略平行の状態となる。   As shown in FIG. 2, when the loading process is completed (before solder melting), the one surface 3a and the other surface 3b of the semiconductor chip 3 are substantially parallel to the one surface 21a of the island portion 21, respectively.

また、ワークは、クリップ４の第１部位４２の一面４２ａが、アイランド部２１の一面２１ａに対して傾斜した状態、すなわち、半導体チップ３の他面３ｂに対して傾斜した状態となる。より具体的には、第１部位４２の一面４２ａは、第１部位４２と凸部４１との境界位置から第１部位４２の端部側に向かうにつれてこの一面４２ａと半導体チップ３の他面３ｂとの間隔が広くなるように、傾斜する。また、上記境界位置が、半導体チップ３の重心よりもリード部２２の側において配置された状態とされている。   Further, the work is in a state where one surface 42 a of the first portion 42 of the clip 4 is inclined with respect to the one surface 21 a of the island portion 21, that is, a state inclined with respect to the other surface 3 b of the semiconductor chip 3. More specifically, the one surface 42a of the first part 42 extends from the boundary position between the first part 42 and the convex part 41 toward the end part side of the first part 42 and the other surface 3b of the semiconductor chip 3. It inclines so that the space | interval may become wide. Further, the boundary position is arranged on the lead portion 22 side with respect to the center of gravity of the semiconductor chip 3.

さらに、ワークは、クリップ４の第２部位４３の一面４３ａが、リード部２２の一面２２ａに対して傾斜した状態となる。より具体的には、第２部位４３の一面４３ａは、第２部位４３と凸部４１との境界位置から第２部位４３の端部側に向かうにつれてこの第２部位４３の一面４３ａとリード部２２の一面２２ａとの間隔が広くなるように、傾斜する。   Furthermore, the workpiece is in a state in which the one surface 43 a of the second portion 43 of the clip 4 is inclined with respect to the one surface 22 a of the lead portion 22. More specifically, the one surface 43a of the second part 43 and the one part 43a and the lead part of the second part 43 move from the boundary position between the second part 43 and the convex portion 41 toward the end of the second part 43. It inclines so that the space | interval with the one surface 22a of 22 may become wide.

ここで、ワークにおいて、クリップ４が上述した形状とされているため、クリップ４の自重は、クリップ４のうち第１部位４２と凸部４１との境界位置の部分、および、クリップ４のうち凸部４１と第２部位４３との境界位置の部分に集中する。このクリップ４の自重が集中する２つの境界位置の一方である第１部位４２と凸部４１との境界位置は、上述したように、半導体チップ３の重心よりもリード部２２の側に配置された状態とされている。このため、積載完了時におけるワークは、半導体チップ３の他面３ｂのうち半導体チップ３の重心から離れた位置に荷重（クリップ４の自重）が加えられた状態とされている。   Here, in the workpiece, since the clip 4 has the shape described above, the weight of the clip 4 is the convex portion of the clip 4 and the portion of the clip 4 at the boundary position between the first portion 42 and the convex portion 41. It concentrates on the part of the boundary position between the part 41 and the second part 43. As described above, the boundary position between the first portion 42 and the convex portion 41, which is one of the two boundary positions where the weight of the clip 4 is concentrated, is disposed closer to the lead portion 22 than the center of gravity of the semiconductor chip 3. It is supposed to be in a state. For this reason, the workpiece at the time of completion of loading is in a state where a load (self weight of the clip 4) is applied to a position away from the center of gravity of the semiconductor chip 3 on the other surface 3b of the semiconductor chip 3.

積載工程ののち、傾斜工程を行う。具体的には、第１のはんだ５、第２のはんだ６、および第３のはんだ７を溶融させることで、半導体チップ３およびクリップ４を図１に示すような状態にする。   After the loading process, the tilting process is performed. Specifically, by melting the first solder 5, the second solder 6, and the third solder 7, the semiconductor chip 3 and the clip 4 are brought into a state as shown in FIG.

すなわち、第１のはんだ５を溶融させたときに、上述したように、半導体チップ３の他面３ｂのうち半導体チップ３の重心から離れた位置に荷重が加えられるため、半導体チップ３の一面３ａがアイランド部２１の一面２１ａに対して傾斜した状態となる。より具体的には、第１部位４２の一面４２ａと半導体チップ３の他面３ｂとの間隔が広くなる方向に向かうにつれて、半導体チップ３とアイランド部２１との間隔が広くなるように、半導体チップ３の一面３ａがアイランド部２１の一面２１ａに対して傾斜する。また、クリップ４の第１部位４２の一面４２ａは、半導体チップ３が上述したように傾斜してもなお、はんだ溶融前と同様、半導体チップ３の他面３ｂに対して傾斜した状態を維持する。また、クリップ４の第２部位４３の一面４３ａも、はんだ溶融前と同様、リード部２２の一面２２ａに対して傾斜した状態を維持する。   That is, when the first solder 5 is melted, a load is applied to a position away from the center of gravity of the semiconductor chip 3 in the other surface 3b of the semiconductor chip 3 as described above. Is inclined with respect to the one surface 21 a of the island portion 21. More specifically, as the distance between the one surface 42a of the first part 42 and the other surface 3b of the semiconductor chip 3 increases, the distance between the semiconductor chip 3 and the island portion 21 increases. 3 is inclined with respect to the one surface 21 a of the island portion 21. In addition, even if the semiconductor chip 3 is inclined as described above, the one surface 42a of the first portion 42 of the clip 4 is still inclined with respect to the other surface 3b of the semiconductor chip 3 as before solder melting. . Further, the one surface 43a of the second portion 43 of the clip 4 also maintains the inclined state with respect to the one surface 22a of the lead portion 22 as before the solder melting.

なお、傾斜工程において、別途の外力（例えば、加圧機による圧力）を作用させることにより、さらに半導体チップ３が傾斜し易くなるようにしてもよい。   In the tilting step, the semiconductor chip 3 may be tilted more easily by applying a separate external force (for example, pressure by a pressurizer).

傾斜工程ののち、固化工程として、半導体チップ３の一面３ａ、クリップ４の第１部位４２の一面４２ａ、およびクリップ４の第２部位４３の一面４３ａのそれぞれの傾斜状態を維持した状態で、第１のはんだ５、第２のはんだ６、および第３のはんだ７の固化を完了させる。   After the tilting process, as the solidification process, the first surface 3a of the semiconductor chip 3, the one surface 42a of the first part 42 of the clip 4 and the one surface 43a of the second part 43 of the clip 4 are maintained in the state where the inclined state is maintained. The solidification of the first solder 5, the second solder 6, and the third solder 7 is completed.

以上のような製造方法により、本実施形態に係る半導体装置１は完成する。このような製造方法では、第１のはんだ５を溶融させてからその固化が完了するまで（傾斜工程から固化工程まで）、半導体チップ３の一面３ａを、アイランド部２１の一面２１ａに対して傾斜した状態に維持している。   The semiconductor device 1 according to this embodiment is completed by the manufacturing method as described above. In such a manufacturing method, the first surface 3a of the semiconductor chip 3 is inclined with respect to the first surface 21a of the island portion 21 until the solidification is completed (from the inclination step to the solidification step) after the first solder 5 is melted. Is maintained.

このため、溶融状態の第１のはんだ５中に存在する気体Ｇ１（例えば、フラックスが分解して発生するガス）が、アイランド部２１の一面２１ａと半導体チップ３の一面３ａとの間隔が広い領域（リード部２２に遠い側の領域）において移動し易くなる。よって、本実施形態に係る製造方法では、この広い領域を通じて気体Ｇ１が第１のはんだ５の外部へ放出され易くなり（図３の符号Ｙ１の矢印参照）、固化後における第１のはんだ５中にボイドが形成され難くなる。   Therefore, a region where the gas G1 (for example, a gas generated by the decomposition of the flux) existing in the molten first solder 5 has a wide gap between the one surface 21a of the island portion 21 and the one surface 3a of the semiconductor chip 3 is wide. It becomes easy to move in (region far from the lead portion 22). Therefore, in the manufacturing method according to the present embodiment, the gas G1 is likely to be released to the outside of the first solder 5 through this wide region (see the arrow Y1 in FIG. 3), and in the first solder 5 after solidification. It becomes difficult to form voids.

さらに、本実施形態に係る製造方法では、クリップ４の自重により、第２のはんだ６を溶融させてからその固化が完了するまで（傾斜工程から固化工程まで）、クリップ４の第１部位４２の一面４２ａが、半導体チップ３の他面３ｂに対して傾斜した状態が維持される。   Furthermore, in the manufacturing method according to the present embodiment, the second solder 6 is melted by the dead weight of the clip 4 until the solidification thereof is completed (from the inclination process to the solidification process). The state where the one surface 42a is inclined with respect to the other surface 3b of the semiconductor chip 3 is maintained.

このため、溶融状態の第２のはんだ６中に存在する気体Ｇ２（例えば、フラックスが分解して発生するガス）が、半導体チップ３の他面３ｂとクリップ４の第１部位４２の一面４２ａとの間隔が広い領域（リード部２２に遠い側の領域）において移動し易くなる。よって、本実施形態に係る製造方法では、この広い領域を通じて気体Ｇ２が第２のはんだ６の外部へ放出され易くなり（図３の符号Ｙ２の矢印参照）、固化後における第２のはんだ６中にボイドが形成され難くなる。   For this reason, the gas G2 (for example, a gas generated when the flux is decomposed) existing in the molten second solder 6 is generated between the other surface 3b of the semiconductor chip 3 and the one surface 42a of the first portion 42 of the clip 4. It is easy to move in a region where the interval is wide (region far from the lead portion 22). Therefore, in the manufacturing method according to the present embodiment, the gas G2 is easily released to the outside of the second solder 6 through this wide region (see the arrow Y2 in FIG. 3), and the second solder 6 in the solidified state after solidification. It becomes difficult to form voids.

さらに、本実施形態に係る製造方法では、第３のはんだ７を溶融させてからその固化が完了するまで（傾斜工程から固化工程まで）、クリップ４の第２部位４３の一面４３ａが、リード部２２の一面２２ａに対して傾斜した状態が維持される。   Furthermore, in the manufacturing method according to the present embodiment, the first surface 43a of the second portion 43 of the clip 4 is a lead portion until the solidification is completed (from the tilting process to the solidifying process) after the third solder 7 is melted. The state inclined with respect to one surface 22a of 22 is maintained.

このため、溶融状態の第３のはんだ７中に存在する気体Ｇ３（例えば、フラックスが分解して発生するガス）が、第２部位４３の一面４３ａとリード部２２の一面２２ａとの間隔が広い領域（リード部２２に遠い側の領域）において移動し易くなる。よって、本実施形態に係る製造方法では、この広い領域を通じて気体Ｇ３が第３のはんだ７の外部へ放出され易くなり（図３の符号Ｙ３の矢印参照）、固化後における第３のはんだ７中にボイドが形成され難くなる。   For this reason, the gap between the one surface 43a of the second portion 43 and the one surface 22a of the lead portion 22 is wide in the gas G3 (for example, gas generated by the decomposition of the flux) present in the molten third solder 7. It becomes easy to move in the region (region far from the lead portion 22). Therefore, in the manufacturing method according to the present embodiment, the gas G3 is easily released to the outside of the third solder 7 through this wide region (see the arrow Y3 in FIG. 3), and in the third solder 7 after solidification. It becomes difficult to form voids.

そして、本発明に係る製造方法では、第１のはんだ５、第２のはんだ６、および第３のはんだ７の固化が完了する前に上記傾斜した状態が解除されず、固化が完了するまで上記傾斜した状態が維持されるため、確実にボイド形成を抑制することができる。   And in the manufacturing method which concerns on this invention, before solidification of the 1st solder 5, the 2nd solder 6, and the 3rd solder 7 is completed, the said inclined state is not cancelled | released but it completes until solidification is completed. Since the inclined state is maintained, void formation can be reliably suppressed.

以上説明したように、本実施形態に係る製造方法では、第１のはんだ５を溶融させてからその固化が完了するまで（傾斜工程から固化工程まで）、半導体チップ３の一面３ａを、アイランド部２１の一面２１ａに対して傾斜した状態に維持している。   As described above, in the manufacturing method according to the present embodiment, the first surface 3a of the semiconductor chip 3 is moved from the first solder 5 to the island portion until the solidification is completed (from the inclination process to the solidification process). 21 is maintained in an inclined state with respect to the one surface 21a.

このため、溶融状態の第１のはんだ５中に存在する気体Ｇ１（例えば、フラックスが分解して発生するガス）が、アイランド部２１の一面２１ａと半導体チップ３の一面３ａとの間隔が広い領域（リード部２２に遠い側の領域）において移動し易くなる。よって、本実施形態に係る製造方法では、この広い領域を通じて気体Ｇ１が第１のはんだ５の外部へ放出され易くなり（図３の符号Ｙ１の矢印参照）、固化後における第１のはんだ５中にボイドが形成され難くなる。   Therefore, a region where the gas G1 (for example, a gas generated by the decomposition of the flux) existing in the molten first solder 5 has a wide gap between the one surface 21a of the island portion 21 and the one surface 3a of the semiconductor chip 3 is wide. It becomes easy to move in (region far from the lead portion 22). Therefore, in the manufacturing method according to the present embodiment, the gas G1 is likely to be released to the outside of the first solder 5 through this wide region (see the arrow Y1 in FIG. 3), and in the first solder 5 after solidification. It becomes difficult to form voids.

（第２実施形態）
本発明の第２実施形態について図４、５を参照して説明する。本実施形態は、第１実施形態に対して、半導体装置１のクリップ４の形状および第１のはんだ５が設けられた領域を変更して、半導体装置１の製造方法における各工程の内容をそれぞれ一部変更したものある。その他に関しては第１実施形態と同様であるため、ここでは説明を省略する。 (Second Embodiment)
A second embodiment of the present invention will be described with reference to FIGS. The present embodiment is different from the first embodiment in the shape of the clip 4 of the semiconductor device 1 and the region where the first solder 5 is provided, and the contents of each step in the method for manufacturing the semiconductor device 1 are respectively described. There are some changes. Since other aspects are the same as those in the first embodiment, description thereof is omitted here.

本実施形態におけるクリップ４は、第１部位４２の一面４２ａおよび第２部位４３の一面４３ａが平行となる形状とされている。また、本実施形態では、アイランド部２１と半導体チップ３とを接合する第１のはんだ５が、半導体チップ３の一面３ａの全面ではなく、半導体チップ３の一面３ａのうちリード部２２に近い側の領域のみに設けられている。   The clip 4 in the present embodiment has a shape in which one surface 42a of the first portion 42 and one surface 43a of the second portion 43 are parallel to each other. Further, in the present embodiment, the first solder 5 that joins the island portion 21 and the semiconductor chip 3 is not the entire surface 3a of the semiconductor chip 3, but the side near the lead portion 22 of the surface 3a of the semiconductor chip 3. It is provided only in the area.

本実施形態に係る半導体装置１の製造方法は、基本的には第１実施形態と同様だが、各工程の内容の一部が第１実施形態と異なる。そこで、この異なる点のみについて以下に説明する。   The manufacturing method of the semiconductor device 1 according to this embodiment is basically the same as that of the first embodiment, but part of the contents of each process is different from that of the first embodiment. Therefore, only this different point will be described below.

本実施形態における用意工程では、クリップ４として、第１部位４２の一面４２ａおよび第２部位４３の一面４３ａが平行となる形状のものを用意する。また、本実施形態における積載工程では、図４に示すように、半導体チップ３の他面３ｂのうちリード部２２に近い側の領域のみに第１のはんだ５を設ける。そして、本実施形態における積載工程では、半導体チップ３の他面３ｂのうちリード部２２に近い側の領域のみに設けられた第１のはんだ５を介して、クリップ４の第１部位４２の一面４２ａと半導体チップ３とを接着する。   In the preparation process in the present embodiment, a clip 4 having a shape in which the one surface 42 a of the first part 42 and the one surface 43 a of the second part 43 are parallel to each other is prepared. Further, in the loading process in the present embodiment, as shown in FIG. 4, the first solder 5 is provided only in the region near the lead portion 22 on the other surface 3 b of the semiconductor chip 3. In the stacking process in the present embodiment, one surface of the first portion 42 of the clip 4 is interposed via the first solder 5 provided only in the region near the lead portion 22 in the other surface 3b of the semiconductor chip 3. 42a and the semiconductor chip 3 are bonded.

このような構成とすることにより、積載完了時におけるワークは、クリップ４の自重が、第１のはんだ５を介して半導体チップ３の他面３ｂのうちリード部２２に近い側の領域のみに加えられる状態となる。すなわち、半導体チップ３の他面３ｂのうち半導体チップ３の重心から離れた位置に荷重（クリップ４の自重）が加えられた状態となる。このため、本実施形態における製造方法においても、図５に示すように、第１のはんだ５を溶融させてからその固化が完了するまで（傾斜工程から固化工程まで）、半導体チップ３の一面３ａが、アイランド部２１の一面２１ａに対して傾斜した状態となる。そして、本実施形態における固化工程では、この傾斜状態を維持した状態で第１のはんだ５の固化を完了させる。   By adopting such a configuration, the workpiece at the completion of loading is added only to the region where the weight of the clip 4 is closer to the lead portion 22 on the other surface 3b of the semiconductor chip 3 via the first solder 5. It will be in the state to be. That is, a load (self weight of the clip 4) is applied to a position away from the center of gravity of the semiconductor chip 3 on the other surface 3b of the semiconductor chip 3. For this reason, also in the manufacturing method according to the present embodiment, as shown in FIG. 5, from the melting of the first solder 5 until the solidification is completed (from the inclination process to the solidification process), one surface 3 a of the semiconductor chip 3. However, it will be in the state inclined with respect to the one surface 21a of the island part 21. FIG. And in the solidification process in this embodiment, solidification of the 1st solder 5 is completed in the state which maintained this inclination state.

このため、第１実施形態の場合と同様、溶融状態の第１のはんだ５中に存在する気体Ｇ４（例えば、フラックスが分解して発生するガス）が、アイランド部２１の一面２１ａと半導体チップ３の一面３ａとの間隔が広い領域（リード部２２に遠い側の領域）において移動し易くなる。よって、本実施形態に係る製造方法では、この広い領域を通じて気体Ｇ１が第１のはんだ５の外部へ放出され易く（図５の符号Ｙ４の矢印参照）、固化後における第１のはんだ５中にボイドが形成され難くなる。   For this reason, as in the case of the first embodiment, the gas G4 (for example, a gas generated by the decomposition of the flux) present in the molten first solder 5 is formed on the one surface 21a of the island portion 21 and the semiconductor chip 3. It becomes easy to move in a region (region far from the lead portion 22) where the distance from the first surface 3a is wide. Therefore, in the manufacturing method according to the present embodiment, the gas G1 is likely to be released to the outside of the first solder 5 through this wide region (see the arrow Y4 in FIG. 5), and in the first solder 5 after solidification. Voids are difficult to form.

（他の実施形態）
上記第１実施形態における傾斜方法および固化工程では、ワークにおいて、荷重（クリップ４の自重）が、半導体チップ３のうちリード部２２に近い側の領域に集中して加えられるようにしていた。このような構成とすることにより、上記第１実施形態では、リード部２２に近い側の領域を通じて気体Ｇ１が第１のはんだ５の外部へ放出され易くなるようにしていた。しかしながら、半導体装置１の製造方法において、荷重（クリップ４の自重）が、半導体チップ３のうちリード部２２に遠い側の領域に集中して加えられるようにしてもよい。 (Other embodiments)
In the tilting method and the solidifying step in the first embodiment, a load (self-weight of the clip 4) is applied to the work in a concentrated manner in a region of the semiconductor chip 3 closer to the lead portion 22. By adopting such a configuration, in the first embodiment, the gas G1 is easily released to the outside of the first solder 5 through the region near the lead portion 22. However, in the method for manufacturing the semiconductor device 1, the load (self-weight of the clip 4) may be applied in a concentrated manner to a region of the semiconductor chip 3 far from the lead portion 22.

例えば、図６、７に示す例のように、半導体装置１において、クリップ４の第１部位４２の一面４２ａが、半導体チップ３の他面３ｂに対して第１実施形態の場合とは逆向きに傾斜した形状のクリップ４を採用することができる。   For example, as in the example illustrated in FIGS. 6 and 7, in the semiconductor device 1, the one surface 42 a of the first portion 42 of the clip 4 is opposite to the case of the first embodiment with respect to the other surface 3 b of the semiconductor chip 3. It is possible to employ a clip 4 having an inclined shape.

この例においては、クリップ４の自重が、クリップ４の第１部位４２の先端、つまり、第１部位４２と凸部４１との境界位置とは反対側の端部付近の部分に集中する。このため、この例における傾斜工程および固化工程では、クリップ４の自重が、半導体チップ３の他面３ｂのうちリード部２２に遠い側の領域に集中して加えられることにより、半導体チップ３の一面３ａをアイランド部２１の一面２１ａに対して傾斜する。したがって、溶融状態の第１のはんだ５中に存在する気体Ｇ５（例えば、フラックスが分解して発生するガス）が、リード部２２に近い側の領域において移動し易くなる。よって、この例では、この領域を通じて気体Ｇ５が第１のはんだ５の外部へ放出され易くなり（図７の符号Ｙ５の矢印参照）、固化後における第１のはんだ５中にボイドが形成され難くなる。さらに、この例では、半導体チップ３の一面３ａとアイランド部２１の一面２１ａとの間隔が広くなるにつれて第１部位４２の一面４２ａと半導体チップ３の他面３ｂとの間隔が広くなるように、クリップ４の第１部位４２の一面４２が傾斜する。このため、溶融状態の第２のはんだ６中に存在する気体Ｇ６（例えば、フラックスが分解して発生するガス）が、リード部２２に近い側の領域において移動し易くなる。よって、この領域を通じて気体Ｇ６が第２のはんだ６の外部へ放出され易くなり（図７の符号Ｙ６の矢印参照）、固化後における第２のはんだ６中にボイドが形成され難くなる。   In this example, the weight of the clip 4 concentrates on the tip of the first portion 42 of the clip 4, that is, the portion near the end on the opposite side to the boundary position between the first portion 42 and the convex portion 41. For this reason, in the tilting step and the solidifying step in this example, the weight of the clip 4 is concentrated on the region of the other surface 3b of the semiconductor chip 3 that is farther from the lead portion 22, thereby providing one surface of the semiconductor chip 3. 3a is inclined with respect to one surface 21a of the island portion 21. Therefore, the gas G5 (for example, a gas generated by the decomposition of the flux) existing in the molten first solder 5 is easily moved in a region near the lead portion 22. Therefore, in this example, the gas G5 is easily released to the outside of the first solder 5 through this region (see the arrow Y5 in FIG. 7), and voids are hardly formed in the first solder 5 after solidification. Become. Further, in this example, as the distance between the one surface 3a of the semiconductor chip 3 and the one surface 21a of the island portion 21 increases, the distance between the one surface 42a of the first portion 42 and the other surface 3b of the semiconductor chip 3 increases. One surface 42 of the first portion 42 of the clip 4 is inclined. For this reason, the gas G6 (for example, a gas generated by decomposition of the flux) existing in the molten second solder 6 is easily moved in a region near the lead portion 22. Therefore, the gas G6 is easily released to the outside of the second solder 6 through this region (see the arrow Y6 in FIG. 7), and voids are hardly formed in the second solder 6 after solidification.

なお、この例においても、クリップ４の第２部位４３の一面４３ａとリード部２２の一面２２ａ、および第３のはんだ７の構成、および、ボイド抑制効果（図７の符号Ｇ７とＹ７を参照）については、第１実施形態等の場合と同様である。   In this example as well, the configuration of the one surface 43a of the second portion 43 of the clip 4 and the one surface 22a of the lead portion 22 and the third solder 7, and the void suppression effect (see symbols G7 and Y7 in FIG. 7). This is the same as in the first embodiment.

また、上記第１、２実施形態などにおける傾斜工程では、ワークにおいて、クリップ４の自重が加えられるようにすることで半導体チップ３の一面３ａを傾斜させていた。しかしながら、傾斜工程において、クリップ４を用いずに、治具を用いて治具による荷重が加えられるようにすることで、半導体チップ３の一面３ａを傾斜させるようにしてもよい。例えば、図８、９に示す例や図１０、１１に示す例のように、半導体チップ３の他面３ｂのうち半導体チップ３の重心から離れた位置に荷重（治具１０による荷重）が加えられるようにすることで、半導体チップ３の一面３ａがアイランド部２１の一面２１ａに対して傾斜するようにしてもよい。この場合、半導体装置１を構成する部材ではない治具１０を用いるだけで、上述したボイド抑制効果と同様の効果（図９のＧ８とＹ８、および、図１０のＧ９とＹ９を参照）を得ることができる。   Further, in the tilting process in the first and second embodiments, the one surface 3a of the semiconductor chip 3 is tilted by applying the weight of the clip 4 to the workpiece. However, in the tilting step, the one surface 3a of the semiconductor chip 3 may be tilted by using a jig to apply a load by the jig without using the clip 4. For example, as in the examples shown in FIGS. 8 and 9 and the examples shown in FIGS. 10 and 11, a load (load by the jig 10) is applied to a position away from the center of gravity of the semiconductor chip 3 on the other surface 3 b of the semiconductor chip 3. By doing so, the one surface 3a of the semiconductor chip 3 may be inclined with respect to the one surface 21a of the island portion 21. In this case, the effect similar to the above-described void suppression effect (see G8 and Y8 in FIG. 9 and G9 and Y9 in FIG. 10) is obtained only by using the jig 10 that is not a member constituting the semiconductor device 1. be able to.

１ 半導体装置
２ リードフレーム
２１ アイランド部
２２ リード部
３ 半導体チップ
４ クリップ
５ 第１のはんだ
６ 第２のはんだ
７ 第３のはんだ
１０ 治具









DESCRIPTION OF SYMBOLS 1 Semiconductor device 2 Lead frame 21 Island part 22 Lead part 3 Semiconductor chip 4 Clip 5 1st solder 6 2nd solder 7 3rd solder 10 Jig









Claims (4)

一面（２１ａ）を有する第１の被接合部（２１）と、一面（３ａ）および当該一面とは反対側の他面（３ｂ）を有し、当該一面が前記第１の被接合部の一面に対向して配置された半導体チップ（３）と、前記第１の被接合部の一面と前記半導体チップの一面との間に介在し前記第１の被接合部と前記半導体チップとを接合する第１のはんだ（５）と、を備える半導体装置の製造方法であって、
前記第１の被接合部および前記半導体チップを用意する用意工程と、
前記用意工程ののち、前記半導体チップを前記第１の被接合部の一面上に積載して、前記半導体チップの一面と前記第１の被接合部の一面とを前記第１のはんだを介して接着させる積載工程と、
前記積載工程ののち、前記第１のはんだを溶融させ、前記半導体チップの一面が前記第１の被接合部の一面に対して傾斜した傾斜状態を形成する傾斜工程と、
前記半導体チップの一面の傾斜状態を維持した状態で前記第１のはんだの固化を完了させる固化工程と、を備え、
前記傾斜工程および前記固化工程では、前記半導体チップの他面のうち、前記半導体チップの重心から離れた位置に荷重を加えることにより、前記半導体チップの一面が前記第１の被接合部の一面に対して傾斜した傾斜状態を形成することを特徴とする半導体装置の製造方法。 It has the 1st to-be-joined part (21) which has one side (21a), the one side (3a), and the other side (3b) opposite to the one side, and the one side is one side of the 1st to-be-joined part A semiconductor chip (3) disposed opposite to the semiconductor chip, and is interposed between one surface of the first bonded portion and one surface of the semiconductor chip, and bonds the first bonded portion and the semiconductor chip. A method of manufacturing a semiconductor device comprising: a first solder (5);
A preparation step of preparing the first bonded portion and the semiconductor chip;
After the preparation step, the semiconductor chip is stacked on one surface of the first bonded portion, and the one surface of the semiconductor chip and the one surface of the first bonded portion are interposed via the first solder. A loading process for bonding;
An inclination step of melting the first solder after the loading step and forming an inclined state in which one surface of the semiconductor chip is inclined with respect to one surface of the first bonded portion;
A solidification step of completing the solidification of the first solder while maintaining an inclined state of one surface of the semiconductor chip, and
In the tilting step and the solidifying step, by applying a load to a position away from the center of gravity of the semiconductor chip among the other surfaces of the semiconductor chip, one surface of the semiconductor chip becomes one surface of the first bonded portion. A manufacturing method of a semiconductor device, wherein an inclined state inclined with respect to the semiconductor device is formed. 前記半導体装置は、一面（２２ａ）を有する第２の被接合部（２２）と、前記半導体チップと前記第２の被接合部に接合されたクリップ（４）と、を備え、
前記クリップは、前記半導体チップの他面に対して接合された第１の面（４２ａ）、および、前記第２の被接合部の一面に対して接合された第２の面（４３ａ）を有し、
前記用意工程では、さらに、前記第２の被接合部および前記クリップを用意し、
前記積載工程では、さらに、前記クリップの第１の面を前記半導体チップの他面上に積載すると共に、前記クリップの第２の面を前記第２の被接合部の一面上に積載し、
前記傾斜工程および前記固化工程では、前記半導体チップの他面のうち、前記半導体チップの重心から離れた位置に前記クリップの自重を加えることにより、前記半導体チップの一面が前記第１の被接合部の一面に対して傾斜した傾斜状態を形成することを特徴とする請求項１に記載の製造方法。 The semiconductor device includes a second bonded portion (22) having one surface (22a), and a clip (4) bonded to the semiconductor chip and the second bonded portion,
The clip has a first surface (42a) bonded to the other surface of the semiconductor chip and a second surface (43a) bonded to one surface of the second bonded portion. And
In the preparation step, the second joined portion and the clip are further prepared,
In the stacking step, the first surface of the clip is further stacked on the other surface of the semiconductor chip, and the second surface of the clip is stacked on one surface of the second bonded portion,
In the tilting step and the solidifying step, by adding the weight of the clip to a position away from the center of gravity of the semiconductor chip among the other surfaces of the semiconductor chip, one surface of the semiconductor chip becomes the first bonded portion. The manufacturing method according to claim 1, wherein an inclined state inclined with respect to one surface is formed. 前記クリップは、前記第１の面が第２のはんだ（６）を介して前記半導体チップの他面に対して接合されたものであり、前記傾斜工程において前記半導体チップの一面が前記第１の被接合部の一面に対して傾斜した傾斜状態を形成するために自重を加えているときに、前記第１の面が前記半導体チップの他面に対して傾斜した傾斜状態となる形状とされたものであり、
前記積載工程では、さらに、前記クリップの第１の面と前記半導体チップの他面とを前記第２のはんだを介して接着させ、
前記傾斜工程では、さらに、前記第２のはんだを溶融させ、前記クリップの第１の面が、前記半導体チップの他面に対して傾斜した傾斜状態を形成し、
前記固化工程では、さらに、前記クリップの第１の面の傾斜状態を維持した状態で前記第２のはんだの固化を完了させることを特徴とする請求項２に記載の製造方法。 In the clip, the first surface is bonded to the other surface of the semiconductor chip via a second solder (6), and one surface of the semiconductor chip is the first surface in the tilting step. The first surface is in a shape that is inclined with respect to the other surface of the semiconductor chip when its own weight is applied to form an inclined state inclined with respect to one surface of the bonded portion. Is,
In the loading step, further, the first surface of the clip and the other surface of the semiconductor chip are bonded via the second solder,
In the tilting step, the second solder is further melted, and the first surface of the clip is tilted with respect to the other surface of the semiconductor chip,
The manufacturing method according to claim 2, wherein in the solidifying step, the solidification of the second solder is further completed in a state where the inclined state of the first surface of the clip is maintained. 前記クリップは、前記第２の面が第３のはんだ（７）を介して前記第２の被接合部の一面に対しても接合されるものであり、前記傾斜工程において前記半導体チップの一面が前記第１の被接合部の一面に対して傾斜した傾斜状態を形成するために自重を加えているときに、前記第２の面が前記第２の被接合部の一面に対して傾斜した傾斜状態となる形状とされたものであり、
前記積載工程では、さらに、前記クリップの第２の面と前記第２の被接合部の一面とを前記第３のはんだを介して接着させ、
前記傾斜工程では、さらに、前記第３のはんだを溶融させ、前記クリップの第２の面が、前記第２の被接合部の一面に対して傾斜した傾斜状態を形成し、
前記固化工程では、さらに、前記クリップの第２の面の傾斜状態を維持した状態で前記第３のはんだの固化を完了させることを特徴とする請求項２または３に記載の製造方法。












































In the clip, the second surface is bonded to one surface of the second bonded portion via a third solder (7), and one surface of the semiconductor chip is bonded in the tilting step. An inclination in which the second surface is inclined with respect to one surface of the second bonded portion when a self-weight is applied to form an inclined state inclined with respect to the one surface of the first bonded portion. It is a shape that becomes a state,
In the loading step, further, the second surface of the clip and one surface of the second bonded portion are bonded via the third solder,
In the inclining step, the third solder is further melted, and the second surface of the clip forms an inclined state inclined with respect to one surface of the second bonded portion,
The manufacturing method according to claim 2, wherein in the solidification step, the solidification of the third solder is further completed in a state where the inclined state of the second surface of the clip is maintained.












































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