JP2015002463A - Photoelectric conversion circuit, photoelectric conversion device, electronic apparatus, and method of limiting optical current for photoelectric conversion circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a photoelectric conversion circuit that allows increasing operating speed as compared to conventional techniques.SOLUTION: A photoelectric conversion circuit includes: a phototransistor 1 outputting an optical current corresponding to the magnitude of incident light; a MOS transistor 3 outputting the optical current to a bias line at the time of standby; and a MOS transistor 2 outputting the optical current to an output line at the time of reading. The photoelectric conversion circuit limits the optical current to be outputted to a predetermined limit current value by using saturation drain currents of the MOS field-effect transistors 2 and 3. The limit current value is set by setting an inter-gate-source voltage applied to each gate of the MOS transistors 2 and 3 or the limit current value is set by setting each transistor size of the MOS transistors 2 and 3.

Description

  The present invention relates to a photoelectric conversion circuit that converts incident light into an electrical signal, a photoelectric conversion device that includes a plurality of photoelectric conversion circuits, an electronic device that includes the photoelectric conversion device, and a photoelectric current limiting method for the photoelectric conversion circuit. .

  A photosensor that uses a phototransistor in a light receiving portion is known as a highly sensitive photosensor. Although the phototransistor has an amplifying function and a large output signal can be obtained, it is possible to increase the sensitivity. However, the upper limit of the dynamic range is determined by the amount of saturation charge that can be accumulated in the junction capacitance like the photodiode. At present, several methods have been devised to avoid this restriction and widen the dynamic range. One of them is that the photocurrent has a linear characteristic over a wide range. There is already known a non-accumulated signal readout system that handles the signal as an output signal as it is.

  In this readout method, it is necessary to stably output a photocurrent according to the amount of irradiation light. However, the phototransistor has a problem that the reaction speed is slow and it takes a certain time until the photocurrent is stabilized. For example, Patent Document 1 discloses a photoelectric conversion device for reducing current consumption, but there is a problem that it takes time from the start of optical signal output until the photocurrent is stabilized, and the operation speed is slow. .

  An object of the present invention is to solve the above problems and provide a photoelectric conversion circuit capable of increasing the operation speed as compared with the prior art.

The photoelectric conversion circuit according to the present invention is
A phototransistor that outputs a photocurrent corresponding to the intensity of incident light;
A first field effect transistor that outputs the photocurrent to the bias line during standby;
A photoelectric conversion circuit including a second field effect transistor that outputs the photocurrent to an output line at the time of reading;
The output photocurrent is limited to a predetermined limit current value by using saturated drain currents of the first and second field effect transistors.

  According to the present invention, it is possible to provide a photoelectric conversion circuit capable of increasing the operation speed as compared with the prior art.

1 is a circuit diagram illustrating a pixel cell circuit 11 that is a photoelectric conversion circuit according to an embodiment of the present invention and a peripheral circuit thereof. FIG. It is a block diagram which shows the structure of the photoelectric conversion apparatus formed by juxtaposing the pixel cell circuit 11 of FIG. 1 in two dimensions. 3 is a graph showing drain current Id characteristics with respect to a drain-source voltage Vds of the switch transistors 2 and 3 when the switch transistors 2 and 3 of the pixel cell circuit 11 of FIG. 1 are N-channel MOS transistors. 4 is a graph showing drain current Id characteristics with respect to a drain-source voltage Vds of the switch transistors 2 and 3 when the switch transistors 2 and 3 of the pixel cell circuit 11 of FIG. 1 are P-channel MOS transistors.

  Hereinafter, embodiments according to the present invention will be described with reference to the drawings. In addition, in each following embodiment, the same code | symbol is attached | subjected about the same component.

  FIG. 1 is a circuit diagram showing a pixel cell circuit 11 which is a photoelectric conversion circuit according to an embodiment of the present invention and its peripheral circuit. In FIG. 1, a pixel cell circuit 11 corresponds to one pixel, and includes a phototransistor 1 and switch transistors 2 and 3 that are N-channel MOS field effect transistors (hereinafter, MOS field effect transistors are referred to as MOS transistors), for example. It is prepared for. Here, the collector of the phototransistor 1 is connected to the DC voltage VDD, and the emitter thereof is connected to the drains of the switch transistors 2 and 3. The phototransistor 1 photoelectrically converts incident light and outputs a photocurrent corresponding to the intensity of the incident light. The source of the switch transistor 2 is connected to the output line 4 that outputs the photocurrent from the phototransistor 1. The source of the switch transistor 3 is connected to a bias line 5 connected to a bias voltage source 7 that generates a predetermined bias voltage. A gate voltage for turning on or off the switch transistors 2 and 3 is applied to each gate of the switch transistors 2 and 3 from the gate voltage generation circuit 6.

  FIG. 2 is a block diagram showing a configuration of a photoelectric conversion device in which the pixel cell circuits 11 of FIG. 1 are juxtaposed in two dimensions. 2 includes a plurality of pixel cell circuits 11-1-1-1 to 11-MN arranged in a two-dimensional array, a plurality of row selection lines 12-1 to 12-M, and a plurality of pixel cell circuits 11-1-1 to 11-MN. Column output lines 4-1 to 4-N (corresponding to the output line 4 in FIG. 1), a row selector 10, an IV conversion circuit 20, and an AD conversion circuit 30 are provided. Here, the pixel cell circuits 11-1-1-1 to 11-MN are the pixel cell circuits 11 of FIG.

  Each of the pixel cell circuits 11-1-1 to 11-MN operates as a photoelectric conversion unit including the phototransistor 1 (FIG. 1) that generates an output current having a magnitude corresponding to the intensity of incident light. Each of the pixel cell circuits 11-1-1 to 11 -M-N is connected to one of the row selection lines 12-1 to 12 -M, and is further connected to the column output lines 4-1 to 4 -N. Connected to one of them. One column output line 4-n (1 ≦ n ≦ N) is connected to pixel cell circuits 11-1-n to 11-Mn connected to different row selection lines 12-1 to 12-M, respectively. Is done. The row selector 10 enables only one of the pixel cell circuits 11-1-n to 11-Mn using the row selection lines 12-1 to 12-M. When light is incident, the enabled pixel cell sends a photocurrent having a magnitude corresponding to the intensity of the incident light to the IV conversion circuit 20 via the column output line.

  The IV conversion circuit 20 includes IV converters 21-1 to 21-N connected to the column output lines 4-1 to 4-N, respectively. The IV converters 21-1 to 21-N operate as current-voltage conversion means that converts the output current of the pixel cell into an output voltage. At this time, each of the IV converters 21-1 to 21-N preferably compresses the dynamic range of the output voltage with respect to the dynamic range of the output current when converting the output current of the pixel cell into the output voltage. It may be. The AD conversion circuit 30 executes processing such as analog / digital conversion on the output voltage of the IV conversion circuit 20 to generate an output image signal.

  The photoelectric conversion device in FIG. 2 includes a photoelectric conversion circuit including a plurality of pixel cell circuits 11, and the photoelectric conversion device is configured. However, the present invention is not limited to this, and a single pixel cell circuit 11 is used for photo A sensor may be configured. In addition, electronic devices such as an image sensor, an image reading device, a digital camera, and a security monitoring camera may be configured using a photoelectric conversion device.

  Next, the operation of the pixel cell circuit 11 according to the present embodiment, in particular, a standby bias current control method in a photoelectric conversion circuit driven by a non-accumulated signal readout method will be described below with reference to FIG. Here, the pixel cell circuit 11 of FIG. 1 is characterized in that current control at the pixel level is performed by providing a current limiting means using the saturation current of the switch transistors 2 and 3 in the pixel.

  In FIG. 1, in each pixel cell circuit 11 that is on standby as an initial state, the gate voltage generation circuit 6 applies a low level voltage to the gate of the switch transistor 2 and applies a high level voltage to the gate of the switch transistor 3. At this time, the switch transistor 2 is turned off, the switch transistor 3 is turned on, the bias line 5 is selected, and a photocurrent is output from the phototransistor 1 to the bias line 5 during light reception. When the order of signal readout reaches a certain pixel cell circuit 11, the switch transistors 2 and 3 are switched on / off. That is, the gate voltage generation circuit 6 applies a high level voltage to the gate of the switch transistor 2 and applies a low level voltage to the gate of the switch transistor 3. At this time, the switch transistor 2 is turned on, the switch transistor 3 is turned off, and the output line 4 is selected. As described above, the switch transistors 2 and 3 are not turned on and off at the same time, and are switched to the bias line 5 via the switch transistor 3 during standby and to the output line 4 via the transistor 2 during the signal readout period. Photocurrent is output.

  By driving with such a pixel configuration, the current that can be output from each pixel cell circuit 11 has an upper limit value (= saturated drain current) that can be supplied to the switch transistors 2 and 3, and this value is set appropriately. Thus, as will be described in detail later, a desired operation speed can be ensured.

  Further, as will be described later, in the circuit according to the comparative example having the bias voltage source with the current limiting function in the bias line 5, the current is limited by the sum of the bias currents, and an upper limit value is set to ensure a constant operation speed. It was necessary to set it higher. However, in the present embodiment, current limitation works for each pixel in a region with strong light, and a bias current continues to flow in a region with low light. Therefore, the upper limit value of the current is increased to ensure the same operation speed. There is no need. As a result, it is possible to limit the current at the pixel level with the pixel cell having such a simple configuration, and it is possible to suppress the overall power consumption.

  FIG. 3 is a graph showing drain current Id characteristics with respect to the drain-source voltage Vds of the switch transistors 2 and 3 when the switch transistors 2 and 3 of the pixel cell circuit 11 of FIG. 1 are N-channel MOS transistors. As shown in FIG. 3, when the drain-source voltage Vds enters the saturation region (Vds> Vgs−Vth), the drain current Id converges to a substantially constant value. The drain current Id in the saturation region is expressed by the following equation (1), and assuming a MOS transistor in which the channel length modulation parameter λ can be ignored, the drain current Id is determined by the gate-source voltage Vgs and the transistor size W / L. Is done.

  Here, μ is the carrier mobility, the gate capacitance per Cox unit area, W is the transistor width, L is the transistor length, and Vth is the threshold voltage.

  The operation when the switch transistors 2 and 3 are N-channel MOS transistors will be described below. When the phototransistor 1 in FIG. 1 is irradiated with light and a photocurrent is generated, the selected switch transistor 2 or 3 has an emitter voltage (switch transistors 2 and 2) to ensure a drain-source voltage Vds corresponding to the photocurrent. 3 drain voltage) increases. As the light intensity increases, the photocurrent increases and the emitter voltage increases, but the voltage does not exceed the power supply voltage VDD. From the characteristics of the drain current Id in FIG. 3, when the photocurrent is relatively small, the drain-source voltage Vds is small and the device operates in a non-saturated region. Therefore, the switch transistors 2 and 3 can pass a current corresponding to the photocurrent, but when the photocurrent increases and the drain-source voltage Vds enters the saturation region, the saturated drain current value calculated from the equation (1) It can only flow.

  From the above, the current that can be output from the phototransistor 1 to the output line 4 and the bias line 5 is limited by the saturation drain current of the transistors 2 and 3, and the limit current value is determined by arbitrarily setting this value. be able to. From the equation (1), the value of the saturation drain current is determined by the voltage Vgs applied to the gates of the switch transistors 2 and 3 and the transistor size W / L. In other words, the limit current value can be set by changing the applied voltage Vgs from the gate voltage generation circuit 6 to the gates of the switch transistors 2 and 3 and the transistor size W / L.

  In the above embodiment, the N-channel MOS transistors are used as the switch transistors 2 and 3. However, the present invention is not limited to this, and the switch transistors 2 and 3 may be configured by a selection switch element of a field effect transistor such as a P-channel MOS transistor. .

  FIG. 4 is a graph showing drain current characteristics with respect to the drain-source voltage of the switch transistors 2 and 3 when the switch transistors 2 and 3 of the pixel cell circuit 11 of FIG. 1 are P-channel MOS transistors. In FIG. 4, the dotted line shows the case of the N channel MOS transistor of FIG. 3 for comparison.

  When the phototransistor 1 is irradiated with light and a photocurrent is generated, the emitter voltage rises in order to secure the drain-source voltage | Vds | even in the P-channel MOS transistor. However, since the emitter in this case corresponds to the source for the phototransistor 1, when the emitter voltage increases, the drain-source voltage | Vds | increases, and at the same time, the gate-source voltage | Vgs | changes. Therefore, unlike the N-channel MOS transistor, the P-channel MOS transistor always outputs a current while performing a saturation operation. As the photocurrent increases, the emitter voltage also increases, but does not exceed the power supply voltage VDD. Further, the gate applied voltage with respect to the upper limit of the emitter voltage becomes the upper limit of the gate-source voltage | Vgs |. The saturation drain current of the P-channel MOS transistor is calculated by the following equation (2), and the voltage | Vgs | applied to the gate from the gate voltage generation circuit 6 and the transistor size W / L are appropriately set as in the N-channel MOS transistor. The current limit can be realized with an arbitrary value. Here, the limit current value is set by setting the gate voltage applied to each gate so that the gate-source voltage Vgs of the MOS transistors 2 and 3 becomes a predetermined value.

  Therefore, even if the switch transistors 2 and 3 are P-channel MOS transistors, they have the same effects as the N-channel MOS transistors.

Differences from the comparative example and operational effects of this embodiment.
As a comparative example, consider a case where the bias voltage source 7 of FIG. 1 is a bias voltage source with a current limiting function as compared to the embodiment of FIG.

  In the comparative example, the bias line 5 is selected for each pixel cell circuit waiting in the initial state, and a photocurrent is output to the bias line 5. When the order of signal readout reaches the pixel, the switch transistor 2 is switched from OFF to ON, and the output line 4 is selected. During the readout period, the photocurrent flows to the output line 4, undergoes voltage conversion in the IV conversion circuit 20, and is processed later as an output signal of each pixel, so that it becomes a photocurrent according to the illuminance during the readout period. It is necessary to stabilize. For early stabilization of the photocurrent, it is effective to suppress fluctuations in the base and emitter potentials during standby and output. In the conventional method that does not output photocurrent during standby, the base and emitter voltages increase during this period. End up. However, in this method, since a photocurrent is allowed to flow to the bias line 5 even during standby, the point is that fluctuations in the base and emitter potentials immediately after switching can be suppressed. The time required for stabilization decreases as the photocurrent increases. However, since the photocurrent of all the pixels on standby flows to the bias line 5 and greatly affects the power consumption of the entire system, a bias voltage source with a current limiting function is used. The upper limit is controlled. Therefore, if this upper limit value is set higher, the operating speed will improve, but the power consumption will increase.If it is set lower, the operating speed will decrease but the power consumption will also be reduced. There was a problem that it was necessary to do.

  That is, the method for detecting the sum of the bias currents according to the comparative example has no problem when uniform light is irradiated on the entire sensor surface where a plurality of pixels are arranged, but there is local light intensity. In such cases, it becomes difficult to respond. For example, if there is a region where the light is partially strong, the photocurrent in that portion increases, so that the total of the total bias current exceeds the current limit value, and there is a possibility that the current limit is applied to the entire sensor. In this case, the base and emitter potentials of the waiting pixels rise, so that in a region where only weak light is received, it takes time to stabilize the photocurrent at the time of reading, and high-speed operation cannot be performed. In order to avoid this and secure a certain operating speed, it is necessary to increase the current limit value. However, if this is done, there is a problem in that the sum of the bias currents increases and the power consumption of the entire sensor increases.

  In contrast, in this embodiment, limit detection can be performed for each pixel by providing the switch transistors 2 and 3 in the pixel with current limiting means. Therefore, since current limitation can be performed for each pixel, a pixel in a region where light is strong exceeds the limit current value and current limitation works. Operation such as continuing to flow is possible. Therefore, the power consumption can be effectively reduced while maintaining the operation speed without increasing the current limit value.

1 ... Phototransistor,
2, 3 ... Switch transistors,
4 ... Output line,
4-1 to 4-N: column output lines,
5 ... Bias line,
6: Gate voltage generation circuit,
7 ... Bias voltage source,
10 ... row selector,
11, 11-1-1 to 11-MN ... pixel cell circuit,
12-1 to 12-M ... row selection lines,
20 ... IV conversion circuit,
21-1 to 21-N ... IV converter,
30: AD conversion circuit.

JP 2000-244004 A

Claims (10)

A phototransistor that outputs a photocurrent corresponding to the intensity of incident light;
A first field effect transistor that outputs the photocurrent to the bias line during standby;
A photoelectric conversion circuit including a second field effect transistor that outputs the photocurrent to an output line at the time of reading;
A photoelectric conversion circuit, wherein the output photocurrent is limited to a predetermined limit current value by using saturated drain currents of the first and second field effect transistors.   2. The photoelectric conversion circuit according to claim 1, wherein the first and second field effect transistors are N-channel field effect transistors.   2. The photoelectric conversion circuit according to claim 1, wherein the first and second field effect transistors are P-channel field effect transistors.   The limit current value is set by setting a gate voltage applied to each gate so that a gate-source voltage of the first and second field effect transistors becomes a predetermined value. The photoelectric conversion circuit as described in any one of 1-3.   The photoelectric conversion circuit according to claim 1, wherein the limit current value is set by setting a transistor size of each of the first and second field effect transistors.   A photoelectric conversion device comprising the plurality of photoelectric conversion circuits according to claim 1.   An electronic apparatus comprising the photoelectric conversion device according to claim 6. A phototransistor that outputs a photocurrent corresponding to the intensity of incident light;
A first field effect transistor that outputs the photocurrent to the bias line during standby;
A photoelectric current limiting method for a photoelectric conversion circuit comprising a second field effect transistor that outputs the photocurrent to an output line at the time of reading,
A photoelectric current limiting method for a photoelectric conversion circuit, comprising limiting the output photocurrent to a predetermined limiting current value by using saturated drain currents of the first and second field effect transistors.   The limitation to the limit current value is achieved by setting the gate voltage applied to each gate so that the gate-source voltages of the first and second field effect transistors have a predetermined value. The photoelectric current limiting method for a photoelectric conversion circuit according to claim 8, further comprising:   9. The photoelectric device according to claim 8, wherein limiting to the limiting current value includes setting the limiting current value by setting each transistor size of the first and second field effect transistors. A photoelectric conversion method of the conversion circuit.

Images