JP2014515889A5 - - Google Patents

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Publication number
JP2014515889A5
JP2014515889A5 JP2014509322A JP2014509322A JP2014515889A5 JP 2014515889 A5 JP2014515889 A5 JP 2014515889A5 JP 2014509322 A JP2014509322 A JP 2014509322A JP 2014509322 A JP2014509322 A JP 2014509322A JP 2014515889 A5 JP2014515889 A5 JP 2014515889A5
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JP
Japan
Prior art keywords
exposure
critical dimension
photoresist relief
plasma
relief shape
Prior art date
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Application number
JP2014509322A
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English (en)
Japanese (ja)
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JP6091490B2 (ja
JP2014515889A (ja
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Publication date
Priority claimed from US13/099,432 external-priority patent/US8354655B2/en
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Publication of JP2014515889A publication Critical patent/JP2014515889A/ja
Publication of JP2014515889A5 publication Critical patent/JP2014515889A5/ja
Application granted granted Critical
Publication of JP6091490B2 publication Critical patent/JP6091490B2/ja
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JP2014509322A 2011-05-03 2012-04-26 レジスト形状におけるクリティカルディメンション及びラフネスの制御方法及び制御システム Active JP6091490B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US13/099,432 2011-05-03
US13/099,432 US8354655B2 (en) 2011-05-03 2011-05-03 Method and system for controlling critical dimension and roughness in resist features
PCT/US2012/035218 WO2012151108A1 (en) 2011-05-03 2012-04-26 Method and system for controlling critical dimension and roughness in resist features

Publications (3)

Publication Number Publication Date
JP2014515889A JP2014515889A (ja) 2014-07-03
JP2014515889A5 true JP2014515889A5 (enExample) 2015-04-02
JP6091490B2 JP6091490B2 (ja) 2017-03-08

Family

ID=46125505

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2014509322A Active JP6091490B2 (ja) 2011-05-03 2012-04-26 レジスト形状におけるクリティカルディメンション及びラフネスの制御方法及び制御システム

Country Status (6)

Country Link
US (2) US8354655B2 (enExample)
JP (1) JP6091490B2 (enExample)
KR (1) KR101911330B1 (enExample)
CN (1) CN103620730B (enExample)
TW (1) TWI532071B (enExample)
WO (1) WO2012151108A1 (enExample)

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8354655B2 (en) * 2011-05-03 2013-01-15 Varian Semiconductor Equipment Associates, Inc. Method and system for controlling critical dimension and roughness in resist features
US8974683B2 (en) * 2011-09-09 2015-03-10 Varian Semiconductor Equipment Associates, Inc. Method and system for modifying resist openings using multiple angled ions
CN104345568A (zh) * 2013-08-07 2015-02-11 中芯国际集成电路制造(上海)有限公司 减小光刻胶图形线宽粗糙度的方法
CN104465333B (zh) * 2013-09-17 2017-12-29 中芯国际集成电路制造(上海)有限公司 光刻胶图形的形成方法、晶体管栅极的形成方法
US9520267B2 (en) * 2014-06-20 2016-12-13 Applied Mateirals, Inc. Bias voltage frequency controlled angular ion distribution in plasma processing
US9837254B2 (en) 2014-08-12 2017-12-05 Lam Research Corporation Differentially pumped reactive gas injector
US9406535B2 (en) 2014-08-29 2016-08-02 Lam Research Corporation Ion injector and lens system for ion beam milling
US10825652B2 (en) 2014-08-29 2020-11-03 Lam Research Corporation Ion beam etch without need for wafer tilt or rotation
US9536748B2 (en) 2014-10-21 2017-01-03 Lam Research Corporation Use of ion beam etching to generate gate-all-around structure
US10935889B2 (en) 2015-05-13 2021-03-02 Tokyo Electron Limited Extreme ultra-violet sensitivity reduction using shrink and growth method
US9779955B2 (en) * 2016-02-25 2017-10-03 Lam Research Corporation Ion beam etching utilizing cryogenic wafer temperatures
DE102016119437B4 (de) * 2016-10-12 2024-05-23 scia Systems GmbH Verfahren zum Bearbeiten einer Oberfläche mittels eines Teilchenstrahls
DE102016119791A1 (de) * 2016-10-18 2018-04-19 scia Systems GmbH Verfahren und Vorrichtung zum Bearbeiten einer Oberfläche eines Substrates mittels eines Teilchenstrahls
KR20180082851A (ko) * 2017-01-11 2018-07-19 삼성전자주식회사 반도체 소자의 패턴 형성 방법 및 이를 이용한 반도체 소자의 제조 방법
CN113519071B (zh) 2019-02-28 2025-04-22 朗姆研究公司 利用侧壁清洁的离子束蚀刻
US11495436B2 (en) * 2020-04-30 2022-11-08 Tokyo Electron Limited Systems and methods to control critical dimension (CD) shrink ratio through radio frequency (RF) pulsing
US12354873B2 (en) * 2020-09-30 2025-07-08 Taiwan Semiconductor Manufacturing Co., Ltd. System and method for multiple step directional patterning

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2716547A1 (fr) * 1994-02-24 1995-08-25 Fujitsu Ltd Procédé pour former un motif de résist et pour fabriquer un dispositif à semi-conducteur.
US7838850B2 (en) * 1999-12-13 2010-11-23 Semequip, Inc. External cathode ion source
EP1630849B1 (en) * 2004-08-27 2011-11-02 Fei Company Localized plasma processing
WO2008054013A1 (fr) * 2006-10-30 2008-05-08 Japan Aviation Electronics Industry Limited Procédé de façonnage d'une surface solide faisant intervenir un faisceau ionique à agrégats gazeux
JP5108489B2 (ja) * 2007-01-16 2012-12-26 株式会社日立ハイテクノロジーズ プラズマ処理方法
US7767977B1 (en) * 2009-04-03 2010-08-03 Varian Semiconductor Equipment Associates, Inc. Ion source
US8623171B2 (en) 2009-04-03 2014-01-07 Varian Semiconductor Equipment Associates, Inc. Plasma processing apparatus
US8778603B2 (en) * 2010-03-15 2014-07-15 Varian Semiconductor Equipment Associates, Inc. Method and system for modifying substrate relief features using ion implantation
US8435727B2 (en) 2010-10-01 2013-05-07 Varian Semiconductor Equipment Associates, Inc. Method and system for modifying photoresist using electromagnetic radiation and ion implantation
US8354655B2 (en) * 2011-05-03 2013-01-15 Varian Semiconductor Equipment Associates, Inc. Method and system for controlling critical dimension and roughness in resist features

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