JP2014510399A - 高速高電力半導体デバイス - Google Patents
高速高電力半導体デバイス Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 52
- 238000002955 isolation Methods 0.000 claims abstract description 5
- 238000000034 method Methods 0.000 claims description 43
- 239000003990 capacitor Substances 0.000 claims description 23
- 229910044991 metal oxide Inorganic materials 0.000 claims description 6
- 150000004706 metal oxides Chemical class 0.000 claims description 6
- 239000012212 insulator Substances 0.000 claims description 4
- 229910052710 silicon Inorganic materials 0.000 claims description 4
- 239000010703 silicon Substances 0.000 claims description 4
- 230000005669 field effect Effects 0.000 claims description 3
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- 229910014299 N-Si Inorganic materials 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 2
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- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 230000001413 cellular effect Effects 0.000 description 1
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- 230000007423 decrease Effects 0.000 description 1
- 238000011156 evaluation Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
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- 238000012546 transfer Methods 0.000 description 1
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Abstract
Description
Ronは、オンになっている場合のNMOSトランジスタ200の抵抗であり、
ηmaxはNMOSトランジスタ200の最大効率であり、
Rloadは電力増幅器の負荷抵抗である。
Cfdはキャパシタ822の容量であり、
VdはNMOSトランジスタ500のドレイン電圧である。
VdはNMOSトランジスタ1000のドレイン電圧である。
Claims (25)
- アクティブゲートとドレインとの間に配置された少なくとも1つの電界ゲートと、
前記少なくとも1つの電界ゲートを横切る方向に形成された少なくとも1つのシャロー・トレンチ・アイソレーション(STI)ストリップと、
前記少なくとも1つのSTIストリップに平行に、そして交互に形成された少なくとも1つのドレイン・アクティブ・ストリップと、
を備える、装置。 - 前記少なくとも1つの電界ゲートは単一の電界ゲートを備える、請求項1に記載の装置。
- 前記少なくとも1つの電界ゲートの各々は、前記アクティブゲートの長さと等しいかまたはそれよりも長い長さを有する、請求項1に記載の装置。
- 各電界ゲートは、前記アクティブゲートまたは別の電界ゲートから最小ポリ間隔の2倍よりも小さいかまたはそれに等しい間隔で配置される、請求項1に記載の装置。
- 前記少なくとも1つのドレイン・アクティブ・ストリップは、前記アクティブゲートと前記ドレインとの間のドレインアクティブ領域内に形成される、請求項1に記載の装置に記載の装置。
- 前記少なくとも1つのSTIストリップは、前記ドレインと前記アクティブゲートとの間に伸びる、請求項1に記載の装置。
- 前記半導体デバイスは、
前記アクティブゲートの下に形成されたP形またはN形ウェルと、
前記アクティブゲートと前記P形またはN形ウェルとの間に形成されたトランジスタゲート酸化物層とをさらに備える、請求項1に記載の装置。 - 前記半導体デバイスは、
各電界ゲートと各ドレイン・アクティブ・ストリップとの間に形成されたトランジスタゲート酸化物層をさらに備える、請求項1に記載の装置。 - 前記少なくとも1つの電界ゲートの各々は、前記アクティブゲートの第1の電圧と前記ドレインの第2の電圧に基づいて決定された異なる電圧を有する、請求項1に記載の装置。
- 前記アクティブゲートまたはソースに結合された第1の端部と、前記少なくとも1つの電界ゲートのうちの1つに結合された第2の端部とを有するキャパシタをさらに備える、請求項1に記載の装置。
- 前記アクティブゲートが電界効果トランジスタ(FET)を制御し、前記少なくとも1つの電界ゲートが金属酸化物半導体(MOS)バラクタ(VAR)を制御する、請求項1に記載の装置。
- 前記半導体デバイスは、N形ソースとN形ドレインとを有するNチャネル金属酸化物半導体(NMOS)トランジスタを備える、請求項1に記載の装置。
- 前記半導体デバイスは、P形ソースとP形ドレインとを有するPチャネル金属酸化物半導体(PMOS)トランジスタを備える、請求項1に記載の装置。
- 前記半導体デバイスは、シリコンオンインシュレータ(SOI)集積回路(IC)プロセスで埋め込み酸化膜層上に作製される、請求項1に記載の装置。
- 前記半導体デバイスは、バルク相補型金属酸化物半導体(CMOS)集積回路(IC)プロセスで作製される、請求項1に記載の装置。
- 前記少なくとも1つの電界ゲートと前記少なくとも1つのSTIストリップと前記少なくとも1つのドレイン・アクティブ・ストリップとを有する半導体デバイスを備えるアクティブ回路をさらに備える、請求項1に記載の装置。
- 前記アクティブ回路は電力増幅器を備える、請求項16に記載の装置。
- 前記装置は集積回路を備える、請求項1に記載の装置。
- アクティブゲートとドレインとの間に少なくとも1つの電界ゲートを形成することと、
前記少なくとも1つの電界ゲートを横切る方向に少なくとも1つのシャロー・トレンチ・アイソレーション(STI)ストリップを形成することと、
前記少なくとも1つのSTIストリップに平行に、そして交互に、少なくとも1つのドレイン・アクティブ・ストリップを形成することと、
を備える、方法。 - 上にソースと前記ドレインと前記少なくとも1つのSTIストリップと前記少なくとも1つのドレイン・アクティブ・ストリップとが形成される埋め込み酸化膜層を形成することをさらに備える、請求項19に記載の方法。
- 上にソースと前記アクティブゲートとが形成されるP形ウェルを形成することと、
上に前記ドレインと前記少なくとも1つの電界ゲートと前記少なくとも1つのSTIストリップと前記少なくとも1つのドレイン・アクティブ・ストリップとが形成されるN形ウェルを形成することと、
をさらに備える、請求項19に記載の方法。 - 上にソースと前記アクティブゲートとが形成されるN形ウェルを形成することと、
上に前記ドレインと前記少なくとも1つの電界ゲートと前記少なくとも1つのSTIストリップと前記少なくとも1つのドレイン・アクティブ・ストリップとが形成されるP形ウェルを形成することと、
をさらに備える、請求項19に記載の方法。 - アクティブゲートとドレインとの間に少なくとも1つの電界ゲートを形成するための手段と、
前記少なくとも1つの電界ゲートを横切る方向に少なくとも1つのシャロー・トレンチ・アイソレーション(STI)ストリップを形成するための手段と、
前記少なくとも1つのSTIストリップに平行に、そして交互に、少なくとも1つのドレイン・アクティブ・ストリップを形成するための手段と、
を備える、装置。 - 上にソースと前記ドレインと前記少なくとも1つのSTIストリップと前記少なくとも1つのドレイン・アクティブ・ストリップとが形成される埋め込み酸化膜層を形成するための手段をさらに備える、請求項23に記載の装置。
- 上にソースと前記アクティブゲートとが形成されるP形ウェルを形成するための手段と、
上に前記ドレインと前記少なくとも1つの電界ゲートと前記少なくとも1つのSTIストリップと前記少なくとも1つのドレイン・アクティブ・ストリップとが形成されるN形ウェルを形成するための手段と、
をさらに備える、請求項23に記載の装置。
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US13/103,918 US9543383B2 (en) | 2011-02-17 | 2011-05-09 | High-speed high-power semiconductor devices |
US13/103,918 | 2011-05-09 | ||
PCT/US2012/025733 WO2012112948A1 (en) | 2011-02-17 | 2012-02-17 | High-speed high-power semiconductor devices |
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Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2017522719A (ja) * | 2014-06-18 | 2017-08-10 | インテル・コーポレーション | 高電圧電界効果トランジスタのための延長型ドレイン構造 |
Families Citing this family (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8963241B1 (en) * | 2009-11-13 | 2015-02-24 | Maxim Integrated Products, Inc. | Integrated MOS power transistor with poly field plate extension for depletion assist |
US8969958B1 (en) * | 2009-11-13 | 2015-03-03 | Maxim Integrated Products, Inc. | Integrated MOS power transistor with body extension region for poly field plate depletion assist |
WO2013176147A1 (ja) * | 2012-05-25 | 2013-11-28 | 株式会社村田製作所 | 電力増幅回路 |
JP6208971B2 (ja) * | 2012-09-14 | 2017-10-04 | ルネサスエレクトロニクス株式会社 | 半導体装置、及び半導体装置の製造方法 |
US9064709B2 (en) * | 2012-09-28 | 2015-06-23 | Intel Corporation | High breakdown voltage III-N depletion mode MOS capacitors |
US10134727B2 (en) | 2012-09-28 | 2018-11-20 | Intel Corporation | High breakdown voltage III-N depletion mode MOS capacitors |
WO2014070779A1 (en) | 2012-10-30 | 2014-05-08 | Anayas360.Com, Llc. | Address based serial communication interface for control and monitoring of system-on-chip implementations |
WO2014089521A1 (en) * | 2012-12-07 | 2014-06-12 | Anayas360.Com, Llc | Highly integrated millimeter-wave soc layout techniques |
CN104900524B (zh) * | 2014-03-06 | 2018-04-13 | 中芯国际集成电路制造(上海)有限公司 | 一种横向扩散半导体器件及其制备方法 |
CN104251751B (zh) * | 2014-09-26 | 2017-01-25 | 中国科学院半导体研究所 | 一种多感官集成的电子皮肤及其制造方法 |
CN105047700B (zh) * | 2015-06-29 | 2017-11-21 | 四川广义微电子股份有限公司 | 一种轻穿通igbt器件的制备方法 |
JP6608312B2 (ja) * | 2016-03-08 | 2019-11-20 | ルネサスエレクトロニクス株式会社 | 半導体装置およびその製造方法 |
US10340289B2 (en) * | 2017-04-28 | 2019-07-02 | Qualcomm Incorporated | Cascode radio frequency (RF) power amplifier on single diffusion |
US10333007B2 (en) | 2017-06-19 | 2019-06-25 | Qualcomm Incorporated | Self-aligned contact (SAC) on gate for improving metal oxide semiconductor (MOS) varactor quality factor |
US10475921B2 (en) * | 2018-02-05 | 2019-11-12 | Globalfoundries Inc. | Laterally diffused field effect transistor and a method of manufacturing the same |
US10411091B1 (en) * | 2018-07-13 | 2019-09-10 | Qualcomm Incorporated | Integrated circuits employing a field gate(s) without dielectric layers and/or work function metal layers for reduced gate layout parasitic resistance, and related methods |
US20210407935A1 (en) * | 2020-06-30 | 2021-12-30 | GLOBALFOUNDRIES U.S.Inc. | Semiconductor transistors suitable for radio-frequency applications |
TW202303979A (zh) * | 2021-02-23 | 2023-01-16 | 麥覺理大學 | 用於無線電接收器及發射器的半導體裝置 |
Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP1073123A2 (en) * | 1999-07-29 | 2001-01-31 | Kabushiki Kaisha Toshiba | High withstand voltage semiconductor device |
WO2002078090A2 (en) * | 2001-03-23 | 2002-10-03 | Koninklijke Philips Electronics N.V. | Field-effect transistor structure and method of manufacture |
US20070120187A1 (en) * | 2003-05-13 | 2007-05-31 | Cambridge Semiconductor Limited | Lateral soi semiconductor device |
US7405443B1 (en) * | 2005-01-07 | 2008-07-29 | Volterra Semiconductor Corporation | Dual gate lateral double-diffused MOSFET (LDMOS) transistor |
US20090039424A1 (en) * | 2007-08-10 | 2009-02-12 | Chao-Yuan Su | High-voltage mos transistor device |
WO2010046794A1 (en) * | 2008-10-20 | 2010-04-29 | Nxp B.V. | Semiconductor device and method of manufacturing such a device |
US20100140715A1 (en) * | 2008-12-04 | 2010-06-10 | Kabushiki Kaisha Toshiba | Semiconductor device |
US20100163987A1 (en) * | 2008-12-26 | 2010-07-01 | Rohm Co., Ltd. | Semiconductor device |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20060071270A1 (en) | 2004-09-29 | 2006-04-06 | Shibib Muhammed A | Metal-oxide-semiconductor device having trenched diffusion region and method of forming same |
JP2008544535A (ja) | 2005-06-22 | 2008-12-04 | エヌエックスピー ビー ヴィ | 絶縁破壊電圧が相対的に高い半導体デバイス及びその製造方法 |
WO2007042850A1 (en) | 2005-10-12 | 2007-04-19 | Acco | Insulated gate field-effet transistor having a dummy gate |
US7936553B2 (en) * | 2007-03-22 | 2011-05-03 | Paratek Microwave, Inc. | Capacitors adapted for acoustic resonance cancellation |
US7847351B2 (en) * | 2008-04-11 | 2010-12-07 | Texas Instruments Incorporated | Lateral metal oxide semiconductor drain extension design |
US8502316B2 (en) * | 2010-02-11 | 2013-08-06 | Taiwan Semiconductor Manufacturing Company, Ltd. | Self-aligned two-step STI formation through dummy poly removal |
US8772871B2 (en) * | 2010-08-20 | 2014-07-08 | Freescale Semiconductor, Inc. | Partially depleted dielectric resurf LDMOS |
-
2011
- 2011-05-09 US US13/103,918 patent/US9543383B2/en active Active
-
2012
- 2012-02-17 EP EP12710002.2A patent/EP2676295A1/en not_active Withdrawn
- 2012-02-17 WO PCT/US2012/025733 patent/WO2012112948A1/en active Application Filing
- 2012-02-17 JP JP2013554658A patent/JP5684410B2/ja not_active Expired - Fee Related
- 2012-02-17 CN CN201280009506.8A patent/CN103380497B/zh not_active Expired - Fee Related
Patent Citations (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP1073123A2 (en) * | 1999-07-29 | 2001-01-31 | Kabushiki Kaisha Toshiba | High withstand voltage semiconductor device |
JP2001044424A (ja) * | 1999-07-29 | 2001-02-16 | Toshiba Corp | 高耐圧半導体装置 |
WO2002078090A2 (en) * | 2001-03-23 | 2002-10-03 | Koninklijke Philips Electronics N.V. | Field-effect transistor structure and method of manufacture |
JP2004519861A (ja) * | 2001-03-23 | 2004-07-02 | コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ | 電界効果トランジスタの構造体及び製造方法 |
US20070120187A1 (en) * | 2003-05-13 | 2007-05-31 | Cambridge Semiconductor Limited | Lateral soi semiconductor device |
US7405443B1 (en) * | 2005-01-07 | 2008-07-29 | Volterra Semiconductor Corporation | Dual gate lateral double-diffused MOSFET (LDMOS) transistor |
US20090039424A1 (en) * | 2007-08-10 | 2009-02-12 | Chao-Yuan Su | High-voltage mos transistor device |
WO2010046794A1 (en) * | 2008-10-20 | 2010-04-29 | Nxp B.V. | Semiconductor device and method of manufacturing such a device |
US20100140715A1 (en) * | 2008-12-04 | 2010-06-10 | Kabushiki Kaisha Toshiba | Semiconductor device |
JP2010157688A (ja) * | 2008-12-04 | 2010-07-15 | Toshiba Corp | 半導体装置 |
US20100163987A1 (en) * | 2008-12-26 | 2010-07-01 | Rohm Co., Ltd. | Semiconductor device |
JP2010157582A (ja) * | 2008-12-26 | 2010-07-15 | Rohm Co Ltd | 半導体装置 |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2017522719A (ja) * | 2014-06-18 | 2017-08-10 | インテル・コーポレーション | 高電圧電界効果トランジスタのための延長型ドレイン構造 |
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