JP2014216466A - Semiconductor package and method of manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor package, along with its manufacturing method, which enables manufacturing of a lamination device in which a plurality of semiconductor package devices in various kinds are laminated.SOLUTION: There are provided a plurality of leads arranged peripherally on four sides of a square semiconductor package being resin sealed. A plurality of first leads provided on two facing sides are formed to have a height similar to that of a semiconductor chip 6 mounted on the semiconductor package, with the semiconductor chip 6 connected to bonding wires 7a, b, c, d, e, f. A plurality of second leads provided on two facing sides which are different from the two sides facing the first leads are formed to have a height that is higher than the bonding wires 7a, b, c, d, e, f, not being connected to the semiconductor chip 6. An end surface of a lower surface side and an end surface of a side surface side of the package of the first lead are exposed from a surface of the semiconductor package, and end surfaces on a lower surface side and an upper surface side as well as an end surface on a side surface side of the package of the second lead are exposed from a surface of the semiconductor package.

Description

  The present invention relates to a semiconductor package and a manufacturing method thereof.

In POP (Package On Package), in order to stack each semiconductor package, each external connection terminal connected to the electrode of the semiconductor chip is exposed on both the front and back sides of the sealing resin.
In order to reduce the thickness of each semiconductor chip, each external connection terminal has a terminal structure in which an external connection electrode and an internal electrode wire-bonded to the electrode of the semiconductor chip are connected by a connecting portion. A structure in which the thickness is made thinner than the thickness of the external electrode is known. In this structure, all the external connection terminals are wire-bonded to any electrode of the semiconductor chip (see, for example, Patent Document 1).

JP 2002-76175 A

  In a stacked package device in which a plurality of semiconductor package devices are stacked, the terminals of each stacked package are stacked in contact with each other, and therefore only for stacking the same type of semiconductor package device. Met. In such a stacked package device and the structure of an individual semiconductor package for this stack, various different types of package devices or surface mount devices, etc., in which wiring is different for each combination of devices, are further provided on the semiconductor package. It was not possible to laminate.

(1) The invention described in claim 1 is a rectangular semiconductor package in which a semiconductor chip is sealed with a resin, and includes a plurality of leads provided around four sides of the semiconductor package. Including a plurality of first leads provided on two opposing sides of the package and a plurality of second leads provided on two opposing sides different from the two opposing sides, wherein the first leads are: The semiconductor chip sealed in the semiconductor package is connected to the bonding wire, and the plurality of second leads are formed so as to be higher than the bonding wire, and are not connected to the semiconductor chip. The end surface and the end surface on the side surface of the package are exposed on the surface of the semiconductor package, and the end surface on the lower surface side and upper surface side of the second lead and the end surface on the side surface of the package are exposed to the semiconductor package. Is a semiconductor package characterized by exposed on the surface.
(2) The invention according to claim 2 is the method of manufacturing a semiconductor package according to claim 1, comprising a plurality of die pads, and a plurality of first leads and a plurality of leads around each of the plurality of die pads. A first step of preparing a lead frame in which a second lead is provided; a first step of placing a semiconductor chip on each of the plurality of die pads and bonding-connecting the semiconductor chip and the plurality of first leads; After the second step, after the second step, a third step of sealing the entire lead frame with resin, after the third step, a fourth step of cutting into individual semiconductor packages with a cutter, A semiconductor package manufacturing method comprising: a fifth step of stacking another semiconductor package or device and connecting to a second lead.
(3) The invention described in claim 3 is the method of manufacturing the semiconductor package according to claim 1, comprising a plurality of die pads, and a plurality of first leads and a plurality of leads around each of the plurality of die pads. A first step of preparing a lead frame in which a second lead is provided; a first step of placing a semiconductor chip on each of the plurality of die pads and bonding-connecting the semiconductor chip and the plurality of first leads; After the second step, after the second step, a third step of sealing the entire lead frame with a resin, and after the third step, another semiconductor package or device is stacked on the semiconductor chip and the second step is performed. A semiconductor package manufacturing method comprising: a fourth step of connecting to a lead; and a fifth step of cutting into individual semiconductor packages with a cutter after the fourth step.

  By using the semiconductor package according to the present invention, it is possible to manufacture a stacked device in which various different types of devices and package devices are stacked. Thereby, a small and high-density laminated device can be manufactured. Moreover, in this invention, such a laminated device can be manufactured efficiently.

It is a figure for demonstrating the manufacturing method of the semiconductor package by this invention, and is a perspective view which shows the structural example of a lead frame. FIG. 2 is a perspective view for explaining a process following FIG. 1 and showing a state in which a semiconductor chip and a lead frame are bonded. FIG. 3 is a diagram for explaining a process following FIG. 2, and is an external perspective view showing a state in which the entire lead frame is molded with resin. FIG. 4 is a diagram for explaining a process following FIG. 3, and is an external perspective view showing a state in which individual semiconductor packages are cut out from a molded lead frame. (A) shows one Embodiment of the semiconductor package of this invention, is a perspective view which permeate | transmits sealing resin and shows an internal structure, (b) is a semiconductor package of (a) by sealing resin C) is a sealed external perspective view, and c) is a multilayer in which another device (semiconductor package, chip resistor, chip capacitor, chip inductor, various sensor packages, small PCB, etc.) is mounted on the semiconductor package of (b). It is an external appearance perspective view of a device. FIG. 5 is a schematic view showing a modification of the method for manufacturing a semiconductor package according to the present invention, in which another element is mounted in the state shown in FIG. 3 and each individual semiconductor package is cut out thereafter. FIG. 2 is a view showing a structure example of a lead frame for providing the lead frame of FIG. 1 with leads for GND connection of a laminated device in a semiconductor package.

With reference to FIGS. 1-7, embodiment and modified example of the semiconductor package by this invention and its manufacturing method are described.
An example of the final form of the semiconductor package according to the present invention is shown in FIGS. 5 (a) and 5 (b). The semiconductor package is configured as a laminated device 23 in which a device (referred to as an upper device) 22 is mounted on a semiconductor package 21 as shown in FIG.

  FIG. 1 shows an example of a lead frame 1 used for manufacturing a semiconductor package according to the present invention. The die pad 2 is mounted with the semiconductor chip 6 illustrated in FIG. 5A (see FIG. 2). Leads 3a to 3f connected to electrodes (not shown) of the semiconductor chip 6 by bonding wires are provided on two opposite sides among the four sides around the die pad 2.

  Moreover, leads 4a to 4h for connecting to the upper device 22 stacked on the upper side of the package device 21 as shown in FIG. Therefore, the leads 4a to 4h are not connected to the electrodes of the semiconductor chip 6. Leads 3a to 3f connected to electrodes (not shown) of the semiconductor chip 6 have the same height (thickness) as that of the die pad 2 or the semiconductor chip 6 placed on the die pad 2. On the other hand, the heights (thicknesses) of the leads 4a to 4h are such that they are higher than the heights of the bonding wires 7a to 7f that connect the semiconductor chip 6 and the leads 3a to 3f.

  Thus, by providing the leads 3a to 3f for connecting the semiconductor chip 6 and the leads 4a to 4h for connecting the upper device 22 respectively, the size of the leads can be reduced, and the semiconductor package 21 used for the stacked device 23 can be made smaller. can do. Both the leads 3a to 3f and the leads 4a to 4h have such a shape that the semiconductor chip 6 or the upper device can be connected, that is, a shape in which the height is low on the semiconductor chip side and high on the outside. A lead (for example, a shape like the terminal portion 110 of Japanese Patent Application Laid-Open No. 2008-60652) can be used, but the lead having such a shape is necessarily large (long), so that the semiconductor package 21 can be reduced in size. Not suitable for conversion.

  The number of leads 3a to 3f and 4a to 4h is not limited to the number as shown in FIGS. Each can be appropriately changed according to the number of connection pads of the semiconductor chip 6 and the specifications of the upper device 22 stacked on the upper side. Alternatively, in order to further secure the degree of freedom of semiconductor chips having different specifications and stacked devices, a larger number may be arranged as appropriate. In FIGS. 1 and 2, the same number of leads is provided on each of two opposing sides, but a different number of leads may be provided on each of the two opposing sides.

  In FIGS. 1 to 4 and 6, only four regions of the semiconductor package 21 are shown for explanation. Accordingly, FIG. 1 shows four regions of the semiconductor package 21 of the lead frame 1 in which the die pad 2, the leads 3a to 3f and 4a to 4h, and the frame portion 5 are integrally formed. In FIG. 1 and FIG. 2, for the sake of explanation, the upper right one of the four semiconductor packages 21 is described with reference numerals, but the other three have the same configuration. It has become. In FIGS. 1 and 2, the leads 3 d to 3 f are shown as not being connected anywhere, but this is because the frame portion 5 in which these leads are integrally formed is omitted for explanation. It is.

  After connecting the semiconductor chip 6 and the leads 3a to 3f with bonding wires as shown in FIG. 2, the entire lead frame 1 on which the plurality of semiconductor chips 6 are placed is sealed up to the height of the leads 4a to 4h. 8 is poured and cured to form as shown in FIG. If necessary, the upper surface is polished so that the upper surfaces of the leads 4a to 4h are exposed.

  After the sealing resin 8 is cured, as shown in FIG. 4, it is cut using a cutter 9 to produce individual semiconductor packages 21. Although not shown in FIG. 4, in order to separate the leads 3 a to 3 f and 4 a to 4 h formed integrally with the frame portion 5 from the frame portion 5, a cutter is used between two adjacent semiconductor packages. The cutting by 9 is actually performed twice.

FIGS. 5A to 5C show one semiconductor package 21 after being cut into individual semiconductor packages 21 as shown in FIG. 4 so that the above manufacturing process can be easily understood.
FIG. 5A shows the sealing resin 8 sealed as shown in FIG. 5B in a transparent manner so that the bonding wire connection state described in FIG. 2 can be seen.

  If necessary, other semiconductor packages, chip resistors, chip capacitors, chip inductors, various sensor packages, small PCBs, and other various devices 22 (referred to as upper devices) are stacked on the semiconductor package 21 as necessary. The stacked package 23 shown in FIG. 5C can be formed by connecting with solder or the like. In the semiconductor package 21 and the upper device 22, the leads 4 a to 4 d are connected to one electrode of the upper device 22, and the leads 4 e to 4 h are connected to the other electrode of the upper device 22. When the upper device 22 has three or more electrodes or a plurality of devices 22 are stacked on the semiconductor package 21, the leads 4 a to 4 h are connected to different electrodes of the upper device 22, respectively. This connection may be made with a conductive adhesive other than solder. Since various devices are placed as the device 22, the lead for soldering the upper device 22 is omitted.

  The size of the semiconductor package 21 is, for example, about several mm to several cm depending on the size of the semiconductor chip 6 to be mounted. The upper device 22 may be mounted with a plurality of the same or different devices, depending on the size, if necessary.

The shape of the semiconductor package 21 according to the present invention described with reference to FIGS. 1 to 5 is similar to a so-called SON type package. That is, the leads connected to the semiconductor chip 6 mounted on the semiconductor package 21 are leads for connection (soldering or the like) to an external circuit on the lower surface and side surface of the package on two opposite sides of the package. The end face of is exposed.
However, in the semiconductor package 21 of the present invention, leads that are not connected to the semiconductor chip are further provided on two opposite sides of the semiconductor package 21. As can be seen from FIGS. 1 to 5, the leads are exposed not only on the lower and side surfaces of the semiconductor package 21 but also on the upper surface.

  For ease of understanding, FIG. 5B shows the end surfaces 31a to 31c where the leads 3a to 3c are exposed on the side surface of the package, the end surface 35a of the die pad support portion 35 (see FIG. 7), and the leads 4a to 4h. End faces 41a to 41h exposed on the upper surface side, and leads 4e to 4h are shown end faces 42e to 42h exposed on the package side face. The other end surfaces of the leads are not shown because they are hidden in the figure.

  The laminated semiconductor package 23 manufactured as described above is placed on a larger PCB (not shown), for example, and is laminated with the semiconductor chip 6 of the semiconductor package 21 by wiring on the PCB. The upper device 22 is incorporated into the desired circuit.

  In the conventional stacked package device, the upper package device and the lower package device of the two stacked package devices are connected. Therefore, the combination of the upper package device and the lower package device has a predetermined configuration. It was a stacked package device. However, in the stacked device using the semiconductor package 21 according to the present invention and this manufacturing method, the upper device (which may be a package device) 22 and the lower semiconductor package 21 can be variously combined. In particular, different devices can be flexibly mounted as the upper device 22 as required.

In summary, the semiconductor package 21 according to the present invention has the following structure.
The semiconductor package 21 according to the present invention is a rectangular semiconductor package in which the semiconductor chip 6 is sealed with the sealing resin 8, and includes a plurality of leads provided around the four sides of the semiconductor package 21. The plurality of leads include first leads 3a to 3f connected to the mounted semiconductor chip 6 by bonding wires, and second leads 4a to 4h not connected to the semiconductor chip. The first leads connected to the semiconductor chip 6 are approximately the same height as the semiconductor chip 6 placed on the die pad 2 of the lead frame 1, and these are opposed to each other across the semiconductor chip 6. Two sides, i.e., two opposing sides of the rectangular semiconductor package 21 are provided. A second lead formed so as to be higher than the bonding wire is provided along two opposing sides other than the two sides. The end surface on the package lower surface side and the end surface on the package side surface of the first lead are exposed on the surface of the semiconductor package 21, and the end surface on the package lower surface side and upper surface side of the second lead and the end surface on the package side surface are the semiconductor package 21. Is exposed on the surface.

  Using the semiconductor package 21 having the structure as described above, a package device different from the semiconductor package 21 and various devices such as a surface mount device are stacked on the semiconductor package 21 as the upper device 22, and the stacked device 23 Configure.

The manufacturing method of the semiconductor package 21 configured as described above according to the present invention is summarized as follows.
In the manufacturing method of the semiconductor package 21 of the present invention, first, a lead frame including a plurality of die pads 2 and having the first lead and the second lead arranged around each of the plurality of die pads is prepared ( First step). Next, the semiconductor chip is placed on each of the plurality of die pads, and the semiconductor chip and the plurality of first leads are bonded and connected (second step). Subsequently, the entire lead frame is sealed with resin and cured (third step). In this step, polishing or cleaning may be performed so that the end surfaces of the first lead and the second lead are sufficiently exposed to the outside of the package as necessary after the resin is cured. After this third step, each semiconductor package is cut with a cutter (fourth step).
After cutting into individual semiconductor packages, another semiconductor package or device (upper device 22) is further stacked on each semiconductor package 21 and connected to the second lead by solder or the like (fifth step).

(Modified Example 1)
FIG. 6 shows a modified embodiment of the manufacturing method of the laminated device using the semiconductor package device according to the present invention.
In the above description, as shown in FIGS. 4 and 5, after each semiconductor package 21 is cut out, another device 22 is placed on each semiconductor package 21 and connected and fixed with solder or the like. However, in the example shown in FIG. 6, in the state shown in FIG. 3, the device 22 is placed corresponding to each semiconductor package and connected and fixed together with a solder dip or the like, and then, as shown in FIG. Cut into individual laminated devices 23. By manufacturing in this way, the process can be omitted and the manufacturing time can be shortened.

(Modified Example 2)
In the method for manufacturing a laminated device according to the present invention described above, different semiconductor chips are mounted on each of the plurality of die pads 2 shown in FIG. 1, and different devices 22 are laminated on the upper side as needed. It can also be mounted (not shown). With such a manufacturing method, a plurality of laminated devices having different functions can be manufactured from one lead frame. Such a manufacturing method is very suitable for the manufacture of a small amount of various types of stacked package devices.

(Modified Example 3)
When manufacturing a variety of stacked devices as described in the above-described modified embodiment 2 from a single lead frame, the surface of the die pad 2 shown in FIG. 1 or the semiconductor package 21 after resin encapsulation shown in FIG. The type of the laminated device 23 is engraved with a laser or the like (not shown) on the upper surface and the lower surface of FIG. Such marking data is stored in the computer of the manufacturing apparatus, and based on the marking data, the upper device to be stacked can be selected, and the type of the final stacked package device can be determined. In this way, it is possible to surely manufacture stacked devices having different functions from one lead frame, and it is also easy to separate stacked devices having different functions.

(Modified Example 4)
In the above description, it has been described that the semiconductor package according to the present invention is similar to the SON type package. However, the present invention can also be applied to various package devices in which the outer portion of the lead for external connection extends further to the outer portion of the package. However, the upper surface portion of the lead connected to the upper device 22, that is, the lead not connected to the semiconductor chip 6 has a shape exposed on the upper surface of the package device 21.

(Modified Example 5)
FIG. 7 shows the structure of the lead frame 1 for providing another connection lead 34 in the semiconductor package described above. For the sake of explanation, only the range of one semiconductor package of the lead frame 1 is shown.

The lead 34 has the same shape as the leads 4 a to 4 h, but further has a semiconductor chip connection portion 34 a for bonding connection to the semiconductor chip 6.
For example, by connecting a GND pad (not shown) of a semiconductor chip to the lead 34, the GND of the semiconductor package 21 and the GND of the upper device 22 stacked on the semiconductor package 21 are connected. The GND is exposed as the end face of the lead 34 on the upper and lower surfaces of the laminated device. With such a structure, it is possible to maintain the GND connection when the stacked device is transported by a mounter or a handler, and damage to the device due to static electricity or the like can be prevented.

  Such leads 34 may be provided at the corners of the rectangular semiconductor package 21 as shown in FIG. 7, for example, as shown in FIG. A plurality of corners may be provided.

  Such a lead 34 is also used for purposes other than the GND connection, for example, when the upper device 22 to be stacked is connected to the semiconductor chip 6 in a circuit state in the state of FIG. 5 or FIG. it can.

  Although not shown, if such a lead 34 is used only for GND connection, a structure in which the lead 34 is connected to, for example, a die pad from the beginning can be used. Alternatively, the lead frame may be formed from the beginning so that the lead 34 is connected to the die pad support portion 35 where the die pad 2 is connected to the frame frame in FIG.

  The above description is an example of embodiments of the present invention, and the present invention is not limited to these embodiments and examples. Those skilled in the art can implement various modifications without impairing the features of the present invention.

DESCRIPTION OF SYMBOLS 1 ... Lead frame 2 ... Die pad 3a-3f ... Semiconductor chip connection lead 4a-4h ... Upper device connection lead 5 ... Lead frame frame 6 ... Semiconductor chip (die)
7a to 7f: bonding wire 8 ... encapsulating resin 9 ... cutter 21 ... semiconductor package
22 ... Upper device
23 ... Laminated devices 31a to 31c ... End surfaces of the leads 3a to 3c on the side of the package 34 ... Connecting leads 34a ... Semiconductor chip connecting part of the connecting lead 34 35 ... Die pad support part 41a ~ 41h: package upper surface side end surfaces of leads 4a-4h 42e-42h: package side surface end surfaces of leads 4e-4h

Claims (5)

A rectangular semiconductor package in which a semiconductor chip is sealed with resin,
A plurality of leads provided around the four sides of the semiconductor package;
The plurality of leads include a plurality of first leads provided on two opposing sides of the semiconductor package, and a plurality of second leads provided on two opposing sides different from the two opposing sides. Including
The first lead is connected to the semiconductor chip sealed in the semiconductor package with a bonding wire,
The plurality of second leads are formed to be higher than the bonding wire and are not connected to the semiconductor chip,
An end surface on the package lower surface side and an end surface on the package side surface of the first lead are exposed on the surface of the semiconductor package,
The semiconductor package according to claim 1, wherein an end surface on the lower surface side and an upper surface side of the second lead and an end surface on the side surface of the package are exposed on the surface of the semiconductor package. A method of manufacturing a semiconductor package according to claim 1,
A first step of providing a lead frame comprising a plurality of die pads, wherein the plurality of first leads and the plurality of second leads are provided around each of the plurality of die pads;
A second step of placing the semiconductor chip on each of the plurality of die pads and bonding-connecting the semiconductor chip and the plurality of first leads;
After the second step, a third step of sealing the entire lead frame with resin;
After the third step, a fourth step of cutting into individual semiconductor packages with a cutter;
5. A method of manufacturing a semiconductor package, comprising: a fifth step of stacking another semiconductor package or device on the semiconductor package and connecting to the second lead. A method of manufacturing a semiconductor package according to claim 1,
A first step of providing a lead frame comprising a plurality of die pads, wherein the plurality of first leads and the plurality of second leads are provided around each of the plurality of die pads;
A second step of placing the semiconductor chip on each of the plurality of die pads and bonding-connecting the semiconductor chip and the plurality of first leads;
After the second step, a third step of sealing the entire lead frame with resin;
A fourth step of stacking another semiconductor package or device on top of the semiconductor chip and connecting to the second lead after the third step;
And a fifth step of cutting each semiconductor package with a cutter after the fourth step. The semiconductor package according to claim 1,
A third lead having the same height as the second lead, the same height as the first lead, and having a connecting portion capable of being bonded to the semiconductor chip is provided. Semiconductor package. 2. A laminated device comprising: a semiconductor package according to claim 1; and another semiconductor package or device placed thereon and connected to the second lead.

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