JP2014216444A - Silicon carbide semiconductor device and manufacturing method of the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a silicon carbide semiconductor device which can inhibit the occurrence of a hysteresis phenomenon without requiring a complicated gate electrode structure.SOLUTION: A silicon carbide semiconductor device comprises a gate electrode 7 provided on a part of a well region 4, a part of a drift layer 2 and a partial upper part of a source region 3 via a gate insulation film 6. The gate electrode 7 is composed of a conductive layer in which a semiconductor material is doped with a second conductivity type impurity, and the conductive layer is further doped with nitrogen. The gate electrode 7 has a concentration of nitrogen higher than a concentration of the impurity on the side contacting the gate insulation film 6.

Description

  The present invention relates to a semiconductor device using silicon carbide.

  In power electronics equipment, an insulated gate bipolar transistor (IGBT: Insulated Gate Bipolar Transistor) or a MOSFET (Metal Oxide Field Transistor Transistor) is used as a means for switching between execution and stop of power supply for driving a load such as an electric motor. Switching elements such as these are used.

  Semiconductor elements are broadly classified into unipolar elements in which only electrons or holes act on conduction when energized, and bipolar elements in which both electrons and holes act on conduction.

  The unipolar element includes a Schottky barrier diode (SBD) or a MOSFET.

  Examples of the bipolar element include a pn diode, a bipolar junction transistor (BJT), a thyristor, a GTO (Gate Turn Off) thyristor, or an IGBT.

  A semiconductor device using a silicon carbide (SiC) semiconductor is superior in high voltage, large current, and high temperature operation as compared with a semiconductor device using a silicon (Si) semiconductor. Accordingly, semiconductor devices using silicon carbide semiconductors are being developed as next-generation power semiconductor devices.

  Among silicon carbide MOSFETs used as power semiconductors, vertical MOSFETs are particularly important applications. There are different types of vertical MOSFETs, such as a planar type and a trench type, depending on the gate structure.

  In a power vertical MOSFET having a planar gate structure, a gate insulating film and a gate electrode are formed on the SiC surface. By applying a voltage to the gate electrode, the p-type SiC (P well) formed on the SiC surface is inverted, and is present under the high-concentration n-type source electrode and P well formed on the SiC surface. An N drift layer made of n-type SiC is connected. The P well below the gate electrode becomes a channel.

  The n-type source electrode is connected to the source wiring. The P well is also connected to the source wiring through a high-concentration p-type contact provided in the P well.

  High-concentration n-type SiC (drain electrode) is formed on the back side of the substrate.

  In a power vertical MOSFET having a trench structure, a trench called a trench is formed in an SiC substrate, and a gate insulating film and a gate electrode are embedded in the trench.

  In this MOSFET, when a voltage is applied to the gate electrode, the P well (channel) in contact with the side wall of the gate insulating film of the trench is inverted, and the source electrode formed on the SiC surface and the lower side of the P well are present. To the drift layer made of n-type SiC.

  In order to realize a large current operation, the vertical MOSFET for power is composed of an element structure in which a large number of MOSFET unit cells (unit cells) are connected in parallel. In order to realize a high-power semiconductor device, it is necessary to sufficiently reduce the on-resistance.

  Further, when this power vertical MOSFET is used in a power converter that drives and controls a load such as a motor, it is necessary to set the threshold voltage (Vth) of the power vertical MOSFET to about 5 V. The threshold voltage is a large value.

  When the power converter is used, heat is generated by the flowing current, and the temperature of the power vertical MOSFET rises. In general, the threshold voltage (Vth) of a MOSFET decreases as its temperature increases.

  The power converter includes a power vertical MOSFET and a gate drive circuit that applies a control signal to the gate electrode of the power vertical MOSFET. When a problem occurs in the gate drive circuit and the gate drive circuit stops outputting a control signal, that is, when the output of the gate drive circuit becomes 0V, a problem occurs.

  When the threshold voltage (Vth) of the power vertical MOSFET is reduced to 0 V or less (negative voltage) due to temperature rise, the power vertical MOSFET is in a normally on state, and current flows continuously. So the temperature rises further. Finally, the element is destroyed. Therefore, the threshold voltage (Vth) of the power vertical MOSFET must be greater than 0 V even when the temperature of the power vertical MOSFET becomes high.

  Normally, the threshold voltage (Vth) increases as the p-type impurity concentration in the P-well in the channel portion is increased. However, in this method, the channel resistance increases as the p-type impurity increases. For this reason, there is a trade-off relationship that the on-resistance of the power vertical MOSFET increases.

  One technique for setting the threshold voltage (Vth) high without increasing the on-resistance of the power vertical MOSFET is to employ a p-type gate electrode. In this technique, polycrystalline silicon containing n-type impurities is usually used for the gate electrode, and polycrystalline silicon containing p-type impurities is used instead for the gate electrode.

  The power vertical MOSFET is an NMOS. Since the channel of the vertical MOSFET for power is p-type, when the gate electrode is p-type, the Fermi levels of the gate electrode and the channel are almost the same value. The closer the Fermi level, the less the conduction band and valence band bending at the interface between the gate insulating film and the channel. For this reason, a large gate voltage is required to invert the channel, that is, the threshold voltage (Vth) increases.

  For example, boron (boron: B) is used as the p-type impurity of the gate electrode. However, since B has a large diffusion coefficient, it has been reported in a MOSFET using Si as a semiconductor that it diffuses from the gate electrode into the gate insulating film by heat treatment during the manufacturing process and reaches the channel (for example, B). Patent Documents 1 to 4).

  In order to prevent the diffusion of B into the channel, nitrogen (N) is introduced into the gate electrode. Since nitrogen suppresses the diffusion of B, the diffusion of B into the channel can be prevented.

  In a MOSFET using Si, the p-type gate electrode is usually used for PMOS. The p-type gate electrode is used to reduce the absolute value of the PMOS threshold voltage (Vth) (the enhancement-type PMOS threshold voltage (Vth) is negative). Contrary to the case of the NMOS described above, since the PMOS channel is n-type, the Fermi levels of the p-type gate electrode and the channel are greatly different values. As the Fermi level is different, the bending of the conduction band and the valence band at the interface between the gate insulating film and the channel increases. Therefore, the channel can be inverted with a small gate voltage, that is, the absolute value of the threshold voltage (Vth) becomes small.

In the technique disclosed in Patent Document 1, the gate electrode is composed of two layers, and the lower gate electrode is introduced with nitrogen by heat treatment in a nitrogen oxide (NO or N ₂ O) atmosphere. Thereafter, an upper gate electrode is formed and B is ion-implanted.

Also in the technique disclosed in Patent Document 2, the gate electrode has two layers, and the lower gate electrode is formed by chemical vapor deposition (CVD) including ammonia (NH ₃ ) gas, and the upper gate is formed by chemical vapor deposition (CVD). The electrodes are each formed by a CVD method containing diborane (B ₂ H ₆ ) gas.

  Even in the technique disclosed in Patent Document 3, the gate electrode has two layers, but nitrogen introduction into the lower gate electrode and B introduction into the upper gate electrode are both performed by ion implantation.

  In the technique disclosed in Patent Document 4, the gate electrode is a single layer, and nitrogen is introduced into the gate insulating film using a CVD method.

Japanese Patent Laid-Open No. 11-251588 Japanese Patent Laid-Open No. 03-181176 JP 2001-015736 A Japanese Patent Laid-Open No. 08-330584

  The MOSFETs disclosed in Patent Documents 1 to 4 are all formed in Si, and the purpose thereof is to prevent the introduction of B, which is an impurity of the second conductivity type, into the channel portion so that the threshold voltage (Vth) is reduced. It was to prevent fluctuations.

  However, it has been found that a new problem occurs in a vertical MOSFET using SiC as a semiconductor. This is a problem that electrical characteristics are deteriorated only by mixing B, which is an impurity of the second conductivity type, into the gate insulating film.

In a vertical MOSFET using SiC, the gate insulating film is formed by oxidizing SiC to SiO ₂ . In this gate insulating film, C, which is a constituent element of SiC, is contained as an impurity, which deteriorates the characteristics of the gate insulating film.

Specifically, when the gate voltage is applied to the vertical MOSFET and the drain current is measured, a phenomenon in which the drain current varies depending on the direction in which the gate voltage is applied (so-called hysteresis phenomenon) occurs. That is, the measured drain current differs between when the gate voltage is swept from a negative voltage to a positive voltage and when the gate voltage is swept from a positive voltage to a negative voltage. This is because B is trapped by defects caused by the impurities C in the SiO ₂ that is the gate insulating film, and a level at which holes are charged and discharged is formed.

Furthermore, in the MOSFETs disclosed in Patent Documents 1 to 3, the gate electrode has two layers, but the manufacturing process is complicated, such as changing the crystal grain size of polycrystalline silicon in each layer. In Patent Document 4, the SiO ₂ film, which is a gate insulating film, is formed by a CVD method using a gas containing NH _3, and it becomes difficult to precisely control the amount of nitrogen contained in the SiO ₂ film. ing.

  The present invention has been made to solve the above-described problems, and an object thereof is to provide a silicon carbide semiconductor device that does not require a complicated gate electrode structure and can suppress the occurrence of a hysteresis phenomenon. And

  A silicon carbide semiconductor device according to an aspect of the present invention includes a first conductivity type silicon carbide semiconductor substrate, a first conductivity type drift layer formed on a surface of the silicon carbide semiconductor substrate, and a surface layer portion of the drift layer. A second conductivity type well region formed in the well region, a first conductivity type source region formed in a part of a surface layer portion of the well region, a part of the well region, a part of the drift layer, and the source A gate insulating film provided on the surface of a part of the region, and a part of the well region, a part of the drift layer, and a part of the source region are provided via the gate insulating film. A gate electrode comprising a conductive layer in which a semiconductor material is doped with an impurity of a second conductivity type, wherein the conductive layer is further doped with nitrogen and is in contact with the gate insulating film of the gate electrode In the concentration of the nitrogen may be higher than the concentration of the impurity.

  A silicon carbide semiconductor device according to another aspect of the present invention includes a first conductivity type silicon carbide semiconductor substrate, a first conductivity type drift layer formed on a surface of the silicon carbide semiconductor substrate, and a surface layer of the drift layer. A second conductivity type well region formed in a portion, a first conductivity type source region formed in a portion of a surface layer portion of the well region, and a surface of the drift layer where the well region is not formed. And a gate insulating film provided on a surface of a part of the well region, a part of the drift layer, and a part of the source region including the trench inner wall, and the trench is provided in the trench. A gate electrode provided on a part of the well region, a part of the drift layer, and a part of the source region via the gate insulating film, and the gate electrode is doped with nitrogen A first semiconductor layer; and a second semiconductor layer formed on the first semiconductor layer and doped with an impurity of a second conductivity type, wherein the impurity is diffused in the first semiconductor layer. Features.

  A method for manufacturing a silicon carbide semiconductor device according to one aspect of the present invention includes: (a) stacking on a surface of a first conductivity type silicon carbide semiconductor substrate to form a first conductivity type drift layer; ) A step of forming a second conductivity type well region in the surface layer portion of the drift layer; and (c) a step of forming a first conductivity type source region in a portion of the surface layer portion of the well region; ) Forming a gate insulating film on a surface of a part of the well region, a part of the drift layer, and a part of the source region; and (e) forming a conductive layer on the surface of the gate insulating film. And (f) a step of ion-implanting nitrogen into the conductive layer; and (g) a step of ion-implanting a second conductivity type impurity into the conductive layer, and the gate insulating film of the conductive layer; On the contact side, the nitrogen concentration is the impurity concentration. And wherein the high Ri.

  A method for manufacturing a silicon carbide semiconductor device according to another aspect of the present invention includes: (a) stacking on a surface of a first conductivity type silicon carbide semiconductor substrate to form a first conductivity type drift layer; (b) forming a second conductivity type well region in a surface layer portion of the drift layer; (c) forming a first conductivity type source region in a part of the surface layer portion of the well region; d) forming a trench in the surface of the drift layer in which the well region is not formed; and (e) a part of the well region, a part of the drift layer, and the source region including the inner wall of the trench. A step of forming the gate insulating film on a part of the surface, (f) a step of ion-implanting nitrogen into the gate insulating film formed on the sidewall of the trench, and (g) in the trench. Forming a conductive layer; h) a step of ion-implanting a second conductivity type impurity into the conductive layer; and (i) a step of diffusing the nitrogen implanted into the gate insulating film and the impurity implanted into the conductive layer. It is characterized by providing.

  A method for manufacturing a silicon carbide semiconductor device according to another aspect of the present invention includes: (a) stacking on a surface of a first conductivity type silicon carbide semiconductor substrate to form a first conductivity type drift layer; (b) forming a second conductivity type well region in a surface layer portion of the drift layer; (c) forming a first conductivity type source region in a part of the surface layer portion of the well region; d) forming a trench in the surface of the drift layer in which the well region is not formed; and (e) a part of the well region, a part of the drift layer, and the source region including the inner wall of the trench. Forming a gate insulating film on a part of the surface of the semiconductor substrate; and (f) forming a first semiconductor layer formed along the gate insulating film and partially filling the trench; ) Formed on the trench sidewall A step of ion-implanting nitrogen into the first semiconductor layer; (h) a step of forming a second semiconductor layer filling the trench; and (i) a second conductivity type impurity in the second semiconductor layer. And a step of ion implantation.

  According to the above aspect of the present invention, since nitrogen is more doped in the lower portion of the gate electrode than the second conductivity type impurity, the diffusion of the second conductivity type impurity into the gate insulating film can be suppressed. Therefore, the occurrence of the hysteresis phenomenon can be suppressed.

1 is a schematic plan view of a silicon carbide semiconductor device in a first embodiment. It is a top view of A-A 'vicinity of FIG. 1 in 1st Embodiment. It is sectional drawing on the B-B 'line of FIG. 2 in 1st Embodiment. It is sectional drawing according to process which shows the manufacturing method of the silicon carbide semiconductor device in 1st Embodiment. It is sectional drawing according to process which shows the manufacturing method of the silicon carbide semiconductor device in 1st Embodiment. It is sectional drawing according to process which shows the manufacturing method of the silicon carbide semiconductor device in 1st Embodiment. It is sectional drawing according to process which shows the manufacturing method of the silicon carbide semiconductor device in 1st Embodiment. It is sectional drawing according to process which shows the manufacturing method of the silicon carbide semiconductor device in 1st Embodiment. It is sectional drawing according to process which shows the manufacturing method of the silicon carbide semiconductor device in 1st Embodiment. It is sectional drawing according to process which shows the manufacturing method of the silicon carbide semiconductor device in 1st Embodiment. It is sectional drawing according to process which shows the manufacturing method of the silicon carbide semiconductor device in 1st Embodiment. It is sectional drawing according to process which shows the manufacturing method of the silicon carbide semiconductor device in 1st Embodiment. It is sectional drawing according to process which shows the manufacturing method of the silicon carbide semiconductor device in 1st Embodiment. It is sectional drawing according to process which shows the manufacturing method of the silicon carbide semiconductor device in 1st Embodiment. It is sectional drawing according to process which shows the manufacturing method of the silicon carbide semiconductor device in 1st Embodiment. It is sectional drawing according to process which shows the manufacturing method of the silicon carbide semiconductor device in 2nd Embodiment. It is sectional drawing according to process which shows the manufacturing method of the silicon carbide semiconductor device in 2nd Embodiment. It is sectional drawing according to process which shows the manufacturing method of the silicon carbide semiconductor device in 2nd Embodiment. It is sectional drawing according to process which shows the manufacturing method of the silicon carbide semiconductor device in 2nd Embodiment. It is sectional drawing according to process which shows the manufacturing method of the silicon carbide semiconductor device in 2nd Embodiment. It is sectional drawing according to process which shows the manufacturing method of the silicon carbide semiconductor device in 2nd Embodiment. It is sectional drawing according to process which shows the manufacturing method of the silicon carbide semiconductor device in 2nd Embodiment. It is sectional drawing according to process which shows the manufacturing method of the silicon carbide semiconductor device in 2nd Embodiment. It is sectional drawing according to process which shows the manufacturing method of the silicon carbide semiconductor device in 2nd Embodiment. It is sectional drawing according to process which shows the manufacturing method of the silicon carbide semiconductor device in 2nd Embodiment. It is sectional drawing according to process which shows the manufacturing method of the silicon carbide semiconductor device in 2nd Embodiment. It is a top view of the silicon carbide semiconductor device in 2nd Embodiment. It is sectional drawing according to process which shows the manufacturing method of the silicon carbide semiconductor device in 3rd Embodiment. It is sectional drawing according to process which shows the manufacturing method of the silicon carbide semiconductor device in 3rd Embodiment. It is sectional drawing according to process which shows the manufacturing method of the silicon carbide semiconductor device in 3rd Embodiment. It is sectional drawing according to process which shows the manufacturing method of the silicon carbide semiconductor device in 3rd Embodiment. It is a figure which shows the capacity | capacitance-voltage characteristic of the silicon carbide semiconductor device in a premise technique. It is a figure which shows the projection range Rp (peak of the implantation depth of an impurity) in each ion implantation voltage, the impurity concentration in the position of a depth of 400 nm, and the Vth shift of a MOS capacitor.

  Hereinafter, embodiments will be described with reference to the accompanying drawings.

  In the present embodiment, terms such as a side surface or a bottom surface are used, but these terms are used for distinguishing each surface for the sake of convenience, and are not related to the actual vertical and horizontal directions.

<First Embodiment>
<Planar gate structure vertical MOSFET>
FIG. 1 is a top view schematically showing a top structure of a silicon carbide semiconductor device according to the present embodiment, specifically, a silicon carbide MOSFET having a switching element having a MOS structure having a cell structure.

  Of the four side surfaces of the MOSFET 40 shown in FIG. 1, an external output gate electrode 15 to which a gate voltage is applied from an external control circuit (not shown) is formed at the center of one side surface. Further, an external output source electrode 10 in which the source electrodes of the unit cells are connected in parallel is formed in a cell array region 20 in which a plurality of unit cells, which are the minimum unit structure of the MOSFET, are arranged in parallel (FIG. Not shown).

  A gate line 15 a connected to the external output gate electrode 15 is formed around the external output source electrode 10. A gate voltage applied to the external output gate electrode 15 is supplied to the gate electrode (not shown) of each unit cell through the external output gate electrode 15 and the gate wiring 15a.

  In normal products, electrodes for temperature sensors and current sensors are often formed on semiconductor elements, but whether or not these electrodes are formed has an effect on the effect of the element described later. It does not affect. In addition, the position and number of the external output gate electrode 15, the shape of the gate wiring 15 a, the shape and number of the external output source electrode 10, and the like may vary depending on the MOSFET. It does not have any influence on the effect of the present apparatus described later.

  FIG. 2 is a top view schematically showing the vicinity of the outermost surface inside the silicon carbide of the silicon carbide MOSFET according to the present embodiment. For simplicity, the interlayer insulating film and the gate electrode are omitted. FIG. 2 corresponds to a top view in the vicinity of the line A-A ′ of FIG. 1.

  A cell array region 20 in which a plurality of unit cells, which are the minimum unit structure of the MOSFET, are arranged in parallel, and a peripheral region (external output gate electrode region) 21 are shown. Here, the cell array region 20 is a region in which a plurality of transistor cells (vertical MOSFET unit cells) are arrayed in a matrix. On the other hand, the peripheral region 21 is a region provided around the cell array region 20 where no transistor cells are formed. In FIG. 2, an oxide film 14 and a gate insulating film 6 are formed between the cell array region 20 and the peripheral region 21. In the peripheral region 21, a gate contact hole 13 is formed, and the whole is covered with the external output gate electrode 15.

  As shown in FIG. 2, each transistor cell includes a p + contact portion 5, a source contact hole 12 formed so as to surround the p + contact portion 5 in plan view, and a source region 3 surrounding the source contact hole 12 in plan view. And a well region 4 surrounding the source region 3 in plan view. Each transistor cell is covered with an external output source electrode 10.

  Here, in FIG. 2, in the cell arrangement region 20, the transistor cells are arranged by 3 × 3 on the left and right and up and down in the drawing. However, the arrangement is not limited to this, and more transistor cells are actually arranged.

  FIG. 3 is a cross-sectional view taken along the line B-B ′ of FIG. 2. 2 and 3, a semiconductor device (MOSFET) includes a silicon carbide (SiC) semiconductor substrate 1, a drift layer 2, a source region 3, a well region 4, and a p + contact portion 5 (well contact region). A gate insulating film 6, a gate electrode 7, a JFET (Junction Field Effect Transistor) region 16 surrounded by the well region 4, an interlayer insulating film 8, a drain electrode 9, an external output source electrode 10, and a back surface. It can be seen that the connection drain electrode 11, the source contact hole 12, the gate contact hole 13, the oxide film 14, the external output gate electrode 15, and the silicide film 18 are provided. A configuration including the gate insulating film 6 and the oxide film 14 is referred to as an “insulating film”.

  Silicon carbide semiconductor substrate 1 is, for example, a high-concentration n-type (hereinafter sometimes simply referred to as n +) semiconductor substrate. Silicon carbide semiconductor substrate 1 is a semiconductor substrate made of silicon carbide and having a wider band gap than silicon. In the present embodiment, the n-type is the first conductivity type.

  On silicon carbide semiconductor substrate 1, drift layer 2, which is a low concentration n-type (hereinafter sometimes simply referred to as n−) semiconductor layer, is formed. Drift layer 2 is formed on silicon carbide semiconductor substrate 1 by, for example, epitaxial growth.

  Focusing on the cell array region 20, a part of the surface of the drift layer 2 includes an n + -type source region 3 (current output region), a p-type well region 4, and a high-concentration p-type (hereinafter, referred to as “cell-type region”). P + contact portions 5) (which may be simply referred to as p +). Here, in this embodiment, the p-type is the second conductivity type.

  The p-type well region 4 is selectively formed on the surface of the drift layer 2 and surrounds the source region 3 in plan view. The depth of the well region 4 from the surface of the drift layer 2 is formed deeper than the depth of the source region 3 from the surface of the drift layer 2.

  The n + type source region 3 is selectively formed on the surface of the well region 4 and surrounds the p + contact portion 5 in plan view. For example, the p + contact portion 5 is formed in the center of the source region 3 in plan view. The p + contact portion 5 is provided to make electrical contact between the external output source electrode 10 and the p-type well region 4.

  In the cell arrangement region 20, the gate insulating film 6 is selectively formed on the drift layer 2. In the peripheral region 21, an oxide film 14 thicker than the gate insulating film 6 is formed on the drift layer 2.

  On the gate insulating film 6 and the oxide film 14 (which can be grasped as the above-described insulating film), a polycrystalline silicon film 71 containing nitrogen and boron, and a polycrystalline silicon film 72 containing boron. A gate electrode 7 is formed. That is, the gate electrode 7 extends from the cell array region 20 to the peripheral region 21 as shown in FIG.

  In this embodiment, the gate electrode 7 is formed so that the nitrogen concentration is higher than the boron concentration at the bottom, that is, near the gate insulating film 6 of the gate electrode 7. In FIG. 3 and subsequent figures, the gate electrode 7 having such a structure is illustrated as a two-layer film. Details will be described later.

  In the following, for simplicity, a region composed of the source region 3, the well region 4, and the p + contact portion 5 may be referred to as SiC regions 3 to 5. Similarly, a region composed of the drift layer 2, the source region 3, the well region 4 and the p + contact portion 5 may be referred to as SiC regions 2 to 5.

An interlayer insulating film 8 made of, for example, a silicon oxide film (SiO ₂ ) is formed so as to cover the gate electrode 7. In the cell arrangement region 20, a source contact hole 12 is opened to make contact between the SiC regions 3 to 5 and the external output source electrode 10. On the other hand, in the peripheral region 21, a gate contact hole 13 is opened to make contact between the gate electrode 7 and the external output gate electrode 15.

In the cell array region 20, an external output source electrode 10 made of, for example, an aluminum (Al) film is formed on the interlayer insulating film 8 so as to fill the source contact hole 12. In the source contact hole 12, a silicide film 18 made of nickel silicide (NiSi ₂ ) is formed between the external output source electrode 10, the n + type source region 3 and the p + contact portion 5. The external output source electrode 10 is electrically connected to the n + type source region 3 and the p + contact portion 5 in the source contact hole 12.

  In contrast, an external output gate electrode 15 made of, for example, an Al film is formed on the interlayer insulating film 8 so as to fill the gate contact hole 13 in the peripheral region 21. The external output gate electrode 15 is electrically connected to the gate electrode 7 in the gate contact hole 13.

  On the back surface of silicon carbide semiconductor substrate 1, drain electrode 9 having a laminated structure made of a metal film and a silicide film is formed (shown in FIG. 3 as a single-layer structure for simplification). In the present embodiment, the metal film of the drain electrode 9 is a Ni film, and the silicide film of the drain electrode 9 is a NiSi film. On the drain electrode 9 (on the lower side in FIG. 3), a back connection drain electrode 11 made of, for example, a Ni / Au laminated film is formed (in FIG. 3, it is illustrated as a single layer structure for simplification. Have been).

  Even when a high voltage is applied between the external output source electrode 10 and the back surface connection drain electrode 11, when no voltage is applied to the gate electrode 7, a channel is formed in the well region 4 immediately below the gate electrode 7. Not. That is, in the case of the voltage application state, the MOSFET is turned off so that electrons do not flow.

  On the other hand, when a high voltage is applied between the external output source electrode 10 and the back surface connection drain electrode 11 and a positive voltage is further applied to the gate electrode 7, a channel is formed above the well region 4 immediately below the gate electrode 7. Is formed. Electrons flow from the source region 3 through a channel region (well region 4), JFET region 16, drift layer 2, silicon carbide semiconductor substrate 1, and drain electrode 9. In other words, the MOSFET is in an on state in which electrons flow when the voltage is applied to the gate electrode 7.

  In this way, the on / off state of the current can be controlled by the gate voltage applied to the gate electrode 7.

<Manufacturing Method of Planar Gate Structure Vertical MOSFET>
Next, the manufacturing method of the semiconductor device according to this embodiment will be described with reference to cross-sectional views according to processes shown in FIGS.

  First, steps required until the structure shown in FIG. 4 is formed will be described.

  For example, n type drift layer 2 is epitaxially grown on the surface of silicon carbide semiconductor substrate 1 by a CVD method. As silicon carbide semiconductor substrate 1, for example, an n-type low-resistance silicon carbide substrate having a 4H polytype is used. Silicon carbide semiconductor substrate 1 is, for example, a substrate whose main surface has an off angle of 4 ° in the <11-20> direction from the (0001) Si surface.

In the present embodiment, the concentration of the n-type impurity in the drift layer 2 is selected in the range of 1 × 10 ¹⁵ to 1 × 10 ¹⁷ cm ⁻³ . The thickness dimension of the drift layer 2 is selected in the range of 5 to 50 μm. Drift layer 2 is a semiconductor layer made of silicon carbide.

  In cell array region 20, p-type well region 4 is selectively formed in the surface of drift layer 2. Further, an n + type source region 3 and a p + contact portion 5 which is a p type well contact region are selectively formed in the surface of the well region 4.

Here, the n-type region is formed by implanting nitrogen (N) ions, for example, and the p-type region is formed by implanting Al ions, for example. In this embodiment, the acceleration voltage of nitrogen ions is selected within a range of 50 to 200 kV. The n-type impurity ion implantation depth is shallower than the thickness of the well region 4. In the present embodiment, the concentration of the n-type impurity ion-implanted, that is, the n-type impurity concentration of the source region 3 is selected within the range of 1 × 10 ¹⁸ to 1 × 10 ²¹ cm ⁻³ , and the acceleration voltage of Al ions is selected. Is selected from the range of 100 to 500 kV.

In this embodiment, the concentration of the ion-implanted p-type impurity, that is, the p-type impurity concentration in the well region 4 is in the range of 1 × 10 ^{17 to} 5 × 10 ¹⁷ cm ⁻³ , and the n-type of the drift layer 2 It is assumed that it is higher than the impurity concentration. The well region 4 may be formed by one ion implantation, or may be formed by performing ion implantation several times while changing the acceleration voltage.

In the present embodiment, the acceleration voltage of Al ions in the p + contact portion 5 is selected within the range of 100 to 200 kV. The depth of ion implantation of the p-type impurity is shallower than the thickness dimension of the well region 4. In the present embodiment, the concentration of the p-type impurity to be ion-implanted, that is, the p-type impurity concentration of the p + contact portion 5 is selected within the range of 1 × 10 ¹⁸ to 1 × 10 ²¹ cm ⁻³ . The n-type region and the p-type region are activated by performing high-temperature annealing at 1500 ° C. or higher. A region surrounded by the well region 4 is a JFET region 16.

Next, an oxide film (SiO ₂ ) having a thickness of about 1 μm is formed on the drift layer 2 by, eg, CVD. Thereafter, the oxide film on the cell array region 20 side is removed by photolithography and etching. As a result, an oxide film 14 is formed on the drift layer 2 in the peripheral region 21.

Thereafter, as shown in FIG. 5, the upper portions of SiC regions 2 to 5 of cell array region 20 are oxidized at a temperature of about 1000 ° C. in an atmosphere containing oxygen and water vapor. Through such steps, a gate insulating film 6 of a thermal oxide film (SiO ₂ ) is formed on the SiC regions 2 to 5 in the cell arrangement region 20. The thickness of the gate insulating film is, for example, 50 nm. The step of forming the oxide film 14 and the gate insulating film 6 is a step of forming an “insulating film” on the upper surface of the drift layer 2 in the cell array region 20 and the peripheral region 21.

  In the present embodiment, the gate insulating film 6 is described as being a thermal oxide film, but is not limited thereto. The gate insulating film 6 may be an oxide film formed by a CVD method or a laminated film of an oxide film formed by a CVD method with a thermal oxide film.

  Next, a single-layer polycrystalline silicon film 73 containing no impurities is formed on the insulating film 6 and the oxide film 14 by CVD. The thickness of the polycrystalline silicon film 73 is selected from a range of 250 to 600 nm. In this embodiment, the thickness is 500 nm.

Next, nitrogen ions 51 are implanted into the polycrystalline silicon film 73. The acceleration voltage of the nitrogen ions 51 has a peak below the polycrystalline silicon film 73 (near the gate insulating film 6) and is selected so as not to be implanted into the SiC regions 2-5. In this embodiment, it was set to 80 kV. The ion implantation amount is preferably in the range of 5 × 10 ¹⁴ to 1 × 10 ¹⁶ / cm ² . In this embodiment, it was set to 4 × 10 ¹⁵ / cm ² . Through the above steps, the structure shown in FIG. 5 is formed.

Further, boron ions 52 (second conductivity type impurities) are implanted into the polycrystalline silicon film 73 into which the nitrogen ions 51 have been implanted. The acceleration voltage of the boron ions 52 has a peak inside the polycrystalline silicon film 73, and is selected so that the boron concentration is lower than the nitrogen concentration below the polycrystalline silicon film 73 (on the side in contact with the gate insulating film 6). It is. In this embodiment, it was set to 30 kV. The ion implantation amount is preferably in the range of 1 × 10 ¹⁵ to 2 × 10 ¹⁶ / cm ² . In this embodiment, it is set to 5 × 10 ¹⁵ / cm ² . Through the above steps, the structure shown in FIG. 6 is formed.

  As described above, the polycrystalline silicon film 73 contains nitrogen and boron, and the concentration of nitrogen is higher than the concentration of boron at the lower portion of the polycrystalline silicon film 73, that is, at the position in contact with the gate insulating film 6.

  As shown in FIG. 7, this is expressed as a gate electrode 7 composed of a polycrystalline silicon film 71 containing nitrogen and boron and a polycrystalline silicon film 72 containing boron. As is clear from the explanation in FIGS. 5 and 6, the gate electrode 7 is not formed by laminating the polycrystalline silicon film 73 twice or more.

  Next, photolithography and etching are performed on the gate electrode 7. Thereby, as shown in FIG. 8, the gate electrode 7 existing above the source region 3 and above the p + contact portion 5 is removed, and the gate electrode 7 is formed on the well region 4, the JFET region 16 and the peripheral region 21. Is formed.

  Next, an oxide film having a thickness of 1 μm is formed on the entire surface of the substrate by using the CVD method to form an interlayer insulating film 8 (FIG. 9).

  Subsequently, as shown in FIG. 10, the source contact hole 12 is formed in a part of the source region 3 in the cell array region 20 and the upper part of the p + contact portion 5 by photolithography and RIE (Reactive Ion Etching) etching. It is formed. By this etching, a part of the source region 3 and the p + contact part 5 are exposed from the bottom surface of the source contact hole 12.

  Next, as shown in FIG. 11, a Ni (nickel) film 17 is formed on the entire surface of the substrate. Further, the Ni film 17 is formed by, for example, a sputtering method. The film thickness of the Ni film 17 is, for example, about 50 nm.

Thereafter, a first annealing treatment is performed on the structure shown in FIG. Through this process, as shown in FIG. 12, a silicide film 18 (NiSi ₂ film in this embodiment) is formed on the bottom surface of the source contact hole 12 on the source region 3 and the p + contact portion 5. .

The first annealing treatment is performed at a temperature of 300 to 800 ° C. by, for example, an RTA (Rapid Thermal Annealing) method. By heating at the temperature, Ni of the Ni film 17 reacts with SiC constituting the p + contact portion 5 and the source region 3 in contact with the Ni film 17 to form a silicide film 18 (NiSi ₂ film).

After being silicide film 18 (NiSi ₂ film) is formed, for example, an acid-based chemical solution containing sulfuric acid and hydrochloric acid, the silicide film 18 (NiSi ₂ film) washing the formed structure. By the cleaning, the Ni film 17 that has not been reacted in the silicidation reaction is removed. FIG. 13 shows the state after the unreacted Ni film 17 is removed.

  Next, as shown in FIG. 14, a gate contact hole 13 is formed above the gate electrode 7 in the peripheral region 21 by photolithography and RIE (Reactive Ion Etching) etching. By the etching, the gate electrode 7 is exposed from the bottom surface of the gate contact hole 13.

  Thereafter, drain electrode 9 is formed on the back surface of silicon carbide semiconductor substrate 1 (see FIG. 14). The drain electrode 9 is formed by the following procedure.

  First, a sputtering method is performed on the back surface of the silicon carbide semiconductor substrate 1 to form a Ni film having a thickness of 300 nm. Next, a second annealing process at 1000 ° C. is performed by, for example, the RTA method.

As described above, in this embodiment, after the unreacted Ni film 17 is removed, the second annealing process at a temperature higher than the temperature of the first annealing process (300 to 800 ° C.) is performed. The time for the second annealing treatment is preferably shorter. This is because a shorter processing time can suppress boron diffusion. In the present embodiment, the second annealing process is performed for 30 seconds. Thereby, the contact resistance of the silicide film 18 (NiSi ₂ film) in the source contact hole 12 can be further reduced.

Further, the Ni film formed on the back surface of the silicon carbide semiconductor substrate 1 reacts with the back surface of the silicon carbide semiconductor substrate 1 to form a NiSi ₂ film at the same time, and a low resistance ohmic contact is realized between them. . Thus, drain electrode 9 made of the Ni film and the NiSi ₂ film is formed on the back surface of silicon carbide semiconductor substrate 1 (see FIG. 14).

  Next, an electrode film is formed on interlayer insulating film 8 so as to fill source contact hole 12 and gate contact hole 13. As the electrode film, for example, an Al film having a film thickness of 3 μm can be adopted, and it is formed, for example, by sputtering.

  Thereafter, photolithography and etching are performed on the electrode film. As a result, the electrode film is patterned to form the external output source electrode 10 and the external output gate electrode 15 as shown in FIG.

Here, the external output source electrode 10 and the external output gate electrode 15 are electrically separated by the patterning. The external output source electrode 10 is formed in the cell array region 20 and is electrically connected to the upper portion of the source region 3 and the upper portion of the p + contact portion 5 through the silicide film 18 (NiSi ₂ film). In contrast, the external output gate electrode 15 is formed in the peripheral region 21 and is electrically connected to the gate electrode 7.

  Finally, the back surface connection drain electrode 11 is formed on the drain electrode 9 by sputtering or the like. For example, a gold (Au) film having a film thickness of 150 nm can be used for the back connection drain electrode 11. In this manner, the silicon carbide semiconductor device shown in FIG. 3 is completed.

  As described above, in the silicon carbide semiconductor device according to the present embodiment, boron, which is a p-type impurity, is introduced into the gate electrode 7, and therefore, an n-type gate electrode doped with phosphorus, which is a normal n-type impurity. The threshold voltage (Vth) is higher than that of the vertical MOSFET having the.

  Since the p-type impurity concentration of the well region 4 is not increased in order to increase the threshold voltage (Vth), the on-resistance is not increased. Furthermore, the gate electrode 7 contains nitrogen and boron, and the concentration of nitrogen is higher than the concentration of boron below the gate electrode 7. Therefore, the diffusion of boron into the gate insulating film 6 by the heat treatment in the manufacturing process after the formation of the gate electrode 7, that is, the annealing process (heating at 300 to 1000 ° C.) for forming the silicide film 18 and the drain electrode 9, is caused by nitrogen. It is suppressed.

  In order to investigate the effect of introducing nitrogen, evaluation was performed with a MOS capacitor. In the same process as the MOSFET, a MOS capacitor having the same structure as described above was prepared, and its hysteresis was evaluated.

  FIG. 32 is a diagram showing a measurement result (example) of CV (capacitance-voltage) characteristics of a MOS capacitor including the gate electrode 7 not containing nitrogen. In FIG. 30, the vertical axis represents capacity (arbitrary scale), and the horizontal axis represents voltage (V).

  When the gate voltage sweep direction (indicated by a dotted arrow in the figure) is changed, a hysteresis phenomenon occurs. A difference in gate voltage showing the same capacitance value, which changes depending on the sweep direction, is used as an index of the hysteresis phenomenon as a Vth shift.

FIG. 33 shows a projection range Rp (impurity implantation depth peak) at each implantation voltage of nitrogen (N), boron (B), and BF ₂ , impurity concentration at a depth of 400 nm, and Vth of the MOS capacitor. It is a figure which shows a shift.

As shown in FIG. 33, nitrogen is implanted at 4 × 10 ¹⁵ / cm ² at an acceleration voltage of 80 kV. The injection amounts of B and BF ₂ are both 5 × 10 ¹⁵ / cm ² .

  As shown in FIG. 33, when the ion implantation species is B, the amount of B implanted is large even if the projection range Rp is smaller than the projection range Rp when nitrogen is used. The boron concentration in the vicinity, that is, the lower portion of the gate electrode 7 may be higher than the nitrogen concentration.

  When boron is implanted at 50 kV, the concentration is equal to the concentration of nitrogen when nitrogen is implanted at 80 kV at a depth of 400 nm. Generally, when the depth exceeds 400 nm, the concentration of boron becomes higher. In this case, it can be seen that a hysteresis phenomenon occurs. This is because even if the projected range Rp of boron is smaller than the projected range Rp of nitrogen, the boron concentration is higher than the nitrogen concentration under the gate electrode 7 because of the large amount of boron implanted.

  It can be seen that the hysteresis phenomenon can be sufficiently suppressed by making the boron concentration below the nitrogen concentration below the gate electrode 7.

  In this embodiment, since the conductivity type of the gate electrode is p-type, the threshold voltage (Vth) of the MOSFET can be increased by 2 V compared to the case of the n-type gate electrode.

  Further, since the concentration of nitrogen in the gate electrode near the gate insulating film is higher than the concentration of B, diffusion of B into the gate insulating film is prevented. Therefore, the hysteresis phenomenon of the MOSFET is suppressed.

  Furthermore, since the p-type gate electrode can be formed by two ion implantations, the number of manufacturing steps is smaller than when the gate electrode is multilayered, and the manufacturing cost can be reduced.

Although a thermal oxide film is used as the gate insulating film 6 in this embodiment, the concentration of nitrogen in the vicinity of the gate insulating film in the gate electrode is not higher than the concentration of B even if a SiO ₂ film formed by CVD is used. Hysteresis occurs. This is because the CVD method SiO ₂ film has defects as much as the thermal oxide film, and the heat treatment temperature after forming the gate electrode is 1000 ° C., and the heat treatment temperature in the MOSFET manufacturing process using Si as the semiconductor This is because it is expensive.

  In Patent Documents 1 to 4, as in this embodiment, the nitrogen concentration in the vicinity of the gate insulating film in the gate electrode cannot be made higher than the B concentration by ion implantation because the gate electrode (polycrystalline silicon) is about 50 nm. This is because it is thin.

Since the implantation amount is large, it is assumed that ion implantation is performed at 20 kV, which is the minimum acceleration voltage applicable to mass production. Then, when Rp + 5ΔRp is obtained from the projected range Rp of B ions and BF ₂ ions and its dispersion ΔRp, it is 208 nm for B ions and 53 nm for BF ₂ ions. This penetrates the gate electrode and reaches the gate insulating film.

  Here, Rp + 5ΔRp is a depth that includes 99.9999713% of the implanted ions, and it can be assumed that ions do not exist at a depth substantially equal to or higher than Rp + 5ΔRp.

For this reason, in Patent Documents 1 to 4, it is not possible to form a p-type gate electrode by performing ion implantation twice for a single gate electrode. Even if the projected range Rp of boron is set to be smaller than the projected range Rp of nitrogen, since the gate electrode is thin, the concentration of nitrogen in the vicinity of the gate insulating film cannot be made higher than the concentration of boron. The ion implantation can be performed even at an acceleration voltage of 10 kV. However, if the acceleration voltage is small, the beam current becomes small, and a long time is required for high concentration implantation such as 5 × 10 ¹⁵ to 1 × 10 ¹⁶ / cm ^2. Therefore, it cannot be applied to mass production.

<Lower film thickness of polycrystalline silicon film>
In this embodiment mode, the acceleration voltage, the implantation amount, and the thickness of the gate electrode may be determined under the ion implantation conditions in which the nitrogen concentration in the vicinity of the gate insulating film is higher than the boron concentration. For example, when the film thickness of polycrystalline silicon (gate electrode) is 300 nm, if the acceleration voltage of nitrogen ions is set to 50 kV and the acceleration voltage of BF ₂ is set to 20 kV, Rp and Rp + 5ΔRp of nitrogen become 112 and 297 nm, respectively. Since BF ₂ Rp and Rp + 5ΔRp are 15 and 53 nm, respectively, the concentration of nitrogen in the vicinity of the gate insulating film is higher than the concentration of boron. When the polysilicon film thickness is 250 nm and the nitrogen ion acceleration voltage is set to 40 kV and the BF ₂ acceleration voltage is set to 20 kV, the nitrogen Rp and Rp + 5ΔRp are 89 and 245 nm, respectively. Since BF ₂ Rp and Rp + 5ΔRp are 15 and 53 nm, respectively, the concentration of nitrogen in the vicinity of the gate insulating film is higher than the concentration of boron. In any case, since Rp + 5ΔRp of nitrogen and BF ₂ is smaller than the thickness of the polycrystalline silicon, nitrogen and B are not implanted into the gate insulating film or the SiC region below the gate insulating film. Considering an acceleration voltage of 20 kV or more suitable for mass production as described above, the lower limit of the thickness of the polycrystalline silicon film of this embodiment is 250 nm.

<Effect>
According to the present embodiment, a silicon carbide semiconductor device includes a first conductivity type silicon carbide semiconductor substrate 1, a first conductivity type drift layer 2, a second conductivity type well region 4, and a first conductivity type. A source region 3, a gate insulating film 6, and a gate electrode 7 are provided.

  Drift layer 2 is formed on the surface of silicon carbide semiconductor substrate 1.

  The well region 4 is formed in the surface layer portion of the drift layer 2.

  The source region 3 is formed in a part of the surface layer portion of the well region 4.

  The gate insulating film 6 is provided on the surface of a part of the well region 4, a part of the drift layer 2, and a part of the source region 3.

  The gate electrode 7 is provided on the gate insulating film 6, and is provided on part of the well region 4, part of the drift layer 2, and part of the source region 3 via the gate insulating film 6.

  The gate electrode 7 is made of a conductive layer doped with an impurity of the second conductivity type. The gate electrode 7 is further doped with nitrogen in the conductive layer. Further, in the gate electrode 7, the nitrogen concentration is higher than the impurity concentration on the side of the gate electrode 7 in contact with the gate insulating film 6 (polycrystalline silicon film 71).

  According to such a configuration, since nitrogen is more doped than the second conductivity type impurity below the gate electrode 7 (polycrystalline silicon film 71), the second conductivity type impurity diffuses into the gate insulating film 6. Can be suppressed. Therefore, a complicated gate electrode structure such as a two-layer structure is not required, and the occurrence of a hysteresis phenomenon can be suppressed.

  Further, since the gate electrode 7 is of the second conductivity type, the threshold voltage (Vth) can be increased without increasing the on-resistance.

  Further, according to the present embodiment, the gate electrode 7 has a thickness of 250 nm or more.

  According to such a configuration, since the gate electrode 7 has a sufficient thickness, a plurality of ion implantations are performed on the gate electrode 7 at an appropriate acceleration voltage, and the upper layer of the gate electrode 7 (polycrystalline silicon film 72). ) And the ion concentration in the lower layer (polycrystalline silicon film 71) can be controlled.

  Further, according to the present embodiment, the gate electrode 7 is made of polycrystalline silicon.

  According to such a configuration, it is possible to form the gate electrode 7 that has been mass-produced at low cost.

  Further, according to the present embodiment, the method for manufacturing a silicon carbide semiconductor device includes (a) a step of forming the first conductivity type drift layer 2 and (b) a step of forming the second conductivity type well region 4. (C) a step of forming a source region 3 of the first conductivity type, (d) a step of forming a gate insulating film 6, (e) a step of forming a polycrystalline silicon film 73 as a conductive layer, (F) a step of implanting nitrogen ions 51 into the polycrystalline silicon film 73; and (g) a step of implanting second conductivity type impurity (boron ions 52) ions into the polycrystalline silicon film 73.

  Step (a) is a step of forming the first conductivity type drift layer 2 by stacking on the surface of the first conductivity type silicon carbide semiconductor substrate 1.

  Step (b) is a step of forming the second conductivity type well region 4 in the surface layer portion of the drift layer 2.

  Step (c) is a step of forming the source region 3 of the first conductivity type in a part of the surface layer portion of the well region 4.

  Step (d) is a step of forming a gate insulating film 6 on the surface of part of the well region 4, part of the drift layer 2 and part of the source region 3.

  Step (e) is a step of forming a polycrystalline silicon film 73 on the surface of the gate insulating film 6.

  Then, on the side of the polycrystalline silicon film 73 in contact with the gate insulating film 6 (polycrystalline silicon film 71), the concentration of nitrogen is higher than the concentration of impurities.

  According to such a configuration, since nitrogen is more doped than the second conductivity type impurity below the gate electrode 7 (polycrystalline silicon film 71), the second conductivity type impurity diffuses into the gate insulating film 6. Can be suppressed. Therefore, a complicated gate electrode structure such as a two-layer structure is not required, and the occurrence of a hysteresis phenomenon can be suppressed.

  In addition, since nitrogen and second conductivity type impurities are introduced by ion implantation, it can be manufactured at a relatively low manufacturing cost.

Second Embodiment
<Vertical MOSFET with trench gate structure>
In the MOSFET using SiC as the substrate in the first embodiment, the drain current flows from the source region 3 through the channel portion (portion immediately below the gate electrode 7 of the well region 4 in FIG. 3) and the JFET region 16 (electron flow). Represents the flow).

  Since the impurity concentration of the JFET region 16 is low, the resistance is high. In order to reduce this on-resistance, that is, to increase the drain current, there is a so-called trench structure MOSFET in which the JFET region 16 has a gate electrode structure.

  In the present embodiment, a silicon carbide semiconductor device using a trench structure as a gate electrode and a manufacturing method thereof will be described. In the present embodiment, portions that are the same as or equivalent to those in the first embodiment will not be described for the sake of brevity.

  FIG. 26 is a cross-sectional view of a vertical MOSFET whose gate electrode has a trench structure, and FIG. 27 is a plan view of the vertical MOSFET whose gate electrode has a trench structure. A cross-sectional view taken along line C-C ′ of FIG. 27 corresponds to FIG. 26.

  In FIG. 26, gate insulating film 6 is formed perpendicular to the thickness direction of silicon carbide semiconductor substrate 1 through well region 4. The gate insulating film 6 is in contact with the source region 3 and the well region 4, and a gate electrode 7 is formed inside thereof.

  The gate electrode 7 is made of polycrystalline silicon doped with p-type impurities. Nitrogen is also introduced into the polycrystalline silicon, and the concentration of nitrogen in the vicinity of the gate insulating film in the polycrystalline silicon is set higher than the concentration of boron.

  The gate electrode 7 is formed deeper than the well region 4. An n-type source region 3 and a p-type p + contact portion 5 are provided above the well region 4.

  An interlayer insulating film 8 is provided on the gate electrode 7 to electrically separate the external output source electrode 10 and the gate electrode 7.

  The external output source electrode 10 is formed on the surface of the source region 3 and the p + contact portion 5 where the interlayer insulating film 8 is not formed. External output source electrode 10 electrically connects part of source region 3 and p + contact portion 5.

  In the source region 3 and the p + contact portion 5, n-type and p-type impurities are introduced at high concentrations, respectively, in order to reduce the contact resistance with the external output source electrode 10.

  Drain electrode 9 is formed on the surface portion on the opposite side to the surface portion on one side in the thickness direction of silicon carbide semiconductor substrate 1, that is, on the surface portion on the other side (back side) in the thickness direction of silicon carbide semiconductor substrate 1.

  In the MOSFET having a trench structure, a region of the well region 4 that faces the gate electrode 7 through the gate insulating film 6 and in which an inversion layer is formed during the on operation is referred to as a channel portion. Unlike the planar structure, the channel portion is formed in a direction perpendicular to the surface of silicon carbide semiconductor substrate 1. A trench-structure MOSFET does not have a JFET portion that exists in a planar-structure MOSFET. The JFET portion is composed of an n-type SIC having a low concentration and has a high resistance. In a trench structure MOSFET, there is no JFET portion having a high resistance, so that the on-resistance can be made lower than in a planar structure MOSFET. Further, since the gate electrode 7 contains a p-type impurity, the threshold voltage (Vth) of the MOSFET can be kept high.

<Trench gate structure vertical MOSFET manufacturing method>
Next, a method for manufacturing a vertical MOSFET having a trench gate structure will be described.

  First, the drift layer 2, the source region 3, the well region 4, the p + contact portion 5, and the oxide film 14 are manufactured by the same process as that shown in the first embodiment.

  Next, as shown in FIG. 16, the drift between the well regions 4 (the portion of the JFET region 16 in FIG. 3 of the first embodiment, that is, the well region 4 is not formed) by photolithography and etching. The drift layer 2 on the surface of the layer 2 is removed, and the trench 19 is formed. The depth of the trench 19 is set to be deeper than that of the well region 4. The width of the trench 19 (the length indicated by D in FIG. 16) is, for example, 0.6 μm.

Next, as shown in FIG. 17, the surface of the cell array region 20 is oxidized at a temperature of about 1000 ° C. in an atmosphere containing oxygen and water vapor. Through such a process, a gate insulating film 6 of a thermal oxide film (SiO ₂ ) is formed on the bottom and side walls (inner walls) of the well region 4, the source region 3, the p + contact portion 5 and the trench 19 in the cell arrangement region 20. Is done. The thickness of the gate insulating film is, for example, 50 nm.

Next, nitrogen ions 53 are obliquely implanted into the gate insulating film 6 in the structure shown in FIG. 17 (see FIG. 18). The ion concentration of the nitrogen ions 53 has a peak near the surface of the gate insulating film 6 so that it is not implanted into the well region 4. For example, an ion implantation amount in the range of 1 × 10 ¹⁴ to 1 × 10 ¹⁶ / cm ² is desirable. In this embodiment, it is 1 × 10 ¹⁵ / cm ² . In this embodiment, the acceleration voltage of the nitrogen ions 53 is 20 kV, and the implantation angle E of the nitrogen ions 53 is 30 °.

  The oblique ion implantation process will be described in detail.

  Silicon carbide semiconductor substrate 1 is tilted to ion implantation angle E. In FIG. 18, the beam of nitrogen ions 53 is tilted and displayed, but actually the silicon carbide semiconductor substrate 1 is tilted to an angle E. The acceleration voltage of the implanted ions is selected from the range of 10 to 50 kV.

  FIG. 27 is a top view schematically showing the vicinity of the outermost surface inside silicon carbide of the silicon carbide MOSFET. As shown in FIG. 27, the channel (well region 4 in contact with the gate electrode 7 through the gate insulating film 6) exists on the four sides of each unit cell square. Therefore, oblique ion implantation must be performed on each of the four sides of the square.

  Specifically, as shown by the solid arrow in FIG. 27, after performing implantation 57 in the lower right corner of the square, the silicon carbide semiconductor substrate 1 is rotated by 90 ° to perform implantation 54 in the upper right oblique direction. . Similarly, silicon carbide semiconductor substrate 1 is rotated by 90 °, and upper left oblique implantation 55 and left oblique lower implantation 56 are performed. With these four implantations, nitrogen ions are formed on all four sides of the square. In FIG. 18, only the obliquely lower right implantation (beam of nitrogen ions 53) shown in FIG. 27 is shown. Further, when nitrogen ions are implanted, the external output source electrode 10 and the external output gate electrode 15 shown in FIG. 27 do not exist.

  This nitrogen ion implantation is not performed at the bottom of the trench 19. That is, nitrogen ions 53 are implanted into the gate insulating film 6 formed on the sidewall of the trench 19. Strictly speaking, if the depth F of the trench 19 (not shown) = the width D of the trench 19 / (Tan (implantation angle) × sin (45)) or more than F shown in FIG. Is not injected.

  It is necessary to determine the width D of the trench 19 and the depth F of the trench 19 by the above formula. In this embodiment, since the width D is 0.6 μm and the implantation angle is 30 °, the depth F is set to 1.47 μm or more.

  In this embodiment, the nitrogen implantation angle was 30 ° and the acceleration voltage was 20 kV. At this time, the projection range Rp and Rp + 5 × ΔRp on the gate insulating film 6 is such that the projection range Rp is 15.3 nm and Rp + 5 × ΔRp is 47.7 nm (depth of vertical implantation × sin ( 30) × cos (45)). On the surface, the projection range Rp is 37.6 nm, and Rp + 5 × ΔRp is 116.8 nm (vertical implantation depth × cos (30)).

  Since the thickness of the gate insulating film 6 on the side wall is 50 nm, the peak of implantation exists on the surface side of the gate insulating film 6 (on the opposite side of the well region 4). Further, no ions are implanted into the well region 4 on the side wall. As described above, ions are not implanted into the bottom surface of the trench. Ions are slightly implanted into the source region 3 and the p + contact portion 5 on the surface. However, since high concentration n-type impurities or p-type impurities are introduced into the source region 3 and the p + contact portion 5, there is a problem. Don't be.

  As shown by the dotted arrow in FIG. 27, when nitrogen ion implantation is obliquely implanted in a direction perpendicular to or parallel to the side of the square (implantation 57a, implantation 54a, implantation 55a, and implantation 56a), Nitrogen is implanted into the bottom surface, which is not preferable because the concentration of the drift layer 2 on the bottom surface increases. In this case, after the trench 19 is formed, it is necessary to vertically implant the same amount of p-type impurity as that of the oblique ion implantation of nitrogen to offset the increased amount of n-type impurity at the bottom of the trench 19.

  Subsequently, as shown in FIG. 19, a polycrystalline silicon film 73 which is a conductive layer is formed on the gate insulating film 6 and the oxide film 14 by the CVD method.

  The thickness of the polycrystalline silicon film 73 is set so as to completely fill the trench 19. In this embodiment, the thickness is 0.4 μm. In this case, since the width D of the trench 19 is 0.6 μm, the trench 19 is completely filled with the polycrystalline silicon film 73, and on the surface, that is, the source region 3, the p + contact portion 5 and the oxide film 14, A polycrystalline silicon film 73 is deposited with a thickness of 0.4 μm.

  Next, as shown in FIG. 20, boron (second conductivity type impurity) is implanted into the polycrystalline silicon film 73. The acceleration voltage of the boron ions 58 has a peak inside the polycrystalline silicon film 73 and is selected so as not to reach the source region 3 and the p + contact portion 5. In this embodiment, it is 40 kV. The implantation angle of boron ions 58 is 0 ° (vertical).

In this case, the projection ranges Rp and Rp + 5 × ΔRp to the polycrystalline silicon film 73 have a projection range Rp of 130.2 nm and Rp + 5 × ΔRp of 351.7 nm. Since the thickness of the polycrystalline silicon film 73 is 0.4 μm (400 nm), boron ions are not implanted into the polycrystalline silicon film 73 inside the trench 19. The injection amount is desirably in the range of 1 × 10 ¹⁵ to 2 × 10 ¹⁶ / cm ² . In this embodiment, it is set to 5 × 10 ¹⁵ / cm ² .

  Thereafter, although not shown, heat treatment is performed for 30 minutes at a temperature of 700 to 900 ° C. in a nitrogen atmosphere.

  Nitrogen implanted into the gate insulating film 6 by this heat treatment diffuses into the polycrystalline silicon film 73. Boron ions diffuse into the polycrystalline silicon film 73 in the trench 19 from the surface side. The temperature and time of this heat treatment may be determined so that the nitrogen and boron are diffused into the polycrystalline silicon film 73 in the trench 19.

  Next, as shown in FIG. 21, a resist 30 is formed on the peripheral region 21 by photolithography. Thereafter, the polycrystalline silicon film 73 on the cell array region 20 is removed by an etching process (excluding the polycrystalline silicon film 73 formed in the trench 19).

  FIG. 22 shows a structure in which the polycrystalline silicon film 73 except the inside of the trench 19 is removed by the above process. In FIG. 22, a gate electrode 7 composed of a polycrystalline silicon film 74 containing nitrogen and boron and a polycrystalline silicon film 75 containing boron is represented.

  As apparent from the description of FIGS. 18 to 21, the gate electrode 7 is not formed by laminating the polycrystalline silicon film 73 twice or more. Through the steps so far, the polycrystalline silicon film 74 in the vicinity of the gate insulating film 6 contains more nitrogen than boron.

  After this step, the MOSFET is manufactured by the same steps as those shown in the first embodiment. Specifically, an interlayer insulating film 8 is formed on the entire surface of the substrate (FIG. 23), and further, a part of the source region 3 of the cell array region 20 and the upper portion of the p + contact portion 5 are formed by photolithography and RIE etching. Then, source contact holes 12 are formed (FIG. 24).

Next, a Ni film is formed on the entire surface of the substrate by sputtering, and a first annealing process is performed. The unreacted Ni film is removed with an acid chemical solution containing sulfuric acid and hydrochloric acid. As a result, as shown in FIG. 24, a silicide film 18 (NiSi ₂ film) is formed on the upper portion of the source region 3 and the upper portion of the p + contact portion 5 exposed from the bottom surface of the source contact hole 12.

  Thereafter, as shown in FIG. 25, a gate contact hole 13 is formed on the gate electrode 7 in the peripheral region 21. Subsequently, drain electrode 9 is formed on the back surface of silicon carbide semiconductor substrate 1. A second annealing process at about 1000 ° C. is performed by the RTA method. Even after the second annealing treatment, the polycrystalline silicon film 74 in the vicinity of the gate insulating film 6 contains more nitrogen than boron. This is because nitrogen suppressed the diffusion of boron.

First, a sputtering method is performed on the back surface of the silicon carbide semiconductor substrate 1 to form a Ni film having a thickness of, for example, 300 nm. Next, for example, a second annealing process at about 1000 ° C. is performed by the RTA method. For the above-described reason, it is preferable that the second annealing process be short. The contact resistance of the silicide film 18 (NiSi ₂ film) in the source contact hole 12 can be further reduced by the second annealing treatment. Further, the Ni film formed on the back surface of the silicon carbide semiconductor substrate 1 reacts with the back surface of the silicon carbide semiconductor substrate 1 to form a NiSi ₂ film at the same time, and a low resistance ohmic contact is realized between them. . Thus, drain electrode 9 made of the Ni film and the NiSi ₂ film is formed on the back surface of silicon carbide semiconductor substrate 1 (FIG. 25).

  Finally, an Al film having a thickness of 3 μm is formed on the interlayer insulating film 8 so as to fill the source contact hole 12 and the gate contact hole 13 (see FIG. 26). Thereafter, photolithography and etching are performed on the Al film.

  Thereby, the electrode film is patterned, and the external output source electrode 10 and the external output gate electrode 15 are formed. A gold (Au) film having a film thickness of 150 nm is formed on the drain electrode 9 by sputtering to form the back connection drain electrode 11.

Here, the external output source electrode 10 and the external output gate electrode 15 are electrically separated by the patterning. The external output source electrode 10 is formed in the cell array region 20 and is electrically connected to the upper portion of the source region 3 and the upper portion of the p + contact portion 5 through the silicide film 18 (NiSi ₂ film). In contrast, the external output gate electrode 15 is formed in the peripheral region 21 and is electrically connected to the gate electrode 7. Through these steps, a trench gate structure vertical MOSFET is manufactured.

  In the trench gate structure vertical MOSFET according to the present embodiment, since the gate electrode has a p-type conductivity, the threshold voltage (Vth) of the MOSFET can be increased by 2 V compared to the n-type gate electrode.

  Since the nitrogen concentration in the vicinity of the gate insulating film in the gate electrode is made higher than the B concentration at the time after the manufacturing process is completed, diffusion of B into the gate insulating film can be prevented, and the hysteresis phenomenon of the MOSFET is suppressed. .

  Since the p-type gate electrode can be formed by two ion implantations, the number of manufacturing steps is less than that in the case where the gate electrode is multilayered, and the manufacturing cost can be suppressed.

  Furthermore, since the trench gate structure is adopted, the on-resistance can be reduced as compared with the planar gate structure vertical MOSFET shown in the first embodiment. Note that nitrogen is not implanted into the gate insulating film 6 on the bottom surface of the trench 19. For this reason, boron slightly diffuses into the gate insulating film 6 on the bottom surface of the trench 19. However, since no channel is formed on the bottom surface of the trench 19, the operation of the vertical MOSFET having a trench gate structure is not affected.

<Effect>
According to the present embodiment, the trench 19 is formed on the surface of the drift layer 2 where the well region 4 is not formed, and the gate insulating film 6 includes a part of the well region 4 including the inner wall of the trench 19. A part and part of the source region 3 are provided on the surface, and the gate electrode 7 is provided in the trench 19.

  According to such a configuration, since the trench gate structure is adopted, the on-resistance can be reduced.

  Further, according to the present embodiment, the method for manufacturing a silicon carbide semiconductor device includes (a) a step of forming the first conductivity type drift layer 2 and (b) a step of forming the second conductivity type well region 4. (C) a step of forming the source region 3 of the first conductivity type, (d) a step of forming the trench 19, (e) a step of forming the gate insulating film 6, and (f) a sidewall of the trench 19 A step of implanting nitrogen ions 53 into the formed gate insulating film 6; (g) a step of forming a polycrystalline silicon film 73 as a conductive layer in the trench 19; A step of implanting second conductivity type impurities (boron ions 58); and (i) a step of diffusing nitrogen implanted into the gate insulating film 6 and impurities implanted into the polycrystalline silicon film 73. .

  Step (a) is a step of forming the first conductivity type drift layer 2 by stacking on the surface of the first conductivity type silicon carbide semiconductor substrate 1.

  Step (b) is a step of forming the second conductivity type well region 4 in the surface layer portion of the drift layer 2.

  Step (c) is a step of forming the source region 3 of the first conductivity type in a part of the surface layer portion of the well region 4.

  Step (d) is a step of forming a trench 19 on the surface of the drift layer 2 where the well region 4 is not formed.

  Step (e) is a step of forming the gate insulating film 6 on the surface of a part of the well region 4, a part of the drift layer 2, and a part of the source region 3 including the inner wall of the trench 19.

  According to such a configuration, since the trench gate structure is adopted, the on-resistance can be reduced.

  In addition, since nitrogen and second conductivity type impurities are introduced by ion implantation, it can be manufactured at a relatively low manufacturing cost.

<Third Embodiment>
<Double-layer gate>
In the second embodiment, nitrogen is introduced into the gate electrode 7 near the gate insulating film 6 by implantation into the gate insulating film 6 and subsequent heat treatment. However, the manufacturing method of the said structure is not restricted to this.

  A method for manufacturing a vertical MOSFET having a trench gate structure according to the third embodiment will be described.

  First, the drift layer 2, the source region 3, the well region 4, the p + contact portion 5, the oxide film 14, and the gate insulating film 6 are manufactured by the same process as that shown in the second embodiment. The cross section after fabrication is the same as FIG.

  Next, as shown in FIG. 28, a polycrystalline silicon film 76 as a first semiconductor layer is formed on the gate insulating film 6 and the oxide film 14 by the CVD method. The film thickness of the polycrystalline silicon film 76 is set to a value that does not bury the trench 19.

  In the second embodiment, the film thickness of the polycrystalline silicon film 76 that does not fill the trench 19 is set to 0.2 μm. In this case, since the width D of the trench 19 is 0.6 μm, the trench 19 is not completely filled with the polycrystalline silicon film 76, and a 0.2 μm gap exists at the center.

  Nitrogen ions 59 are obliquely implanted into the polycrystalline silicon film 76 in the structure shown in FIG. 28 (FIG. 29). The acceleration voltage and the implantation angle Ea of the nitrogen ions 59 are selected so that the nitrogen ion concentration has a peak in the polycrystalline silicon film 76 and nitrogen ions are not implanted into the well region 4. The implantation angle Ea must also be selected so that ions are uniformly implanted into the polycrystalline silicon film 76 on the side wall of the trench 19.

In this embodiment, the acceleration voltage is 30 kV and the implantation angle is 11 °. Also, the injection direction is set according to the directions of injection 57, injection 54, injection 55 and injection 56 in FIG. The implantation angle is generally determined by tan ⁻¹ (trench void / trench depth).

In this embodiment, the trench gap is 0.2 μm, and the direction of implantation is the direction of implantation 57, implantation 54, implantation 55, and implantation 56 in FIG. 27, so that the trench gap is substantially 0.2 / cos (45) = 0. .28 μm. The ion implantation amount is preferably in the range of 1 × 10 ¹⁴ to 1 × 10 ¹⁶ / cm ² . In this embodiment, it was set to 4 × 10 ¹⁵ / cm ² .

  At this time, the projection ranges Rp and Rp + 5 × ΔRp to the polycrystalline silicon film 76 are 8.8 nm and Rp + 5 × ΔRp is 25.8 nm (depth of vertical implantation × sin) on the side wall. (11) × cos (45)). At the surface, the projection range Rp is 64.3 nm and Rp + 5 × ΔRp is 187.5 nm (depth of vertical implantation × cos (11)).

  Since the thickness of the polycrystalline silicon film 76 on the side wall is 200 nm, no ions are implanted into the well region 4 on the side wall. Further, ions are not implanted into the surface side, that is, the source region 3 and the p + contact portion 5 at all. As shown in FIG. 29, after the implantation of nitrogen ions 59 is completed, the polycrystalline silicon film 76 becomes a polycrystalline silicon film 77 as a first semiconductor layer containing nitrogen.

  Next, as shown in FIG. 30, a polycrystalline silicon film 78 as a second semiconductor layer not containing impurities is formed on the polycrystalline silicon film 77 by the CVD method. The film thickness of the polycrystalline silicon film 78 is set to a value that completely fills the trench 19. In this embodiment, the thickness is 0.2 μm.

Next, as shown in FIG. 31, boron is implanted into the polycrystalline silicon film 78. The acceleration voltage of the boron ions 58 is selected so that the ion concentration has a peak inside the polycrystalline silicon film 78 and the ions do not reach the source region 3 and the p + contact portion 5. In this embodiment, it is 40 kV. The values of boron projection range Rp and Rp + ΔRp are the same as in the second embodiment. The ion implantation amount is desirably in the range of 1 × 10 ¹⁵ to 2 × 10 ¹⁶ / cm ² . In this embodiment, it is set to 5 × 10 ¹⁵ / cm ² . As shown in FIG. 31, after the implantation of boron ions 58 is completed, the polycrystalline silicon film 78 becomes a polycrystalline silicon film 79 as a second semiconductor layer containing an impurity of the second conductivity type.

  Thereafter, the vertical MOSFET is completed by the same process as in the second embodiment.

  Also in this embodiment, the same heat treatment as that after the boron implantation in the second embodiment, that is, a heat treatment for 30 minutes at 700 to 900 ° C. is performed in a nitrogen atmosphere. Boron implanted into the polycrystalline silicon film 79 by this heat treatment diffuses into the polycrystalline silicon film 77. The temperature and time of this heat treatment may be determined so that the nitrogen concentration in the vicinity of the gate insulating film of the polycrystalline silicon film 77 becomes higher than the B concentration after the completion of all steps.

<Effect>
According to the present embodiment, a silicon carbide semiconductor device includes a first conductivity type silicon carbide semiconductor substrate 1, a first conductivity type drift layer 2, a second conductivity type well region 4, and a first conductivity type. A source region 3, a trench 19, a gate insulating film 6, and a gate electrode are provided.

  Drift layer 2 is formed on the surface of silicon carbide semiconductor substrate 1.

  The well region 4 is formed in the surface layer portion of the drift layer 2.

  The source region 3 is formed in a part of the surface layer portion of the well region 4.

  The trench 19 is formed on the surface of the drift layer 2 where the well region 4 is not formed.

  The gate insulating film 6 is provided on the surface of a part of the well region 4, a part of the drift layer 2, and a part of the source region 3 including the inner wall of the trench 19.

  The gate electrode is provided in the trench 19, and is provided on a part of the well region 4, a part of the drift layer 2, and a part of the source region 3 via the gate insulating film 6.

  The gate electrode is formed on the polycrystalline silicon film 77 as the first semiconductor layer doped with nitrogen and the first semiconductor layer (polycrystalline silicon film 77), and is doped with the second conductivity type impurity. It comprises a polycrystalline silicon film 79 as a semiconductor layer.

  According to such a configuration, although the number of processes is increased, since nitrogen ions are not implanted into the gate insulating film 6, the reliability of the gate insulating film 6 in the trench gate structure vertical MOSFET is improved.

  Further, according to the present embodiment, the method for manufacturing a silicon carbide semiconductor device includes (a) a step of forming the first conductivity type drift layer 2 and (b) a step of forming the second conductivity type well region 4. (C) a step of forming a source region 3 of the first conductivity type, (d) a step of forming a trench 19, (e) a step of forming a gate insulating film 6, and (f) a first semiconductor layer. (G) a step of implanting nitrogen ions 59 into the first semiconductor layer (polycrystalline silicon film 76) formed on the sidewall of the trench 19, and (h) a trench 19 (I) implanting second conductivity type impurity ions (boron ions 58) into the second semiconductor layer (polycrystalline silicon film 78); And a step of performing.

  Step (a) is a step of forming the first conductivity type drift layer 2 by stacking on the surface of the first conductivity type silicon carbide semiconductor substrate 1.

  Step (b) is a step of forming the second conductivity type well region 4 in the surface layer portion of the drift layer 2.

  Step (c) is a step of forming the source region 3 of the first conductivity type in a part of the surface layer portion of the well region 4.

  Step (d) is a step of forming a trench 19 on the surface of the drift layer 2 where the well region 4 is not formed.

  Step (e) is a step of forming the gate insulating film 6 on the surface of a part of the well region 4, a part of the drift layer 2, and a part of the source region 3 including the inner wall of the trench 19.

  Step (f) is a step of forming a first semiconductor layer (polycrystalline silicon film 76) formed along the gate insulating film 6 and partially filling the trench 19.

  According to such a configuration, although the number of steps is increased, nitrogen ions 59 are not implanted into the gate insulating film 6, so that the reliability of the gate insulating film 6 in the trench gate structure vertical MOSFET is improved.

<Modification>
In the above embodiment, the gate electrode is formed of p-type polycrystalline silicon. However, in order to switch the power vertical MOSFET at a higher speed, it may be necessary to lower the resistance of the gate electrode. In that case, a metal silicide having a lower resistance than the polycrystalline silicon film, specifically, tungsten silicide (WSi ₂ ) or titanium silicide (TiSi ₂ ) may be formed on the p-type polycrystalline silicon film.

  In the above embodiment, an example in which the sense vertical MOSFET does not exist is shown. The vertical MOSFET of the above embodiment is referred to as a main vertical MOSFET. A power vertical MOSFET incorporating a sense vertical MOSFET can also be fabricated in exactly the same process.

  Further, the Vth of the sense and main vertical MOSFETs may be changed by changing the concentration of boron implanted into the gate electrodes of the sense and main vertical MOSFETs using a resist mask. If the boron concentration of the sense vertical MOSFET is set lower than that of the main vertical MOSFET, the Vth of the sense vertical MOSFET becomes lower than that of the main. This is because when the concentration of boron is low, the bending of the band becomes larger and the channel is inverted with a small gate voltage. Even if phosphorus (P) is implanted into the gate electrode of the sense vertical MOSFET to make it n-type, Vth of the sense vertical MOSFET is similarly lowered. The current density of the vertical MOSFET having a low Vth is larger than the current density of the vertical MOSFET having a high Vth. As described above, if the Vth of the vertical MOSFET for sensing is set to be lower than that for the main MOSFET, the resist mask forming process and the ion implantation process are increased, but the current of the vertical MOSFET can be detected in an earlier time. Before reaching the current value, the current of the vertical MOSFET can be turned off with a sufficient margin. For this reason, there is an effect of preventing the vertical MOSFET incorporating the sense vertical MOSFET from being destroyed by overcurrent.

  In the second and third embodiments, low resistance metal silicide must be provided inside the trench. In that case, the width of the trench and the thickness of the polycrystalline silicon film may be adjusted so that the trench is not completely filled with the polycrystalline silicon film, and metal silicide may be formed in the gap in the trench.

  In the above embodiment, the case where the semiconductor element is a vertical MOSFET is disclosed, but a bipolar element in which both electrons and holes contribute to conduction, for example, FIG. 3, FIG. 26 or FIG. Even if a semiconductor element having an IGBT cell region in which the conductivity type of the silicon carbide semiconductor substrate 1 shown is the second conductivity type (p-type) is configured, the effects of the present invention described above can be similarly achieved. Needless to say. Therefore, the scope of the present invention includes a semiconductor element as a bipolar element such as MOSFET or IGBT.

  In each of the above embodiments, the first conductivity type is n-type and the second conductivity type is p-type. However, the first conductivity type may be p-type and the second conductivity type may be n-type. When the first conductivity type is p-type, the conductivity type of the gate electrode needs to be n-type. Moreover, the unit of the angle in this specification is degree (degree).

  In the said embodiment, although the material of each component, material, the conditions of implementation, etc. are described, these are illustrations and are not restricted to what was described.

  In addition, within the scope of the present invention, the present invention can be freely combined with each embodiment, modified with any component in each embodiment, or omitted with any component in each embodiment.

  The present invention is suitable for application to a power converter such as an inverter.

  DESCRIPTION OF SYMBOLS 1 Silicon carbide semiconductor substrate, 2 drift layer, 3 source region, 4 well region, 5 p + contact part, 6 gate insulating film, 7 gate electrode, 8 interlayer insulating film, 9 drain electrode, 10 external output source electrode, 11 back surface connection Drain electrode, 12 source contact hole, 13 gate contact hole, 14 oxide film, 15 external output gate electrode, 15a gate wiring, 16 JFET region, 17 Ni film, 18 silicide film, 19 trench, 20 cell array region, 21 peripheral region , 30 resist, 40 MOSFET, 51, 53, 59 nitrogen ion, 52, 58 boron ion, 54-57, 54a-57a implantation, 71-79 polycrystalline silicon film.

Claims (9)

A first conductivity type silicon carbide semiconductor substrate;
A drift layer of a first conductivity type formed on the surface of the silicon carbide semiconductor substrate;
A second conductivity type well region formed in a surface layer portion of the drift layer;
A source region of a first conductivity type formed in a part of a surface layer portion of the well region;
A gate insulating film provided on a surface of a part of the well region, a part of the drift layer, and a part of the source region;
A gate electrode provided on a part of the well region, a part of the drift layer and a part of the source region via the gate insulating film;
The gate electrode is made of a conductive layer in which a semiconductor material is doped with a second conductivity type impurity, and the conductive layer is further doped with nitrogen,
The nitrogen concentration is higher than the impurity concentration on the side of the gate electrode in contact with the gate insulating film,
Silicon carbide semiconductor device. The gate electrode is composed of a single layer,
The silicon carbide semiconductor device according to claim 1. The conductive layer has a thickness of 250 nm or more,
The silicon carbide semiconductor device according to claim 1 or 2. The gate electrode is made of polycrystalline silicon,
The silicon carbide semiconductor device in any one of Claims 1-3. A trench is further formed on the surface of the drift layer where the well region is not formed;
The gate insulating film is provided on a surface of a part of the well region, a part of the drift layer, and a part of the source region including the inner wall of the trench;
The gate electrode is provided in the trench,
The silicon carbide semiconductor device in any one of Claims 1-4. A first conductivity type silicon carbide semiconductor substrate;
A drift layer of a first conductivity type formed on the surface of the silicon carbide semiconductor substrate;
A second conductivity type well region formed in a surface layer portion of the drift layer;
A source region of a first conductivity type formed in a part of a surface layer portion of the well region;
A trench formed in the surface of the drift layer in which the well region is not formed;
A gate insulating film provided on a surface of a part of the well region, a part of the drift layer and a part of the source region, including the inner wall of the trench;
A gate electrode provided in the trench and provided in part of the well region, part of the drift layer and part of the source region via the gate insulating film;
The gate electrode is
A first semiconductor layer doped with nitrogen;
A second semiconductor layer formed on the first semiconductor layer and doped with an impurity of a second conductivity type;
The impurity is diffused in the first semiconductor layer,
Silicon carbide semiconductor device. (A) forming a first conductivity type drift layer by stacking on a surface of a first conductivity type silicon carbide semiconductor substrate;
(B) forming a second conductivity type well region in a surface layer portion of the drift layer;
(C) forming a first conductivity type source region in a portion of the surface layer of the well region;
(D) forming a gate insulating film on a surface of a part of the well region, a part of the drift layer, and a part of the source region;
(E) forming a conductive layer on the surface of the gate insulating film;
(F) a step of ion-implanting nitrogen into the conductive layer;
(G) ion-implanting a second conductivity type impurity into the conductive layer,
On the side of the conductive layer in contact with the gate insulating film, the nitrogen concentration is higher than the impurity concentration.
A method for manufacturing a silicon carbide semiconductor device. (A) forming a first conductivity type drift layer by stacking on a surface of a first conductivity type silicon carbide semiconductor substrate;
(B) forming a second conductivity type well region in a surface layer portion of the drift layer;
(C) forming a first conductivity type source region in a portion of the surface layer of the well region;
(D) forming a trench in the surface of the drift layer where the well region is not formed;
(E) forming the gate insulating film on the surface of a part of the well region, a part of the drift layer, and a part of the source region, including the trench inner wall;
(F) a step of ion-implanting nitrogen into the gate insulating film formed on the trench sidewall;
(G) forming a conductive layer in the trench;
(H) ion-implanting a second conductivity type impurity into the conductive layer;
(I) diffusing the nitrogen implanted into the gate insulating film and the impurities implanted into the conductive layer,
A method for manufacturing a silicon carbide semiconductor device. (A) forming a first conductivity type drift layer by stacking on a surface of a first conductivity type silicon carbide semiconductor substrate;
(B) forming a second conductivity type well region in a surface layer portion of the drift layer;
(C) forming a first conductivity type source region in a portion of the surface layer of the well region;
(D) forming a trench in the surface of the drift layer where the well region is not formed;
(E) forming the gate insulating film on the surface of a part of the well region, a part of the drift layer, and a part of the source region, including the trench inner wall;
(F) forming a first semiconductor layer formed along the gate insulating film and partially filling the trench;
(G) a step of ion-implanting nitrogen into the first semiconductor layer formed on the trench sidewall;
(H) forming a second semiconductor layer filling the trench;
(I) a step of ion-implanting a second conductivity type impurity into the second semiconductor layer.
A method for manufacturing a silicon carbide semiconductor device.

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