JP2019083354A - Semiconductor device - Google Patents

Abstract

To provide a semiconductor device which allows improvement in on-resistance characteristics.SOLUTION: A semiconductor device comprises: a MOS gate structure of a trench gate structure provided on an ntype drift layer 2 on a first principal surface side; a deposited insulation layer 6 provided inside a trench 5 closer to a collector than a gate electrode 8; and a floating-state p type embedded region 9 which is selectively provided inside the ntype drift layer 2 and away from a ptype base region 3 so as to surround a bottom of the trench 5. In the semiconductor device, in an off state, a p type inversion layer 12 is formed at a portion of the ntype drift layer 2, which is sandwiched between the ptype base region 3 and the p type embedded region 9 and along a gate insulation film 7 thereby to electrically connect the ptype base region 3 and the p type embedded region 9. In order to form the p type inversion layer 12 in the off state, an impurity concentration of the ndrift layer 2 and a thickness t2 of the gate insulation film 7 and a work function of the gate electrode 8 are set accordingly.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a semiconductor device.

  Conventionally, a MOS gate is embedded in a trench formed in a semiconductor substrate as a semiconductor device (hereinafter referred to as a MOS semiconductor device) having a MOS gate (insulated gate made of metal-oxide film-semiconductor) structure used for power devices. Devices having a trench gate structure are known. In the MOS type semiconductor device of this trench gate structure, generally, there is a trade-off between high breakdown voltage and low on-resistance. As a MOS semiconductor device in which such a trade-off relationship is improved, a floating region of a conductivity type different from the drift layer is provided so as to surround the bottom (drain side end) of the trench in which the MOS gate is embedded. An apparatus has been proposed (see, for example, Patent Document 1 below).

The structure of a conventional MOS semiconductor device will be described. FIG. 6 is a cross-sectional view showing the structure of the main part of a conventional semiconductor device. FIG. 6 shows a unit cell (functional unit of device) structure disposed in an active region through which current flows in the on state. FIG. 6 corresponds to FIG. 1 of Patent Document 1 below. As shown in FIG. 6, the conventional semiconductor device 100 has a MOS gate structure on the first main surface side of the n ⁻ -type drift layer 102 and an n ⁺ -type drain layer 101 on the second main surface side. The MOS gate structure comprises ap ⁻ -type base region 103, an n ⁺ -type source region 104, a trench 105, a deposited insulating layer 106, a gate insulating film 107 and a gate electrode 108. The n ⁺ -type source region 104 is selectively provided inside the p ⁻ -type base region 103.

The trench 105 penetrates the n ⁺ -type source region 104 and the p ⁻ -type base region 103 in the depth direction to reach the n ⁻ -type drift layer 102. The deposited insulating layer 106 is buried on the drain side of the trench 105. The gate electrode 108 is provided on the deposited insulating layer 106 (on the source side) inside the trench 105. The gate electrode 108 faces the p ⁻ -type base region 103 and the n ⁺ -type source region 104 with the gate insulating film 107 provided on the sidewall of the trench 105 interposed therebetween. Inside the n ⁻ type drift layer 102, a floating p type diffusion region (hereinafter, referred to as a p type buried region) 109 is provided. The bottom of the trench 105 is located inside the p-type buried region 109. Reference numerals 110 and 111 denote a source electrode and a drain electrode, respectively.

The conventional semiconductor device 100 has the following characteristics by having a structure (hereinafter, referred to as a floating structure) in which a p-type embedded region 109 in a floating state is provided inside the n ⁻ -type drift layer 102. A gate voltage is not applied in (or negative gate voltage was applied) OFF state, n ^- inside the type drift layer 102, p ^- the pn junction 121 between the type drift layer 102 ^- -type base region 103 and n A depletion layer (not shown) spreads. When this depletion layer reaches the p-type buried region 109, the p-type buried region 109 is punched through, and the pn junction 121 between the p ^-- type base region 103 and the n ^-- type drift layer 102 is p-type buried. The potential up to the region 109 is fixed. Further, n ^- in the interior of the type drift layer 102, p-type buried region 109 and the n ^- depletion layer from the pn junction 122 between the type drift layer 102 (not shown) is increased.

As described above, the depletion layer spreads from the pn junction 121 between the p ⁻ -type base region 103 and the n ⁻ -type drift layer 102, so that the area near the pn junction 121 has a peak of electric field strength. Further, the depletion layer spreads from the pn junction 122 between the p-type buried region 109 and the n ⁻ -type drift layer 102, so that a peak of electric field intensity is also formed near the pn junction 122. That is, the peaks of the electric field strength can be dispersed at two places. Therefore, the maximum peak value of the electric field strength can be reduced, and the breakdown voltage can be increased. In addition, since a high breakdown voltage can be secured, the impurity concentration of the n ⁻ -type drift layer 102 can be increased to reduce the on-resistance. Regarding the mechanism of such a floating structure, the calculation result of the electric field strength distribution is disclosed in detail (for example, see Patent Document 2 below).

For example, in a normal MOS semiconductor device used for an inverter circuit or the like, the drain voltage Vd generally changes by controlling the on / off of the semiconductor device by the gate voltage Vg. FIG. 7 is a characteristic diagram showing voltage waveforms of the conventional semiconductor device. Specifically, as shown in FIG. 7, an on state in which a gate voltage Vg equal to or higher than the threshold voltage is applied (hereinafter referred to as a first state A)
Then, since the depletion layer does not spread in the n ⁻ -type drift layer, the drain voltage Vd is low, and the device operates in a low on-state. On the other hand, while the off state is maintained without applying the gate voltage Vg (hereinafter referred to as the second state B), the depletion layer spreads in the n ⁻ type drift layer (high on resistance state). The drain voltage Vd is maintained high. That is, the breakdown voltage between the drain and the source is maintained by the spread of the depletion layer. Then, the transition from the off state to the on state again (hereinafter referred to as the third state C) narrows the width of the depletion layer which was spread in the second state, so that the state of the low on resistance is obtained again. Works with Thereafter, the second state B and the third state C are alternately repeated. Thus, in the conventional MOS type semiconductor device (MOS-type semiconductor device not floating structure), when in the second state B, n ^- inside the type drift layer p ^- type base region and the n ^- the type drift layer The depletion layer extends from the pn junction between them. Then, p when in the second state B ^- type base region and the n ^- width of the depletion layer spread from the pn junction between the type drift layer, p when the third state C ^- n -type base region ^- The supply of holes to the type drift layer narrows immediately.

However, in the semiconductor device 100 of the conventional floating structure shown in FIG. 6, it is difficult to return from the state of high on resistance to the state of low on resistance in the third state C, as compared to a normal MOS semiconductor device. The reason is as follows. In the conventional semiconductor device 100, in the second state B, the pn junction 121 between the p ^-- type base region 103 and the n ^-- type drift layer 102, the p-type buried region 109 and the n ^-- type drift layer 102 The depletion layer spreads from two places with the pn junction 122 between them. Then, in the third state C, holes are supplied from the outside to the p ⁻ -type base region 103 connected to the source electrode 110, but since the p-type buried region 109 is in a floating state, the p-type buried region No external supply of holes is performed at 109. For this reason, in the third state C, the amount of holes sufficient to narrow the width of the depletion layer spread to the drain side of the p-type buried region 109 only by the supply of holes from the p-type buried region 109 itself. Can not be compensated in a short time. That is, the amount of holes to be supplied in order to narrow the width of the depletion layer in the third state C is insufficient, and the width of the depletion layer expanded to the drain side of the p-type buried region 109 is narrowed again. Takes time. As a result, as indicated by a dotted line in FIG. 7, the drain voltage Vd gradually decreases in the third state C and reaches the lowest value. For this reason, the low on-resistance state is not immediately returned, and the transient on-resistance characteristic is adversely affected. In particular, when the chip size is large, the amount of holes to be supplied in order to narrow the width of the depletion layer in the third state C is large, so that the larger the chip size, the more delayed the supply of holes. Generally, the chip size that adversely affects the on-resistance characteristics is about several mm square or more.

Also, as another device of the conventional floating structure, the p ^-- type base region is connected to the floating p-type diffusion region (p-type buried region) along the gate insulating film provided on the sidewall of the trench. There is proposed a device provided with ap ⁻ -type diffusion region which is provided as described above and serves as a hole supply path to the p-type diffusion region in the floating state when in the on state (for example, see Patent Document 3 below).

The structure shown to following patent document 3 is demonstrated. FIG. 8 is a cross-sectional view showing the structure of another example of the conventional semiconductor device. FIG. 8 shows a cross-sectional structure in which the gate electrode 108 embedded in the trench 105 having a linear planar shape is cut in parallel to the longitudinal direction of the trench 105. FIG. 8 corresponds to FIG. 4 of Patent Document 3 below. The conventional semiconductor device 200 shown in FIG. 8 is different from the conventional semiconductor device 100 shown in FIG. 6 in that ap ⁻ -type diffusion region 112 is provided inside the n ⁻ -type drift layer 102. The p ⁻ -type diffusion region 112 is provided along the sidewall of the trench 105 of the deposited insulating layer 106 and connects the p ⁻ -type base region 103 and the p-type buried region 109.

The p ⁻ -type diffusion region 112 has an extremely low impurity concentration, and becomes a very high resistance region due to the depletion layer extending from the pn junction with the n ⁻ -type drift layer 102. Therefore, in the off state, the p-type embedded region 109 is in the floating state as in the conventional semiconductor device 100 (patent documents 1 and 2 below) shown in FIG. Therefore, as in the case of the above-described floating structure, the withstand voltage between the drain and the source is maintained, and a high withstand voltage can be achieved.
On the other hand, in the ON state, the p ^- type diffusion region 112 fixes the p-type buried region 109 to the source potential, whereby holes are supplied from the p-type buried region 109 to the n ⁻ -type drift layer 102. Therefore, the amount of holes supplied in the on state can be increased.

In FIG. 8, reference numerals 115 to 119 denote a trench, a deposited insulating layer, a gate insulating film, a gate electrode and a p-type buried region of the termination structure portion 202, respectively. The trench 115, the deposited insulating layer 116, the gate insulating film 117, the gate electrode 118 and the p-type buried region 119 of the termination structure portion 202 are the trench 105 of the active region 201, the deposited insulating layer 106, the gate insulating film 107, the gate electrode 108 and the gate It has a structure similar to that of the p-type buried region 109. The gate electrode 118 is provided in the trench 115 closest to the active region 201, and the deposition insulating layer 116 is embedded in the other trenches 115. The termination structure portion 202 is a region surrounding the active region 201 and relaxing the electric field on the first major surface side of the n ⁻ -type drift layer 102 to maintain the breakdown voltage.

JP, 2005-142243, A JP-A-9-191109 JP, 2007-242852, A

  However, although the electric field strength in the vicinity of the bottom of the trench 105 can be reduced in the Patent Documents 1 and 2, no mention is made of preventing the extraction of minority carriers (holes) in the ON state. Further, even if the above Patent Documents 1 and 2 are applied to a device utilizing the conductivity modulation effect such as an insulated gate bipolar transistor (IGBT: Insulated Gate Bipolar Transistor), the conductivity modulation effect is not improved. Further, in Patent Document 3 described above, when applied to a device utilizing a conductivity modulation effect such as IGBT, holes are pulled out from the p-type embedded region 109 fixed to the source potential in the ON state. Therefore, there is a problem that conductivity modulation hardly occurs and the on-resistance characteristic is deteriorated.

  An object of the present invention is to provide a semiconductor device capable of improving the on-resistance characteristic in order to solve the above-mentioned problems of the prior art.

  In order to solve the problems described above and achieve the object of the present invention, a semiconductor device according to the present invention has the following features. A first semiconductor region of a second conductivity type is provided on the first main surface side of the semiconductor layer of the first conductivity type. A second semiconductor region of the first conductivity type is selectively provided in the first semiconductor region. A trench penetrates the second semiconductor region and the first semiconductor region to reach the semiconductor layer. An insulating layer is embedded in the bottom of the trench. A gate insulating film is provided inside the trench along the sidewall of the trench. A gate electrode is provided inside the gate insulating film inside the trench and on the surface of the insulating layer. A third semiconductor region of the second conductivity type is selectively provided in the semiconductor layer to surround the bottom of the trench. The third semiconductor region faces the gate electrode with the insulating layer interposed therebetween. A fourth semiconductor region is provided on the second main surface side of the semiconductor layer. The first electrode is electrically connected to the first semiconductor region and the second semiconductor region. The second electrode is electrically connected to the fourth semiconductor region. The gate electrode is a second conductive type semiconductor layer or a polysilicon layer doped with a second conductive type impurity. Then, a first conductivity type inversion layer is formed along the gate insulating film in a portion of the first semiconductor region which is larger than 0 V and is sandwiched between the second semiconductor region and the semiconductor layer. A portion of the semiconductor layer sandwiched between the first semiconductor region and the third semiconductor region when a second gate voltage in a range lower than the gate threshold voltage which is the lowest voltage of the first gate voltage is applied. A second inversion layer of the second conductivity type is formed along the gate insulating film. The inversion layer electrically connects the first semiconductor region and the third semiconductor region.

  In the semiconductor device according to the present invention, in the semiconductor device according to the above-mentioned invention, the impurity concentration is selectively provided in the semiconductor layer away from the first semiconductor region and the third semiconductor region more than the semiconductor layer. And a fifth semiconductor region of high first conductivity type.

  In the semiconductor device according to the present invention, in the above-mentioned invention, the fifth semiconductor region is provided between the first semiconductor region and the third semiconductor region of the semiconductor layer. Do.

  In the semiconductor device according to the present invention, in the semiconductor device according to the above-mentioned invention, the semiconductor layer is set to an impurity concentration that causes the second conductivity type inversion layer to be generated when the second gate voltage is applied to the gate electrode. It is characterized by

  In the semiconductor device according to the present invention, in the semiconductor device according to the above-mentioned invention, the semiconductor layer is set to an impurity concentration such that the second conductivity type inversion layer is not generated when the first gate voltage is applied to the gate electrode. It is characterized by

  In the semiconductor device according to the present invention as set forth above, the third semiconductor region is in a floating state when the first gate voltage is applied to the gate electrode.

  In the semiconductor device according to the present invention, in the above-described invention, the first semiconductor region and the third semiconductor region may be provided between the first semiconductor region and the third semiconductor region in the semiconductor layer. The semiconductor device may further include a sixth semiconductor region of a second conductivity type which is selectively provided in contact and which extends from the first semiconductor region side to a position deeper than the bottom of the trench.

  In the semiconductor device according to the present invention described above, the semiconductor device according to the present invention is characterized by including the fourth semiconductor region of the second conductivity type.

  According to the invention described above, since the third semiconductor region is in the floating state when in the on state, extraction of minority carriers (holes) from the third semiconductor region to the first electrode does not occur. Therefore, conductivity modulation is not hindered in a device utilizing conductivity modulation effect such as IGBT. This can prevent the deterioration of the on-resistance characteristic.

  Further, according to the above-described invention, the carrier density in the semiconductor layer can be increased by providing the fifth semiconductor region in the semiconductor layer.

  According to the semiconductor device of the present invention, the on-resistance characteristic can be improved.

FIG. 1 is a cross-sectional view showing a structure of a semiconductor device according to a first embodiment. FIG. 6 is a cross-sectional view showing a structure of a semiconductor device according to a second embodiment. FIG. 7 is a cross-sectional view showing a structure of a semiconductor device according to a third embodiment. FIG. 16 is a cross-sectional view showing the structure of the semiconductor device according to Fourth Embodiment; FIG. 18 is a cross-sectional view showing a structure of a semiconductor device according to a fifth embodiment. FIG. 20 is a cross-sectional view showing a structure of a main part of a conventional semiconductor device. It is a characteristic view showing the voltage waveform of the conventional semiconductor device. FIG. 18 is a cross-sectional view showing the structure of another example of a conventional semiconductor device.

  Hereinafter, preferred embodiments of a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings. In the present specification and the accompanying drawings, in the layer or region having n or p, it is meant that electrons or holes are majority carriers, respectively. Further, + and-attached to n and p mean that the impurity concentration is higher and the impurity concentration is lower than that of the layer or region to which it is not attached, respectively. In the following description of the embodiments and the accompanying drawings, the same components are denoted by the same reference numerals and redundant description will be omitted.

Embodiment 1
The structure of the semiconductor device according to the first embodiment will be described. FIG. 1 is a cross-sectional view showing the structure of the semiconductor device according to the first embodiment. FIG. 1 shows a cross-sectional structure of the semiconductor device according to the first embodiment in the off state. The off state is a state in which the semiconductor device does not operate, and is a state in which the gate voltage is at least 0 V (a state in which the gate voltage is not applied or a negative gate voltage is applied to the gate electrode). The on state is a state in which the semiconductor device operates and is a state in which the gate voltage is equal to or higher than the threshold voltage (gate voltage 電 圧 threshold voltage). As shown in FIG. 1, in the semiconductor device according to the first embodiment, an n ⁻ -type drift layer (semiconductor layer)
A trench gate MOS gate structure is provided on the side of the first main surface 2. The MOS gate structure includes ap ^-- type base region (first semiconductor region) 3, an n ⁺ -type emitter region (second semiconductor region) 4, a trench 5, a deposited insulating layer (insulating layer) 6, a gate insulating film 7 and a gate electrode It consists of eight.

A p ⁺ -type collector layer (fourth semiconductor region) 1 is provided on the second major surface side of the n ⁻ -type drift layer 2. The p ⁺ -type collector layer 1 may be a diffusion region formed by ion implantation, for example, in the surface layer of the second main surface of the n ⁻ -type drift layer 2, and the semiconductor device according to the first embodiment is manufactured (manufactured ) May be composed of a p ⁺ -type starting substrate (semiconductor chip) prepared to If the p ⁺ -type collector layer 1 and the p ⁺ -type starting substrate, n ^- -type drift layer 2 is an epitaxial layer deposited for example the front surface of the p ⁺ -type starting substrate comprising the p ⁺ -type collector layer 1 . The p ⁻ -type base region 3 is provided on the first major surface side of the n ⁻ -type drift layer 2. p ^- type base region 3, n ^- may be an epitaxial layer deposited on the first major surface of the type drift layer 2, n ^- the surface layer, for example, ion implantation of the first main surface of the type drift layer 2 It may be a formed diffusion region.

The lower the impurity concentration of the p ⁻ -type base region 3 is, the lower the threshold voltage is. However, when the gate voltage is at least 0 V or less, a channel (a portion facing the gate electrode 8 in the p ⁻ -type base region 3) It is preferable that the n-type inversion layer be as low as not formed (not turned on). The n ⁺ -type emitter region 4 is selectively provided inside the p ⁻ -type base region 3. The n ⁺ -type emitter region 4 may be an epitaxial layer or, for example, a diffusion region formed by ion implantation. Trench 5 penetrates n ⁺ -type emitter region 4 and p ⁻ -type base region 3 to reach n ⁻ -type drift layer 2. The deposited insulating layer 6 is provided on the collector side inside the trench 5. That is, the deposited insulating layer 6 is embedded in the bottom (collector side end) of the trench 5.

The gate electrode 8 is provided on the surface (emitter side) of the deposited insulating layer 6 inside the trench 5. Gate electrode 8 opposes p ⁻ base region 3, n ⁺ emitter region 4 and n ⁻ drift layer 2 with gate insulating film 7 provided on the side wall of trench 5 interposed therebetween. That is, the collector side end of the gate electrode 8 is located closer to the collector than the pn junction 21 between the p ⁻ -type base region 3 and the n ⁻ -type drift layer 2. Inside the n ⁻ type drift layer 2, ap type diffusion region (p type buried region (third semiconductor region)) 9 is selectively provided apart from the p ⁻ type base region 3. The p-type buried region 9 is buried in the n ⁻ -type drift layer 2 so as to surround the bottom of the trench 5, and faces the gate electrode 8 with the deposited insulating layer 6 interposed therebetween. That is, the bottom of the trench 5 is located inside the p-type buried region 9.

The p-type buried region 9 may extend along the inner wall of the trench 5 toward the emitter side so as not to face the gate electrode 8 with the gate insulating film 7 provided on the side wall of the trench. That is, thickness t1 of deposited insulating layer 6 is so thick that p type buried region 9 and gate electrode 8 do not face each other with gate insulating film 7 provided on the side wall of trench 5 interposed therebetween. The p-type buried region 9 has a function of relaxing the electric field applied to the n ⁻ -type drift layer 2. The p-type buried region 9 may be, for example, a diffusion region formed by ion implantation. The impurity concentration of the p-type buried region 9 can be variously changed in accordance with the design conditions, and may be as high as the degeneracy of the energy level does not occur (the Fermi level does not move into the valence band). For example, the impurity concentration of the p-type buried region 9 is high enough to prevent depletion of the entire p-type buried region 9 even when a high voltage is applied to the collector, for example, about the same as the impurity concentration of the n ⁻ -type drift layer 2 It is set above.

n ^- type drift layer 2, p ^- the portion held -type base region 3 and the p-type buried region 9, the inversion layer 12 of p-type along the gate insulating film 7 in the off state is formed (Part indicated by hatching in the figure). The p-type inversion layer 12 electrically connects the p ^-- type base region 3 and the p-type buried region 9. Therefore, the p-type buried region 9 is fixed at the emitter potential in the off state. Type drift layer 2, p ^{- -} n in the off state in order to cause the inversion layer 12 of p-type to type base region 3 and the p-type buried region 9 and the portion sandwiched between, n ^- -type drift layer 2 The impurity concentration, the thickness t2 of the gate insulating film 7, and the work function of the gate electrode 8 are appropriately set. Specifically, n ^- type drift layer 2, p ^- impurity concentration type base region 3 and the p-type buried region 9 and the portion sandwiched by the inversion layer 12 of p-type occurs in the off state ( That is, the holes are set as low as possible.

n ^- type drift layer 2, p ^- impurity concentration type base region 3 and the p-type buried region 9 and the portion sandwiched by the, n ^- may be different from the impurity concentration of the other parts of the type drift layer 2 . For example, n ^- when the impurity concentration of the type drift layer 2 is in the range of degree 1 × 10 ¹⁴ / cm ³ or more 1 × 10 ¹⁶ / cm ³ or less, n ^- type drift layer 2, p ^- type base region 3 The impurity concentration of the portion sandwiched between the p-type and the p-type buried regions 9 is, for example, about 1 × 10 ¹⁷ / cm ³ or less. The thickness t2 of the gate insulating film 7 is the p-type inversion layer 12 in the portion of the n ^-- type drift layer 2 sandwiched between the p ^-- type base region 3 and the p-type buried region 9 in the off state. It may be set as thin as possible. That is, the thickness t2 of the gate insulating film 7 may satisfy the above conditions, and may be thinner than the thickness of the deposited insulating layer 6, or may be the same thickness as the deposited insulating layer 6, for example. .

For example, the thickness t2 of the gate insulating film 7 is 100 nm, and the impurity concentration of the portion of the n ^-- type drift layer 2 sandwiched between the p ^-- type base region 3 and the p-type buried region 9 is 1 × 10 ¹⁷ / cm. ^In the case of ³ , when the gate voltage is about -10 V, the p-type inversion layer 12 is formed. n ^- type drift layer 2, p ^- if type base region 3 and the degree impurity concentration 1 × 10 ¹⁷ / cm ³ or less of a portion held with p-type buried region 9, the gate voltage to approximately -15V The p-type inversion layer 12 can be formed also in an application (product) shifted to a low level. In addition, when the impurity concentration of the n ⁻ -type drift layer 2 is uniformly about 5 × 10 ¹⁴ / cm ³ or less (for example, 13 kV class withstand voltage), the p-type inversion layer 12 is formed even if the gate voltage is about −2 V It can be formed.

Further, even if the gate voltage is about 0 V, the p-type inversion layer 12 can be formed by setting the work function of the gate electrode 8 appropriately. In this case, the gate electrode 8, for example, n ^- by the work function difference between the type drift layer 2 n ^- type drift layer 2, p ^- type base region 3 and the p-type buried region 9 and the portion sandwiched between (n ^- type drift layer 2, the interface vicinity) between the gate insulating film 7 may be formed in the electrode material having a work function that can cause the hole. Specifically, for example, a p-type silicon carbide (SiC) semiconductor having a high impurity concentration of about 1 × 10 ¹⁸ / cm ³ or an doped polysilicon (doped poly) doped with a p-type impurity as an electrode material of the gate electrode 8. -Si) or the like may be used. Emitter electrode (first electrode) 10 is in contact with p ⁻ -type base region 3 and n ⁺ -type emitter region 4 and is electrically insulated from gate electrode 8 by an interlayer insulating film (not shown). The collector electrode (second electrode) 11 is in contact with the p ⁺ -type collector layer 1.

Although not particularly limited, for example, when the semiconductor device according to the first embodiment has a breakdown voltage of 13 kV, the n ⁺ -type emitter region 4 and the p ⁺ -type collector layer 1 have a sufficiently high impurity concentration (1 × 10 ¹⁸ / cm ³ or more). And its thickness is about 0.1 μm or more. The impurity concentration of the p ⁻ -type base region 3 is about 1 × 10 ¹⁵ / cm ³ or more and 1 × 10 ¹⁷ / cm ³ or less depending on the thickness t 2 of the gate insulating film 7. The thickness of the n ⁻ -type drift layer 2 is about 100 μm to 150 μm. The impurity concentration of the n ⁻ -type drift layer 2 is about the above-mentioned range, and preferably about 5 × 10 ¹⁴ / cm ³ or less. The depth of the trench 5 is about 1 μm to 3 μm. The thickness t2 of the gate insulating film 7 is about 50 nm or more and 200 nm or less. The impurity concentration of the p-type buried region 9 is about 1 × 10 ¹⁸ / cm ³ or more.

Next, the operation of the semiconductor device according to the first embodiment will be described. The emitter electrode 10 is in a state of being grounded to the ground or in a state in which a negative voltage is applied (emitter potential ≦ 0). The collector electrode 11 is in a state in which a positive voltage is applied (collector potential> 0). In this state, p ^- type base region 3 and n ^- pn junction 21 between the type drift layer 2 is reverse biased. Therefore, a depletion layer (not shown) spreads inside the p ^-- type base region 3 and the n ^-- type drift layer 2, and the path (channel) of electrons which are conduction carriers is blocked. At this time, in a state where a gate voltage is not applied to the gate electrode 8 or a negative gate voltage is applied (gate voltage ≦ 0 V), no current flows between the emitter and the collector. That is, the off state is maintained. While the off state is maintained, a portion of the n ⁻ -type drift layer 2 between the p ⁻ -type base region 3 and the p-type buried region 9 along the gate insulating film 7 is a p-type inversion layer 12. There is formed, p ^- type base region 3 and the p-type and the buried region 9 are electrically connected. Therefore, p-type buried region 9 is fixed at substantially the same base (emitter) potential as p ^-- type base region 3, and pn junction 22 between p-type buried region 9 and n ^-- type drift layer 2 is also reverse biased. Ru.

On the other hand, when the voltage applied to the gate electrode 8 is equal to or higher than the threshold voltage (gate voltage 閾 値 threshold voltage)
, N-type inversion along the gate insulating film 7 in a portion (portion facing the gate electrode 8) of the p ^-- type base region 3 sandwiched between the n ⁺ -type emitter region 4 and the n ^-- type drift layer 2 A layer (channel (not shown)) is formed. Thus, the n ⁺ -type emitter region 4, the n-type inversion layer, and the n ⁻ -type drift layer 2 become paths of electrons as conduction carriers. That is, electrons emitted from the emitter electrode 10 move to the collector electrode 11 through the n ⁺ -type emitter region 4, the n-type inversion layer and the n ⁻ -type drift layer 2, and a current flows between the emitter and the collector. This state is on. In the ON state, the p-type buried region 9 is floating because the p-type inversion layer 12 does not occur in the portion of the n ⁻ -type drift layer 2 between the p ⁻ -type base region 3 and the p-type buried region 9. It becomes a state. Then, by setting the voltage applied to the gate electrode 8 to at least 0 V or less (gate voltage ≦ 0 V), the on state shifts to the off state. Thus, the on / off of the semiconductor device is controlled by the voltage applied to the gate electrode 8.

In the state where the gate voltage is greater than 0 and less than the threshold voltage (0 <gate voltage <threshold voltage)
In the same manner as in the case where the gate voltage is 0 V or less, the n-type inversion layer (channel) is not formed. However, in practice, the semiconductor device according to the first embodiment is performed until the gate voltage becomes 0 V after the command value (gate voltage <threshold voltage) for the off control is externally applied to the gate electrode 8. Is in a transition state until the operation is stopped, and has not completely stopped. Therefore, in the above description, although at least 0V following conditions in the OFF state which is the gate voltage operation is completely stopped in a semiconductor device according to the first embodiment, n ^- the type drift layer 2 of p-type The gate voltage when the inversion layer 12 is formed is equal to the gate voltage (that is, the threshold voltage) when the n-type inversion layer (channel) is formed in the p ⁻ -type base region 3 (on state) If the gate voltage is less than the threshold voltage (gate voltage <threshold voltage), it may be turned off.

Further, in the above description, a device using conductivity modulation effect such as IGBT is described as an example, but the present invention is applied to an insulated gate field effect transistor (MOSFET: Metal Oxide Semiconductor Field Effect Transistor). May be In this case, instead of the p ⁺ -type collector layer 1, an n ⁺ -type drain layer is provided, and the n ⁺ -type emitter region 4, the emitter electrode 10 and the collector electrode 11 are n ⁺ -type source region, source electrode and drain electrode, respectively. In addition, a silicon (Si) semiconductor may be used as a semiconductor material of the semiconductor device according to the first embodiment, and a semiconductor having a wider band gap than silicon, such as a silicon carbide semiconductor (hereinafter referred to as a wide band gap semiconductor) ) May be used.

  As described above, according to the first embodiment, since the p-type buried region is in the floating state in the on state, minority carriers (holes) are drawn from the p-type buried region to the emitter electrode. Absent. Therefore, conductivity modulation is not hindered in a device utilizing conductivity modulation effect such as IGBT. This can prevent the deterioration of the on-resistance characteristic. That is, for example, the on-resistance characteristic can be improved as compared with the case where the p-type embedded region is fixed to the emitter potential in the on state as in Patent Document 3 described above.

Further, for example, when the p-type buried region is in the floating state in the off state as in Patent Document 3 described above, the potential difference between the gate electrode and the p-type buried region becomes large depending on the potential state of the p-type buried region. A high electric field may be concentrated on the insulating layer. On the other hand, according to the first embodiment, in the off state, the p-type buried region is electrically connected to the p ⁻ -type base region by the p ^- type inversion layer and fixed at the emitter potential (eg, ground). As a result, even if a high voltage is applied to the collector electrode, the potential difference between the gate electrode and the p-type buried region (voltage applied to the deposited insulating layer) becomes about the gate voltage, so the high electric field is not concentrated on the deposited insulating layer . Further, by fixing the p-type buried region to the emitter potential, the portion along the gate insulating film of the n ⁻ -type drift layer is also maintained at a potential close to the emitter potential, and the voltage applied to the gate insulating film is about the gate voltage It becomes. Therefore, the high electric field is not concentrated on the gate insulating film. Therefore, the withstand voltage characteristics can be improved as compared with the conventional case, and the occurrence of the operation failure or the dielectric breakdown can be prevented. Further, since the high electric field is not concentrated on the gate oxide film, the allowable upper limit of the collector voltage can be increased to such an extent that an electric field close to the maximum electric field strength of the semiconductor material is generated. As a result, for example, using a wide band gap semiconductor, it is possible to increase the breakdown voltage to a state close to the characteristic limit of the wide band gap semiconductor material.

Further, according to the first embodiment, a p-type inversion layer is formed inside the n ⁻ -type drift layer in the off state, and the p ⁻ -type base region and the p-type buried region are formed by the p-type inversion layer. the order can be electrically connected, for example p as disclosed in Patent Document 3 ^- it is not necessary to form a diffusion region for connecting the type base region and the p-type buried region. Therefore, the manufacturing process can be simplified as compared with the prior art.

Second Embodiment
Next, the structure of the semiconductor device according to the second embodiment will be described. FIG. 2 is a cross-sectional view showing the structure of the semiconductor device according to the second embodiment. The semiconductor device differs from that according to the semiconductor device according to the first embodiment of the second embodiment, n ^- inside the type drift layer 2, n ^- -type drift layer 2 high n-type diffusion region impurity concentration than (or less , N-type blocking region (fifth semiconductor region) 13 is provided. The n-type blocking region 13 acts as a barrier to minority carriers (holes) inside the n ⁻ -type drift layer 2 when in the on state, and has a function of enhancing the minority carrier accumulation effect. As a result, the carrier density of the n ⁻ -type drift layer 2 can be increased, so that the on-resistance can be reduced.

n-type blocking region 13, n ^- type drift layer 2, p ^- between type base region 3 and the p-type buried region 9, p ^- be provided apart -type base region 3 and the p-type buried region 9 Is preferred. The reason is as follows. The electric field strength in the vicinity of the pn junction 21 between the p ⁻ type base region 3 and the n ⁻ type drift layer 2 or the electric field strength in the vicinity of the bottom of the trench 5 (near the p type buried region 9 and the deposited insulating layer 6) Rate limiting. This is because it is preferable not to provide the n-type blocking region 13 so that the impurity concentration of the n ⁻ -type drift layer 2 does not increase at the portion where the breakdown voltage is limited. That is, by providing the n-type blocking region 13 between the p ⁻ -type base region 3 and the p-type buried region 9, the n-type blocking region 13 substantially does not change the electric field strength at the bottom of the trench 5 and the p-type buried region 9. A blocking area 13 can be provided. Thus, the on-resistance can be reduced without lowering the withstand voltage.

The impurity concentration of the n-type blocking region 13 is higher than the impurity concentration of the n ⁻ -type drift layer 2. In addition, the impurity concentration of n-type blocking region 13 is high even if the electric field intensity on the collector side of p-type buried region 9 does not exceed the breakdown voltage limit (for example, about 1 × 10 ¹⁷ / cm ³ ). Good. The thickness of the n-type blocking region 13 is, for example, about several μm. The n-type blocking region 13 may be an epitaxial layer or, for example, a diffusion region formed by ion implantation. When forming the n-type blocking region 13 made of the epitaxial layer, for example, the p ⁺ -type starting substrate comprising the p ⁺ -type collector layer 1, n ^- after depositing a type drift layer 2 and the n-type blocking regions 13, again n ^- n by depositing the type drift layer 2 ^- may be adjusted thickness of the type drift layer 2. When forming the n-type blocking region 13 composed of a diffusion region by ion implantation, for example, the acceleration energy of ion implantation is variously changed to an n-type blocking region at a predetermined depth from the first major surface of the n ⁻ -type drift layer 2 It is sufficient to form 13.

n-type blocking region 13, n ^- across the type drift layer 2, for example p ^- type base region 3 and the n ^- may be opposed to the pn junction 21 over the entire surface between the type drift layer 2. In addition, the n-type blocking region 13 may be provided closer to the collector than the bottom of the trench 5. In this case, by setting the impurity concentration and thickness of the n-type blocking region 13 appropriately, the reduction in breakdown voltage can be minimized.

  As described above, according to the second embodiment, the same effect as that of the first embodiment can be obtained. Further, according to the second embodiment, the on-resistance characteristic can be further improved by providing the n-type blocking region.

Third Embodiment
Next, the structure of the semiconductor device according to the third embodiment will be described. FIG. 3 is a cross-sectional view showing the structure of the semiconductor device according to the third embodiment. The semiconductor device according to the third embodiment differs from the semiconductor device according to the second embodiment in that the p-type buried region 9 is always in a floating state (both in the on state and in the off state).

In the third embodiment, the off-state, n ^- inside the type drift layer 2, p ^- type base region 3 and n ^- depletion from the pn junction 21 between the type drift layer 2 (not shown) It spreads, and the vicinity of the pn junction 21 becomes a peak of electric field strength. Further, n ^- in the interior of the type drift layer 2, p-type buried region 9 and the n ^- depletion layer from the pn junction 22 between the type drift layer 2 (not shown) is spread, in the vicinity of the pn junction 22 A peak of electric field strength is formed. That is, the peaks of the electric field intensity can be dispersed at two places inside the n ⁻ -type drift layer 2, and the maximum peak value of the electric field intensity can be reduced. Therefore, the withstand voltage can be improved. Further, by providing the n-type blocking region 13 inside the n ^-- type drift layer 2, the on-resistance characteristic can be improved as in the second embodiment.

  As described above, according to the third embodiment, the same effect as that of the second embodiment can be obtained.

Embodiment 4
Next, the structure of the semiconductor device according to the fourth embodiment will be described. FIG. 4 is a cross-sectional view showing the structure of the semiconductor device according to the fourth embodiment. The semiconductor device according to the fourth embodiment is different from the semiconductor device according to the third embodiment in that the semiconductor device according to the fourth embodiment is always fixed at the emitter potential at a depth deeper than that of the trench 5 in a portion sandwiched between adjacent trenches 5. The point is that a p-type region (hereinafter referred to as a p-type column region (third semiconductor region)) 14 is provided. In the fourth embodiment, the p-type embedded region is not provided. Further, n-type blocking region (fifth semiconductor region) 15 is near the point (deposited insulating layer 6 which determines the rate of breakdown voltage, and which will be described later p-type column region 14 and n ^- pn junction near 23 between the type drift layer 2 ) Is provided on the collector side of the bottom of the trench 5 so that the impurity concentration of the n ⁻ -type drift layer 2 does not increase.

The p-type column region 14 is provided between the adjacent trenches 5 so as to be separated from the trench 5 and electrically connected to the emitter electrode 10. The depth of the p-type column region 14 is deeper than the depth of the trench 5. For example, the p-type column region 14 may penetrate the n ⁺ -type emitter region 4 and the p ⁻ -type base region 3 to reach the n-type blocking region 15 provided inside the n ⁻ -type drift layer 2 . By providing the p-type column region 14 deeper than the trench 5, the electric field can be concentrated on the pn junction 23 between the p-type column region 14 and the n ⁻ -type drift layer 2. The electric field strength can be reduced. The impurity concentration of the p-type column region 14 can be variously changed in accordance with the design conditions, and may be high enough to prevent degradation of energy levels.

As described above, according to the fourth embodiment, the on-resistance characteristic can be improved as in the second embodiment by providing the n-type blocking region inside the n ⁻ -type drift layer.

Fifth Embodiment
Next, the structure of the semiconductor device according to the fifth embodiment will be described. FIG. 5 is a cross-sectional view showing the structure of the semiconductor device according to the fifth embodiment. The semiconductor device according to the fifth embodiment is different from the semiconductor device according to the fourth embodiment in that the p ⁻ -type base region 3 and the p-type embedded region (sixth semiconductor region) are separated by the p-type column region (seventh semiconductor region) 16. ) And 9). That is, similar to the p-type column region of the fourth embodiment, p ^- type base region 3, p-type column region 16 and p-type embedded region 9 allow trench 5 to be interposed between adjacent trenches 5. Also, a p-type region provided at a deep depth and always fixed to the emitter potential is configured. Specifically, p type column region 16 is formed of gate insulating film 7 provided on the sidewall of trench 5 between p ⁻ type base region 3 and p type buried region 9 of n ⁻ type drift layer 2. It is provided along. The configuration of the n-type blocking region 15 is the same as that of the fourth embodiment.

  As described above, according to the fifth embodiment, the same effect as that of the fourth embodiment can be obtained.

  The present invention can be variously modified without departing from the spirit of the present invention. In each of the embodiments described above, for example, the dimensions of each part, the impurity concentration, and the like are variously set according to the required specifications. In each of the above-described embodiments, the first conductivity type is n-type and the second conductivity type is p-type, but in the present invention, the first conductivity type is p-type and the second conductivity type is n-type. The same holds true.

  As described above, the semiconductor device according to the present invention is useful for a trench gate MOS type semiconductor device having a high withstand voltage.

1 p ⁺ type collector layer 2 n ⁻ type drift layer 3 p ⁻ type base region 4 n ⁺ type emitter region 5 trench 6 deposited insulating layer 7 gate insulating film 8 gate electrode 9 p type buried region 10 emitter electrode 11 collector electrode 12 p Type inversion layer 13, 15 n-type blocking region 14, 16 p-type column region 21 p ^- type base region and n ^- type drift layer between pn junctions 22 p-type buried region and n ^- type drift layer Pn junction 23 pn junction between p-type column region and n ^- type drift layer

Claims (8)

A first semiconductor region of a second conductivity type provided on the first main surface side of the semiconductor layer of the first conductivity type;
A second semiconductor region of a first conductivity type selectively provided inside the first semiconductor region;
A trench penetrating the second semiconductor region and the first semiconductor region to reach the semiconductor layer;
An insulating layer buried at the bottom of the trench;
A gate insulating film provided along the sidewall of the trench inside the trench;
A gate electrode provided inside the gate insulating film and on the surface of the insulating layer inside the trench;
A third semiconductor region of a second conductivity type that is selectively provided inside the semiconductor layer to surround the bottom of the trench and that faces the gate electrode with the insulating layer interposed therebetween;
A fourth semiconductor region provided on the second main surface side of the semiconductor layer;
A first electrode electrically connected to the first semiconductor region and the second semiconductor region;
A second electrode electrically connected to the fourth semiconductor region;
Equipped with
The gate electrode is a second conductivity type semiconductor layer or a polysilicon layer doped with a second conductivity type impurity,
A first conductivity type inversion layer is formed along the gate insulating film in a portion of the first semiconductor region which is larger than 0 V and is sandwiched between the second semiconductor region and the semiconductor layer. When a second gate voltage in a range of less than a gate threshold voltage which is a lowest voltage of one gate voltage is applied, the semiconductor layer is provided in a portion sandwiched between the first semiconductor region and the third semiconductor region. A semiconductor device characterized in that a second conductivity type inversion layer is generated along a gate insulating film, and the first semiconductor region and the third semiconductor region are electrically connected by the second conductivity type inversion layer.   The semiconductor layer may further include a fifth semiconductor region of a first conductivity type higher in impurity concentration than the semiconductor layer, which is selectively provided apart from the first semiconductor region and the third semiconductor region inside the semiconductor layer. The semiconductor device according to claim 1, characterized in that   The semiconductor device according to claim 2, wherein the fifth semiconductor region is provided in the semiconductor layer between the first semiconductor region and the third semiconductor region.   4. The semiconductor layer according to claim 1, wherein the semiconductor layer is set to have an impurity concentration which causes the second conductivity type inversion layer to be generated when the second gate voltage is applied to the gate electrode. Semiconductor device according to claim 1.   5. The semiconductor layer according to claim 1, wherein the semiconductor layer is set to have an impurity concentration such that the second conductivity type inversion layer does not occur when the first gate voltage is applied to the gate electrode. The semiconductor device described in one.   The semiconductor device according to any one of claims 1 to 5, wherein the third semiconductor region is in a floating state when the first gate voltage is applied to the gate electrode.   The semiconductor layer is selectively provided in contact with the first semiconductor region and the third semiconductor region between the first semiconductor region and the third semiconductor region inside the semiconductor layer, and from the first semiconductor region side The semiconductor device according to any one of claims 1 to 6, further comprising a sixth semiconductor region of a second conductivity type reaching a position deeper than the bottom of the trench.   The semiconductor device according to any one of claims 1 to 7, comprising the fourth semiconductor region of the second conductivity type.

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