JP2014203846A - High frequency semiconductor module - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a high frequency semiconductor module whose performance can be made high.SOLUTION: A high frequency semiconductor module 10 in an embodiment comprises: a package 13; a first semiconductor element 17; a second semiconductor element 18; an inter-stage circuit board 15; a first inter-stage high frequency signal line 25a; a second inter-stage high frequency signal line 25b; and a first capacitor 38. The inter-stage circuit board 15 is arranged between the first semiconductor element 17 and the second semiconductor element 18, and has a first pattern 28 for a monitor and a second pattern 29 for a second monitor on its surface. The first inter-stage high frequency signal line 25a and the second inter-stage high frequency signal line 25b are provided on the surface of the inter-stage circuit board 15, so that the other end of the first inter-stage high frequency signal line 25a and one end of the first inter-stage high frequency signal line 25b are isolated from each other. The first capacitor 38 is arranged on the other end of the first inter-stage high frequency signal line 25a.

Description

  Embodiments described herein relate generally to a high-frequency semiconductor module.

  As a conventional high-frequency semiconductor module in which two semiconductor elements are connected in series with an RF line, two modules are used to individually monitor the operation of the preceding semiconductor element and the subsequent semiconductor element. There is known a high-frequency semiconductor module in which an RF line for connecting the semiconductor elements is divided and a monitor pattern is provided in the vicinity of the RF line.

  This high-frequency semiconductor module connects the divided RF lines with wires during normal operation. However, when the preceding semiconductor element approaches saturation operation, the signal output from the semiconductor element is distorted, and harmonics having a frequency twice or three times the signal frequency are generated. Since a signal including such harmonics and having distortion is input to the subsequent semiconductor element, the harmonics included in the signal output from the subsequent semiconductor element are further increased, and the distortion is further increased. That is, in the conventional high-frequency semiconductor module, when the input signal level is raised in order to output a desired high-power signal, there is a problem that a highly distorted signal including a large harmonic is output.

  Further, in order to perform high-performance operation (high gain, high-efficiency operation) of the high-frequency semiconductor module, when different bias voltages are supplied to the output side of the preceding semiconductor element and the input side of the subsequent semiconductor element, the high-frequency semiconductor module is divided. Since a potential difference is generated between the RF lines and a current flows between them, the power supply may be short-circuited. Therefore, it is difficult to operate the high-frequency semiconductor module with high performance.

JP 2012-151274 A

  An object of the embodiment is to provide a high-frequency semiconductor module capable of improving performance.

  The high-frequency semiconductor module according to the embodiment includes a package, a first semiconductor element, a second semiconductor element, an inter-stage circuit board, a first inter-stage high-frequency signal line, a second inter-stage high-frequency signal line, and a first 1 capacitor. The package has an input terminal, an output terminal, a first monitor terminal, and a second monitor terminal. The first semiconductor element is disposed in the package and electrically connected to the input terminal. The second semiconductor element is disposed in the package at a position spaced apart from the first semiconductor element, and is electrically connected to the output terminal. The interstage circuit board is disposed between the first semiconductor element and the second semiconductor element, and has a first monitor pattern connected to the first monitor terminal on the surface and the second monitor circuit. A second monitor pattern connected to the monitor terminal. The first inter-stage high-frequency signal line is provided on the surface of the inter-stage circuit board, and one end thereof is connected to the first semiconductor element. The second inter-stage high-frequency signal line has one end provided on the surface of the inter-stage circuit board at a position spaced from the first inter-stage high-frequency signal line, and the other end is the second inter-stage circuit signal board. Connected to the semiconductor element. The first capacitor is disposed on the other end of the first inter-stage high-frequency signal line.

  The high-frequency semiconductor module according to the embodiment includes a package, a first semiconductor element, a second semiconductor element, an inter-stage circuit board, a first inter-stage high-frequency signal line, a second inter-stage high-frequency signal line, A third inter-stage high frequency signal line and a capacitor are provided. The package has an input terminal, an output terminal, and a monitor terminal. The first semiconductor element is disposed in the package and electrically connected to the input terminal. The second semiconductor element is disposed in the package at a position spaced apart from the first semiconductor element, and is electrically connected to the output terminal. The inter-stage circuit board is disposed between the first semiconductor element and the second semiconductor element, and has a monitor pattern connected to the monitor terminal on the surface. The first inter-stage high-frequency signal line is provided on the surface of the inter-stage circuit board, and one end thereof is connected to the first semiconductor element. The second inter-stage high-frequency signal line has one end provided on the surface of the inter-stage circuit board at a position spaced from the first inter-stage high-frequency signal line, and the other end is the second inter-stage circuit signal board. Connected to the semiconductor element. The third inter-stage high-frequency signal line is disposed between the first inter-stage high-frequency signal line and the second inter-stage high-frequency signal line on the surface of the inter-stage circuit board. It is provided so as to be separated from the signal line. The capacitor is disposed on the third inter-stage high-frequency signal line.

  The high-frequency semiconductor module according to the embodiment includes a package, a first semiconductor element, a second semiconductor element, an inter-stage circuit board, a first inter-stage high-frequency signal line, a second inter-stage high-frequency signal line, An interdigital filter. The package has an input terminal and an output terminal. The first semiconductor element is disposed in the package and electrically connected to the input terminal. The second semiconductor element is disposed in the package at a position spaced apart from the first semiconductor element, and is electrically connected to the output terminal. The interstage circuit board is disposed between the first semiconductor element and the second semiconductor element, and a monitor terminal is provided on a surface thereof. The first inter-stage high-frequency signal line is provided on the surface of the inter-stage circuit board, and one end thereof is connected to the first semiconductor element. The second inter-stage high-frequency signal line has one end provided on the surface of the inter-stage circuit board at a position separated from the first inter-stage high-frequency signal line, and the other end is the second inter-stage circuit line. Connected to the semiconductor element. The interdigital filter is provided between the first inter-stage high-frequency signal line and the second inter-stage high-frequency signal line on the surface of the inter-stage circuit board.

It is a top view which shows the high frequency semiconductor module which concerns on 1st Embodiment. FIG. 2 is a plan view showing the configuration when monitoring the operation of the first semiconductor element in the high-frequency semiconductor module shown in FIG. 1. FIG. 3 is a plan view showing a configuration when monitoring the operation of a second semiconductor element in the high-frequency semiconductor module shown in FIG. 1. It is a top view which shows the high frequency semiconductor module which concerns on 2nd Embodiment. FIG. 5 is a plan view showing a configuration when the operations of the first semiconductor element and the second semiconductor element are individually monitored in the high-frequency semiconductor module shown in FIG. 4. It is a top view which shows the high frequency semiconductor module which concerns on 3rd Embodiment. FIG. 7 is a plan view showing the configuration when monitoring the operation of the first semiconductor element in the high-frequency semiconductor module shown in FIG. 6. FIG. 7 is a plan view showing a configuration when the operation of the second semiconductor element is monitored in the high-frequency semiconductor module shown in FIG. 6. It is a top view which shows the modification of the high frequency semiconductor module which concerns on 3rd Embodiment. It is a top view which shows the high frequency semiconductor module which concerns on 4th Embodiment. FIG. 11 is a plan view showing the configuration when monitoring the operation of the first semiconductor element in the high-frequency semiconductor module shown in FIG. 10. FIG. 11 is a plan view showing the configuration when monitoring the operation of the second semiconductor element in the high-frequency semiconductor module shown in FIG. 10. It is a top view which shows the high frequency semiconductor module which concerns on 5th Embodiment. It is a top view which shows the high frequency semiconductor module which concerns on 6th Embodiment. FIG. 15 is a plan view showing a configuration when the operation of the first semiconductor element is monitored in the high-frequency semiconductor module shown in FIG. 14. FIG. 15 is a plan view showing the configuration when monitoring the operation of the second semiconductor element in the high-frequency semiconductor module shown in FIG. 14. It is a top view which shows the high frequency semiconductor module which concerns on 7th Embodiment. FIG. 18 is a plan view showing the configuration when monitoring the operation of the first semiconductor element in the high-frequency semiconductor module shown in FIG. 17. FIG. 18 is a plan view showing the configuration when monitoring the operation of the second semiconductor element in the high-frequency semiconductor module shown in FIG. 17.

  Hereinafter, the present embodiment will be described with reference to the drawings. In addition, in each figure, the same code | symbol is attached | subjected about the same location. In each embodiment described below, the FET chip, the circuit board, and the matching circuit are separate parts, but they are not necessarily separate parts. That is, it includes a case where these components are integrally configured, such as MMIC.

(First embodiment)
FIG. 1 is a plan view showing the high-frequency semiconductor module according to the first embodiment. In the high frequency semiconductor module 10 shown in FIG. 1, an input side circuit board 14, an interstage circuit board 15, and an output side circuit board 16 are input in this order in a package 13 provided with an input terminal 11 and an output terminal 12. Between the terminal 11 and the output terminal 12, it arrange | positions in the linear form in the position mutually spaced apart. A first semiconductor element 17 is disposed between the input side circuit board 14 and the interstage circuit board 15, and a second semiconductor element 17 is disposed between the interstage circuit board 15 and the output side circuit board 16. The semiconductor element 18 is arranged. Each of the first semiconductor element 17 and the second semiconductor element 18 is a semiconductor amplifying element such as a GaAs FET or a GaN HEMT.

  On the input side circuit board 14, an input high-frequency signal line 19 made of, for example, gold or nickel (hereinafter, a high-frequency signal line made of, for example, gold or nickel is referred to as an RF line) is provided. Yes. One end of the input RF line 19 is connected to the input terminal 11 by a connection conductor 20, and the other end of the input RF line 19 is connected to the first semiconductor element 17 by a connection conductor 21. .

  The connection conductors 20 and 21 described above are bonding wires, for example, but may be metal foils or the like. Similarly, each connection conductor described below is a bonding wire, a metal foil, or the like.

  Similarly, an output RF line 22 is provided on the output side circuit board 16. One end of the output RF line 22 is connected to the second semiconductor element 18 by a connection conductor 23, and the other end of the output RF line 22 is connected to the output terminal 12 by a connection conductor 24. Yes.

  On the interstage circuit board 15, an interstage RF line is provided. The interstage RF line is constituted by a first interstage RF line 25a and a second interstage RF line 25b which are electrically insulated from each other. One end of the first interstage RF line 25a is connected to the first semiconductor element 17 by a connection conductor 26, and the other end of the first interstage RF line 25a is connected to the second interstage RF line 25a. It is in a state of being electrically insulated from one end of the RF line 25b for use. The other end of the second interstage RF line 25 b is connected to the second semiconductor element 18 by a connection conductor 27.

  Further, on the interstage circuit board 15, a first monitor pattern 28 and a second monitor pattern 29 are provided at positions separated from the interstage RF lines 25 a and 25 b. These monitor patterns 28 and 29 are provided at positions where the interstage RF lines 25 a and 25 b are sandwiched by these patterns 28 and 29. The first and second monitor patterns 28 and 29 are provided so that the longitudinal direction of the patterns 28 and 29 intersects the longitudinal direction of the interstage RF lines 25a and 25b, respectively. These patterns 28 and 29 are provided so that the impedance is, for example, 50Ω. It is to be noted that the lengths of the monitor patterns 28 and 29 are preferably shorter in consideration of the monitor application.

  Of the first monitor pattern 28, the end far from the interstage RF lines 25 a and 25 b is connected to a first monitor terminal 30 provided in the package 13 by a connection conductor 31. Similarly, the end of the second monitor pattern 29 far from the interstage RF lines 25 a and 25 b is connected to the second monitor terminal 32 provided in the package 13 by the connection conductor 33. Yes.

  A matching circuit pattern 34 for matching the impedance of the input terminal 11 and the input RF line 19 with the impedance of the first semiconductor element 17 is provided on the input side circuit board 14. Similarly, a matching circuit pattern 35 for matching the impedance of the output terminal 12 and the output RF line 22 with the impedance of the second semiconductor element 18 is provided on the output circuit board 16. On the interstage circuit board 15, a matching circuit pattern 36 for matching the impedance of the first interstage RF line 25a with the impedance of the first semiconductor element 17, and the second interstage RF A matching circuit pattern 37 for matching the impedance of the line 25a and the impedance of the second semiconductor element 18 is provided. Since the matching circuit patterns 34, 35, 36, and 37 are thus provided, the reflection of the RF signal at each portion connected by the connection conductors 21, 23, 26, and 27 is suppressed.

  Each of the matching circuit patterns 34, 35, 36, and 37 described above is not necessarily provided on the interstage circuit board 15, and may be configured by another component such as a chip capacitor or a dielectric substrate. Good.

  In FIG. 1, parts not related to RF such as a bias circuit are omitted.

  In such a high-frequency semiconductor module 10, for example, a microchip capacitor is mounted as the capacitor 38 on the other end of the first interstage RF line 25 a. The capacitor 38 is mounted on the other end of the first inter-stage RF line 25a by, for example, a conductive adhesive or solder.

  The capacitor 38 may be a thin film capacitor formed simultaneously with the formation of the interstage circuit board 15. When the capacitor 38 is a thin film capacitor, the conductor pattern having the same function as a thin film capacitor and a conductor such as a wire connected to the thin film capacitor can be formed integrally with the formation of the interstage circuit board 15. Good.

  During normal operation of the high-frequency semiconductor module 10 described above (when the first semiconductor element 17 and the second semiconductor element 18 are connected in series), the capacitor 38 and the second inter-stage RF line are used. The one end of 25b is connected by a connection conductor 39. Thereby, an LC resonance circuit is formed between the first semiconductor element 17 and the second semiconductor element 18.

  That is, when the capacitor 38 and one end of the second inter-stage RF line 25b are connected by the connection conductor 39, the capacitance C of the capacitor 38, the inductance of the connection conductor 39, and the inductance component of the capacitor 38 itself slightly The LC resonance circuit is formed by the combined inductance L. This LC resonance circuit has a characteristic that the attenuation characteristic becomes larger as it goes away from its own resonance frequency f toward the high frequency side and the low frequency side. Therefore, by substantially matching the resonance frequency f of the LC resonance circuit with the frequency f of a high-frequency signal (hereinafter referred to as an RF signal) input to the high-frequency semiconductor module 10, the LC resonance circuit is Undesirable waves such as high-order harmonics that are remarkably generated during the saturation operation of the semiconductor element 17 and half-frequency generated by a loop circuit formed between the first semiconductor element 17 and the second semiconductor element 18. Is greatly attenuated.

  Note that the resonance frequency f of the LC resonance circuit described above is calculated by f = 1 / {2 × π × √ (L × C)}. Therefore, by appropriately determining the diameter, length, and number of capacitors 38 and connecting conductors 39, the resonance frequency f of the LC resonance circuit substantially matches the frequency f of the RF signal input to the high-frequency semiconductor module 10. Can be made.

  Further, as described above, it is preferable that the resonance frequency f of the LC resonance circuit substantially matches the frequency f of the RF signal input to the high-frequency semiconductor module 10, but the resonance frequency f is input to the high-frequency semiconductor module 10. If the frequency f of the RF signal is ½ or more and twice or less of the frequency f, high-order harmonics and loop oscillation can be sufficiently attenuated.

  When an RF signal (RFin) is input from the input terminal 11 of the high-frequency semiconductor module 10 during such normal operation, predetermined signal processing is performed in the first semiconductor element 17. The RF signal output from the first semiconductor element 17 is input to the LC resonance circuit via the first interstage RF line 25a. In the LC resonance circuit, an unnecessary wave or the like included in the RF signal output from the first semiconductor element 17 is attenuated, and the RF signal in which the unnecessary wave is attenuated is transmitted through the second interstage RF line 25b. Are input to the semiconductor element 18. An RF signal (RFout) that has undergone predetermined signal processing in the second semiconductor element 18 is output from the output terminal 12 of the high-frequency semiconductor module 10.

  Next, a method for monitoring the operations of the first semiconductor element 17 and the second semiconductor element 18 in the high-frequency semiconductor module 10 will be described. The method for monitoring the overall operation of the high-frequency semiconductor module 10 is realized in the configuration shown in FIG.

  FIG. 2 is a plan view showing the high-frequency semiconductor module 10 when the operation of the first semiconductor element 17 is monitored. FIG. 3 is a plan view showing the high-frequency semiconductor module 10 when the operation of the second semiconductor element 18 is monitored.

  As shown in FIG. 2, when the operation of the first semiconductor element 17 is monitored, a capacitor 38 mounted on the first interstage RF line 25a and one end of the second interstage RF line 25b. The connection conductor 39 that connects the two parts is removed, and the first interstage RF line 25a, the first monitor pattern 28, and the connection conductor 40 are connected.

  When an RF signal (RFin) is input from the input terminal 11 of such a high-frequency semiconductor module 10, predetermined signal processing is performed in the first semiconductor element 17. The RF signal output from the first semiconductor element 17 propagates through the first monitor pattern 28 and is output from the first monitor terminal 30 (RFout).

  Further, as shown in FIG. 3, when the operation of the second semiconductor element 18 is monitored, the capacitor 38 mounted on the first interstage RF line 25a and the second interstage RF line 25b are used. The connection conductor 39 that connects to one end of the second connection is removed, and the second interstage RF line 25 b, the second monitor pattern 29, and the connection conductor 41 are connected.

  When an RF signal (RFin) is input from the second monitor terminal 32 of such a high-frequency semiconductor module 10, the RF signal propagates through the second monitor pattern 29 and is input to the second semiconductor element 18. Predetermined signal processing is performed in the two semiconductor elements 18. The RF signal output from the second semiconductor element 18 is output from the output terminal 12 (RFout).

  In this way, by monitoring the RF signal output from the first monitor terminal 30 and the RF signal output from the output terminal 12, the operations of the first semiconductor element 17 and the second semiconductor element 18 are controlled. Each can be monitored. The RF signals output from the terminals 30 and 12 are input to a measuring instrument such as a vector network analyzer, for example, so that the gain and reflection coefficient of the first semiconductor element 17 and the second semiconductor element 18 can be obtained. Can be confirmed. By adjusting the matching circuit patterns 34, 35, 36, and 37 on the circuit boards 14, 15, and 16 while confirming the gain, reflection coefficient, and the like, performance degradation of the high-frequency semiconductor module 10 is suppressed.

  According to the high-frequency semiconductor module 10 according to the present embodiment described above, the LC resonance circuit is provided between the first semiconductor element 17 and the second semiconductor element 18 during normal operation. The higher-order harmonics output together with the RF signal from the semiconductor element 17 can be suppressed from being input to the second semiconductor element 18. Therefore, distortion of the output signal can be reduced. Furthermore, loop oscillation between the first semiconductor element 17 and the second semiconductor element 18 can be suppressed.

  Even if different bias voltages are supplied to the output side of the first semiconductor element 17 and the input side of the second semiconductor element 18, the LC resonance circuit is provided between them, so that the potentials are mutually different. Is prevented from flowing between the first inter-stage RF line 25a and the second inter-stage RF line 25b. As a result, it is possible to suppress a short circuit of the power supply that supplies the bias voltage to each of the semiconductor elements 17 and 18, and the high-frequency semiconductor module 10 can be operated with high performance.

  That is, according to the present embodiment, the high-frequency semiconductor module 10 can be improved in performance.

(Second Embodiment)
FIG. 4 is a plan view showing the high-frequency semiconductor module 50 according to the second embodiment. Compared with the high-frequency semiconductor module 10 shown in FIG. 1, the high-frequency semiconductor module 50 shown in FIG. 4 is provided with the first inter-stage RF line 25a and the first monitor pattern 28 ′ as an integrated pattern. The second difference is that the second inter-stage RF line 25b and the second monitor pattern 29 'are provided as an integral pattern.

  Further, the first monitor pattern 28 ′ has a length of λ / 4, where λ is the wavelength of the RF signal input to the high frequency semiconductor module 50. One end of the first monitor pattern 28 ′ far from the interstage RF lines 25 a and 25 b is connected to the first monitor terminal 30 and connected to the ground via the capacitor 51. In a similar manner, the second monitor pattern 29 ′ has a length of λ / 4. One end of the second monitor pattern 29 ′ far from the interstage RF lines 25 a and 25 b is connected to the second monitor terminal 32 and is connected to the ground via the capacitor 52.

  Thus, by providing the first monitor pattern 28 ′ and the second monitor pattern 29 ′, these patterns 28 ′ and 29 ′ are opened in view of the RF signal output from the first semiconductor element 17. (Open). Therefore, even during normal operation, the RF signal output from the first semiconductor element 17 is suppressed from being propagated to the first monitor pattern 28 'and the second monitor pattern 29'.

  Since the normal operation of the high-frequency semiconductor module 50 is the same as that of the high-frequency semiconductor module 10 according to the first embodiment, the description thereof is omitted.

  FIG. 5 is a plan view showing the high-frequency semiconductor module 50 when the operations of the first semiconductor element 17 and the second semiconductor element 18 are individually monitored. As shown in FIG. 5, when individually monitoring the operations of the first semiconductor element 17 and the second semiconductor element 18, the capacitor 38 and one end of the second interstage RF line 25b are connected. While removing from the connection conductor 39, the first monitor pattern 28 'and the second monitor pattern 29' are removed from the ground.

  When an RF signal (RF1in) is input from the input terminal 11 of such a high-frequency semiconductor module 50, predetermined signal processing is performed in the first semiconductor element 17, and the RF signal propagates through the first monitor pattern 28 '. Then, it is output from the first monitor terminal 30 (RF1out). When an RF signal (RF2in) is input from the second monitor terminal 32, the RF signal propagates through the second monitor pattern 29 'and is input to the second semiconductor element 18, and the second semiconductor element 18 is input. Is subjected to predetermined signal processing, and the RF signal is output from the output terminal 12 (RF2in).

  In this way, by monitoring the RF signal output from the first monitor terminal 30 and the RF signal output from the output terminal 12, the operations of the first semiconductor element 17 and the second semiconductor element 18 are controlled. Each of the high frequency semiconductor modules 50 can be monitored, and the performance degradation of the high frequency semiconductor module 50 is suppressed by adjusting the matching circuit patterns 34, 35, 36, 37 on the circuit boards 14, 15, 16 based on the monitoring results.

  Also in the high-frequency semiconductor module 50 according to the present embodiment described above, the LC resonance circuit is provided between the first semiconductor element 17 and the second semiconductor element 18 during normal operation. The high-order harmonic component output together with the RF signal from the semiconductor element 17 can be suppressed from being input to the second semiconductor element 18. Therefore, distortion of the output signal can be reduced. Furthermore, loop oscillation between the first semiconductor element 17 and the second semiconductor element 18 can be suppressed.

  Even if different bias voltages are supplied to the output side of the first semiconductor element 17 and the input side of the second semiconductor element 18, the LC resonance circuit is provided between them, so that the potentials are mutually different. Is prevented from flowing between the first inter-stage RF line 25a and the second inter-stage RF line 25b. As a result, it is possible to suppress a short circuit of the power supply that supplies the bias voltage to each of the semiconductor elements 17 and 18, and the high-frequency semiconductor module 50 can be operated with high performance.

  That is, according to the present embodiment, the high-frequency semiconductor module 50 can be improved in performance.

(Third embodiment)
FIG. 6 is a plan view showing a high-frequency semiconductor module 60 according to the third embodiment. The high frequency semiconductor module shown in FIG. 6 differs from the high frequency semiconductor module 10 according to the first embodiment shown in FIG. 1 in the configuration of the interstage RF line.

  In the high-frequency semiconductor module 60, a third stage electrically insulated from these lines 25a and 25b is provided between the first inter-stage RF line 25a and the second inter-stage RF line 25b. An inter-use RF line 25c is provided.

  In such a high-frequency semiconductor module 60, as in the high-frequency semiconductor module 10 shown in FIG. 1, a capacitor 38 (hereinafter referred to as the first capacitor 38 is connected to the first inter-stage RF line 25 a) The second capacitor 61 is also mounted on one end of the second interstage RF line 25b. The reason why the second capacitor 61 is mounted on one end of the second interstage RF line 25b is as follows. The second capacitor 61 is also a chip capacitor, for example, like the first capacitor 38.

  In general, the bias voltage is superimposed on the RF signal when the first and second semiconductor elements 17 and 18 are operated. In such a case, a similar signal may be input to each of the monitor terminals 30 and 32. However, depending on the configuration, a bias supply circuit is separately provided in the package 13, and only the RF signal is supplied to each of the monitor terminals 30 and 32. Sometimes you want to pass. In such a case, when monitoring the second semiconductor element 18, a bias also flows to the second monitor terminal 32. Therefore, the second capacitor 61 is mounted on one end of the second interstage RF line 25b.

  During the normal operation of the high-frequency semiconductor module 60 described above, the first capacitor 38 and one end of the third interstage RF line 25 c are connected by the connection conductor 62. Further, the other end of the third interstage RF line 25 c and the second capacitor 61 are connected by a connection conductor 63. Thereby, two LC resonance circuits are formed between the first semiconductor element 17 and the second semiconductor element 18. Therefore, high-order harmonics that are remarkably generated during the saturation operation of the first semiconductor element 17 and the like are generated by a loop circuit formed between the first semiconductor element 17 and the second semiconductor element 18. Unnecessary waves such as frequency are greatly attenuated.

  When an RF signal (RFin) is input from the input terminal 11 of the high-frequency semiconductor module 60 during such normal operation, predetermined signal processing is performed in the first semiconductor element 17. Then, the RF signal output from the first semiconductor element 17 is input to the two LC resonance circuits via the first interstage RF line 25a. In each LC resonance circuit, the unnecessary wave is attenuated, and the RF signal with the harmonic component attenuated is input to the second semiconductor element 18 via the second inter-stage RF line 25b. An RF signal that has been subjected to predetermined signal processing in the second semiconductor element 18 is output from the output terminal 12 of the high-frequency semiconductor module 60 (RFout).

  Next, a method for monitoring the operations of the first semiconductor element 17 and the second semiconductor element 18 in the high-frequency module 60 will be described. The method for monitoring the overall operation of the high-frequency module 60 is realized in the configuration shown in FIG.

  FIG. 7 is a plan view showing the high-frequency semiconductor module 60 when the operation of the first semiconductor element 17 is monitored. FIG. 8 is a plan view showing the high-frequency semiconductor module 60 when the operation of the second semiconductor element 18 is monitored.

  As shown in FIG. 7, when the operation of the first semiconductor element 17 is monitored, the first capacitor 38 and the third inter-stage RF line mounted on the first inter-stage RF line 25a. The connection conductor 62 that connects one end of 25c, and the other end of the third interstage RF line 25c and the second capacitor 61 mounted on the second interstage RF line 25b are connected. The connection conductor 63 is removed, and the first capacitor 38, the first monitor pattern 28, and the connection conductor 64 are connected.

  When an RF signal (RFin) is input from the input terminal of such a high-frequency semiconductor module 60, predetermined signal processing is performed in the first semiconductor element 17. The RF signal output from the first semiconductor element 17 propagates through the first monitor pattern 28 and is output from the first monitor terminal 30 (RFout).

  Further, as shown in FIG. 8, when the operation of the second semiconductor element 18 is monitored, the first capacitor 38 mounted on the first interstage RF line 25a and the third interstage The connection conductor 62 that connects one end of the RF line 25c, and the other end of the third interstage RF line 25c and the second capacitor 61 mounted on the second interstage RF line 25b. The connection conductor 63 to be connected is removed, and the second capacitor 61 and the second monitor pattern 29 are connected by the connection conductor 65.

  When an RF signal (RFin) is input from the second monitor terminal 32 of such a high-frequency semiconductor module 60, the RF signal propagates through the second monitor pattern 29 and is input to the second semiconductor element 18. Predetermined signal processing is performed in the two semiconductor elements 18. The RF signal output from the second semiconductor element 18 is output from the output terminal 12 (RFout).

  In this way, by monitoring the RF signal output from the first monitor terminal 30 and the RF signal output from the output terminal 12, the operations of the first semiconductor element 17 and the second semiconductor element 18 are controlled. The performance of the high-frequency semiconductor module 60 can be suppressed by adjusting the matching circuit patterns 34, 35, 36, and 37 on the circuit boards 14, 15, and 16 based on the monitoring results. it can.

  Also in the high-frequency semiconductor module 60 according to the present embodiment described above, the LC resonance circuit is provided between the first semiconductor element 17 and the second semiconductor element 18 during normal operation. The high-order harmonic component output together with the RF signal from the semiconductor element 17 can be suppressed from being input to the second semiconductor element 18. Therefore, distortion of the output signal can be reduced. Furthermore, loop oscillation between the first semiconductor element 17 and the second semiconductor element 18 can be suppressed.

  Even if different bias voltages are supplied to the output side of the first semiconductor element 17 and the input side of the second semiconductor element 18, the LC resonance circuit is provided between them, so that the potentials are mutually different. Is prevented from flowing between the first inter-stage RF line 15a and the second inter-stage RF line 25b. As a result, it is possible to suppress a short circuit of the power supply that supplies the bias voltage to each of the semiconductor elements 17 and 18, and the high-frequency semiconductor module 60 can be operated with high performance.

  That is, according to the present embodiment, the high-frequency semiconductor module 60 can be improved in performance.

  In the high-frequency semiconductor module 60 according to the present embodiment, since two LC resonance circuits are provided, the higher-order harmonic component is further prevented from being input to the second semiconductor element 18 and the output signal The distortion can be further reduced, the loop oscillation can be further suppressed, and the power supply for supplying the bias voltage to the semiconductor elements 17 and 18 can be further prevented from being short-circuited. 60 can be improved in performance.

(Modification of the third embodiment)
In the high-frequency semiconductor module 60 according to the third embodiment, since two LC circuits are provided, the performance can be improved as compared with the high-frequency semiconductor module 10 according to the first embodiment, but the loss is reduced. Increase. In order to make this loss comparable to that of the high-frequency semiconductor module 10 according to the first embodiment, a configuration as shown in FIG.

  FIG. 9 is a plan view showing a high-frequency semiconductor module 70 according to a modification of the third embodiment. In the high-frequency semiconductor module 70 shown in FIG. 9, the second capacitor 61 is provided at a position away from one end of the second interstage RF line 25b by a predetermined distance toward the second high-frequency semiconductor element 18 side. .

  During normal operation of the high-frequency semiconductor module 70, the first capacitor 38 and one end of the third interstage RF line 25c are connected by the connection conductor 62, and further, the third interstage RF line 25c. The other end of the second stage and one end of the second inter-stage RF line 25 b are connected by the connection conductor 71. Thereby, one LC resonance circuit is formed between the first semiconductor element 17 and the second semiconductor element 18. Therefore, compared with the high-frequency semiconductor module 60 according to the third embodiment, it is possible to suppress the loss reduction due to the LC resonance circuit.

  Note that the monitoring method of the first semiconductor element 17 and the second semiconductor element 18 by the high-frequency semiconductor module 70 is the same as that of the high-frequency semiconductor module 60 according to the third embodiment, and thus the description thereof is omitted.

  The high-frequency semiconductor module 70 according to the modified example described above can also achieve high performance in the same manner as the high-frequency semiconductor module 60 according to the third embodiment. Further, the high-frequency semiconductor according to the third embodiment Compared with the module 60, it is possible to suppress a reduction in loss due to the LC resonance circuit.

  However, since the second inter-stage RF line 25b between the second capacitor 61 and one end of the second inter-stage RF line 25b becomes a high-frequency stub, it flows through the second inter-stage RF line 25b. This affects the RF signal, which causes a measurement error in the monitoring result of the second semiconductor element 18.

(Fourth embodiment)
FIG. 10 is a plan view showing a high-frequency semiconductor module 80 according to the fourth embodiment. Compared with the high-frequency semiconductor module 60 according to the third embodiment shown in FIG. 6, the high-frequency semiconductor module 80 shown in FIG. 10 eliminates the second capacitor 61 and the second monitor pattern 29, and The position where the capacitor 38 'is mounted, the configuration of the third inter-stage RF line 25c', and the position of the first monitor pattern 28 "are different.

  In the high-frequency semiconductor module 80, no capacitor is provided on the first inter-stage RF line 25a and the second inter-stage RF line 25b, and on the third inter-stage RF line 25c '. Only the first capacitor 38 'is mounted.

  The third inter-stage RF line 25c 'on which the capacitor 38' is mounted has substantially the same electrical length and line as the first inter-stage RF line 25a and the second inter-stage RF line 25b. It is wide. The third inter-stage RF line 25c ′ is provided such that its own longitudinal direction intersects the longitudinal direction of the first inter-stage RF line 25a and the second inter-stage RF line 25b. It has been. Thus, the first inter-stage RF line 25a, the second inter-stage RF line 25b, and the third inter-stage RF line 25c ′ have the same high-frequency impedance on the same substrate 15, Configure circuit patterns with different transmission directions. Thus, since it has the same high frequency impedance on the same board | substrate 15, it can suppress that RF signal is reflected between these RF lines 25a, 25b, 25c, and can flow RF signal smoothly.

  The first monitor pattern 28 ″ has a longitudinal direction in the longitudinal direction of the third inter-stage RF line 25 ′ only at a position separated from the third inter-stage RF line 25 c ′. It is provided so that it may become parallel with respect to. Since there is only one monitor pattern 28 ″ in this way, there is also one monitor terminal 30 provided on the package 13 ′. The monitor pattern 28 ″ and the monitor terminal 30 are connected conductors. 81 is connected.

  During the normal operation of the high-frequency semiconductor module 80 described above, the other end of the first inter-stage RF line 25a and the capacitor 38 'are connected by the connection conductor 82. Further, in the third inter-stage RF line 25c ′, the space above the mounting position of the capacitor 38 ′ and one end of the second inter-stage RF line 25b are connected by the connection conductor 83. . As a result, an LCL resonance circuit is formed between the first semiconductor element 17 and the second semiconductor element 18. The LCL resonance circuit has the same characteristics as the LC resonance circuit. By selecting the diameter, length, and number of the capacitor 38 'and the two connection conductors 82 and 83, the LCL resonance circuit The resonance frequency f can be made to substantially coincide with the frequency f of the RF signal input to the high-frequency semiconductor module 80, or more than 1/2 of the frequency f of the RF signal input to the high-frequency semiconductor module 80, and 2 It can also be in the range of less than twice.

  When an RF signal (RFin) is input from the input terminal 11 of the high-frequency semiconductor module 80 during such normal operation, predetermined signal processing is performed in the first semiconductor element 17. The RF signal output from the first semiconductor element 17 is input to the LCL resonance circuit via the first interstage RF line 25a. In the LCL resonance circuit, the unnecessary wave included in the RF signal output from the first semiconductor element 17 is attenuated, and the RF signal in which the unnecessary wave is attenuated is transmitted through the second interstage RF line 25b. Input to the semiconductor element 18. An RF signal that has been subjected to predetermined signal processing in the second semiconductor element 18 is output from the output terminal 12 of the high-frequency semiconductor module 80 (RFout).

  Next, a method for monitoring the operations of the first semiconductor element 17 and the second semiconductor element 18 in the high-frequency module 80 will be described. Note that the method of monitoring the operation of the entire high-frequency module 80 is realized in the configuration shown in FIG.

  FIG. 11 is a plan view showing the high-frequency semiconductor module 80 when the operation of the first semiconductor element 17 is monitored. FIG. 12 is a plan view showing the high-frequency semiconductor module 80 when monitoring the operation of the second semiconductor element 18.

  As shown in FIG. 11, when the operation of the first semiconductor element 17 is monitored, the connection for connecting the third inter-stage RF line 25c ′ and one end of the second inter-stage RF line 25b. The conductor 83 is removed, and the third interstage RF line 25 c ′ and the monitor pattern 28 ″ are connected by the connection conductor 84.

  When an RF signal (RFin) is input from the input terminal 11 of such a high-frequency semiconductor module 80, predetermined signal processing is performed in the first semiconductor element 17. The RF signal output from the first semiconductor element 17 propagates through the monitor pattern 28 ″ and is output from the monitor terminal 30 (RFout).

  Also, as shown in FIG. 12, when monitoring the operation of the second semiconductor element 18, the connection conductor 82 connecting the other end of the first interstage RF line 25a and the capacitor 38 'is removed. The third inter-stage RF line 25c ′ and the monitor pattern 28 ″ are connected by the connection conductor 84 as shown in FIG.

  When an RF signal (RFin) is input from the monitor terminal 30 of such a high-frequency semiconductor module 80, the RF signal propagates through the monitor pattern 28 '' and is input to the second semiconductor element 18, and the second semiconductor element In 18, predetermined signal processing is performed. The RF signal output from the second semiconductor element 18 is output from the output terminal 12 (RFout).

  In this way, by monitoring the RF signal output from the monitor terminal 30 and the RF signal output from the output terminal 12, the operations of the first semiconductor element 17 and the second semiconductor element 18 are monitored. In addition, by adjusting the matching circuit patterns 34, 35, 36, and 37 on the circuit boards 14, 15, and 16 based on the monitoring result, it is possible to suppress the performance deterioration of the high-frequency semiconductor module 80.

  Note that the high-frequency semiconductor module 80 according to the present embodiment can be monitored with less measurement error than the high-frequency semiconductor module 60 according to the third embodiment. Therefore, it is possible to adjust the matching circuit patterns 34, 35, 36, and 37 with higher accuracy, and it is possible to further suppress the performance deterioration of the high-frequency semiconductor module 80.

  Also in the high-frequency semiconductor module 80 according to the present embodiment described above, the LCL resonance circuit is provided between the first semiconductor element 17 and the second semiconductor element 18 during normal operation. The high-order harmonic component output together with the RF signal from the semiconductor element 17 can be suppressed from being input to the second semiconductor element 18. Therefore, distortion of the output signal can be reduced. Furthermore, loop oscillation between the first semiconductor element 17 and the second semiconductor element 18 can be suppressed.

  Even if different bias voltages are supplied to the output side of the first semiconductor element 17 and the input side of the second semiconductor element 18, the LCL resonance circuit is provided between them, so that the potentials are mutually different. Is prevented from flowing between the first inter-stage RF line 25a and the second inter-stage RF line 25b. As a result, it is possible to suppress a short circuit of the power supply that supplies the bias voltage to each of the semiconductor elements 17 and 18, and the high-frequency semiconductor module 80 can be operated with high performance.

  That is, according to the present embodiment, the high-frequency semiconductor module 80 can be improved in performance.

  Furthermore, according to the high-frequency semiconductor module 80 according to the present embodiment, the number of capacitors can be reduced to one as compared with the high-frequency semiconductor module 60 according to the third embodiment. Can be realized.

(Fifth embodiment)
FIG. 13 is a plan view showing a high-frequency semiconductor module 90 according to the fifth embodiment. The high-frequency semiconductor module 90 shown in FIG. 13 differs from the high-frequency semiconductor module 70 according to the modification of the third embodiment shown in FIG. 9 in the configuration of the second inter-stage RF line 25b ′.

  In the high-frequency semiconductor module 90, one end of the second inter-stage RF line 25b ′ is cut out in a substantially U shape. In other words, two protruding portions 91 are provided at one end of the second inter-stage RF line 25b ′.

  By providing the protrusion 91 in this way, measurement errors due to the high-frequency stub, which has been a problem in the high-frequency semiconductor module 70 according to the modification of the third embodiment, are suppressed. That is, since the width of the two protruding portions 91 is narrower than the width of the second inter-stage RF line 25b ′ excluding these protruding portions 91, each protruding portion 91 is a second step excluding the protruding portion 91. Compared with the interim RF line 25b ', the high-frequency stub has a very high impedance. Therefore, the RF signal flowing through the second inter-stage RF line 25 b ′ is difficult to propagate to each protrusion 91. That is, the protrusions 91 serving as the high-frequency stubs are less likely to affect the RF signal flowing through the second interstage RF line 25b ′. As a result, the measurement error of the monitoring result of the second semiconductor element 18 is suppressed.

  During the normal operation of the high-frequency semiconductor module 90 described above, the first capacitor 38 and one end of the third interstage RF line 25 c are connected by the connection conductor 62. Further, the other end of the third inter-stage RF line 25c and the protrusion 91 of the second inter-stage RF line 25b ′ are connected by the connection conductor 92 as described above. Thereby, an LC resonance circuit is formed between the first semiconductor element 17 and the second semiconductor element 18 by the first capacitor 38 and the connection conductor 62 connected thereto. Therefore, high-order harmonics that are remarkably generated during the saturation operation of the first semiconductor element 17 and the like are generated by a loop circuit formed between the first semiconductor element 17 and the second semiconductor element 18. Unwanted waves such as frequency can be greatly attenuated.

  In addition, about the other structure at the time of normal operation | movement of this high frequency semiconductor module, and the method to monitor the 1st semiconductor element 17 and the 2nd semiconductor element 18, the high frequency semiconductor module 70 which concerns on the modification of 3rd Embodiment, and Since it is the same, description is abbreviate | omitted.

  The high-frequency semiconductor module 90 according to the present embodiment described above can achieve high performance in the same way as the high-frequency semiconductor module 70 according to the modification of the third embodiment. Compared with the high-frequency semiconductor module 60, it is possible to suppress a reduction in loss due to the LC resonance circuit.

  Furthermore, according to the high-frequency semiconductor module 90 according to the present embodiment, an increase in RF signal loss during normal operation is also suppressed as compared with the high-frequency semiconductor module 70 according to the modification of the third embodiment. That is, each protrusion 91 has high impedance, but when these protrusions 91 and the third interstage RF line 25c are connected by the connecting conductor 92 during normal operation, the second interstage including the protrusions 91 is connected. The entire line width of the general RF line 25b ′ can be regarded as substantially the same. For this reason, compared with the high frequency semiconductor module 70 which concerns on the modification of 3rd Embodiment which has a high frequency stub, the increase in the loss of RF signal at the time of normal operation can also be suppressed.

  Furthermore, according to the high-frequency semiconductor module 90 according to the present embodiment, the solder, adhesive, or the like used when mounting the second capacitor 61 on the second inter-stage RF line 25b ′ is the second capacitor 61. The third inter-stage RF line 25c and the second inter-stage RF line 15b ′ are connected without being affected by the protrusion of the solder, adhesive, etc. be able to.

  Furthermore, according to the high-frequency semiconductor module 90 according to the present embodiment, a space for connecting the connection conductor is provided as in the third inter-stage RF line 25c ′ of the high-frequency semiconductor module 80 according to the fourth embodiment. Since it is not necessary to provide the first and second interstage RF lines 25a and 25b at right angles, the area of the third interstage RF line 25c can be reduced and the mounting area is severely restricted. Can also be applied.

(Sixth embodiment)
FIG. 14 is an enlarged plan view showing a configuration on the interstage circuit board 15 in the high-frequency semiconductor module according to the sixth embodiment. In FIG. 14, the matching circuit patterns 36 and 37 provided in the first inter-stage RF line 25a and the second inter-stage RF line 25b are omitted. Further, since the high-frequency semiconductor module is the same as the high-frequency semiconductor module 10 according to the first embodiment except for the configuration on the interstage circuit board 15, the illustration is omitted and the description is also omitted.

  As shown in FIG. 14, on the interstage circuit board 15 made of alumina, for example, the first interstage RF line 25a and the second interstage RF that are separated from each other so as to be electrically insulated from each other. A line 25b is provided. An interdigital filter 101 is provided between the first interstage RF line 25a and the second interstage RF line 25b.

  The interdigital filter 101 is configured by providing four linear patterns 101a to 101d in parallel with each other, where λ is the wavelength of the RF signal input thereto, and each has an electrical length of λ / 4. It is. In the following description of the interdigital filter 101, the four patterns 101a to 101d are arranged in order from the upper side to the lower side of the drawing, the first pattern 101a, the second pattern 101b, the third pattern 101c, and the fourth pattern. This pattern is referred to as a pattern 101d.

  Each of the four patterns 101 a to 101 d constituting the interdigital filter 101 is connected to the ground via a through via 102 that penetrates the interstage circuit board 15. The first pattern 101a and the third pattern 101c are connected to the ground at the right end of the drawing, and the second pattern 101b and the fourth pattern 101d are connected to the ground at the left side of the drawing. Yes.

  Like the LC resonance circuit, the interdigital filter 101 configured in this manner has a characteristic of transmitting a signal of the frequency f and increasing the attenuation characteristic as the frequency f is separated from the high frequency side and the low frequency side. .

  Further, the interstage circuit board 15 is provided with first and second monitor patterns 28 and 29 for monitoring the RF signal, and these are connected to the package 13 (this figure by connection conductors 31 and 33). Are omitted) and are connected to the first and second monitor terminals 30 and 32.

  During normal operation of the high-frequency semiconductor module described above, the other end of the first interstage RF line 25a and one end of the first pattern 101a constituting the interdigital filter 101 (left end in the figure). Are connected by a connection conductor 105. Further, the other end portion (right end portion in the figure) of the fourth pattern 101 d constituting the interdigital filter 101 and one end portion of the second inter-stage RF line 25 b are connected by the connection conductor 106. . Thereby, the interdigital filter 101 is connected between the first semiconductor element 17 and the second semiconductor element 18. Therefore, high-order harmonics that are remarkably generated during the saturation operation of the first semiconductor element 17 and the like are generated by a loop circuit formed between the first semiconductor element 17 and the second semiconductor element 18. Unwanted waves such as frequency can be greatly attenuated. Furthermore, an unnecessary wave (cross modulation wave) having a frequency close to the frequency of the RF signal can be greatly attenuated.

  When an RF signal is input from the input terminal 11 of the high-frequency semiconductor module during such normal operation, predetermined signal processing is performed in the first semiconductor element 17. The RF signal (RFin) output from the first semiconductor element 17 is input to the interdigital filter 101 via the first interstage RF line 25a. In the interdigital filter 101, the unnecessary wave included in the RF signal output from the first semiconductor element 17 is attenuated, and the RF signal in which the unnecessary wave is attenuated is transmitted through the second interstage RF line 25b. Is input to the semiconductor element 18 (RFout). An RF signal that has undergone predetermined signal processing in the second semiconductor element 18 is output from the output terminal 12 of the high-frequency semiconductor module.

  Each pattern constituting the interdigital filter 101 has an electrical length of λ / 4, but the output end of the interdigital filter 101 (the other end of the fourth pattern 101d) is the second interstage RF. Since it is connected to the line 25b, the RF signal input to the interdigital filter 101 passes through the filter 101 without being reflected at the input end of the filter 101 (one end portion of the first pattern 101a), and the second The interstage RF line 25b is reached.

  Next, a method for monitoring the operations of the first semiconductor element 17 and the second semiconductor element 18 in the high-frequency module will be described. Note that the method for monitoring the operation of the entire high-frequency module is realized in the configuration shown in FIG.

  FIG. 15 is a plan view showing the high-frequency semiconductor module when the operation of the first semiconductor element 17 is monitored. FIG. 16 is a plan view showing the high-frequency semiconductor module when the operation of the second semiconductor element 18 is monitored.

  As shown in FIG. 15, when the operation of the first semiconductor element 17 is monitored, the other end of the first interstage RF line 25a and one end of the first pattern 101a constituting the interdigital filter 101 are displayed. Connecting conductor 105 that connects the first portion (left end portion in the figure), and the other end portion (right end portion in the figure) of the fourth pattern 101d that constitutes the interdigital filter 101, and the second inter-stage RF. The connection conductor 106 that connects one end of the line 25 b is removed, and the other end of the first interstage RF line 25 a and the first monitor pattern 28 are connected by the connection conductor 107.

  When an RF signal is input from the input terminal of such a high-frequency semiconductor module, predetermined signal processing is performed in the first semiconductor element 17. The RF signal (RFin) output from the first semiconductor element 17 propagates through the first inter-stage RF line 25a and is output from the first monitor terminal 30 (RFout).

  Each of the patterns 101a to 101d constituting the interdigital filter 101 has an electrical length of λ / 4, and the output end of the interdigital filter 101 is not connected to the second interstage RF line 25b. The RF signal propagating through the first interstage RF line 25 a is reflected at the input end of the interdigital filter 101 and propagated to the first monitor pattern 28.

As shown in FIG. 16, when monitoring the operation of the second semiconductor element 18, the other end of the first interstage RF line 25a and the first pattern 101a constituting the interdigital filter 101 are used. A connection conductor 105 that connects one end of the second pattern, and a connection conductor 106 that connects the other end of the fourth pattern 101d constituting the interdigital filter 101 and one end of the second inter-stage RF line 25b. removal,
The second monitoring pattern 29 is connected to one end of the second inter-stage RF line 25b by a connecting conductor 108.

  When an RF signal (RFin) is input from the second monitor terminal 32 of such a high-frequency semiconductor module, the RF signal propagates through the second interstage RF line 25b and is output to the second semiconductor element 18 ( RFout), predetermined signal processing is performed in the second semiconductor element 18. The RF signal output from the second semiconductor element 18 is output from the output terminal.

  Each of the patterns 101a to 101d constituting the interdigital filter 101 has an electrical length of λ / 4, and the input end of the interdigital filter 101 is not connected to the first interstage RF line 25a. The RF signal input from the second monitor terminal 32 is reflected at the output end of the interdigital filter 101 and propagates through the second inter-stage RF line 25b.

  In this way, by monitoring the RF signal output from the first monitor terminal 30 and the RF signal output from the output terminal, respectively, the operations of the first semiconductor element 17 and the second semiconductor element 18 are each controlled. The performance of the high-frequency semiconductor module can be suppressed by adjusting the matching circuit pattern on each circuit board based on the monitoring result.

  In the evaluation of the semiconductor elements 17 and 18, the RF signal input to and output from the semiconductor elements 17 and 18 is not affected by attenuation outside the passband by the interdigital filter 101. Since an accurate monitoring result can be obtained in a wide frequency range and the matching circuit tone pattern can be adjusted more accurately, the performance deterioration of the high-frequency semiconductor module can be further suppressed.

  In the high-frequency semiconductor module according to the present embodiment described above, since the interdigital filter 101 is provided between the first semiconductor element 17 and the second semiconductor element 18, the RF signal from the first semiconductor element 17 to the RF It is possible to suppress the high-order harmonic component output together with the signal from being input to the second semiconductor element 18. Therefore, distortion of the output signal can be reduced. Furthermore, loop oscillation between the first semiconductor element 17 and the second semiconductor element 18 can be suppressed.

  Even if different bias voltages are supplied to the output side of the first semiconductor element 17 and the input side of the second semiconductor element 18, the interdigital filter 101 is provided between them, so It is possible to suppress a current from flowing between the first inter-stage RF line 25a and the second inter-stage RF line 25b having different potentials. As a result, it is possible to suppress a short circuit of the power source that supplies the bias voltage to each of the semiconductor elements 17 and 18, and the high-frequency semiconductor module can be operated with high performance.

  That is, according to this embodiment, the high-frequency semiconductor module can be improved in performance.

(Seventh embodiment)
FIG. 17 is an enlarged plan view showing the configuration on the interstage circuit board 15 in the high-frequency semiconductor module according to the seventh embodiment. In FIG. 17, the matching circuit patterns 36 and 37 provided in the first inter-stage RF line 25a and the second inter-stage RF line 25b are omitted. Further, since the high-frequency semiconductor module is the same as the high-frequency semiconductor module 10 according to the first embodiment except for the configuration on the interstage circuit board 15, the illustration is omitted and the description is also omitted.

  The configuration on the interstage circuit board 15 of the high-frequency semiconductor module shown in FIG. 17 is different from the configuration on the interstage circuit board 15 shown in FIG. The difference is that a bias supply circuit for two semiconductor elements 18 is added.

  That is, the first capacitor 111 is mounted on the first monitor pattern 28, and the second capacitor 112 is mounted on the second monitor pattern 29. Each of the first and second capacitors 111 and 112 is, for example, a microchip capacitor.

  In addition, on the interstage circuit board 15, the first pattern 101a 'of the interdigital filter 101' is shorter than the second pattern 101b ', and the third pattern 101a' is located at a position spaced from the other end to the right side of the drawing. The capacity 113 is mounted. The other end of the first pattern 101 a ′ and the third capacitor 113 are connected by a connection conductor 116. The first pattern 101a ′ is configured such that the electrical length obtained by adding the pattern 101a ′ and the connection wiring 116 is approximately λ / 4, and the second pattern 101b ′ has an electrical length of λ / 4 is configured.

  Further, on the interstage circuit board 15, the fourth pattern 101d ′ of the interdigital filter 101 ′ is shorter than the third pattern 101c ′ having substantially the same length as the second pattern 101b ′. A fourth capacitor 114 is mounted at a position spaced from one end to the left side of the drawing. The one end portion of the fourth pattern 101d ′ and the fourth capacitor 114 are connected by a connection conductor 117. The fourth pattern 101d ′ is configured such that the electrical length obtained by adding the pattern 101d ′ and the connection wiring 117 is approximately λ / 4.

  Each of the third and fourth capacitors 113 and 114 is, for example, a microchip capacitor, and is connected to the ground via a through via 115 immediately below.

  Each through via 115 is provided at a position separated from the fourth pattern 101d ′ and the first pattern 101a ′ of the interdigital filter 101 ′ by a predetermined distance. Thereby, the malfunction by the protrusion of the solder, adhesive agent, etc. used when mounting the 3rd capacitor 113 and the 4th capacitor 114 can be controlled.

  Note that a through via 102 is provided at one end (left end) of the second pattern 101b ′ and the other end (right end) of the third pattern 101c ′. This is the same as the filter 101.

  During normal operation of the high-frequency semiconductor module described above, the other end of the first interstage RF line 25a and one end of the first pattern 101a ′ constituting the interdigital filter 101 ′ are connected conductors. 105, and the other end of the fourth pattern 101d 'constituting the interdigital filter 101' and one end of the second inter-stage RF line 25b are connected by a connecting conductor 106. Thereby, the interdigital filter 101 ′ is connected between the first semiconductor element 17 and the second semiconductor element 18.

  Further, the fourth capacitor 114 and the first monitor pattern 28 are connected by the connection conductor 118, thereby forming a bias circuit for the first semiconductor element 17. Then, the third capacitor 113 and the second monitor pattern 29 are connected by a connection conductor 119, thereby forming a bias circuit for the second semiconductor element 18.

  In such a high-frequency semiconductor module during normal operation, a gate bias is supplied from the input terminal of the high-frequency semiconductor module to the first semiconductor element 17, and the second monitor terminal 32 supplies the second semiconductor element 17 to the second semiconductor element 17. A drain bias (BIASdrain 1) is supplied through the monitor pattern 29 and the third capacitor 113. Then, a drain bias is supplied from the output terminal of the high-frequency semiconductor module to the second semiconductor element 18, and the second semiconductor element is connected via the first monitor terminal 30 or the first monitor pattern 28 and the fourth capacitor 114. 18 is supplied with a gate bias (BIASgate 2). When an RF signal is input from the input terminal of the high-frequency semiconductor module to which the bias is supplied in this way, predetermined signal processing is performed in the first semiconductor element 17. The RF signal (RFin) output from the first semiconductor element 17 is input to the interdigital filter 101 ′ via the first interstage RF line 25a. In the interdigital filter 101 ′, the unnecessary wave included in the RF signal output from the first semiconductor element 17 is attenuated, and the RF signal in which the unnecessary wave is attenuated passes through the second interstage RF line 25b. 2 is input to the semiconductor element 18 (RFout). An RF signal that has undergone predetermined signal processing in the second semiconductor element 18 is output from the output terminal of the high-frequency semiconductor module.

  Next, a method for monitoring the operations of the first semiconductor element 17 and the second semiconductor element 18 in the high-frequency module will be described. Note that the method of monitoring the operation of the entire high-frequency module is realized in the configuration shown in FIG.

  FIG. 18 is a plan view showing the high-frequency semiconductor module when the operation of the first semiconductor element 17 is monitored. FIG. 19 is a plan view showing the high-frequency semiconductor module when the operation of the second semiconductor element 18 is monitored.

  As shown in FIG. 18, when the operation of the first semiconductor element 17 is monitored, the connection conductors 106 and 117 connected to both ends of the fourth pattern 101d ′ constituting the interdigital filter 101 ′ are removed. Then, the connection conductor 118 that connects the fourth capacitor 114 and the first monitor pattern 28 is removed. Then, the first capacitor 111 and the other end of the first interstage RF line 25 a are connected by the connection conductor 120.

  A gate bias is supplied from the input terminal of the high-frequency semiconductor module to the first semiconductor element 17, and the drain bias (BIASdrain 1) is supplied from the second monitor terminal 32 to the first semiconductor element 17 through the third capacitor 113. ). As described above, when the RF signal is input from the input terminal of the high-frequency semiconductor module to which the bias is supplied to the first semiconductor element 17, predetermined signal processing is performed in the first semiconductor element 17. An RF signal (RFin) output from the first semiconductor element 17 is output from the first monitor terminal 30 via the first capacitor 111.

  The second and third patterns 101b ′ and 101c ′ constituting the interdigital filter 101 ′ have an electrical length of λ / 4, and the total length of the first pattern 101a ′ and the connection conductor 116 is λ The electrical length is / 4. The output end of the interdigital filter 101 ′ is not connected to the second interstage RF line 25b, and the other end of the first pattern 101a ′ constituting the interdigital filter 101 ′ is the third end. The capacitor 113 is grounded. Accordingly, the RF signal propagating through the first interstage RF line 25 a is reflected at the input end of the interdigital filter 101 ′ and propagated to the first monitor terminal 30.

  Further, as shown in FIG. 19, when monitoring the operation of the second semiconductor element 18, the connection conductors 105 and 116 connected to both ends of the first pattern 101a 'constituting the interdigital filter 101' are provided. At the same time, the connection conductor 119 connecting the third capacitor 113 and the second monitor pattern 29 is removed. Then, the second capacitor 112 and one end of the second interstage RF line 25 b are connected by the connection conductor 121.

  A gate bias (BIASgate 2) is supplied from the first monitor terminal 30 of such a high-frequency semiconductor module to the second semiconductor element 18 via the fourth capacitor 114, and the drain is supplied from the output terminal to the second semiconductor element 18. Supply bias. As described above, when the RF signal (RFin) is input from the second monitor terminal 32 of the high-frequency semiconductor module to which the bias is supplied to the second semiconductor element 18, the RF signal is passed through the second capacitor 112. Then, it propagates through the second inter-stage RF line 25b and is input to the second semiconductor element 18 (RFout). When the RF signal is input to the second semiconductor element 18, predetermined signal processing is performed in the second semiconductor element 18 and output from the output terminal of the high-frequency semiconductor module.

  The second and third patterns 101b ′ and 101c ′ constituting the interdigital filter 101 ′ have an electrical length of λ / 4, and the total length of the fourth pattern 101d ′ and the connection conductor 117 is λ The electrical length is / 4. The input end of the interdigital filter 101 'is not connected to the first interstage RF line 25a, and one end of the fourth pattern 101d' constituting the interdigital filter 101 'is a fourth capacitor. 114 is grounded. Therefore, the RF signal input from the second monitor terminal 32 is reflected at the output end of the interdigital filter 101 ′ and propagates through the second interstage RF line 25 b.

  Thus, by monitoring the RF signal output from the first monitor terminal 30 and the RF signal output from the output terminal, the operations of the first semiconductor element 17 and the second semiconductor element 18 are controlled. Each can be monitored, and by adjusting the matching circuit pattern on each circuit board based on the monitoring result, performance degradation of the high-frequency semiconductor module can be suppressed.

  In the evaluation of each of the semiconductor elements 17 and 18, as in the high-frequency semiconductor module according to the sixth embodiment, the RF signal input to and output from each of the semiconductor elements 17 and 18 101 is not affected by the attenuation outside the passband by 101, so that an accurate monitoring result can be obtained in a wide frequency range, and the matching circuit tone pattern can be more accurately adjusted, thereby further suppressing the performance deterioration of the high-frequency semiconductor module. be able to.

  Also in the high-frequency semiconductor module according to the present embodiment described above, since the interdigital filter 101 is provided between the first semiconductor element 17 and the second semiconductor element 18, the RF signal from the first semiconductor element 17 to the RF It is possible to suppress the high-order harmonic component output together with the signal from being input to the second semiconductor element 18. Therefore, distortion of the output signal can be reduced. Furthermore, loop oscillation between the first semiconductor element 17 and the second semiconductor element 18 can be suppressed.

  Even if different bias voltages are supplied to the output side of the first semiconductor element 17 and the input side of the second semiconductor element 18, the interdigital filter 101 is provided between them, so It is possible to suppress a current from flowing between the first inter-stage RF line 25a and the second inter-stage RF line 25b having different potentials. As a result, it is possible to suppress a short circuit of the power source that supplies the bias voltage to each of the semiconductor elements 17 and 18, and the high-frequency semiconductor module can be operated with high performance.

  That is, according to this embodiment, the high-frequency semiconductor module can be improved in performance.

  Furthermore, according to the high-frequency semiconductor module according to the present embodiment, the bias supply circuit can be obtained by simply mounting the plurality of capacitors 111 to 114 on the configuration of the interstage circuit board 15 in the high-frequency semiconductor module according to the sixth embodiment. Therefore, the increase in the size of the interstage circuit board 15 due to the addition of the bias supply circuit can be suppressed.

  Although the embodiment of the present invention has been described above, this embodiment is presented as an example and is not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the spirit of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

10, 50, 60, 70, 80, 90 ... high frequency semiconductor module 11 ... input terminal 12 ... output terminal 13, 13 '... package 14 ... input side circuit board 15 ... stage Inter-circuit board 16 ... output-side circuit board 17 ... first semiconductor element 18 ... second semiconductor element 19 ... input high-frequency signal line (input RF line)
20, 21, 23, 24, 26, 27, 31, 33, 39, 40, 41, 62, 63, 64, 65, 71, 81, 82, 83, 84, 92, 105, 106, 107, 108, 116, 117, 118, 119, 120, 121 ... connecting conductor 22 ... output RF line 25a ... first inter-stage RF line 25b, 25b '... second inter-stage RF Lines 25c, 25c '... third inter-stage RF lines 28, 28', 28 "... first monitor patterns 29, 29 '... second monitor patterns 30 ... First monitor terminal 32 ... second monitor terminals 34, 35, 36, 37 ... matching circuit patterns 38, 38 '... (first) capacitors 51, 52 ... capacitors 61. Second capacitor 91: protrusions 101, 10 '... interdigital filter 101a, 101a' ... first pattern 101b, 101b '... second pattern 101c, 101c' ... third pattern 101d, 101d '... fourth Pattern 102, 115 ... Through-via 111 ... First capacitor 112 ... Second capacitor 113 ... Third capacitor 114 ... Fourth capacitor

Claims (10)

A package having an input terminal, an output terminal, a first monitor terminal, and a second monitor terminal;
A first semiconductor element disposed in the package and electrically connected to the input terminal;
A second semiconductor element disposed in a position spaced apart from the first semiconductor element and electrically connected to the output terminal in the package;
A first monitoring pattern disposed between the first semiconductor element and the second semiconductor element and connected to the first monitor terminal on the surface and a second pattern connected to the second monitor terminal An interstage circuit board having two monitor patterns;
A first interstage high-frequency signal line provided on the surface of the interstage circuit board and having one end connected to the first semiconductor element;
On the surface of the interstage circuit board, one end is provided at a position separated from the first interstage high-frequency signal line, and the other end is connected to the second semiconductor element. A high-frequency signal line;
A first capacitor disposed on the other end of the first interstage high-frequency signal line;
A high-frequency semiconductor module comprising: The first inter-stage RF line is provided integrally with the first monitor pattern,
The second inter-stage RF line is provided integrally with the second monitor pattern,
2. The first monitor pattern and the second monitor pattern each have an electrical length corresponding to a quarter of a wavelength of a high-frequency signal input from the input terminal of the package. The high frequency semiconductor module according to 1. On the surface of the inter-stage circuit board, a third inter-stage signal is provided between the first inter-stage high-frequency signal line and the second inter-stage high-frequency signal line so as to be separated from these signal lines. High-frequency signal line for interstage,
A second capacitor disposed on the second inter-stage high-frequency signal line;
The high-frequency semiconductor module according to claim 1, further comprising:   4. The high-frequency semiconductor module according to claim 3, wherein the second capacitor is disposed at a position spaced apart from one end of the second inter-stage high-frequency signal line by a predetermined distance. 5.   The high-frequency semiconductor module according to claim 3, wherein a plurality of protrusions are provided at one end of the second inter-stage high-frequency signal line. A package having an input terminal, an output terminal, and a monitor terminal;
A first semiconductor element disposed in the package and electrically connected to the input terminal;
A second semiconductor element disposed in a position spaced apart from the first semiconductor element and electrically connected to the output terminal in the package;
An interstage circuit board having a monitor pattern disposed between the first semiconductor element and the second semiconductor element and connected to the monitor terminal on the surface;
A first interstage high-frequency signal line provided on the surface of the interstage circuit board and having one end connected to the first semiconductor element;
On the surface of the interstage circuit board, one end is provided at a position separated from the first interstage high-frequency signal line, and the other end is connected to the second semiconductor element. A high-frequency signal line;
On the surface of the inter-stage circuit board, a third inter-stage signal is provided between the first inter-stage high-frequency signal line and the second inter-stage high-frequency signal line so as to be separated from these signal lines. High-frequency signal line for interstage,
A capacitor disposed on the third inter-stage high-frequency signal line;
A high-frequency semiconductor module comprising: The first inter-stage high-frequency signal line and the second inter-stage high-frequency signal line are provided such that the longitudinal directions of these signal lines are the same direction,
The third inter-stage high-frequency signal line has a longitudinal direction intersecting with the longitudinal direction of the first inter-stage high-frequency signal line and the second inter-stage high-frequency signal line. 7. The high-frequency semiconductor module according to claim 6, wherein the high-frequency semiconductor module is provided and has the same electrical length as that of the first inter-stage high-frequency signal line and the second inter-stage high-frequency signal line. . A package having an input terminal and an output terminal;
A first semiconductor element disposed in the package and electrically connected to the input terminal;
A second semiconductor element disposed in a position spaced apart from the first semiconductor element and electrically connected to the output terminal in the package;
An interstage circuit board disposed between the first semiconductor element and the second semiconductor element and provided with a monitor terminal on the surface;
A first interstage high-frequency signal line provided on the surface of the interstage circuit board and having one end connected to the first semiconductor element;
On the surface of the interstage circuit board, one end is provided at a position separated from the first interstage high-frequency signal line, and the other end is connected to the second semiconductor element. A high-frequency signal line;
On the surface of the interstage circuit board, an interdigital filter provided between the first interstage high-frequency signal line and the second interstage high-frequency signal line;
A high-frequency semiconductor module comprising: The interdigital filter includes a first pattern;
A second pattern arranged parallel to the first pattern and grounded;
A third pattern arranged in parallel to the second pattern and grounded;
A fourth pattern disposed parallel to the third pattern;
The high-frequency semiconductor module according to claim 8, comprising: A first capacitor disposed on the other end of the first interstage high-frequency signal line;
A second capacitor disposed on one end of the second inter-stage high-frequency signal line;
A third capacitor disposed on the interstage circuit board at a position spaced from the fourth pattern;
A fourth capacitor disposed on the interstage circuit board at a position spaced from the first pattern;
Further comprising
10. The high-frequency semiconductor module according to claim 9, wherein each of the third capacitor and the fourth capacitor is grounded through a through via provided in the interstage circuit board.

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