JP2014192369A - Semiconductor element manufacturing method and semiconductor element manufacturing apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor element manufacturing method and a semiconductor element manufacturing apparatus, which can inhibit formation of an Al oxide film on a surface of an Al-containing semiconductor layer.SOLUTION: A semiconductor element manufacturing method comprises: forming a mesa structure 9 by selectively dry etching a semiconductor laminated structure 7 by using an SiOfilm 8 as a mask; forming an amorphous As film 10 on the mesa structure 9; exporting a semiconductor wafer 40 having the mesa structure 9 on which the amorphous As film 10 is formed from a processing chamber 49 of a manufacturing apparatus 50; carrying in the semiconductor wafer 40 in a chamber of a crystal growth apparatus (represented as an MOCVD apparatus in the present embodiment); performing heating to a temperature of 250°C and over to desorb the amorphous As film; and burying a p-type InP buried layer 11, an n-type InP current block layer 12, a p-type InP current block layer 13 and an n-type InP buried layer 14 on both sides of the mesa structure.

Description

  The present invention relates to a method for manufacturing a semiconductor element having a semiconductor layer containing Al, and a semiconductor element manufacturing apparatus.

  In an optical semiconductor device such as a semiconductor laser or a semiconductor optical modulator, it is necessary to narrow the current path in order to efficiently supply current to the active layer. Therefore, in many optical semiconductor devices, current confinement is performed by forming a mesa structure by etching a semiconductor laminated structure having an active layer and limiting a region through which a current flows. Furthermore, from the viewpoints of protection of the active layer exposed on the side surface of the mesa structure, heat dissipation, parasitic capacitance of the element, etc., both sides of the mesa structure are embedded with, for example, n / p / n / p type InP buried layers. . In this case, the side surface of the mesa structure needs to be covered with the p-type InP buried layer.

  The semiconductor stacked structure may have a semiconductor layer containing Al as an active layer, a clad layer, a SCH (Separate Confinement Heterostructure) layer, or the like. The semiconductor layer containing Al is easily oxidized by oxygen in the atmosphere.

  In general, crystal growth apparatuses such as a dry etching apparatus and an MOCVD apparatus are separate apparatuses and have different chambers. After the mesa structure is formed in the chamber of the dry etching apparatus, it is necessary to carry out the semiconductor substrate having the mesa structure from the one end chamber and transport it into the chamber of the MOCVD apparatus. During the transfer process, the semiconductor substrate having this mesa structure is exposed to the atmosphere. Then, an Al oxide film is formed on the surface of the semiconductor layer containing Al due to the property of being easily oxidized as described above. In addition to dry etching, when wet etching such as hydrofluoric acid is performed, an Al oxide film is formed on the surface of the semiconductor layer containing Al by subsequent washing with water or exposure to the atmosphere.

  This Al oxide film has a problem of deteriorating the characteristics of the semiconductor element. For example, when a p-type InP buried layer is grown on a side surface of a mesa structure by etching a semiconductor laminated structure having an active layer, if an Al oxide film is formed on the side surface of the mesa structure, the p-type on the side surface The growth of the InP buried layer is hindered. In this case, if an n-type InP buried layer is further laminated, the p-type InP buried layer is insufficiently grown, and therefore the n-type InP buried layer and the active layer are in contact with each other to form a reactive current path. was there.

  Thus, in order to solve this problem, a so-called in-situ etching apparatus has been proposed in which a dry etching apparatus is provided in parallel with MOCVD so that the mesa structure is not exposed to the atmosphere (see, for example, Non-Patent Document 1). .

JP 2010-10435 A JP-A-6-291032 Japanese Patent Laid-Open No. 10-284466

Ogura Goro, "In-situ ECR dry etching and gas etching / embedded AlGaAs laser by MOCVD regrowth process", Vol. 64, No. 3, Vol. 3, No. 3 N. J. et al. KAWAI et al., “Arsenic passage: a possible remedy for MBE growth-interruption problems”, Electronics letters, January 5, 1984, Vol. 20, no. 1

  In the in-situ MOCVD parallel dry etching apparatus according to the above Non-Patent Document 1, the dry etching apparatus and the MOCVD apparatus are connected by a passage portion. The space in the passage is shielded from the atmosphere. Therefore, a product being manufactured can be transferred from the chamber of the dry etching apparatus to the MOCVD chamber while avoiding exposure of the exposed surface of the semiconductor layer containing Al to the atmosphere through the passage portion.

  However, required functions are greatly different between an etching apparatus and a crystal growth apparatus such as MOCVD. Since the crystal growth apparatus is an apparatus for forming a high-quality crystal structure, it does not like that the inside is contaminated with impurities. If the etching apparatus and the crystal growth apparatus are connected, it is necessary to thoroughly prevent contamination such as gas isolation between the two chambers, that is, etching gas entering the crystal growth apparatus side. In addition, it is necessary to newly provide a complicated transport mechanism for wafer transfer from the etching chamber to the chamber for crystal growth. For these reasons, an apparatus in which an etching apparatus and a crystal growth apparatus, as described in Non-Patent Document 1, are inevitably high in cost, and the manufacturing cost is considered. In that case, there was still room for improvement.

  The present invention has been made in order to solve the above-described problems, and a semiconductor capable of suppressing the formation of an Al oxide film on the surface of a semiconductor layer containing Al in consideration of manufacturing cost. An object is to provide an element manufacturing method and a semiconductor element manufacturing apparatus.

A method for manufacturing a semiconductor device according to the present invention includes:
Etching is performed on a semiconductor substrate on which a semiconductor layer containing Al is stacked in the same chamber or in a plurality of chambers that are separated from the atmosphere through a passage portion to expose at least a part of the semiconductor layer. Forming a mesa structure and forming an antioxidant film for preventing oxidation of the semiconductor layer containing Al exposed in the mesa structure; and
A transfer step of unloading the semiconductor substrate from the same chamber or the plurality of chambers after the mesa structure forming step and loading the semiconductor substrate into another chamber included in the semiconductor crystal growth apparatus;
In the other chamber, the embedding step of embedding both sides of the mesa structure with an embedding layer after removing the antioxidant film;
It is characterized by providing.

A semiconductor device manufacturing apparatus according to the present invention includes:
A chamber with a pedestal;
An etching gas supply for communicating with the chamber and etching the semiconductor substrate on the pedestal;
An anti-oxidation film forming portion for forming an anti-oxidation film on the semiconductor substrate on the pedestal, communicating with the chamber;
An opening / closing mechanism that selectively switches between communication and blocking of the etching gas supply unit and the antioxidant film forming unit to the chamber;
It is characterized by providing.

  According to the present invention, it is possible to suppress the formation of an Al oxide film on the surface of a semiconductor layer containing Al in consideration of the manufacturing cost.

It is a figure which shows the structure of the manufacturing apparatus of the semiconductor element concerning Embodiment 1 of this invention, and is sectional drawing which showed the internal structure of the manufacturing apparatus. It is a flowchart for demonstrating the manufacturing method of the semiconductor element concerning Embodiment 1 of this invention. It is a manufacturing flow figure showing a process in which a semiconductor device is manufactured with a manufacturing method of a semiconductor device concerning Embodiment 1 of the present invention. It is a manufacturing flow figure showing a process in which a semiconductor device is manufactured with a manufacturing method of a semiconductor device concerning Embodiment 1 of the present invention. It is a manufacturing flow figure showing a process in which a semiconductor device is manufactured with a manufacturing method of a semiconductor device concerning Embodiment 1 of the present invention. It is a manufacturing flow figure showing a process in which a semiconductor device is manufactured with a manufacturing method of a semiconductor device concerning Embodiment 1 of the present invention. It is a manufacturing flow figure showing a process in which a semiconductor device is manufactured with a manufacturing method of a semiconductor device concerning Embodiment 1 of the present invention. It is a manufacturing flowchart which shows the process in which a semiconductor element is manufactured with the manufacturing method of the semiconductor element concerning Embodiment 2 of this invention. It is a manufacturing flowchart which shows the process in which a semiconductor element is manufactured with the manufacturing method of the semiconductor element concerning Embodiment 2 of this invention. It is a manufacturing flowchart which shows the process in which a semiconductor element is manufactured with the manufacturing method of the semiconductor element concerning Embodiment 2 of this invention. It is a manufacturing flowchart which shows the process in which a semiconductor element is manufactured with the manufacturing method of the semiconductor element concerning Embodiment 2 of this invention. It is a manufacturing flowchart which shows the process in which a semiconductor element is manufactured with the manufacturing method of the semiconductor element concerning Embodiment 3 of this invention. It is a manufacturing flowchart which shows the process in which a semiconductor element is manufactured with the manufacturing method of the semiconductor element concerning Embodiment 3 of this invention. It is a manufacturing flowchart which shows the process in which a semiconductor element is manufactured with the manufacturing method of the semiconductor element concerning Embodiment 3 of this invention. It is a manufacturing flowchart which shows the process in which a semiconductor element is manufactured with the manufacturing method of the semiconductor element concerning Embodiment 3 of this invention.

Embodiment 1 FIG.
[Configuration of Apparatus According to First Embodiment]
FIG. 1 is a diagram showing a configuration of a semiconductor device manufacturing apparatus 50 according to the first embodiment of the present invention, and is a cross-sectional view showing an internal configuration of the manufacturing apparatus 50. The main role of the manufacturing apparatus 50 is a dry etching apparatus for performing dry etching, and the manufacturing apparatus 50 has a configuration of a general dry etching apparatus. Further, as a characteristic configuration of the manufacturing apparatus 50, there are provided an As molecule supply mechanism such as that used in an MBE apparatus and a mechanism for preventing adverse effects on etching applications that are concerned by the As molecule supply.

  As shown in FIG. 1, the manufacturing apparatus 50 includes a processing chamber 49. As a configuration of the dry etching apparatus, an anode 45 and a cathode 46 are provided inside the processing chamber 49. The cathode 46 also has a role as a pedestal on which the semiconductor wafer 40 is placed.

  The processing chamber 49 is provided with an etching end detector 41 that is opened and closed via a shutter 42 and an etching gas inlet 43 that is opened and closed via a shutter 44. The etching gas inlet 43 is connected to an etching gas supply device 43a. A blocking capacitor 47 and an RF oscillator 48 are electrically connected to the anode 45 and the cathode 46.

  The manufacturing apparatus 50 includes an As molecule supply mechanism for forming an amorphous As film. Specifically, an opening is provided in the processing chamber 49, and a crucible (As cell) 38 filled with As raw material is communicated with the inside of the processing chamber 49 through this opening. A shutter 39 is provided between the crucible 38 and the processing chamber 49. A heater for heating the crucible 38 is provided. Specifically, the heater includes a heater resistor 38a and an energization control unit 38b for energizing the resistor.

  By energizing the resistor 38 a and heating the crucible 38, As is evaporated, the supply of As to the semiconductor wafer 40 is controlled by opening and closing the shutter 39 and adjusting the temperature of the crucible 38.

  In addition, a shutter 42 is provided in the window portion of the etching end detector (light emission detector) 41, and when the amorphous As film is formed, the shutter 42 is closed, and As accumulates on the detector to cause a problem. Can be prevented.

  Similarly, a shutter 44 is provided at the etching gas inlet 43. When the amorphous As film is formed, the shutter 44 can be closed to prevent As from accumulating in the inflow path of the etching gas.

  As described above, the crucible shutter 39 and the shutter 44 are open / close mechanisms that selectively switch between communication and blocking of the etching gas inlet 43 and the crucible 38 with respect to the processing chamber 49.

  The manufacturing apparatus 50 includes a temperature adjustment chiller 51. Refrigerant supply parts 51 a and 51 b of the temperature control chiller 51 are attached to the lower surface of the cathode 46. The temperature adjustment chiller 51 can control the temperature of the semiconductor wafer 40 placed on the upper surface of the cathode 46 by using a fluorine-based refrigerant or the like as the refrigerant. Although not shown, a thermometer for measuring the temperature of the semiconductor wafer 40 or the cathode 46 is also provided. In addition, although the refrigerant | coolant supply parts 51a and 51b of the temperature control chiller 51 showed the example attached to the lower surface of the cathode 46, you may provide a refrigerant | coolant supply part in the inside of the cathode 46. FIG.

[Manufacturing Method According to First Embodiment]
FIG. 2 is a flowchart for explaining a method of manufacturing a semiconductor element according to the first embodiment of the present invention. 3 to 7 are manufacturing flowcharts showing a process in which a semiconductor element is manufactured by the method for manufacturing a semiconductor element according to the first embodiment of the present invention. A semiconductor light emitting device is manufactured by the manufacturing method according to the present embodiment.

(Step S100: 1st lamination process)
First, in the flowchart shown in FIG. 2, the first stacking step according to step S100 is performed. In this step, first, a semiconductor multilayer structure 7 is formed on a p-type InP substrate 1 as shown in FIG. 3 using a crystal growth apparatus (not shown) such as MOCVD. The semiconductor multilayer structure 7 includes a p-type InP cladding layer 2, a p-type Al (Ga) InAs lower light confinement layer 3, an AlGaInAs multiple quantum well active layer 4, an n-type Al (Ga) InAs upper light confinement layer 5, n A type InP cladding layer 6 is laminated on a p-type InP substrate 1 in this order. The semiconductor layers containing Al are the p-type Al (Ga) InAs lower light confinement layer 3, the AlGaInAs multiple quantum well active layer 4, and the n-type Al (Ga) InAs upper light confinement layer 5.

  The p-type InP substrate 1 on which the semiconductor multilayer structure 7 is formed is unloaded from the chamber of this crystal growth apparatus. Hereinafter, the entire semiconductor substrate including the semiconductor multilayer structure 7 on the p-type InP substrate 1 is also referred to as a semiconductor wafer 40 for convenience.

(Step S101: SiO ₂ film forming step)
Next, in step S101, a SiO ₂ film 8 that is a silicon oxide film is selectively formed on the semiconductor multilayer structure 7 using a known photolithography technique and apparatus (not shown).

(Step S102: Etching Step and Amorphous As Film Formation Step)
Next, in step S102, the formation of the mesa structure 9 by the etching process and the formation process of the amorphous As film 10 are performed using the manufacturing apparatus 50 shown in FIG. That is, first, in step S101, the SiO ₂ film 8 selectively formed on the semiconductor multilayer structure 7 (this is the semiconductor wafer 40 of FIG. 1) is carried into the processing chamber 49 of the manufacturing apparatus 50.

As shown in FIG. 4, a mesa structure 9 is formed by selectively dry etching the semiconductor multilayer structure 7 using the SiO ₂ film 8 as a mask. That is, dry etching is performed by opening the shutter 44, introducing an etching gas through the etching gas inlet 43, and controlling the RF oscillator 48.

  Next, an amorphous As film 10 is formed on the surface of the mesa structure 9 at a temperature of 10 ° C. or less. That is, the temperature control chiller 51 is controlled to cool the semiconductor wafer 40 to 10 ° C. or lower, and As molecules are supplied from the crucible 38 to form the amorphous As film 10 on the mesa structure 9 as shown in FIG. . However, these processes are continuously performed in the processing chamber 49 so that the mesa structure 9 is not exposed to the atmosphere from the dry etching to the formation of the amorphous As film 10.

(Step S104: Conveying process)
Next, a conveyance process is implemented by step S104. The semiconductor wafer 40 having the mesa structure 9 on which the amorphous As film 10 is formed is unloaded from the processing chamber 49 of the manufacturing apparatus 50. Then, the semiconductor wafer 40 is carried into a chamber of a crystal growth apparatus (not shown) (in this embodiment, an MOCVD apparatus).

  During the transfer, the amorphous As film 10 is formed of a semiconductor layer containing Al exposed by the mesa structure 9 (that is, a p-type Al (Ga) InAs lower light confinement layer 3, an AlGaInAs multiple quantum well active layer 4, an n-type). It functions as an antioxidant film that prevents surface oxidation of the light confinement layer 5) on Al (Ga) InAs.

(Step S106: heating step and buried layer forming step)
Next, the heating process and the buried layer forming process of step S106 are performed. Specifically, the amorphous As film is desorbed by heating the semiconductor wafer 40 to 250 ° C. or higher in an MOCVD apparatus (not shown) carrying the semiconductor wafer 40. This is because the crystal growth itself by the MOCVD apparatus is normally performed in a sufficiently high temperature environment, so that the amorphous As film 10 is desorbed with heating for carrying out the crystal growth.

  As shown in FIG. 6, both sides of the mesa structure are embedded with a p-type InP buried layer 11, an n-type InP current blocking layer 12, a p-type InP current blocking layer 13, and an n-type InP buried layer 14. At this time, after the amorphous As film 10 is detached from the mesa structure 9, the film forming process is continuously performed from the heating process so that the mesa structure 9 is not exposed to the atmosphere.

(Step S108: Second lamination step)
Next, as shown in FIG. 7, after removing the SiO ₂ film 8, an n-type InP contact layer 15 and an n-type InGaAs contact layer 16 are formed. This is the second stacking step. The optical semiconductor element according to the present embodiment is manufactured through other general processes. Subsequent general steps may be performed using various known techniques, and thus description thereof is omitted.

  As the As film is deposited on the inner wall of the processing chamber 49 and the electrodes (anode 45, cathode 46) of the manufacturing apparatus 50, there is a concern that the environment in the manufacturing apparatus 50 changes and adversely affects etching. Therefore, it is preferable to perform cleaning by heating the inner wall of the processing chamber 49 and the electrode to 250 ° C. or higher as necessary.

  During this cleaning, the shutter 42 is closed with respect to the window portion of the etching end detector 41 and the shutter 44 of the etching gas inlet 43 is closed. Thus, the evaporated As is prevented from reaching the etching end detector 41 and the etching gas inflow path (etching gas inlet 43 and etching gas supply device 43a).

[Effects of First Embodiment]
By supplying As molecules with the mesa structure 9 at a low temperature of 10 ° C. or lower, the amorphous As film 10 can be formed on the surface of the mesa structure 9. The amorphous As film 10 functions to prevent contamination such as surface oxidation when the mesa structure is exposed to the atmosphere. The amorphous As film 10 can be detached from the mesa structure 9 by heating to 250 ° C. or higher. The usefulness and properties of the amorphous As film on the semiconductor as described above are described in Non-Patent Document 2, for example.

  In the first embodiment, after the mesa structure 9 is formed, the amorphous As film 10 is formed without being exposed to the atmosphere, and the amorphous As film 10 is used as an antioxidant film while being different between chambers (that is, the processing chamber 49 and the processing chamber 49). The semiconductor wafer 40 can be transported between the chambers of the MOCVD apparatus. Thereafter, the amorphous As film 10 is desorbed by heating, and a buried layer can be formed.

  In addition, according to the first embodiment, since the manufacturing apparatus 50 shown in FIG. 1 has the function of forming an amorphous As film, after the mesa structure 9 is formed using the inexpensive manufacturing apparatus 50, The amorphous As film 10 can be formed without exposing the semiconductor layer containing Al to the atmosphere.

  That is, the structure for forming the amorphous As film 10 included in the manufacturing apparatus 50 is not an apparatus for forming a buried structure such as the p-type buried layer 11 but an apparatus for performing recrystallization growth. Absent. The environment required in the chamber by a crystal growth apparatus such as MOCVD or MBE is different from the environment required for forming the amorphous As film 10 in the processing chamber 49.

  The film forming environment necessary for forming the amorphous As film 10 in the processing chamber 49 needs to have a low impurity environment, temperature and other film forming environments as high as required for crystal growth. No. Further, the heating mechanism for heating to a high temperature of 400 ° C. or higher required for crystal growth and the durability of the member that can withstand the high temperature are not required. For this reason, the structure for forming an amorphous As film to be mounted on the manufacturing apparatus 50 has a film forming capability that allows the amorphous As film 10 to be used as an antioxidant film (cover film) on the surface of the mesa structure 9. It is sufficient if only one type of amorphous As film 10 can be formed. Therefore, the cost of the manufacturing apparatus 50 itself can be low.

  According to the manufacturing method and the manufacturing apparatus according to the first embodiment described above, it is possible to reliably prevent the formation of an Al oxide film on the surface of the Al-containing semiconductor layer and to manufacture the optical semiconductor element at low cost. it can.

[Modification of Embodiment 1]
In the first embodiment, by using the amorphous As film 10 as an antioxidant film, a semiconductor layer containing Al (that is, a p-type Al (Ga) InAs lower light confinement layer 3, an AlGaInAs multiple quantum well active layer 4). The optical confinement layer 5) on the n-type Al (Ga) InAs was coated. However, the present invention is not limited to this.
Instead of the amorphous As film 10, it has an antioxidation performance that can be desorbed at a low temperature and can prevent an Al oxide film from being formed on the Al-containing semiconductor layer exposed by the mesa structure 9. An antioxidant film may be used.

  In the above embodiment, both sides of the mesa structure 9 are formed on the p-type / P-type InP buried layer 11, the n-type InP current blocking layer 12, the p-type InP current blocking layer 13, and the n-type InP buried layer 14. The n-type / p-type / n-type stacked structure is used. However, the structure of the buried layer according to the present invention is not limited to this. Even in the case of various other embedded structures in which conductivity and capacitance are adjusted, such as a laminated structure of n-type / p-type / i-type / n-type / p-type and a laminated structure of p-type / i-type / n-type / p-type. Similar effects can be obtained. However, i-type is undoped.

  Further, a semiconductor layer such as a high resistance InP buried layer doped with Fe or Ru or a high resistance undoped InAlAs layer may be buried.

  Furthermore, a crystal growth apparatus other than the MOCVD apparatus, for example, an MBE apparatus may be used in step S100 and step S106. Amorphous As film detachment by crystal growth or heating in the apparatus may be similarly performed.

  In the first embodiment, the p-type InP substrate 1 is used, but the same effect can be obtained even in the case of the inversion layer structure using the n-type substrate. Note that the buried structure in the case of the inversion layer structure is a p-type / n-type / p-type structure, and in addition to this, the same effect can be obtained in the case of various other buried structures in which conductivity and capacitance are adjusted. It is done.

  In the first embodiment, the manufacturing apparatus 50 shown in FIG. 1 is an apparatus that can perform dry etching and amorphous As film formation in one chamber. However, the present invention is not limited to this. The chamber of the existing dry etching apparatus and the chamber of the amorphous MB film forming apparatus using the existing MBE apparatus, vacuum deposition apparatus, etc. are connected through a passage portion connected so as to be shielded from the atmosphere. May be. The mesa structure 9 after etching may be covered with the amorphous As film 10 without being exposed to the atmosphere by transporting the semiconductor wafer 40 through this passage portion (conveyance passage).

Embodiment 2. FIG.
8 to 11 are manufacturing flowcharts for explaining the method of manufacturing an optical semiconductor element according to the second embodiment of the present invention. Unlike the first embodiment, the manufacturing method according to the second embodiment manufactures a semiconductor light receiving element.

  Note that the manufacturing apparatus 50 is used for dry etching and mesomorphous As film formation for mesa structure formation, as in the first embodiment. In the second embodiment, the semiconductor wafer 240 is carried into and out of the processing chamber 49 of the manufacturing apparatus 50.

  The basic flow of the manufacturing method according to the second embodiment is the same as the manufacturing method flowchart according to the first embodiment shown in FIG. However, the content of each block of the flowchart shown in FIG. 2 is different. In the following description, each process of the second embodiment will be described while corresponding to each block of the flowchart of FIG. 2, and the flowchart for the second embodiment will be omitted.

(First lamination step)
This process is a process corresponding to step S100 of FIG. In the second embodiment, as shown in FIG. 8, the semiconductor multilayer structure 23 is formed on the n-type InP substrate 17. The semiconductor stacked structure 23 includes an n-type InP buffer layer 18, an n-type AlGaInAs multiple quantum well avalanche multiplication layer 19, a p-type InGaAs light absorption layer 20, a p-type InP cap layer 21, and a p-type InGaAs contact layer 22 in this order. It is laminated on the InP substrate 17. The n-type multiple quantum well avalanche multiplication layer 19 is a semiconductor layer containing Al.

(SiO ₂ film forming step)
Next, a SiO ₂ film 24 patterned by photolithography or the like is formed on the semiconductor multilayer structure 23. This step corresponds to step S101 in FIG.

(Etching process and amorphous As film formation process)
Next, the semiconductor wafer 240 in which the SiO ₂ film 24 is selectively formed on the semiconductor laminated structure 23 is carried into the processing chamber 49 of the manufacturing apparatus 50. As shown in FIG. 9, the mesa structure 25 is formed by dry etching the semiconductor multilayer structure 23 using the SiO ₂ film 24 as a mask. At this time, etching is performed using the manufacturing apparatus 50 shown in FIG.

  Next, an amorphous As film 26 is formed on the surface of the mesa structure 25 at a temperature of 10 ° C. or less. That is, the temperature control chiller 51 is controlled to cool the inside of the processing chamber 49 to 10 ° C. or less, and As molecules are supplied from the crucible 38 to form the amorphous As film 26 on the mesa structure 25 as shown in FIG. Let However, from the dry etching to the formation of the amorphous As film 26, these steps are continuously performed so that the mesa structure 25 is not exposed to the atmosphere. These processes are processes corresponding to step S102 of FIG.

(Conveying process)
Next, a conveyance process is implemented. This process corresponds to step S104 in FIG. In the second embodiment, the semiconductor wafer 240 having the mesa structure 25 on which the amorphous As film 26 is formed is unloaded from the processing chamber 49 of the manufacturing apparatus 50. Then, the semiconductor wafer 240 is carried into a chamber of a crystal growth apparatus (not shown) (in this embodiment, an MOCVD apparatus).

(Heating process and buried layer forming process)
Next, a heating step and a buried layer forming step are performed. This step is a step corresponding to step S106 in FIG. In the second embodiment, the amorphous As film 26 is desorbed by heating to 250 ° C. or higher in an MOCVD apparatus, and the high resistance InP buried layer 27 is formed on both sides of the mesa structure 25 as shown in FIG. Embed with The high resistance InP buried layer 27 is doped with Fe, Ru, or the like. At this time, after the amorphous As film 26 is detached, the filling is continuously performed so that the mesa structure 25 is not exposed to the atmosphere.

(Other general processes)
After the formation of the high-resistance buried layer 27, the optical semiconductor element (semiconductor light-receiving element) according to the present embodiment is manufactured through other general processes. Subsequent general steps may be performed by using various known techniques, and are not a new matter, and thus description thereof is omitted.

  In the semiconductor light receiving element, there is a problem that dark current increases when an Al oxide film is formed on the surface of a semiconductor layer containing Al.

  In the second embodiment, after forming the mesa structure 25, the amorphous As film 26 is formed without being exposed to the atmosphere, and the amorphous As film 26 is used as an antioxidant film while being different between chambers (that is, the processing chamber 49 and the processing chamber 49). The semiconductor wafer 240 can be transported between the chambers of the MOCVD apparatus. Thereafter, the amorphous As film 26 is desorbed by heating, and a buried layer can be formed.

  Moreover, according to the third embodiment, since the manufacturing apparatus 50 shown in FIG. 1 has the function of forming an amorphous As film, the mesa structure 25 is formed using the inexpensive manufacturing apparatus 50. The amorphous As film 26 can be formed without exposing the semiconductor layer containing Al to the atmosphere.

  According to the manufacturing method and the manufacturing apparatus according to the second embodiment described above, it is possible to reliably prevent an increase in dark current due to the formation of the Al oxide film and to manufacture the semiconductor light receiving element at a low cost.

  In the above embodiment, the mesa structure 25 is embedded on both sides with the high resistance InP buried layer 27. However, the present invention is not limited to this, and a semiconductor layer such as a high resistance undoped InAlAs layer may be buried. .

  Furthermore, in the heating process and the buried layer forming process described above, the amorphous As film may be removed by crystal growth or heating in the apparatus using a crystal growth apparatus other than the MOCVD apparatus, for example, an MBE apparatus. .

  The same effect can be obtained even in the case of a structure having a window layer, a structure having no avalanche doubling layer, a structure in which the light absorption layer and the avalanche structure are reversed, or a structure having a field drop layer.

  The same effect can be obtained even in a structure having a light absorption layer containing Al and a high-resistance buried layer using GaSb as a substrate.

Embodiment 3 FIG.
12 to 15 are manufacturing flowcharts for explaining a method of manufacturing an optical semiconductor element according to the third embodiment of the present invention. Unlike the first embodiment, the manufacturing method according to the third embodiment manufactures an electroabsorption optical modulator.

  Note that the manufacturing apparatus 50 is used for dry etching and mesomorphous As film formation for mesa structure formation, as in the first embodiment. In the third embodiment, the semiconductor wafer 340 is carried into and out of the processing chamber 49 of the manufacturing apparatus 50.

  The basic flow of the manufacturing method according to the third embodiment is the same as the manufacturing method flowchart according to the first embodiment shown in FIG. However, the content of each block of the flowchart shown in FIG. 2 is different. In the following description, each step in the third embodiment will be described while corresponding to each block in the flowchart of FIG. 2, and the flowchart for the third embodiment will be omitted.

(First lamination step)
This process is a process corresponding to step S100 of FIG. In the third embodiment, first, as shown in FIG. 12, an n-type InP cladding layer 29, an AlGaInAs multiple quantum well core layer 30, a p-type InP cladding layer 31, and a p-type InGaAs contact layer are formed on an n-type InP substrate 28. A semiconductor multilayer structure 33 having 32 is formed. The AlGaInAs multiple quantum well core layer 30 is a semiconductor layer containing Al.

(SiO ₂ film forming step)
Next, a SiO ₂ film 34 patterned by photolithography or the like is formed on the semiconductor multilayer structure 33. This step corresponds to step S101 in FIG.

(Etching process and amorphous As film formation process)
Next, as shown in FIG. 13, the mesa structure 35 is formed by dry etching the semiconductor multilayer structure 33 using the SiO ₂ film 34 as a mask. At this time, etching is performed using the manufacturing apparatus 50 shown in FIG.

  Next, the temperature control chiller 51 is controlled to cool the inside of the processing chamber 49 to 10 ° C. or less, and As molecules are supplied from the crucible 38. As shown in FIG. 14, the amorphous As film 36 is formed on the mesa structure 35. To form. However, these processes are continuously performed in the processing chamber 49 so that the semiconductor wafer 340 is not exposed to the atmosphere from the dry etching to the formation of the amorphous As film. This step corresponds to step S102 in FIG.

(Conveying process)
Next, a conveyance process is implemented. This process corresponds to step S104 in FIG. In the third embodiment, the semiconductor wafer 340 having the mesa structure 35 on which the amorphous As film 36 is formed is unloaded from the processing chamber 49 of the manufacturing apparatus 50. Then, a semiconductor wafer 340 is carried into a chamber of a crystal growth apparatus (not shown) (in this embodiment, an MOCVD apparatus).

(Heating process and buried layer forming process)
Next, the amorphous As film 36 is desorbed by heating to 250 ° C. or higher in the MOCVD apparatus, and as shown in FIG. 15, both sides of the mesa structure are buried with high resistance InP doped with Fe, Ru, or the like. Embed with layer 37. At this time, after the amorphous As film 36 is removed, it is continuously buried so that the mesa structure 35 is not exposed to the atmosphere. This step is a step corresponding to step S106 in FIG.

(Other general processes)
Thereafter, the optical semiconductor element (an electroabsorption optical modulator) according to the third embodiment is manufactured through other general processes. Subsequent general steps may be performed by using various known techniques, and are not a new matter, and thus description thereof is omitted.

  In an electroabsorption optical modulator, when an Al oxide film is formed on the surface of a semiconductor layer containing Al, a leak current is generated, voltage cannot be applied, the extinction ratio is lowered, and EA (Electroabsorption) operation occurs. There is a problem of inhibiting.

  In the third embodiment, after forming the mesa structure 35, the amorphous As film 36 is formed without being exposed to the atmosphere, and the amorphous As film 36 is used as an anti-oxidation film between different chambers (that is, the processing chamber 49 and the processing chamber 49). The semiconductor wafer 340 can be transported between the chambers of the MOCVD apparatus. Thereafter, the amorphous As film 36 is desorbed by heating, and a buried layer can be formed.

  Moreover, according to the third embodiment, since the manufacturing apparatus 50 shown in FIG. 1 has the function of forming an amorphous As film, the mesa structure 35 is formed using the inexpensive manufacturing apparatus 50. The amorphous As film 36 can be formed without exposing the semiconductor layer containing Al to the atmosphere.

  According to the manufacturing method and the manufacturing apparatus according to the third embodiment described above, it is possible to reliably prevent the occurrence of the above problem due to the formation of the Al oxide film and to manufacture the electroabsorption optical modulator at a low cost.

  In the above embodiment, both sides of the mesa structure 35 are buried with the high resistance InP buried layer 37. However, the present invention is not limited to this, and a semiconductor layer such as a high resistance undoped InAlAs layer may be embedded.

  Furthermore, in the heating process and the buried layer forming process described above, the amorphous As film may be removed by crystal growth or heating in the apparatus using a crystal growth apparatus other than the MOCVD apparatus, for example, an MBE apparatus. .

  In the third embodiment, the n-type InP substrate 28 is used. However, the same effect can be obtained even in the case of an inversion layer structure using a p-type substrate. The same effect can be obtained even when a high-resistance semiconductor substrate such as semi-insulating InP is used for the substrate.

1 p-type InP substrate, 2 p-type InP cladding layer, 3 p-type Al (Ga) InAs lower light confinement layer, 4 AlGaInAs multiple quantum well active layer, 5 n-type Al (Ga) InAs light confinement layer, 6 n-type InP cladding layer, 7 semiconductor laminated structure, 8 SiO ₂ film, 9 mesa structure, 10 amorphous As film, 11 p-type InP buried layer, 12 n-type current blocking layer, 13 p-type InP current blocking layer, 14 n-type InP buried layer, 15 n-type contact layer, 16 n-type InGaAs contact layer, 38 crucible, 38a heater resistance, 38b energization control unit, 39 crucible shutter, 40 semiconductor wafer, 41 etching termination detector, 42 Shutter, 43 Etching gas inlet, 43a Etching gas supply device, 44 Shutter, 45 Anode, 46 Cathode, 47 Blocking condenser , 48 RF oscillator 49 processing chamber 50 manufacturing apparatus, 51 the temperature regulating chiller, 51a, 51b the coolant supply unit

Claims (8)

Etching is performed on a semiconductor substrate on which a semiconductor layer containing Al is stacked in the same chamber or in a plurality of chambers that are separated from the atmosphere through a passage portion to expose at least a part of the semiconductor layer. Forming a mesa structure and forming an antioxidant film for preventing oxidation of the semiconductor layer containing Al exposed in the mesa structure; and
A transfer step of unloading the semiconductor substrate from the same chamber or the plurality of chambers after the mesa structure forming step and loading the semiconductor substrate into another chamber included in the semiconductor crystal growth apparatus;
In the other chamber, the embedding step of embedding both sides of the mesa structure with an embedding layer after removing the antioxidant film;
An optical semiconductor device manufacturing method comprising: The antioxidant film is an amorphous As film;
2. The method of manufacturing an optical semiconductor element according to claim 1, wherein the embedding step desorbs the amorphous As film from the mesa structure by heating the amorphous As film.   3. The method of manufacturing a semiconductor device according to claim 2, wherein in the embedding step, the amorphous As film is removed by heating the amorphous As film to a temperature of 250 ° C. or more.   4. The method of manufacturing a semiconductor device according to claim 2, wherein the mesa structure forming step forms the amorphous As film on the surface of the mesa structure at a temperature of 10 [deg.] C. or less. The mesa structure forming step includes
A dry etching apparatus having an antioxidant film forming portion in the chamber;
An anti-oxidation film forming apparatus, a dry etching apparatus, and an apparatus provided with a transfer passage for isolating and connecting the chambers of these apparatuses from the atmosphere;
Using one of the
5. The method of manufacturing a semiconductor device according to claim 1, wherein the antioxidant film is continuously formed on a surface of the mesa structure after the etching for forming the mesa structure. 6. A chamber with a pedestal;
An etching gas supply for communicating with the chamber and etching the semiconductor substrate on the pedestal;
An anti-oxidation film forming portion for forming an anti-oxidation film on the semiconductor substrate on the pedestal, communicating with the chamber;
An opening / closing mechanism that selectively switches between communication and blocking of the etching gas supply unit and the antioxidant film forming unit to the chamber;
An apparatus for manufacturing a semiconductor element, comprising: The antioxidant film is an amorphous As film;
The said antioxidant film | membrane formation part is an As supply part which supplies an As molecule | numerator in a recording chamber so that an amorphous As film | membrane may be formed in the semiconductor substrate on the said base. Semiconductor device manufacturing equipment.   The semiconductor device manufacturing apparatus according to claim 7, wherein the As supply unit includes a crucible communicating with the chamber and a heater for heating the crucible.

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