JP2014175621A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device that allows improving a withstand voltage.SOLUTION: A semiconductor device has a first guard-ring layer formed on an element region side; and a second guard-ring layer surrounding the first guard-ring layer and having a predetermined distance. Moreover, the semiconductor device has a first trench formed between the first guard-ring layer and the second guard-ring layer and being in contact with the first guard-ring layer; and a second trench formed between the first guard-ring layer and the second guard-ring layer, having a predetermined spacing from the first guard-ring layer, and being in contact with the second guard-ring layer.

Description

  Embodiments described herein relate generally to a semiconductor device.

  For example, in a semiconductor device used as a power device, a plurality of guard ring layers are formed so as to surround an element region of the semiconductor device. In general, a region where the guard ring layer is formed is called a termination region. When a reverse voltage is applied to the element region, a depletion layer is formed from the portion of the element region where the PN junction is formed and extends to the termination region, thereby preventing electric field concentration and improving the breakdown voltage.

  The narrower the gap between the guard ring layers in the termination region, the easier it is to form a depletion layer in the direction of termination, so that the effect of improving the breakdown voltage of the semiconductor device is easily obtained. However, the narrower the gap between the guard ring layers, the more likely that the gap will vary during formation.

JP 2003-273291 A

  The problem to be solved by the present invention is to provide a semiconductor device capable of improving the breakdown voltage.

The semiconductor device of the embodiment includes a first guard ring layer formed on the element region side,
A second guard ring layer surrounding the first guard ring layer and having a predetermined distance is included. A first trench formed between the first guard ring layer and the second guard ring layer and in contact with the first guard ring layer; the first guard ring; and the second guard ring. A second trench formed between the layers, having a predetermined distance from the first guard ring layer and in contact with the second guard ring layer;

1 is a schematic plan view showing a surface of a termination region of a semiconductor substrate 2 according to a first embodiment. Sectional drawing which shows the cross section in the A-A 'line shown in FIG. Sectional drawing which shows the structure of the semiconductor device 1b which concerns on 2nd Embodiment.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. The drawings used in the description in the embodiments are schematic for ease of description, and the shape, size, magnitude relationship, etc. of each element in the drawings are not necessarily shown in the drawings in actual implementation. The present invention is not limited to the above, and can be appropriately changed within a range in which the effect of the present invention can be obtained. Although the first conductivity type is described as N-type and the second conductivity type is described as P-type, the opposite conductivity types may be used. In addition, when N-type conductivity is represented by N ⁺ , N, and N ⁻ , the N-type impurity concentration decreases in this order.

[First Embodiment]
FIG. 1 is a schematic plan view showing the surface of the termination region 30 of the semiconductor substrate 2 according to the first embodiment. In FIG. 1, details of the insulating film, the electrode, and the element region are omitted. FIG. 2 is a cross-sectional view showing a cross section taken along line AA ′. As shown in FIGS. 1 and 2, the semiconductor substrate 2 of the semiconductor device 1 a has an element region 31 and a termination region 30. The element region 31 is located in the central region of the semiconductor substrate 2, and the termination region 30 is a region formed so as to surround the element region 31. For example, silicon (Si) is used for the semiconductor substrate 2, but it can also be applied to compound semiconductors such as silicon carbide (SiC) and nitride semiconductor (GaN).

  The structure of the element region 31 will be described. In the element region 31, elements having functions such as a MOSFET (Metal Oxide Semiconductor Field Effect Transistor), an IGBT (Insulated-Gate Bipolar Transistor), and a diode are formed, for example. In the present embodiment, an IGBT is formed in the element region 31.

The semiconductor substrate 2 has an N ⁻ -type base layer 3 common to the element region 31 and the termination region 30, and a P-type base layer 10 on the surface of the element region 3 1. The semiconductor substrate 2 has a plurality of gate trenches 11 so as to be in contact with the P-type base layer 10 and the N ⁻ -type base layer 3. The gate trench 11 is electrically connected to the gate electrode 13 through the gate insulating film 12. The plurality of N-type emitter layers 14 are provided so as to be in contact with the side surface of the gate trench 11. The emitter electrode 15 is connected to the N-type emitter layer 14. As the gate insulating film 12, for example, silicon oxide is used, but other insulators such as silicon nitride, silicon oxynitride, and alumina can also be used.

A P-type collector layer 16 is provided on the other surface of the semiconductor substrate 2 via an N ^{+ -type} buffer layer 4. The P-type collector layer 16 is in contact with the collector electrode 17.

The structure of the termination region 30 will be described. First, the semiconductor substrate 2 lists the elements that constitute the termination region. The termination region includes an N ⁻ -type base layer 3, first to fourth guard ring layers 18 to 21, first and second trenches 40 and 41, and the like. The first to fourth P-type guard ring layers 18 to 21 are sequentially arranged from the element region 31 side. The first to fourth P-type guard ring layers 18 to 21 extend from the surface of the semiconductor substrate 2 in the termination region 30 into the semiconductor substrate 2. The distance between the first to fourth P-type guard ring layers 18 to 21 is shorter as it is closer to the element region 31. That is, the distance between the first P-type guard ring layer 18 and the second P-type guard ring layer 19 is the shortest. The first to fourth P-type guard ring layers 18 to 21 prevent a high electric field from being applied near the end of the P-type base layer 10 when a reverse voltage is applied to the semiconductor device 1a.

  The semiconductor substrate 2 is in contact with the first P-type guard ring layer 18 and the second P-type guard ring layer 19 between the first P-type guard ring layer 18 and the second P-type guard ring layer 19. First and second trenches 40 and 41 are provided. The first and second trenches 40 and 41 have first and second trench electrodes 42 and 43 made of, for example, conductive polysilicon in the trench insulating film 44. The first and second trench electrodes 42 and 43 may be a semiconductor other than polysilicon or a metal. As the trench insulating film 44, for example, silicon oxide is used, but other insulators such as silicon nitride, silicon oxynitride, and alumina can also be used.

  The aluminum electrode 24 covers the first to fourth P-type guard ring layers 18 to 21. The aluminum electrode 24 relaxes the concentration of the electric field distribution in the vicinity of the first to fourth P-type guard ring layers 18 to 21. The aluminum electrode 24 also has the function of a field plate electrode.

An insulating film 22 is formed between the first to fourth P-type guard ring layers. The insulating film 22 protects the upper surface of the N ⁻ -type base layer 3. As the insulating film 22, silicon oxide will be described as an example, but other insulators such as silicon nitride, silicon oxynitride, and alumina may be used.

  In FIG. 1, the first and second trenches 40 and 41 are formed to make the distance between the first and second P-type guard ring layers 18 and 19 constant. You may form between the shape guard ring layers 20 and 21. FIG. The number of P-type guard ring layers is not particularly limited because it is generally determined by the breakdown voltage required for the semiconductor device 1a.

Next, the operation of the semiconductor device 1a will be described. As shown in FIG. 2, the semiconductor device 1 a includes an N-channel MOS transistor, an N-type emitter layer 14, a P-type base layer 10, and an N ⁻ -type base layer 3 provided along the gate trench 11 side. Consists of. The PNP-type bipolar transistor includes a P-type base layer 10, an N ⁻ -type base layer 3, and a P-type collector layer 16. The semiconductor device 1a operates by a combined operation of these MOS transistors and PNP transistors.

  For example, a positive voltage larger than the threshold voltage is applied to the gate electrode 13 with a positive potential applied to the collector electrode 17 with respect to the emitter electrode 15. In this case, an inversion layer is formed on the surface of the P-type base layer 10 in contact with the gate insulating film 12. As a result, the MOS transistor is turned on, and an electronic current flows through the MOS transistor.

This electron current flows from the emitter electrode 15 to the collector electrode 17 through the N-type emitter layer 14, the inversion layer (that is, the channel of the MOS transistor), the N ⁻ -type base layer 3, and the N ^{+ -type} buffer layer 4.

This electron current functions as the base current of the PNP transistor described above. That is, when an electron current flows, the PNP transistor is turned on, and a hole current flows through the PNP transistor. This hole current flows from the collector electrode 17 to the emitter electrode 15 through the P-type collector layer 16, the N ^{+ -type} buffer layer 4, the N ⁻ -type base layer 3, and the P-type base layer 10.

  As described above, by applying a positive voltage equal to or higher than the threshold value to the gate electrode 13, an electronic current flows through the MOS transistor. The electron current supplies a base current to the PNP transistor, and then the PNP transistor is turned on.

  By applying zero or a negative voltage to the gate electrode 13, the inversion layer that is an electron path is eliminated, and the electron current from the emitter electrode 15 is cut off. Therefore, the hole current from the collector electrode 17 is also eliminated, and the semiconductor device 1a is turned off.

  Accordingly, in the semiconductor device 1a, the on-state and off-state of the PNP transistor are switched by controlling the voltage of the gate electrode 13 to switch the on-state and off-state of the MOS transistor.

  Here, it is generally known that the avalanche phenomenon is likely to occur in the semiconductor device 1a at the time of turn-off of a high current density, and the element may be destroyed by the avalanche current. In particular, the semiconductor device 1a having the trench structure as in this embodiment has a structure in which the electric field concentration at the bottom surface of the gate trench 11 is large. For example, the avalanche current is locally concentrated on the bottom surface of the gate trench 11, The gate insulating film 12 is easily destroyed.

On the other hand, in the case of an IGBT, first to fourth P-type guard ring layers 18 to 21 are provided in the termination region 30 of the semiconductor device 1a. In the off state, N ^- than the application of a reverse bias voltage between -type base layer 3 and the P-type base layer 10, N of the element region 31 ^- to form a depletion layer between -type base layer 3 and the P-type base layer 10. Thereby, electric field concentration at the end of the element region 31 can be suppressed.

  The depletion layer extends around the first to fourth P-type guard ring layers 18 to 21 and finally extends to the entire termination region 30. Thereafter, the depletion layer reaches the stopper layer 21.

  The effect of the semiconductor device 1a will be described. As a comparative example, consider a case where the first and second trenches 40 and 41 are not provided between the first P-type guard ring layer 18 and the second P-type guard ring layer 19.

As described above, when the OFF state of the semiconductor device 1a, N ^- from the interface -type base layer 3 and the P-type base layer 10, N ^- depletion occurs stretching toward -type base layer 3. At this time, the shorter the distance between the guard ring layers, the easier the depletion layer extends to the termination region, leading to an improvement in breakdown voltage. However, in the case of the comparative example, the diffusion depth of the guard ring layer in the direction of the termination region 30 and the element region direction 31 varies by about 5% at the time of formation, so the interval between the P-type guard ring layers is controlled with high accuracy. It is difficult to do. For example, when a guard ring layer having a depth of 8 μm is formed, the gap between the guard ring layers varies by about 1 μm. In the present embodiment, first and second trenches 40 and 41 are formed in advance so as to partition the first and second P-type guard ring layers 18 and 19. Thus, the first and second trenches 40 and 41 suppress the P-type guard ring layer from spreading beyond a predetermined width when forming the first and second P-type guard ring layers 18 and 19. . That is, variation in the width of the P-type guard ring layer can be reduced. In the semiconductor device 1a of the present embodiment, since the distance between the first and second trenches 40 and 41 can be formed with 1 μm or less, the distance between the P-type guard ring layers can be controlled with high accuracy. is there.

  For example, when there is a heat treatment step during manufacturing, in the comparative example, the distance between the P-type guard ring layers changes due to diffusion. For this reason, it is difficult to control the interval between the P-type guard ring layers during the heat treatment. In the case of the present embodiment, the first and second trenches 40 and 41 suppress variation in the distance between the P-type guard ring layers due to the diffusion of the P-type guard ring layer. For this reason, the interval between the P-type guard ring layers after the heat treatment can be controlled with high accuracy.

Thereby, as described above, in the off state, a depletion layer formed by applying a reverse bias to the PN junction between the N ⁻ -type base layer 3 and the P-type base layer 10 extends in the direction of the termination region 30, In addition to suppressing the electric field concentration in the region 31, the electric field concentration in the gate electrode 13 can be reduced. Therefore, as a result, the breakdown voltage of the semiconductor device 1a can be improved.

[Second Embodiment]
The semiconductor device 1b according to the second embodiment includes a second P-type base layer between the first and second trenches 40 and 41 that is shallower than the first and second trenches 40 and 41. 39. FIG. 3 is a cross-sectional view showing the structure of the semiconductor device 1b according to the second embodiment. Since other structures are the same as those of the semiconductor device 1a of the first embodiment, the description thereof is omitted. The second P-type base layer 39 only needs to be shallower than the P-type base layer 10 and may not have the same depth as the P-type base layer 10.

  In the off state, the equipotential line having a high potential extends to the side wall portions of the first and second trenches 40 and 41 due to the field plate effect of the first and second trenches 40 and 41. At this time, as the first and second trenches 40 and 41 are deeper, the electric field is more likely to be concentrated on the end portions of the first and second trenches 40 and 41, so that the portions are easily destroyed. By providing the second P-type base layer 39 between the first and second trenches 40 and 41, the equipotential lines are unlikely to penetrate deeply between the first and second trenches 40 and 41 in the off state. Become. This makes it difficult for the electric field to concentrate on the end portions of the first and second trenches 40 and 41, and prevents the first and second trenches 40 and 41 from being destroyed.

  Although the embodiment of the present invention has been described, this embodiment is presented as an example and is not intended to limit the scope of the invention. This embodiment can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the spirit of the invention. This embodiment and its modifications are included in the scope of the present invention and the gist thereof, and are also included in the invention described in the claims and the equivalent scope thereof.

1a, 1b ... semiconductor device, 2 ... semiconductor substrate, 3 ... N ^- -type base layer, 4 ... N ⁺ buffer layer, 10 ... P-type base layer, 11 ... gate trenches, 12 ... gate insulating film, 13 ... gate electrode, 14 ... N-type emitter layer, 15 ... Emitter electrode, 16 ... P-type collector layer, 17 ... Collector electrode, 18 ... First P-type guard ring layer, 19 ... Second P-type guard ring layer, 20 ... Third P-type guard ring layer, 21 ... fourth P-type guard ring layer, 22 ... insulating film, 23 ... stopper layer, 24 ... aluminum electrode, 30 ... termination region, 31 ... element region, 39 ... second P-type Base layer layer 40 ... first trench 41 ... second trench 42 ... first trench electrode 43 ... second trench electrode 44 ... trench insulating film

Claims (4)

A first guard ring layer formed on the element region side;
A second guard ring layer provided so as to surround the first guard ring layer;
A first trench formed between the first guard ring layer and the second guard ring layer and in contact with the first guard ring layer;
A second trench provided at a predetermined interval from the first trench and in contact with the second guard ring layer;
A semiconductor device.   A second conductivity type base layer provided between the first trench and the second trench and provided to be shallower than the first trench and the second trench in the depth direction of the semiconductor substrate. The semiconductor device according to claim 1, comprising: The semiconductor device according to claim 1, wherein an electrode is provided in the first trench and the second trench via an insulating film. The semiconductor device according to claim 1, wherein an interval between the first trench and the second trench is 1 μm or less.

Images