JP2014161099A5 - - Google Patents
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- JP2014161099A5 JP2014161099A5 JP2014091789A JP2014091789A JP2014161099A5 JP 2014161099 A5 JP2014161099 A5 JP 2014161099A5 JP 2014091789 A JP2014091789 A JP 2014091789A JP 2014091789 A JP2014091789 A JP 2014091789A JP 2014161099 A5 JP2014161099 A5 JP 2014161099A5
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- JP
- Japan
- Prior art keywords
- duty ratio
- cycle
- ratio calculation
- period
- pwm control
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Description
図１から明らかなとおり、このデジタルＰＷＭ制御装置は、デューティ比演算部がデューティ比の演算に要する時間Ｔｓ１と、パルス出力部が出力することのできる最大デューティ比のパルス長に相当する時間Ｔｓ２の合計が、基本クロックの周期Ｔ０よりも長い。この関係は、デューティ比演算部がパルス出力部と並列に動作できることによって達成される。また、図１から明らかなとおり、デューティ比演算の周期とパルス出力の周期はともに基本クロックの周期Ｔｓ０に等しく、パルス出力はデューティ比演算に要する一定時間Ｔｓ１の後となるので、パルス出力の周期はその位相がデューティ比演算に要する時間だけデューティ比演算の周期よりずれることになる。 As is apparent from FIG. 1, this digital PWM control device includes a time Ts1 required for the duty ratio calculation unit to calculate the duty ratio and a time Ts2 corresponding to the pulse length of the maximum duty ratio that can be output by the pulse output unit. The sum is longer than the period T0 of the basic clock. This relationship is achieved by the fact that the duty ratio calculation unit can operate in parallel with the pulse output unit. As is clear from FIG. 1, both the duty ratio calculation period and the pulse output period are equal to the basic clock period Ts0, and the pulse output is after a certain time Ts1 required for the duty ratio calculation. The phase shifts from the duty ratio calculation period by the time required for the duty ratio calculation.
Claims (1)
前記第２の周期は、前記第１の周期より位相を前記デューティ比演算に要する時間だけずらして制御する、
ことを特徴とするデジタルＰＷＭ制御装置。 The length of the first cycle that is the cycle of the duty ratio calculation of the PWM control is the same as the length of the second cycle that is the cycle of outputting the pulse of the duty ratio determined by the duty ratio calculation,
The second period is controlled by shifting the phase by the time required for the duty ratio calculation from the first period.
A digital PWM control device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2014091789A JP2014161099A (en) | 2014-04-25 | 2014-04-25 | Digital pwm control device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2014091789A JP2014161099A (en) | 2014-04-25 | 2014-04-25 | Digital pwm control device |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2009000494A Division JP2010161432A (en) | 2009-01-06 | 2009-01-06 | Digital pwm controller |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2014161099A JP2014161099A (en) | 2014-09-04 |
| JP2014161099A5 true JP2014161099A5 (en) | 2014-10-16 |
Family
ID=51612413
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2014091789A Pending JP2014161099A (en) | 2014-04-25 | 2014-04-25 | Digital pwm control device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2014161099A (en) |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04295290A (en) * | 1991-03-20 | 1992-10-20 | Nec Corp | Pulse width modulation signal generating system for digital servo |
| JPH05110441A (en) * | 1991-10-16 | 1993-04-30 | Matsushita Electric Ind Co Ltd | Prediction output d/a converter |
| JPH07111796A (en) * | 1993-10-12 | 1995-04-25 | Nippondenso Co Ltd | Driving circuit |
| JP4886287B2 (en) * | 2005-12-08 | 2012-02-29 | 株式会社ケーヒン | Brushless motor system |
| JP4908129B2 (en) * | 2006-09-26 | 2012-04-04 | 住友重機械工業株式会社 | Current control method and drive control apparatus using the method |
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2014
- 2014-04-25 JP JP2014091789A patent/JP2014161099A/en active Pending
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