JP2014154685A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To facilitate improvement of the performance of a semiconductor device, which is represented by reduction of on-resistance.SOLUTION: An n-type semiconductor region SNR for a source contact, and an n-type semiconductor region DNR for a drain contact are formed so that the distance between the n-type semiconductor region SNR for a source contact and the n-type semiconductor region DNR for a drain contact is smaller than the distance between a source electrode SE and a drain electrode DE. The source electrode SE is directly in contact with the n-type semiconductor region SNR for a source contact, and the drain electrode DE is directly in contact with the n-type semiconductor region DNR for a drain contact. Furthermore, the depth of the n-type semiconductor region SNR for a source contact and the depth of the n-type semiconductor region DNR for a drain contact are shallower than a heterojunction interface between a channel layer CH and an electron supply layer ES.

Description

  The present invention relates to a semiconductor device and a manufacturing technique thereof, for example, a semiconductor device using a nitride semiconductor layer and a technique effective when applied to the manufacturing technique thereof.

  Japanese Patent Laying-Open No. 2010-192716 (Patent Document 1) describes a technique for forming a source region in contact with a source electrode in the electron supply layer and forming a drain region in contact with the drain electrode in the electron supply layer. ing. In this technique, a thermal diffusion region formed by thermally diffusing an n-type impurity is formed between the source region and the drain region in self-alignment with the gate electrode.

  Japanese Unexamined Patent Application Publication No. 2009-152318 (Patent Document 2) describes a technique in which a metal layer (TiAl layer) is formed between an electron supply layer and a source electrode and between an electron supply layer and a drain electrode. Has been.

JP 2010-192716 A JP 2009-152318 A

  Group III nitride semiconductors typified by gallium nitride (GaN) have a high breakdown voltage of 3 MV / cm. Therefore, semiconductor devices using nitride semiconductors are high frequency power amplifiers such as microwaves, inverters, etc. Application to power supply circuits is expected. Further, for semiconductor devices using nitride semiconductors, further improvement in performance represented by reduction of on-resistance is desired for application to the above-described high-frequency power amplifier and power supply circuit.

  Other problems and novel features will become apparent from the description of the specification and the accompanying drawings.

  In the semiconductor device (field effect transistor) in one embodiment, the first distance between the source contact n-type semiconductor region and the drain contact n-type semiconductor region is the second distance between the source electrode and the drain electrode. Smaller than. The source electrode and the source contact n-type semiconductor region are in direct contact, and the drain electrode and the drain contact n-type semiconductor region are in direct contact. Furthermore, the depth of the source contact n-type semiconductor region and the depth of the drain contact n-type semiconductor region are both shallower than the interface between the channel layer and the electron supply layer.

  In one embodiment, a method for manufacturing a semiconductor device includes a step of forming a reaction film on an electron supply layer, performing a heat treatment, and then removing the reaction film.

  According to one embodiment, it is possible to improve performance represented by reduction of on-resistance.

It is sectional drawing which shows the structural example of the semiconductor device in related technology. 3 is a cross-sectional view illustrating a configuration example of a semiconductor device in Embodiment 1. FIG. 7 is a cross-sectional view showing a manufacturing step of the semiconductor device in the first embodiment. FIG. FIG. 4 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 3; FIG. 5 is a cross-sectional view showing the manufacturing process of the semiconductor device, following FIG. 4; FIG. 6 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 5; FIG. 7 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 6; FIG. 8 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 7; FIG. 9 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 8; FIG. 10 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 9; FIG. 7 is a band diagram showing the distribution of the band potential of the conduction band before the n-type semiconductor region for drain contact is formed, and is a band diagram along the line AB in FIG. 6. FIG. 11 is a band diagram showing a band potential distribution of a conduction band after an n-type semiconductor region for drain contact is formed, and is a band diagram along the line AB in FIG. 10. FIG. 10 is a cross-sectional view illustrating a configuration example of a semiconductor device in a second embodiment. 7 is a cross-sectional view illustrating a configuration example of a semiconductor device in Embodiment 3. FIG. FIG. 10 is a cross-sectional view illustrating a configuration example of a semiconductor device in a fourth embodiment. FIG. 10 is a cross-sectional view showing a manufacturing step of the semiconductor device in the fourth embodiment. FIG. 17 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 16; FIG. 18 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 17; FIG. 19 is a cross-sectional view showing the manufacturing process of the semiconductor device, following FIG. 18; FIG. 20 is a cross-sectional view showing the manufacturing process of the semiconductor device, following FIG. 19; FIG. 21 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 20;

  In the following embodiments, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant to each other. There are some or all of the modifications, details, supplementary explanations, and the like.

  Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), especially when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number.

  Further, in the following embodiments, the constituent elements (including element steps and the like) are not necessarily indispensable unless otherwise specified and apparently essential in principle. Needless to say.

  Similarly, in the following embodiments, when referring to the shape, positional relationship, etc., of components, etc., unless otherwise specified, and in principle, it is considered that this is not clearly the case, it is substantially the same. Including those that are approximate or similar to the shape. The same applies to the above numerical values and ranges.

  In all the drawings for explaining the embodiments, the same members are denoted by the same reference symbols in principle, and the repeated explanation thereof is omitted. In order to make the drawings easy to understand, even a plan view may be hatched.

(Embodiment 1)
<Description of related technologies>
FIG. 1 is a cross-sectional view illustrating a configuration example of a semiconductor device in the related art. In the related art, a field effect transistor (FET) composed of a high electron mobility transistor will be described as an example of a semiconductor device.

  In the field effect transistor in the related art shown in FIG. 1, a channel layer CH made of GaN (gallium nitride) is formed on a semiconductor substrate 1S made of sapphire, SiC (silicon carbide), Si (silicon), or the like. . On the channel layer CH, an electron supply layer ES made of AlGaN, InGaN, InAlN, or the like is stacked. Thereby, the electron supply layer ES and the channel layer CH form a heterojunction. At this time, the channel layer CH and the electron supply layer are affected by the conduction band offset based on the difference in electron affinity between the channel layer CH and the electron supply layer ES, and the influence of piezoelectric polarization and spontaneous polarization existing in the channel layer CH and the electron supply layer ES. A well-type potential lower than the Fermi level is generated near the interface of the ES. As a result, electrons are accumulated in the well-type potential, thereby generating a two-dimensional electron gas DEG near the interface between the channel layer CH and the electron supply layer ES.

  A gate electrode GE made of W (tungsten), W alloy (tungsten alloy), Mo (molybdenum), or Mo alloy (molybdenum alloy) is disposed on the surface of the electron supply layer ES. A source electrode SE and a drain electrode DE are arranged so as to be sandwiched. That is, the gate electrode GE is disposed so as to be sandwiched between the pair of source electrode SE and drain electrode DE.

  Under the source electrode SE, a source whose carrier concentration is increased by ion implantation of silicon (Si) or tin (Sn) as an n-type impurity (donor) and heat treatment after ion implantation (ion activation heat treatment). Region 101 is formed. Similarly, a drain region 102 in which the carrier concentration is increased is formed under the drain electrode DE by ion implantation of n-type impurities and heat treatment after ion implantation. As shown in FIG. 1, the source region 101 and the drain region 102 are formed so as to be deeper than the heterojunction surface between the electron supply layer ES and the channel layer CH.

  Further, in the related art, a thermal diffusion region 103 and a thermal diffusion region 104 in which n-type impurities such as silicon (Si) and Sn (tin) are thermally diffused are formed in a self-aligned manner with respect to the gate electrode GE. Yes. As shown in FIG. 1, the depths of the thermal diffusion region 103 and the thermal diffusion region 104 are deeper than the heterojunction surface between the electron supply layer ES and the channel layer CH, and the source region 101 and the drain region 102. It is formed shallower than the depth of.

  As described above, in the related art, the source region 101, the drain region 102, the thermal diffusion region 103, and the thermal diffusion region 104, which are regions where the n-type impurity is added to increase the carrier concentration, are formed. As a result, according to the related art, the contact resistance between the source electrode SE or the drain electrode DE and the semiconductor layer, and between the source electrode SE and the gate electrode GE, and between the drain electrode DE and the gate electrode GE. Access resistance can be reduced. Therefore, according to the related art, it is possible to reduce the on-resistance composed of the contact resistance, the access resistance, and the channel resistance of the channel region, thereby realizing a field effect transistor having a low on-resistance. For example, according to the related art, in a field effect transistor having a withstand voltage of 100 V, it is possible to realize electrical characteristics with a gate leakage current of 5 nA / mm, a drain leakage current of 8 nA / mm, and an on-resistance of 2.8 Ωmm.

<Room for improvement in related technologies>
However, as a result of the present inventors diligently examining the related technique shown in FIG. 1, it has become clear that there is some room for improvement in the related technique. Below, the room for improvement existing in the related art will be described.

  As a room for first improvement, since W, W alloy, Mo or Mo alloy is used for the gate electrode GE, Ni (nickel) generally used in a field effect transistor using a nitride semiconductor material. Compared with the gate electrode GE made of Pt (platinum) or Pt (platinum), the gate leakage current is increased.

  As a room for the second improvement, the source region 101, the drain region 102, the thermal diffusion region 103, and the thermal diffusion region 104 are formed deeper than the heterojunction surface between the electron supply layer ES and the channel layer CH. The so-called drain leakage current that flows between the source electrode SE and the drain electrode DE when the field effect transistor is in an off state increases.

  As a room for the third improvement, since the thermal diffusion region 103 and the thermal diffusion region 104 are formed deeper than the heterojunction surface between the electron supply layer ES and the channel layer CH, the effect of reducing access resistance is limited. There is a point.

  Further, as a fourth room for improvement, the ion implantation method is used to form the source region 101 and the drain region 102, and therefore the effect of reducing the contact resistance is limited.

  Hereinafter, the cause of such improvement in the related art will be described in detail. First, the increase in the gate leakage current, which is a room for the first improvement, is due to the use of W, W alloy, Mo or Mo alloy for the gate electrode GE. That is, in the related art, a heat treatment at a high temperature of 800 ° C. or higher is required to form the thermal diffusion region 103 and the thermal diffusion region 104. For this reason, as a material of the gate electrode GE, W, W alloy, Mo, or Mo alloy having a high melting point that can withstand high-temperature heat treatment is used. However, these metals have a work function smaller than that of Ni (nickel) or Pt (platinum) generally used in a field effect transistor using a nitride semiconductor material. Therefore, the height of the Schottky barrier formed between the gate electrode GE and the semiconductor layer (electron supply layer ES) is reduced. This means that the number of carriers that surpass the Schottky barrier in terms of energy increases. Therefore, according to the related art that forms the gate electrode GE from a material having a low Schottky barrier, the gate leakage current may increase. Recognize.

  Next, an increase in drain leakage current, which is a room for second improvement, is that the source region 101, the drain region 102, the thermal diffusion region 103, and the thermal diffusion region 104 are between the electron supply layer ES and the channel layer CH. This is due to the fact that it is formed deeper than the heterojunction surface formed in the step. The drain leakage current is a leakage current that flows around under the depletion layer extending from the gate electrode GE when the field effect transistor is in the off state. Accordingly, if the distance between the high concentration carrier region (source region 101 and thermal diffusion region 103) on the source electrode SE side and the high concentration carrier region (drain region 102 and thermal diffusion region 104) on the drain electrode DE side is short. The closer it is, and the deeper the formation depth of the high-concentration carrier region, the greater the drain leakage current.

  In this regard, in the related art, the thermal diffusion region 103 and the thermal diffusion region 104 are formed in a self-aligned manner with respect to the gate electrode GE. For this reason, the distance between the high-concentration carrier region on the source electrode SE side and the high-concentration carrier region on the drain electrode DE side is extremely small, about the gate length. In the related art, the thermal diffusion region 103 and the thermal diffusion region 104 are formed deeper than the heterojunction surface between the electron supply layer ES and the channel layer CH, which also increases the drain leakage current. Further, in the related technology, the source region 101 and the drain region 102 are formed deeper than the thermal diffusion region 103 and the thermal diffusion region 104, and the drain leakage current resulting from this overlaps. It can be seen that the drain leakage current increases.

  Subsequently, the effect of reducing the access resistance mentioned as the third room for improvement is limited in that the thermal diffusion region 103 and the thermal diffusion region 104 are heterojunctions between the electron supply layer ES and the channel layer CH. This is because it is formed deeper than the surface. That is, in the related art, since the n-type impurity crosses the heterojunction surface by thermal diffusion, the atomic arrangement in the vicinity of the heterojunction surface is disturbed, and the steepness of the heterojunction surface is impaired. As a result, the carrier mobility of the two-dimensional electron gas DEG existing on the channel layer CH side of the heterojunction surface is greatly reduced, which causes an increase in access resistance. That is, forming the thermal diffusion region 103 and the thermal diffusion region 104 deeper than the heterojunction surface between the electron supply layer ES and the channel layer CH reduces the access resistance due to an increase in carrier concentration and reduces the two-dimensional electrons. There is a tradeoff with an increase in access resistance due to a decrease in carrier mobility of the gas DEG, and as a result, the effect of reducing the access resistance is limited.

  Further, the effect of reducing the contact resistance mentioned as the fourth room for improvement is limited in that ion implantation and heat treatment following ion implantation are used for forming the source region 101 and the drain region 102. caused by. In particular, when a method of epitaxially growing a nitride semiconductor layer on a silicon substrate, which is known as an effective means for reducing the manufacturing cost of a field effect transistor using a nitride semiconductor material, as in the related art, is remarkable. It becomes.

As a result of intensive studies by the inventors, high-temperature heat treatment at 1150 ° C. or higher is necessary to increase the activation rate of the n-type impurity ion-implanted to such an extent that a contact resistance as low as 10 ⁻⁶ Ωcm ² can be obtained. I understood. However, when a high-temperature heat treatment at 1100 ° C. or higher is performed on the semiconductor substrate 1S obtained by epitaxially growing a nitride semiconductor layer on a silicon substrate, an increase in warpage and the occurrence of cracks become obvious as problems. For this reason, when the temperature of the heat treatment for activating the ion-implanted n-type impurity was limited to 1100 ° C. or less, it was found that crystal defects caused by the ion implantation were not sufficiently recovered by this heat treatment, As a result, the contact resistance was 10 ⁻⁵ Ωcm ² or more, and it was found that a sufficient reduction effect of the contact resistance could not be obtained. That is, when an ion implantation method is used to form the source region 101 and the drain region 102, a heat treatment at a high temperature of 1150 ° C. or higher is required to sufficiently reduce the contact resistance. However, when such high-temperature heat treatment is performed, the semiconductor substrate 1S is warped and cracks are generated, so that the high-temperature heat treatment cannot be performed, and thus the effect of reducing contact resistance is limited. It becomes a thing.

  From the above, there is a room for improvement as described above in the related art. Therefore, in the first embodiment, a device for overcoming the room for improvement existing in the related art is taken. Below, the technical idea in this Embodiment 1 which gave this device is demonstrated.

<Configuration of Semiconductor Device in Embodiment 1>
FIG. 2 is a cross-sectional view illustrating a configuration example of the semiconductor device according to the first embodiment. In Embodiment 1, a field effect transistor including a high electron mobility transistor is described as an example of a semiconductor device.

  As shown in FIG. 2, in the field effect transistor according to the first embodiment, a buffer layer BUF made of, for example, an AlN layer is formed on a semiconductor substrate 1S made of, for example, silicon. A channel layer (electron transit layer) CH made of, for example, a GaN layer or an InGaN layer is formed on the buffer layer BUF. For example, an AlGaN layer, an InAlN layer, or an InAlGaN layer is formed on the channel layer CH. An electron supply layer ES is formed.

  Here, the buffer layer BUF is formed for the purpose of relaxing mismatch between the lattice spacing of silicon (Si) constituting the semiconductor substrate 1S and the lattice spacing of the group III nitride semiconductor layer constituting the channel layer CH. That is, when the channel layer CH made of a group III nitride semiconductor layer is formed directly on the semiconductor substrate 1S made of silicon, a large number of crystal defects are formed in the channel CH, leading to performance degradation of the field effect transistor. It will be. Therefore, the buffer layer BUF for the purpose of lattice relaxation is inserted between the semiconductor substrate 1S and the channel layer CH. By forming the buffer layer BUF, it is possible to improve the quality of the channel layer CH formed on the buffer layer BUF, thereby improving the performance of the field effect transistor.

In the first embodiment, an example in which silicon (Si) is used as the semiconductor substrate 1S is described. However, the present invention is not limited to this, and silicon carbide (SiC), sapphire (Al ₂ O ₃ ), gallium nitride ( A substrate made of GaN) or diamond (C) may be used.

  Subsequently, in the field effect transistor according to the first embodiment, the source electrode SE and the drain electrode DE are formed on the electron supply layer ES, and the electron supply layer is sandwiched between the source electrode SE and the drain electrode DE. A gate electrode GE is formed on the ES. Side wall spacers SW are formed on the sidewalls on both sides of the gate electrode GE. The source contact n-type semiconductor region is formed in the surface region of the electron supply layer ES in alignment with the side wall spacers SW. An n-type semiconductor region DNR for SNR and drain contact is formed.

  That is, in the field effect transistor according to the first embodiment, the source contact n-type semiconductor region SNR and the drain contact n-type semiconductor region DNR are formed in the surface region of the electron supply layer ES so as to be separated from each other. The source contact n-type semiconductor region SNR and the drain contact n-type semiconductor region DNR are formed in alignment with the sidewall spacer SW. A source electrode SE is formed on the source contact n-type semiconductor region SNR, and the source contact n-type semiconductor region SNR and the source electrode SE are in direct contact with each other. Similarly, a drain electrode DE is formed on the drain contact n-type semiconductor region DNR, and the drain contact n-type semiconductor region DNR and the drain electrode DE are in direct contact with each other.

  At this time, in the first embodiment, as shown in FIG. 2, the distance L1 between the source contact n-type semiconductor region SNR and the drain contact n-type semiconductor region DNR is equal to the source electrode SE and the drain electrode DE. Is smaller than the distance L2. In other words, the distance L2 between the source electrode SE and the drain electrode DE is larger than the distance L1 between the source contact n-type semiconductor region SNR and the drain contact n-type semiconductor region DNR.

  Further, as shown in FIG. 2, the depth of the n-type semiconductor region SNR for source contact and the depth of the n-type semiconductor region DNR for drain contact are both from the interface between the channel layer CH and the electron supply layer ES. Is also shallower. In other words, the interface between the channel layer CH and the electron supply layer ES is formed at a position deeper than the depth of the source contact n-type semiconductor region SNR and the depth of the drain contact n-type semiconductor region DNR. become.

  In the field effect transistor according to the first embodiment configured as described above, the two-dimensional electron gas DEG is generated near the interface between the channel layer CH and the electron supply layer ES. That is, the channel layer CH and the electron supply layer ES are affected by the conduction band offset based on the difference in electron affinity between the channel layer CH and the electron supply layer ES, and the influence of piezoelectric polarization and spontaneous polarization existing in the channel layer CH and the electron supply layer ES. A well-type potential lower than the Fermi level is generated near the interface. As a result, electrons are accumulated in the well-type potential, and as a result, a two-dimensional electron gas DEG is generated near the interface between the channel layer CH and the electron supply layer ES.

Next, the gate electrode GE is formed of, for example, a nickel (Ni) film or a platinum (Pt) film, and the sidewall spacer SW formed on the side walls on both sides of the gate electrode GE is, for example, silicon nitride. It is formed from a film. Further, the source electrode SE and the drain electrode DE disposed so as to sandwich the gate electrode GE apart from each other are formed to include, for example, a titanium (Ti) film and an aluminum (Al) film. Furthermore, the source contact n-type semiconductor region SNR that is in direct contact with the source electrode SE includes, for example, nitrogen vacancies of 1 × 10 ¹⁹ cm ⁻³ or more. At this time, since the nitrogen vacancy functions as a donor type defect, the source contact n-type semiconductor region SNR functions as an n-type semiconductor region. Similarly, the drain contact n-type semiconductor region DNR that is in direct contact with the drain electrode DE also includes, for example, nitrogen vacancies of 1 × 10 ¹⁹ cm ⁻³ or more. Accordingly, the drain contact n-type semiconductor region DNR also functions as an n-type semiconductor region. Note that the source contact n-type semiconductor region SNR and the drain contact n-type semiconductor region DNR may contain silicon (Si) that functions as an n-type impurity. In this case, the source contact n-type semiconductor region SNR and the drain contact n-type semiconductor region DNR are caused by both nitrogen vacancies functioning as donor-type defects and silicon (Si) functioning as donors (n-type impurities). It will function as an n-type semiconductor region.

  In addition, the source contact n-type semiconductor region SNR and the drain contact n-type semiconductor region DNR have titanium (Ti), tantalum (Ta), molybdenum (due to the manufacturing method of the semiconductor device in the first embodiment). Any element of Mo), vanadium (V), niobium (Nb), chromium (Cr), Zr (zirconium), hafnium (Hf), and aluminum (Al) is contained. That is, in the first embodiment, the above-mentioned element is included in the source contact n-type semiconductor region SNR and the drain contact n-type semiconductor region DNR. It is contained not as an element necessary for the semiconductor region SNR and the drain contact n-type semiconductor region DNR but as an impurity element. That is, in the first embodiment, the above-mentioned elements are not intentionally introduced into the source contact n-type semiconductor region SNR and the drain contact n-type semiconductor region DNR. The above-described elements are contained as impurity elements in the type semiconductor region SNR and the drain contact n-type semiconductor region DNR.

  Therefore, if the above-described elements are contained in the source contact n-type semiconductor region SNR and the drain contact n-type semiconductor region DNR, the manufacturing method of the semiconductor device according to the first embodiment is inevitably required. It means that it was implemented. In other words, when the semiconductor device manufacturing method according to the first embodiment is performed, the source contact n-type semiconductor region SNR and the drain contact n-type semiconductor region DNR of the field effect transistor included in the final product are included. The trace that the above-mentioned element is contained will remain.

<Method for Manufacturing Semiconductor Device in Embodiment 1>
The semiconductor device according to the first embodiment is configured as described above, and the manufacturing method thereof will be described below with reference to the drawings.

  First, as shown in FIG. 3, a semiconductor substrate 1S made of silicon is prepared. Then, for example, a buffer layer BUF made of an AlN layer is formed on the semiconductor substrate 1S by using metal organic chemical vapor deposition (MOCVD), and GaN is formed on the buffer layer BUF. A channel layer CH composed of layers is formed. Further, an electron supply layer ES made of an AlGaN layer is formed on the channel layer CH by using the MOCVD method. At this time, the buffer layer BUF, the channel layer CH, and the electron supply layer ES are formed by epitaxial growth, and in particular, the channel layer CH and the electron supply layer ES are formed in a Ga plane mode. A two-dimensional electron gas DEG is generated near the interface between the channel layer CH and the electron supply layer ES (near the heterojunction interface).

  Next, as shown in FIG. 4, a platinum film is formed on the electron supply layer ES by, eg, sputtering. Thereafter, by using a photolithography technique and a dry etching technique, the platinum film is patterned to form the gate electrode GE. Specifically, after applying a resist film on the platinum film, the resist film is patterned by exposing and developing the resist film. The patterning of the resist film is performed so that the resist film remains in the gate electrode formation region. Thereafter, the platinum film is patterned by etching using the patterned resist film as a mask. For this etching, for example, dry etching represented by reactive ion etching (RIE) can be used. As a result, a gate electrode GE made of a platinum film is formed, and then the patterned resist film is removed (ashed).

  Subsequently, as shown in FIG. 5, an insulating film IF1 is formed so as to cover the electron supply layer ES on which the gate electrode GE is formed. The insulating film IF1 is formed of, for example, a silicon nitride film, and can be formed by using, for example, a plasma CVD method (Chemical Vapor Deposition). Then, as shown in FIG. 6, for example, by using anisotropic etching typified by reactive ion etching, sidewall spacers (sidewall insulating films) SW are formed on the sidewalls on both sides of the gate electrode GE.

  Thereafter, as shown in FIG. 7, a reaction film RF1 is formed so as to cover the electron supply layer ES on which the gate electrode GE and the sidewall spacer SW are formed. The reaction film RF1 includes, for example, titanium (Ti), tantalum (Ta), molybdenum (Mo), vanadium (V), niobium (Nb), chromium (Cr), Zr (zirconium), hafnium (Hf), aluminum (Al ), Or a metal silicide film.

  Next, as shown in FIG. 8, a heat treatment is performed on the semiconductor substrate 1S. This heat treatment is performed, for example, as a heat treatment at a temperature of 400 ° C. or higher and 650 ° C. or lower for 30 minutes in a nitrogen atmosphere. As a result, in the region where the electron supply layer ES and the reaction film RF1 are in direct contact, part of the nitrogen contained in the electron supply layer ES moves to the reaction film RF1 side, and one of the elements contained in the reaction film RF1. Part moves to the electron supply layer ES side. As a result, nitrogen vacancies are formed in the surface region of the electron supply layer ES. Since the nitrogen vacancies are donor-type defects, the source contact n-type semiconductor region SNR and the drain contact n-type semiconductor region DNR are formed. Is done. That is, the source contact n-type semiconductor region SNR and the drain contact n-type semiconductor region DNR function as n-type semiconductor regions due to the nitrogen vacancies that are donor-type defects.

  In the first embodiment, since the sidewall spacers SW are formed on the side walls on both sides of the gate electrode GE, the source contact n-type semiconductor region SNR and the drain contact n-type semiconductor region DNR The spacer SW is formed so as to be self-aligned with the spacer SW. In the first embodiment, the source contact n-type semiconductor region SNR and the drain contact n-type semiconductor region DNR are formed so as to be shallower than the heterojunction interface between the channel layer CH and the electron supply layer ES. Is done.

  As described above, since a part of the elements contained in the reaction film RF1 diffuses in the surface region of the electron supply layer ES, the source contact n formed in the surface region of the electron supply layer ES. The elements contained in the reaction film RF1 are inevitably introduced as impurity elements into the type semiconductor region SNR and the drain contact n-type semiconductor region DNR. Specifically, in the first embodiment, titanium (Ti), tantalum (Ta), molybdenum (Mo), vanadium (V), n-type semiconductor region SNR for source contact, and n-type semiconductor region DNR for drain contact are used. Any element of niobium (Nb), chromium (Cr), Zr (zirconium), hafnium (Hf), and aluminum (Al) is included.

  In particular, when the reaction film RF1 is composed of a metal silicide film, silicon (Si) present in the reaction film RF1 also diffuses into the surface region of the electron supply layer ES. In this case, the source contact n-type semiconductor region SNR and the drain contact n-type semiconductor region DNR are introduced not only with nitrogen vacancies which are donor-type defects but also with silicon (Si) functioning as n-type impurities. Therefore, the nitrogen vacancy and silicon (Si) function as an n-type semiconductor region.

  Subsequently, as shown in FIG. 9, the reaction film RF1 is removed by using, for example, hydrofluoric acid. As a result, the source contact n-type semiconductor region SNR and the drain contact n-type semiconductor region DNR formed in self-alignment with the sidewall spacer SW are exposed.

  Thereafter, as shown in FIG. 10, a patterned resist film is formed by using a photolithography technique. The resist film is patterned so as to have openings in the source electrode formation region and the drain electrode formation region. Then, for example, by using a vacuum deposition method, a laminated film composed of a titanium (Ti) film and an aluminum (Al) film is formed on the resist film including the inside of the opening. Next, by using the lift-off method, the resist film is removed together with the unnecessary laminated film, thereby forming the source electrode SE and the drain electrode DE made of a laminated film of a titanium (Ti) film and an aluminum (Al) film. . At this time, the distance between the source electrode SE and the drain electrode DE is formed to be larger than the distance between the source contact n-type semiconductor region SNR and the drain contact n-type semiconductor region DNR. As described above, the field effect transistor (semiconductor device) in the first embodiment can be manufactured.

<Characteristics in Embodiment 1>
Next, feature points in the first embodiment will be described. The feature of the first embodiment is that a source contact n-type semiconductor region SNR and a drain contact n-type semiconductor region DNR are provided. Specifically, in the first embodiment, the source contact n-type semiconductor region SNR and the drain contact n-type semiconductor region DNR are located between the source contact n-type semiconductor region SNR and the drain contact n-type semiconductor region DNR. Is formed to be smaller than the distance (second distance) between the source electrode SE and the drain electrode DE. The source electrode SE and the source contact n-type semiconductor region SNR are in direct contact, and the drain electrode DE and the drain contact n-type semiconductor region DNR are in direct contact. Further, the depth of the source contact n-type semiconductor region SNR and the depth of the drain contact n-type semiconductor region DNR are both shallower than the heterojunction interface between the channel layer CH and the electron supply layer ES. Then, the source contact n-type semiconductor region SNR and the drain contact n-type semiconductor region DNR are formed.

The method of forming the source contact n-type semiconductor region SNR and the drain contact n-type semiconductor region DNR thus configured is also characterized in the first embodiment. That is, in forming the source contact n-type semiconductor region SNR and the drain contact n-type semiconductor region DNR, the reaction film RF1 is formed so as to be in direct contact with a predetermined surface region of the electron supply layer ES. At this time, the reaction film RF1 includes, for example, titanium (Ti), tantalum (Ta), molybdenum (Mo), vanadium (V), niobium (Nb), chromium (Cr), Zr (zirconium), hafnium (Hf), Any element of aluminum (Al) is contained. Then, heat processing are implemented at the temperature of 400 to 650 degreeC. By this heat treatment, an interface reaction occurs between the electron supply layer ES and the reaction film RF1, and a part of nitrogen near the surface region of the electron supply layer ES diffuses into the reaction film RF1. As a result, for example, a large amount of nitrogen vacancies of 1 × 10 ¹⁹ cm ⁻³ or more are formed in the vicinity of the surface region of the electron supply layer ES. This nitrogen vacancy is known to function as a donor-type defect in the group III nitride semiconductor, and thereby, a source contact n-type including a large amount of nitrogen vacancy in the vicinity of the surface region of the electron supply layer ES. The semiconductor region SNR and the drain contact n-type semiconductor region DNR are formed. Since the semiconductor device according to the first embodiment has the n-type semiconductor region SNR for source contact and the n-type semiconductor region DNR for drain contact formed as described above, compared to the related technology, It has the following advantages.

  First, according to the first embodiment, the gate leakage current can be reduced as compared with the related art. That is, the temperature of the heat treatment performed in the step of forming the n-type semiconductor region SNR for source contact and the n-type semiconductor region DNR for drain contact in the first embodiment is 400 ° C. to 650 ° C. This is significantly lower than 800 ° C., which is the temperature of the heat treatment performed in the formation process of the diffusion region 103 and the thermal diffusion region 104.

  Therefore, in the first embodiment, a nickel (Ni) film, a platinum (Pt) film, or the like having a high Schottky barrier with respect to the nitride semiconductor layer can be used as the gate electrode GE. That is, in the first embodiment, the heat resistance against high-temperature heat treatment is alleviated, so that a refractory metal film such as a molybdenum (Mo) film or a tungsten (W) film is not used as in the related art. There are also good advantages.

  For example, in the related art, since heat treatment at a high temperature of 800 ° C. is performed, the gate electrode GE needs a refractory metal film having high heat resistance. However, molybdenum (Mo) films and tungsten (W) films, which are refractory metal films, have a higher Schottky barrier to the nitride semiconductor layer than nickel (Ni) films and platinum (Pt) films. Low. For this reason, in the related art, the Schottky barrier between the gate electrode GE and the nitride semiconductor layer is lowered, and thus the gate leakage current is increased.

  In contrast, the heat treatment performed in the first embodiment is performed at a lower temperature than the heat treatment performed in the related art. As a result, in the first embodiment, heat resistance is not required for the gate electrode GE as in the related art. Therefore, a molybdenum (Mo) film or a tungsten (W) film, which is a refractory metal film, is used for the gate electrode GE. There is no need, and a nickel (Ni) film, a platinum (Pt) film, or the like can be used for the gate electrode GE. A nickel (Ni) film, a platinum (Pt) film, or the like has a higher Schottky barrier with respect to the nitride semiconductor layer than a molybdenum (Mo) film or a tungsten (W) film. For this reason, according to the first embodiment, the Schottky barrier between the gate electrode GE and the nitride semiconductor layer can be made higher than in the related art, so that the gate leakage current can be reduced.

  Secondly, according to the first embodiment, the drain leakage current can be reduced as compared with the related art. As described in the room for improvement existing in the related art, the closer the distance between the high-concentration carrier region on the source electrode SE side and the high-concentration carrier region on the drain electrode DE side, the higher the concentration carrier. The deeper the region formation depth, the greater the drain leakage current.

  In this regard, the thermal diffusion region 103 and the thermal diffusion region 104, which are high-concentration carrier regions of the related art, are formed in alignment with the gate electrode GE as shown in FIG. On the other hand, the source contact n-type semiconductor region SNR and the drain contact n-type semiconductor region DNR, which are the high-concentration carrier regions of the first embodiment, are formed on the sidewalls on both sides of the gate electrode GE, as shown in FIG. It is formed in alignment with the sidewall spacer SW.

  Therefore, the distance between the source contact n-type semiconductor region SNR and the drain contact n-type semiconductor region DNR according to the first embodiment is equal to the thermal diffusion region 103 which is the high-concentration carrier region of the related art. And the distance between the thermal diffusion region 104 is larger. Therefore, in the first embodiment, the source contact n-type semiconductor region SNR which is a high concentration carrier region on the source electrode SE side and the drain which is a high concentration carrier region on the drain electrode DE side are compared with the related art. The distance from the contact n-type semiconductor region DNR is increased.

  In addition, the thermal diffusion region 103 and the thermal diffusion region 104, which are high-concentration carrier regions of the related art, are formed deeper than the heterojunction interface between the electron supply layer ES and the channel layer CH. On the other hand, the source contact n-type semiconductor region SNR and the drain contact n-type semiconductor region DNR, which are high-concentration carrier regions of the first embodiment, are formed shallower than the heterojunction interface between the electron supply layer ES and the channel layer CH. Has been.

  From the above, according to the first embodiment, the distance between the high-concentration carrier region on the source electrode SE side and the high-concentration carrier region on the drain electrode DE side is large compared to the related art, and Since the formation depth of the high concentration carrier region is shallow, the drain leakage current can be reduced.

  Next, thirdly, the point that the access resistance can be reduced according to the first embodiment will be described. Here, the access resistance refers to, for example, a resistance obtained by combining a resistance component between the source electrode SE and the gate electrode GE and a resistance component between the drain electrode DE and the gate electrode GE in FIG. And The contact resistance is, for example, the resistance component between the source electrode SE and the two-dimensional electron gas DEG formed in the region immediately below the source electrode SE, the drain electrode DE, and the drain electrode in FIG. The resistance is the sum of the resistance components between the two-dimensional electron gas DEG formed in the region directly under the DE. Further, the channel resistance refers to a resistance component of the channel region formed in the region immediately below the gate electrode GE. Therefore, the on-resistance of the field effect transistor is composed of a contact resistance, an access resistance, and a channel resistance.

FIG. 11 is a band diagram showing the distribution of the band potential (E _c ) of the conduction band before the n-type semiconductor region DNR for drain contact is formed. Specifically, for example, it is a band diagram along the line AB in FIG. On the other hand, FIG. 12 is a band diagram showing the distribution of the band potential (E _c ) of the conduction band after the n-type semiconductor region DNR for drain contact is formed. Specifically, for example, it is a band diagram along the line AB in FIG. Note that, in FIGS. 11 and 12, _{E F} represents the Fermi level.

First, as shown in FIG. 11, before the drain contact n-type semiconductor region DNR is formed, since there is almost no impurity inside the electron supply layer ES, the polarization charge generated in the electron supply layer ES and the layer thickness are reduced. A uniform slope determined accordingly is formed in the band potential of the conduction band. At the heterojunction interface between the electron supply layer ES and the channel layer CH, a conduction band offset based on a difference in electron affinity between the channel layer CH and the electron supply layer ES, and piezo polarization existing in the channel layer CH and the electron supply layer ES. and due to the influence of the spontaneous polarization, a low well potential than the Fermi level E _F near the interface of the channel layer CH and the electron supply layer ES is generated. As a result, electrons are accumulated in the well-type potential, and as a result, a two-dimensional electron gas DEG is generated near the interface between the channel layer CH and the electron supply layer ES.

On the other hand, as shown in FIG. 12, after forming the drain contact n-type semiconductor region DNR, a large amount of nitrogen of, for example, 1 × 10 ¹⁹ cm ⁻³ or more is formed in the drain contact n-type semiconductor region DNR. Vacancy (donor type defect) is included. Therefore, as shown in FIG. 12, the band potential of the conduction band is greatly bent in the drain contact n-type semiconductor region DNR formed in the surface region of the electron supply layer ES, and some of the band potentials are Fermi level. Will be below. As a result, carriers (electrons) are also accumulated in the vicinity of the interface between the drain contact n-type semiconductor region DNR and the electron supply layer ES. Further, the band potential on the surface side of the electron supply layer ES in which the n-type semiconductor region DNR for drain contact is formed is bent, so that the band potential at the heterojunction interface between the electron supply layer ES and the channel layer CH is also lowered. It is done. For this reason, the carriers (electrons) of the two-dimensional electron gas DEG accumulated on the channel layer CH side also increase.

  That is, by forming the drain contact n-type semiconductor region DNR as in the first embodiment, for example, between the drain electrode DE and the gate electrode GE, between the channel layer CH and the electron supply layer ES. A first current path is formed by the two-dimensional electron gas DEG near the heterojunction interface, and carriers (electrons) are accumulated near the interface between the drain contact n-type semiconductor region DNR and the electron supply layer ES. Two current paths are formed. In the first embodiment, the carriers of the two-dimensional electron gas DEG constituting the first current path also increase.

  Similarly, in the first embodiment, since the source contact n-type semiconductor region SNR is also formed, between the source electrode SE and the gate electrode GE, for example, between the channel layer CH and the electron supply layer ES. A first current path is formed by the two-dimensional electron gas DEG near the heterojunction interface, and carriers (electrons) are accumulated near the interface between the source contact n-type semiconductor region SNR and the electron supply layer ES. Two current paths are formed. In the first embodiment, carriers (electrons) of the two-dimensional electron gas DEG constituting the first current path also increase.

  As a result, according to the first embodiment, the access resistance of the field effect transistor can be reduced. The reason for this will be described below.

  First, as the first factor that can reduce the access resistance, according to the first embodiment, the first current path is configured by providing the n-type semiconductor region DNR for drain contact and the n-type semiconductor region SNR for source contact. The number of carriers (electrons) of the two-dimensional electron gas DEG to be increased is mentioned.

  Next, as a second factor that can reduce the access resistance, according to the first embodiment, by providing the drain contact n-type semiconductor region DNR and the source contact n-type semiconductor region SNR, The point generated is mentioned. That is, according to the first embodiment, not only the first current path by the two-dimensional electron gas DEG but also the second current path is formed, so that the number of carriers (electrons) responsible for current transport is greatly increased.

  Further, as a third factor that can reduce the access resistance, the depths of the n-type semiconductor region DNR for drain contact and the n-type semiconductor region SNR for source contact formed in the first embodiment depend on the electron supply layer ES and the channel. The point which is formed shallower than the heterojunction interface with layer CH can be mentioned.

  For example, in the related art, as shown in FIG. 1, the thermal diffusion region 103 and the thermal diffusion region 104 are formed deeper than the heterojunction interface between the electron supply layer ES and the channel layer CH. Accompanied by a decrease in degree.

  On the other hand, in the first embodiment, the drain contact n-type semiconductor region DNR and the source contact n-type semiconductor region SNR are formed shallower than the heterojunction interface between the electron supply layer ES and the channel layer CH. Therefore, the atomic arrangement of the heterojunction interface is not affected and the steep heterojunction interface is maintained. As a result, according to the first embodiment, it is possible to suppress a decrease in carrier mobility of the two-dimensional electron gas DEG.

  From the above, according to the first embodiment, the access resistance can be effectively reduced by the synergistic effect of the first factor, the second factor, and the third factor described above. In particular, in the first embodiment, the source contact n-type semiconductor region SNR and the drain contact n-type semiconductor region DNR are the distances between the source contact n-type semiconductor region SNR and the drain contact n-type semiconductor region DNR. The (first distance) is formed to be smaller than the distance (second distance) between the source electrode SE and the drain electrode DE. The source contact n-type semiconductor region SNR and the drain contact n-type semiconductor region DNR are formed in alignment with the sidewall spacers SW formed on the side walls on both sides of the gate electrode GE.

  Thus, the source contact n-type semiconductor region SNR and the drain contact n-type semiconductor region DNR are formed between the source electrode SE and the gate electrode GE where the access resistance is generated and between the drain electrode DE and the gate electrode GE. Can do. In other words, the source contact n-type semiconductor region SNR and the drain contact n-type semiconductor region DNR can be formed so as to overlap with the access resistance generation region in plan view. The first factor, the second factor, and the third factor can be expressed. As a result, according to the field effect transistor of the first embodiment, the access resistance can be reduced.

  Next, fourthly, the point that the contact resistance can be reduced according to the first embodiment will be described. In the field effect transistor according to the first embodiment shown in FIG. 2, the source electrode SE is formed so as to be in direct contact with the source contact n-type semiconductor region SNR, and so as to be in direct contact with the drain contact n-type semiconductor region DNR. A drain electrode DE is formed. Here, since the contact resistance in the region immediately below the source electrode SE is equal to the contact resistance in the region immediately below the drain electrode DE, the following description will be made by paying attention to the contact resistance in the region immediately below the drain electrode DE. To.

  First, as shown in FIG. 2, when the drain electrode DE is formed so as to be in direct contact with the drain contact n-type semiconductor region DNR, the contact resistance from the drain electrode DE to the two-dimensional electron gas DEG is the same as that of the drain electrode DE. This is the sum of the first contact resistance between the drain contact n-type semiconductor region DNR and the second connection resistance between the drain contact n-type semiconductor region DNR and the two-dimensional electron gas DEG.

  Here, in the first embodiment, as shown in FIG. 12, the drain electrode (in FIG. 12, the band potential of the conduction band is greatly bent inside the n-type semiconductor region DNR for drain contact. The thickness of the potential barrier between the n-type semiconductor region DNR for drain contact and the drain contact is reduced. A reduction in the thickness of the potential barrier means that a tunnel current that tunnels through the potential barrier easily flows. Therefore, in the first embodiment, the first contact resistance between the drain electrode DE and the drain contact n-type semiconductor region DNR is reduced.

On the other hand, in the first embodiment, as shown in FIG. 12, as a result of the band potential in the electron supply layer ES being greatly lowered, between the drain contact n-type semiconductor region DNR and the two-dimensional electron gas DEG, There is only a very small potential barrier. This means that carriers (electrons) easily move between the n-type semiconductor region DNR for drain contact and the two-dimensional electron gas DEG. Therefore, in the first embodiment, the second connection resistance between the n-type semiconductor region DNR for drain contact and the two-dimensional electron gas DEG is also reduced. From the above, by forming the drain electrode DE so as to be in direct contact with the drain contact n-type semiconductor region DNR as in the first embodiment, the above-described first contact resistance and second contact resistance are Both can be reduced. This means that the contact resistance composed of the sum of the first contact resistance and the second contact resistance can be reduced. That is, according to the first embodiment, the contact resistance from the drain electrode DE to the two-dimensional electron gas DEG can be reduced. With the same mechanism, according to the first embodiment, the contact resistance from the source electrode SE to the two-dimensional electron gas DEG can also be reduced. As a result of examination by the present inventor using experiments and simulations, from the viewpoint of sufficiently reducing the contact resistance, the nitrogen vacancies in the n-type semiconductor region DNR for drain contact and the n-type semiconductor region SNR for source contact are reduced. It was found that the density (concentration) is desirably 1 × 10 ¹⁹ cm ⁻³ or more.

  Further, in the first embodiment, the ion implantation method as in the related art is not used for forming the drain contact n-type semiconductor region DNR and the source contact n-type semiconductor region SNR, which are high concentration carrier regions. . For this reason, in this Embodiment 1, the crystal defect resulting from an ion implantation method hardly arises. Furthermore, in the first embodiment, the temperature of the heat treatment performed when forming the drain contact n-type semiconductor region DNR and the source contact n-type semiconductor region SNR is 400 ° C. or more and 650 ° C. or less, and 800 ° C. Compared to related technologies that require a certain degree of heat treatment, it is sufficiently low.

  Therefore, according to the first embodiment, when a method of epitaxially growing a nitride semiconductor layer on a silicon substrate, which is an effective means for reducing the manufacturing cost of a field effect transistor using a nitride semiconductor material, is used. Even so, it is possible to effectively reduce the contact resistance while suppressing an increase in warping and cracking of the semiconductor substrate 1S accompanying the heat treatment.

  For example, in the related art, the source region 101 and the drain region 102 are formed by using an ion implantation method. In this case, in order to sufficiently reduce the contact resistance, a high temperature of 1150 ° C. or higher is used. Heat treatment is required. However, when such a high-temperature heat treatment is performed, the semiconductor substrate 1S is warped and cracked, so that the high-temperature heat treatment cannot be performed. For this reason, if the temperature of the heat treatment for activating the ion-implanted conductive impurities is limited to 1100 ° C. or less, crystal defects caused by the ion implantation are not sufficiently recovered by this heat treatment. A sufficient reduction effect cannot be obtained.

On the other hand, in the present first embodiment, the ion implantation method is not used for forming the drain contact n-type semiconductor region DNR and the source contact n-type semiconductor region SNR, and the following formation method is adopted. That is, in forming the source contact n-type semiconductor region SNR and the drain contact n-type semiconductor region DNR, after forming the reaction film RF1 so as to be in direct contact with a predetermined surface region of the electron supply layer ES, the temperature is 400 ° C. or higher. Heat treatment is performed at a temperature of 650 ° C. or lower. By this heat treatment, an interface reaction occurs between the electron supply layer ES and the reaction film RF1, and a part of nitrogen near the surface region of the electron supply layer ES diffuses into the reaction film RF1. As a result, for example, a large amount of nitrogen vacancies of 1 × 10 ¹⁹ cm ⁻³ or more are formed in the vicinity of the surface region of the electron supply layer ES. Since the nitrogen vacancies function as donor-type defects in the group III nitride semiconductor, the source contact n-type semiconductor region SNR including a large amount of nitrogen vacancies in the vicinity of the surface region of the electron supply layer ES and The n-type semiconductor region DNR for drain contact is formed.

  That is, the basic idea of forming the drain contact n-type semiconductor region DNR and the source contact n-type semiconductor region SNR in the first embodiment is to form an n-type semiconductor region by introducing an n-type impurity by an ion implantation method. Instead, the n-type semiconductor region is formed by intentionally forming a large amount of nitrogen vacancies by utilizing the interface reaction with the reaction film RF1. Thus, according to the first embodiment, the drain contact n-type semiconductor region DNR and the source contact n-type semiconductor region SNR can be formed without using the ion implantation method. For this reason, in this Embodiment 1, since the generation | occurrence | production of the crystal defect based on an ion implantation method can be suppressed, it becomes unnecessary to implement the heat processing of 1150 degreeC or more required for recovery of a crystal defect. This means that according to the first embodiment, it is not necessary to perform a heat treatment at a high temperature of 1150 ° C. or higher in order to reduce the contact resistance. Furthermore, according to the first embodiment, since heat treatment at a high temperature of 1150 ° C. or higher is not necessary, it is possible to suppress an increase in warpage and cracking of the semiconductor substrate 1S accompanying the heat treatment. That is, in the first embodiment, a method of epitaxially growing a nitride semiconductor layer on a silicon substrate can be positively used, thereby reducing the manufacturing cost of the semiconductor device. Thus, according to the first embodiment, it is possible to achieve both reduction in contact resistance and reduction in manufacturing cost.

  In addition, the semiconductor device manufacturing method according to the first embodiment also provides the following advantages. For example, when a metal silicide film is used as the reaction film RF1, a large amount of nitrogen vacancies are formed in the drain contact n-type semiconductor region DNR and the source contact n-type semiconductor region SNR and diffused from the reaction film RF1. Silicon (Si) to be introduced is also introduced. Since silicon (Si) functions as an n-type impurity (donor) in the group III nitride semiconductor region, nitrogen vacancies are formed in the drain contact n-type semiconductor region DNR and the source contact n-type semiconductor region SNR. In addition, the donor density due to silicon increases. As a result, the contact resistance reduction effect and the access resistance reduction effect described above can be further improved.

  From the above, according to the first embodiment, both the access resistance and the contact resistance can be reduced. As a result, the on-resistance composed of the access resistance, the contact resistance, and the channel resistance can also be reduced. You can see that

  In the semiconductor device manufacturing method according to the first embodiment, for example, as shown in FIG. 10, the drain contact n-type is self-aligned with the sidewall spacers SW formed on the sidewalls on both sides of the gate electrode GE. A semiconductor region DNR and a source contact n-type semiconductor region SNR are formed. Therefore, in the field effect transistor according to the first embodiment, the length of the drift region between the gate electrode GE and the drain electrode DE can be controlled by the thickness of the sidewall spacer SW. For this reason, according to the first embodiment, for example, a minute drift region of 0.4 μm or less can be easily formed, so that a field effect transistor having a low breakdown voltage of 120 V or less is easily manufactured, for example. be able to.

  According to the field effect transistor in the first embodiment, for example, in a field effect transistor having a withstand voltage of 100 V, the performance of a gate leakage current of 2 nA / mm, a drain leakage current of 3 nA / mm, and an on-resistance of 1.8 Ωmm is realized. We were able to.

(Embodiment 2)
In the field effect transistor according to the second embodiment, an example in which a p-type nitride semiconductor layer is formed between the gate electrode GE and the electron supply layer ES will be described.

<Configuration of Semiconductor Device in Second Embodiment>
The configuration of the semiconductor device according to the second embodiment will be described with reference to the drawings. FIG. 13 is a cross-sectional view showing the configuration of the field effect transistor according to the second embodiment. Since the field effect transistor according to the second embodiment has substantially the same configuration as the field effect transistor according to the first embodiment, the description will focus on the differences.

  In the field effect transistor according to the second embodiment, as shown in FIG. 13, a p-type cap layer CAP made of, for example, a p-type nitride semiconductor layer is formed between the gate electrode GE and the electron supply layer ES. This is different from the first embodiment. The p-type cap layer CAP is formed so as to exist only in a region immediately below the gate electrode GE, for example.

<Method for Manufacturing Semiconductor Device in Second Embodiment>
The field effect transistor according to the second embodiment is configured as described above, and a manufacturing method thereof will be briefly described below (see FIG. 13). The manufacturing method of the field effect transistor in the second embodiment is almost the same as the manufacturing method of the field effect transistor in the first embodiment.

  First, for example, by using the MOCVD method, the buffer layer BUF made of an AlN layer, the channel layer CH made of a GaN layer, and the electron supply layer ES made of an AlGaN layer are formed on the semiconductor substrate 1S made of silicon (Si). After that, the p-type cap layer CAP made of, for example, a p-type nitride semiconductor layer to which magnesium (Mg) is added is sequentially epitaxially grown on the electron supply layer ES in the Ga plane mode.

  Next, for example, a nickel (Ni) film or a platinum (Pt) film is formed on the surface of the p-type cap layer CAP by using, for example, a sputtering method. Thereafter, using the patterned resist film as a mask, the gate electrode GE is formed by, for example, dry etching represented by reactive ion etching.

  Subsequently, using the gate electrode GE as a mask, the p-type cap layer CAP is selectively removed by dry etching using, for example, inductively coupled plasma (ICP). As a result, the p-type cap layer CAP remains only in the region immediately below the gate electrode GE. That is, the p-type cap layer CAP is formed so as to be sandwiched between the gate electrode GE and the electron supply layer ES.

  Thereafter, an insulating film made of, for example, a silicon nitride film is formed on the electron supply layer ES covering the gate electrode GE by using, for example, a plasma CVD method, and anisotropic etching is performed on the insulating film. By carrying out, sidewall spacers SW are formed on the sidewalls on both sides of the gate electrode GE. Subsequent steps are the same as those in the first embodiment, so that the field effect transistor in the second embodiment can be finally manufactured.

<Effect in Embodiment 2>
Also in the second embodiment, the same effect as in the first embodiment can be obtained. Comparing the field effect transistor in the second embodiment and the field effect transistor in the first embodiment, the configuration of the n-type semiconductor region DNR for drain contact and the n-type semiconductor region SNR for source contact, which are high concentration carrier regions It can be seen that the manufacturing method is exactly the same. Therefore, in the second embodiment, as in the first embodiment, both the gate leakage current and the drain leakage current can be reduced and the on-resistance including the access resistance and the contact resistance can be reduced as compared with the field effect transistor in the related art. An effect of reducing the resistance is obtained.

  In addition, in the field effect transistor according to the second embodiment, the gate leakage current can be further reduced as compared with the field effect transistor according to the first embodiment. In the field effect transistor according to the first embodiment, since the gate electrode GE and the electron supply layer ES are in direct contact, the Schottky barrier between the metal material constituting the gate electrode GE and the electron supply layer ES is a gate leak. It is a potential barrier that determines the current. For example, when a platinum (Pt) film is used for the gate electrode GE as in the first embodiment, the height of the potential barrier is about 1.0 eV.

  In contrast, in the field effect transistor according to the second embodiment, a barrier layer made of the p-type cap layer CAP is disposed between the gate electrode GE and the electron supply layer ES. As a result, in the second embodiment, the potential barrier that determines the gate leakage current increases to 3.4 eV, which is substantially the same as the diffusion potential of the pn junction formed of GaN. As a result, according to the field effect transistor in the second embodiment, the gate leakage current can be greatly reduced as compared with the field effect transistor in the first embodiment.

  In the field effect transistor according to the second embodiment, the Al composition and the layer thickness of the electron supply layer ES and the amount of the p-type impurity (p-type dopant) added to the p-type cap layer CAP are appropriately controlled. Thus, a normally-off (enhancement) type field effect transistor can also be manufactured.

  That is, in the field effect transistor according to the second embodiment, since the p-type cap layer CAP is formed under the gate electrode GE, the threshold voltage can be positive, that is, a normally-off device.

  For example, when a nitride semiconductor is used for the channel layer CH and the electron supply layer ES, in addition to the well-type potential due to the conduction band offset between the channel layer CH and the electron supply layer ES, the piezo due to the use of the nitride semiconductor. The bottom of the well-type potential is pushed down by polarization and spontaneous polarization. As a result, when there is no p-type cap layer CAP, a two-dimensional electron gas DEG is generated near the interface between the channel layer CH and the electron supply layer ES without applying a voltage to the gate electrode GE. As a result, it becomes a normally-on type device.

  On the other hand, in the case of the field effect transistor according to the second embodiment in which the p-type cap layer CAP is formed in the region immediately below the gate electrode GE, the negative charge due to the ionization of the acceptor of the p-type cap layer CAP causes the electron supply layer ES to The conduction band is raised. As a result, the two-dimensional electron gas DEG can be prevented from being formed in the channel layer CH in the thermal equilibrium state. In this manner, a normally-off device can be realized in the field effect transistor according to the second embodiment.

  According to the field effect transistor of the second embodiment, for example, in a field effect transistor having a breakdown voltage of 100 V, the gate leakage current is 0.1 nA / mm, the drain leakage current is 3 nA / mm, and the on-resistance is 1.8 Ωmm. We were able to realize the performance.

(Embodiment 3)
In the field effect transistor according to the third embodiment, an example in which the gate insulating film GOX is formed between the gate electrode GE and the electron supply layer ES will be described.

<Configuration of Semiconductor Device in Embodiment 3>
The configuration of the semiconductor device according to the third embodiment will be described with reference to the drawings. FIG. 14 is a cross-sectional view showing the configuration of the field effect transistor according to the third embodiment. Since the field effect transistor according to the third embodiment has substantially the same configuration as the field effect transistor according to the first embodiment, the description will focus on the differences.

  In the field effect transistor according to the third embodiment, as shown in FIG. 14, a gate insulating film GOX made of, for example, a silicon oxide film is formed between the gate electrode GE and the electron supply layer ES. This is different from the first embodiment. The gate insulating film GOX is formed so as to exist only in a region immediately below the gate electrode GE, for example.

<Method for Manufacturing Semiconductor Device in Embodiment 3>
The field effect transistor according to the third embodiment is configured as described above, and the manufacturing method thereof will be briefly described below (see FIG. 14). The manufacturing method of the field effect transistor according to the third embodiment is almost the same as the manufacturing method of the field effect transistor according to the first embodiment.

  First, for example, by using the MOCVD method, the buffer layer BUF made of an AlN layer, the channel layer CH made of a GaN layer, and the electron supply layer ES made of an AlGaN layer are formed on the semiconductor substrate 1S made of silicon (Si) by Ga. After sequential epitaxial growth in the surface mode, a gate insulating film GOX made of, for example, a silicon oxide film is formed on the electron supply layer ES by using, for example, an atomic layer deposition (ALD) method.

  Next, for example, a nickel (Ni) film or a platinum (Pt) film is formed on the surface of the gate insulating film GOX by using, for example, a sputtering method. Thereafter, using the patterned resist film as a mask, the gate electrode GE is formed by, for example, dry etching represented by reactive ion etching.

  Subsequently, the gate insulating film GOX is selectively removed by dry etching using, for example, inductively coupled plasma (ICP) using the gate electrode GE as a mask. As a result, the gate insulating film GOX remains only in the region immediately below the gate electrode GE. That is, the gate insulating film GOX is formed so as to be sandwiched between the gate electrode GE and the electron supply layer ES.

  Thereafter, an insulating film made of, for example, a silicon nitride film is formed on the electron supply layer ES covering the gate electrode GE by using, for example, a plasma CVD method, and anisotropic etching is performed on the insulating film. By carrying out, sidewall spacers SW are formed on the sidewalls on both sides of the gate electrode GE. Subsequent steps are the same as those in the first embodiment, so that the field effect transistor in the third embodiment can be finally manufactured.

<Effect in Embodiment 3>
Also in the third embodiment, the same effect as in the first embodiment can be obtained. Comparing the field effect transistor in the third embodiment and the field effect transistor in the first embodiment, the configuration of the n-type semiconductor region DNR for drain contact and the n-type semiconductor region SNR for source contact, which are high concentration carrier regions It can be seen that the manufacturing method is exactly the same. Therefore, in the third embodiment, as in the first embodiment, both the gate leakage current and the drain leakage current can be reduced and the on-resistance including the access resistance and the contact resistance can be reduced as compared with the field effect transistor in the related art. An effect of reducing the resistance is obtained.

  In addition, in the field effect transistor according to the third embodiment, the gate leakage current can be further reduced as compared with the field effect transistor according to the first embodiment. In the field effect transistor according to the first embodiment, since the gate electrode GE and the electron supply layer ES are in direct contact, the Schottky barrier between the metal material constituting the gate electrode GE and the electron supply layer ES is a gate leak. It is a potential barrier that determines the current. For example, when a platinum (Pt) film is used for the gate electrode GE as in the first embodiment, the height of the potential barrier is about 1.0 eV.

On the other hand, in the field effect transistor according to the third embodiment, a gate insulating film GOX made of, for example, a silicon oxide film is disposed between the gate electrode GE and the electron supply layer ES. As a result, in the third embodiment, the potential barrier that determines the gate leakage current increases to 2.5 eV, which is substantially the same as the conduction band discontinuity (ΔE _c ) of silicon oxide and GaN. As a result, according to the field effect transistor in the third embodiment, the gate leakage current can be greatly reduced as compared with the field effect transistor in the first embodiment.

  In the field effect transistor according to the third embodiment, for example, in a field effect transistor having a withstand voltage of 100 V, the gate leakage current is 0.8 nA / mm, the drain leakage current is 3 nA / mm, and the on-resistance is 1.8 Ωmm. We were able to realize the performance.

(Embodiment 4)
In the first to third embodiments, the drain contact n-type semiconductor region DNR and the source contact n-type semiconductor region SNR are formed in self-alignment with the sidewall spacers SW formed on the sidewalls on both sides of the gate electrode GE. An example has been described. In the fourth embodiment, an example in which the n-type semiconductor region DNR for drain contact and the n-type semiconductor region SNR for source contact are formed without self-alignment will be described.

<Configuration of Semiconductor Device in Embodiment 4>
The configuration of the semiconductor device according to the fourth embodiment will be described with reference to the drawings. FIG. 15 is a cross-sectional view showing the configuration of the field effect transistor according to the fourth embodiment. As shown in FIG. 15, in the field effect transistor according to the fourth embodiment, for example, a buffer layer BUF made of a group III nitride semiconductor layer for lattice relaxation is formed on a semiconductor substrate 1S made of silicon (Si). A channel layer CH made of, for example, a GaN layer is formed on the buffer layer BUF. An electron supply layer ES made of, for example, an AlGaN layer is formed on the channel layer CH, and a cap layer CF made of, for example, a GaN layer is formed on the surface of the electron supply layer ES. The buffer layer BUF, the channel layer CH, the electron supply layer ES, and the cap layer CF are stacked so that the surface becomes a Ga plane (Ga plane mode). At this time, the cap layer CF is provided, for example, in order to suppress degradation of the performance of the field effect transistor due to oxidation of aluminum contained in the electron supply layer ES. That is, the cap layer CF is formed so that the surface of the electron supply layer ES is not oxidized.

  Subsequently, on the cap layer CF, the source electrode SE and the drain electrode DE are arranged to face each other, and a two-dimensional electron gas generated by an action such as polarization charge generated at the heterojunction interface between the channel layer CH and the electron supply layer ES. Electrically connected to DEG.

  A gate electrode GE is formed on a predetermined region of the electron supply layer ES sandwiched between the source electrode SE and the drain electrode DE. Of the region on the cap layer CF, the region other than the source electrode SE, the drain electrode DE, and the gate electrode GE is covered with the protective insulating film PIF, and a part of the gate electrode GE is Also formed on the protective insulating film PIF.

  Further, an n-type semiconductor region for source contact SNR and an n-type semiconductor region for drain contact DNR are formed from the lower cap layer CF where the source electrode SE and the drain electrode DE are formed to the electron supply layer ES, respectively.

  The source contact n-type semiconductor region SNR and the drain contact n-type semiconductor region DNR have a distance (first distance) between the source contact n-type semiconductor region SNR and the drain contact n-type semiconductor region DNR as a source. It is formed to be smaller than the distance (second distance) between the electrode SE and the drain electrode DE. The source electrode SE and the source contact n-type semiconductor region SNR are in direct contact, and the drain electrode DE and the drain contact n-type semiconductor region DNR are in direct contact. Further, the depth of the source contact n-type semiconductor region SNR and the depth of the drain contact n-type semiconductor region DNR are both shallower than the heterojunction interface between the channel layer CH and the electron supply layer ES. Then, the source contact n-type semiconductor region SNR and the drain contact n-type semiconductor region DNR are formed.

  In particular, in the field effect transistor according to the fourth embodiment, the distance LD between the drain contact n-type semiconductor region DNR and the gate electrode GE and the distance between the source contact n-type semiconductor region SNR and the gate electrode GE. LS is different. Specifically, the distance LD is larger than the distance LS (LD> LS). In other words, the distance LS is smaller than the distance LD.

The source contact n-type semiconductor region SNR that is in direct contact with the source electrode SE includes, for example, nitrogen vacancies of 1 × 10 ¹⁹ cm ⁻³ or more. At this time, since the nitrogen vacancy functions as a donor type defect, the source contact n-type semiconductor region SNR functions as an n-type semiconductor region. Similarly, the drain contact n-type semiconductor region DNR that is in direct contact with the drain electrode DE also includes, for example, nitrogen vacancies of 1 × 10 ¹⁹ cm ⁻³ or more. Accordingly, the drain contact n-type semiconductor region DNR also functions as an n-type semiconductor region.

  Note that the source contact n-type semiconductor region SNR and the drain contact n-type semiconductor region DNR may contain silicon (Si) that functions as an n-type impurity. In this case, the source contact n-type semiconductor region SNR and the drain contact n-type semiconductor region DNR are caused by both nitrogen vacancies functioning as donor-type defects and silicon (Si) functioning as donors (n-type impurities). It will function as an n-type semiconductor region.

  Further, in the n-type semiconductor region SNR for source contact and the n-type semiconductor region DNR for drain contact, titanium (Ti), tantalum (Ta), molybdenum ( Any element of Mo), vanadium (V), niobium (Nb), chromium (Cr), Zr (zirconium), hafnium (Hf), and aluminum (Al) is contained.

<Method for Manufacturing Semiconductor Device in Embodiment 4>
The semiconductor device according to the fourth embodiment is configured as described above, and the manufacturing method thereof will be described below with reference to the drawings.

  First, as shown in FIG. 16, for example, by using the MOCVD method, a buffer layer BUF made of an AlN layer, a channel layer CH made of a GaN layer, and an AlGaN layer are formed on a semiconductor substrate 1S made of silicon (Si). After forming the electron supply layer ES, a cap layer CF made of, for example, a GaN layer is epitaxially grown sequentially on the electron supply layer ES in the Ga plane mode.

  Next, as shown in FIG. 17, a patterned resist film is formed on the cap layer CF by using a photolithography technique, and then the patterned resist film is covered by using, for example, a vacuum deposition method. Thus, a titanium (Ti) film is formed. Then, by using a lift-off method, an unnecessary titanium (Ti) film is removed, and a patterned reaction film RF1 is formed. This reaction film RF1 includes titanium (Ti), tantalum (Ta), molybdenum (Mo), vanadium (V), niobium (Nb), chromium (Cr), Zr (zirconium), hafnium (Hf), aluminum ( A metal film or a metal silicide film containing any element of Al) can be used.

  Subsequently, as illustrated in FIG. 18, for example, in a nitrogen atmosphere, a heat treatment is performed at a temperature of 400 ° C. to 650 ° C. and a heating time of 20 minutes, and then, for example, the reaction film RF1 is removed with hydrofluoric acid. . Thereby, for example, the source contact n-type semiconductor region SNR and the drain contact n-type semiconductor region DNR are formed across the cap layer CF in which the reaction film RF1 is formed and the electron supply layer ES formed thereunder. The

Specifically, the above-described heat treatment causes an interface reaction between the electron supply layer ES and the reaction film RF1, and a part of nitrogen contained in the cap layer CF and the electron supply layer ES diffuses into the reaction film RF1. . As a result, for example, a large amount of nitrogen vacancies of 1 × 10 ¹⁹ cm ⁻³ or more are formed in the cap layer CF and the electron supply layer ES. Since this nitrogen vacancy functions as a donor-type defect in the group III nitride semiconductor, the n-type semiconductor for source contact which includes a large amount of nitrogen vacancy in the inner region of the cap layer CF and the electron supply layer ES. Region SNR and drain contact n-type semiconductor region DNR are formed.

  Next, as shown in FIG. 19, after the patterned resist film is formed on the cap layer CF, the source contact n-type semiconductor region SNR, and the drain contact n-type semiconductor region DNR by using a photolithography technique. For example, by using a vacuum deposition method, a laminated film made of a titanium (Ti) film and an aluminum (Al) film is formed so as to cover the patterned resist film. Then, by using the lift-off method, unnecessary stacked films are removed, and the source electrode SE and the drain electrode DE are formed.

  Then, as shown in FIG. 20, for example, after forming a silicon nitride film using a plasma CVD method, a protective insulating film PIF made of a silicon nitride film is formed by using a photolithography technique and an etching technique. To do.

  Subsequently, as shown in FIG. 21, a patterned resist film is formed on the protective insulating film PIF, the source electrode SE, and the drain electrode DE by using a photolithography technique, and then, for example, a vacuum evaporation method is used. Thus, a laminated film made of a nickel (Ni) film and a gold (Au) film is formed so as to cover the patterned resist film. Then, by using a lift-off method, an unnecessary laminated film is removed and a gate electrode GE is formed. As described above, the field effect transistor according to the fourth embodiment can be manufactured.

<Effect in Embodiment 4>
Also in the fourth embodiment, the same effect as in the first embodiment can be obtained. In the field effect transistor according to the fourth embodiment, as in the field effect transistor according to the first embodiment, (1) the source contact n-type semiconductor region SNR and the drain contact n which are high-concentration carrier regions. This is because the ion implantation method is not used to form the type semiconductor region DNR. Furthermore, (2) the temperature of the heat treatment is as low as 400 ° C. to 650 ° C., and a metal having a high Schottky barrier with respect to the GaN layer can be used, and (3) the n-type semiconductor region SNR for source contact and drain contact This is also because the n-type semiconductor region DNR is formed shallower than the heterojunction interface between the electron supply layer ES and the channel layer CH. Further, (4) the distance (first distance) between the source contact n-type semiconductor region SNR and the drain contact n-type semiconductor region DNR is the distance between the source electrode SE and the drain electrode DE (second distance). (5) The source electrode SE and the source contact n-type semiconductor region SNR are in direct contact, and the drain electrode DE and the drain contact n-type semiconductor region DNR are also in direct contact. To do.

  Therefore, in the fourth embodiment, as in the first embodiment, both the gate leakage current and the drain leakage current can be reduced and the on-resistance including the access resistance and the contact resistance can be reduced as compared with the field effect transistor in the related art. An effect of reducing the resistance is obtained.

  In addition, unlike the field effect transistors in the first to third embodiments, the field effect transistor in the fourth embodiment is suitable for providing a field effect transistor having a high breakdown voltage, for example, a breakdown voltage of 600 V or more. It has a configuration.

  The reason is that the source contact n-type semiconductor region SNR and the drain contact n-type semiconductor region DNR are not formed in a self-aligned manner with respect to the gate electrode GE, and therefore, between the source electrode SE and the gate electrode GE. This is because it is easy to increase the distance LD between the gate electrode GE and the drain electrode DE without changing the distance LS.

  For example, in the configurations according to the first to third embodiments, since the source contact n-type semiconductor region SNR and the drain contact n-type semiconductor region DNR are formed by a self-alignment process, the distance LS and the distance LD are the same. There is a restriction that Therefore, if the distance LD corresponding to the drift region is increased in order to increase the breakdown voltage of the field effect transistor, the distance LS also increases at the same time. This means that the access resistance between the source electrode SE and the gate electrode GE increases, and this causes an increase in on-resistance.

  On the other hand, in the configuration according to the fourth embodiment, since the self-alignment process is not used, the distance LD can be increased without changing the distance LS. Therefore, according to the field effect transistor of the fourth embodiment, the breakdown voltage of the field effect transistor can be increased without increasing the access resistance between the source electrode SE and the gate electrode GE.

  According to the field effect transistor of the fourth embodiment, for example, in a field effect transistor having a breakdown voltage of 750 V, the performance of a gate leakage current of 2 nA / mm, a drain leakage current of 3 nA / mm, and an on-resistance of 4 Ωmm is realized. I was able to.

  In the field effect transistor according to the fourth embodiment, the example in which the gate electrode GE is in direct contact with the cap layer CF has been described. However, the present invention is not limited thereto. For example, the second embodiment is applied by analogy, A configuration in which the p-type cap layer CAP is disposed between the gate electrode GE and the cap layer CF, or a configuration in which the gate insulating film GOX is disposed between the gate electrode GE and the cap layer CF by analogy with the third embodiment. Can also be adopted.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  For example, for the semiconductor substrate 1S, sapphire, SiC, GaN, AlN, diamond, or a structure obtained by bonding them can be used in addition to silicon (Si) described in the present specification.

  In addition to the AlN layer, the buffer layer BUF uses a layer suitable for epitaxially growing a group III nitride semiconductor crystal on the semiconductor substrate 1S, such as a GaN layer, an AlGaN layer, or a stacked body in which these are stacked. be able to.

  As the channel layer CH, in addition to the GaN layer, an InGaN layer, an AlGaN layer, an InAlN layer, an AlInGaN layer, or a stacked body of these layers can be used. In particular, a high mobility two-dimensional electron gas is used. It is desirable to use a GaN layer that can use DEG or an InGaN layer.

  In addition to the AlGaN layer, an InAlN layer, an AlInGaN layer, or the like can be used for the electron supply layer ES. In this case, the composition ratio of the electron supply layer ES is adjusted so as to increase the band gap with respect to the material constituting the channel layer CH, thereby moving to the vicinity of the heterojunction interface between the channel layer CH and the electron supply layer ES. A two-dimensional electron gas DEG having a high degree is generated, and this two-dimensional electron gas DEG can be used as a carrier (electron h) responsible for current transport of the field effect transistor.

  For the source electrode SE or the drain electrode DE, not only a laminated film of a titanium film and an aluminum film, but also a Ti film, a TiN film, a TiSi film, an Al film, an AlSi film, a W film, a WSi film, a Ni film, a NiSi film A polysilicon film or a laminated film thereof can be used.

  In addition to the platinum film, the gate electrode GE uses a Ni film, a NiSi film, an Au film, a W film, a WSi film, a TiN film, a TiSi film, an Al film, an AlSi film, a polysilicon film, or a laminated film thereof. can do.

  In addition to the silicon nitride film, the sidewall spacer SW is a film used as a surface protective film on the semiconductor surface, such as a silicon oxide film, a silicon oxynitride film, an AlN film, a diamond, a polyimide film, or a laminated film thereof. Can be used widely.

  As the gate insulating film GOX, in addition to the silicon oxide film, a SiON film, an aluminum oxide film, an AlN film, a zirconium oxide film, a hafnium oxide film, or a stacked film thereof can be used.

  The embodiment includes the following aspects.

(Appendix 1)
(A) forming a channel layer made of the first nitride semiconductor layer;
(B) forming an electron supply layer made of a second nitride semiconductor layer on the channel layer;
(C) forming a reaction film on the electron supply layer and patterning the reaction film;
(D) a step of performing a heat treatment after the step (c);
(E) after the step (d), removing the reaction film;
(F) After the step (e), forming a source electrode and a drain electrode spaced apart from each other on the electron supply layer;
(G) after the step (f), forming a gate electrode on a region sandwiched between the source electrode and the drain electrode on the electron supply layer;
A method for manufacturing a semiconductor device.

(Appendix 2)
In the method for manufacturing a semiconductor device according to attachment 1,
After the step (d), the n-type semiconductor region for source contact and the n-type semiconductor region for drain contact which are separated from each other are formed in the surface region of the electron supply layer.

(Appendix 3)
In the method for manufacturing a semiconductor device according to attachment 2,
The depth of the n-type semiconductor region for source contact and the depth of the n-type semiconductor region for drain contact are formed shallower than the interface between the electron supply layer and the channel layer. Method.

(Appendix 4)
In the method for manufacturing a semiconductor device according to attachment 3,
In the step (f), the second distance between the source electrode and the drain electrode is larger than the first distance between the n-type semiconductor region for source contact and the n-type semiconductor region for drain contact. Forming the source electrode and the drain electrode,
The source electrode formed in the step (f) is in direct contact with the n-type semiconductor region for source contact, and the drain electrode formed in the step (f) is connected to the n-type semiconductor region for drain contact. A method of manufacturing a semiconductor device in direct contact.

(Appendix 5)
In the method for manufacturing a semiconductor device according to attachment 1,
In the step (d), the heat treatment is performed at a temperature of 400 ° C. or higher and 650 ° C. or lower.

(Appendix 6)
In the method for manufacturing a semiconductor device according to attachment 1,
The method for manufacturing a semiconductor device, wherein the reaction film formed in the step (c) is a metal film or a metal silicide film.

(Appendix 7)
In the method for manufacturing a semiconductor device according to attachment 6,
The method for manufacturing a semiconductor device, wherein the metal film or the metal silicide film contains any element of titanium, tantalum, molybdenum, vanadium, niobium, chromium, zirconium, hafnium, and aluminum.

1S semiconductor substrate 101 source region 102 drain region 103 thermal diffusion region 104 thermal diffusion region BUF buffer layer CAP p-type cap layer CF cap layer CH channel layer DE drain electrode DEG two-dimensional electron gas DNR n-type semiconductor region for drain contact ES electron supply Layer GE gate electrode GOX gate insulating film IF1 insulating film L1 distance L2 distance LD distance LS distance PIF protective insulating film RF1 reaction film SE source electrode SNR n-type semiconductor region for source contact SW sidewall spacer

Claims (19)

Including field effect transistors,
The field effect transistor is
(A) a channel layer made of a first nitride semiconductor layer;
(B) an electron supply layer comprising a second nitride semiconductor layer formed on the channel layer;
(C) a pair of source and drain electrodes formed on the electron supply layer;
(D) a gate electrode formed on the electron supply layer so as to be sandwiched between the source electrode and the drain electrode;
(E) a source contact n-type semiconductor region and a drain contact n-type semiconductor region formed in the surface region of the electron supply layer so as to be spaced apart from each other;
With
A first distance between the source contact n-type semiconductor region and the drain contact n-type semiconductor region is smaller than a second distance between the source electrode and the drain electrode;
The source electrode and the source contact n-type semiconductor region are in direct contact,
The drain electrode and the n-type semiconductor region for drain contact are in direct contact,
Both the depth of the source contact n-type semiconductor region and the depth of the drain contact n-type semiconductor region are shallower than the interface between the channel layer and the electron supply layer.
Semiconductor device. The semiconductor device according to claim 1,
The n-type semiconductor region for source contact and the n-type semiconductor region for drain contact contain any element of titanium, tantalum, molybdenum, vanadium, niobium, chromium, zirconium, hafnium, and aluminum. Semiconductor device. The semiconductor device according to claim 1,
A semiconductor device in which the n-type semiconductor region for source contact and the n-type semiconductor region for drain contact contain nitrogen vacancies. The semiconductor device according to claim 3.
The density of the said nitrogen vacancy is a semiconductor device which is 1 * 10 < ¹⁹ > cm < ^-3 > or more. The semiconductor device according to claim 3.
The semiconductor device, wherein the n-type semiconductor region for source contact and the n-type semiconductor region for drain contact further contain silicon. The semiconductor device according to claim 1,
Side wall spacers are formed on the side walls on both sides of the gate electrode,
The n-type semiconductor region for source contact and the n-type semiconductor region for drain contact are formed in alignment with the sidewall spacer. The semiconductor device according to claim 1,
The distance between the source contact n-type semiconductor region and the gate electrode is different from the distance between the drain contact n-type semiconductor region and the gate electrode. The semiconductor device according to claim 7,
The semiconductor device, wherein a distance between the drain contact n-type semiconductor region and the gate electrode is larger than a distance between the source contact n-type semiconductor region and the gate electrode. The semiconductor device according to claim 1,
The gate electrode is a semiconductor device including a nickel film or a platinum film. The semiconductor device according to claim 1,
The semiconductor device, wherein the gate electrode is in direct contact with the electron supply layer. The semiconductor device according to claim 1,
A semiconductor device, wherein a p-type nitride semiconductor layer is formed between the gate electrode and the electron supply layer. The semiconductor device according to claim 1,
A semiconductor device, wherein a gate insulating film is formed between the gate electrode and the electron supply layer. (A) forming a channel layer made of the first nitride semiconductor layer;
(B) forming an electron supply layer made of a second nitride semiconductor layer on the channel layer;
(C) forming a gate electrode on the electron supply layer;
(D) forming a reaction film on the electron supply layer;
(E) a step of performing a heat treatment after the step (d);
(F) After the step (e), a step of removing the reaction film;
(G) after the step (f), forming a source electrode and a drain electrode spaced apart from each other on the electron supply layer;
A method for manufacturing a semiconductor device. In the manufacturing method of the semiconductor device according to claim 13,
After the step (e), the n-type semiconductor region for source contact and the n-type semiconductor region for drain contact which are separated from each other are formed in the surface region of the electron supply layer. In the manufacturing method of the semiconductor device according to claim 14,
The depth of the n-type semiconductor region for source contact and the depth of the n-type semiconductor region for drain contact are formed shallower than the interface between the electron supply layer and the channel layer. Method. In the manufacturing method of the semiconductor device according to claim 15,
In the step (g), the second distance between the source electrode and the drain electrode is larger than the first distance between the n-type semiconductor region for source contact and the n-type semiconductor region for drain contact. Forming the source electrode and the drain electrode,
The source electrode formed in the step (g) is in direct contact with the n-type semiconductor region for source contact, and the drain electrode formed in the step (g) is connected to the n-type semiconductor region for drain contact. A method of manufacturing a semiconductor device in direct contact. In the manufacturing method of the semiconductor device according to claim 13,
In the step (e), the heat treatment is performed at a temperature of 400 ° C. or higher and 650 ° C. or lower. In the manufacturing method of the semiconductor device according to claim 13,
The method for manufacturing a semiconductor device, wherein the reaction film formed in the step (d) is a metal film or a metal silicide film. In the manufacturing method of the semiconductor device according to claim 18,
The method for manufacturing a semiconductor device, wherein the metal film or the metal silicide film contains any element of titanium, tantalum, molybdenum, vanadium, niobium, chromium, zirconium, hafnium, and aluminum.

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