JP2014151217A - Game machine - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent a tampering action of a signal path between a command input port and a sub control circuit in a sub board of a game machine to improve security.SOLUTION: A sub board 32 of a game machine comprises: an interface circuit 80 which operates at a first source power voltage Vcc1; a sub control unit 71 which operates at a second source power voltage Vcc2 different from the first source power voltage Vcc1, receives prescribed data through the interface circuit 80, and controls an operation of a notification device 43 on the basis of the prescribed data; and a voltage monitoring unit 93 which monitors a change in the first source power voltage Vcc1 applied to the interface circuit 80, and outputs a signal to the sub control unit 71 when abnormality is found in the first source power voltage Vcc1. The sub control unit 71 performs, when a signal is inputted from a first voltage monitoring unit 94, a prescribed notification in a sub device which does not share a drive power source with the interface circuit 80.

Description

  The present invention relates to a gaming machine.

  Conventionally, a game called pachislot, comprising a plurality of reels each having a plurality of symbols arranged on each surface, a start switch, a stop switch, a stepping motor provided for each reel, and a control unit. The machine is known. The start switch detects that the start lever has been operated by the player (hereinafter also referred to as “start operation”) after a game medium such as a medal or coin has been inserted into the gaming machine, and the rotation of all reels is detected. Outputs a signal requesting start. The stop switch detects that a stop button provided for each reel has been pressed by the player (hereinafter also referred to as “stop operation”), and outputs a signal requesting the rotation of the corresponding reel to stop. To do. The stepping motor transmits the driving force to the corresponding reel. Further, the control unit controls the operation of the stepping motor based on the signals output from the start switch and the stop switch, and performs the rotation operation and stop operation of each reel.

  In such a gaming machine, when a start operation is detected, lottery processing using random numbers (hereinafter referred to as “internal lottery processing”) is performed on the program, and the result of the lottery (hereinafter referred to as “internal winning combination”). And the rotation of the reel is stopped based on the timing of the stop operation. Then, when the rotation of all the reels is stopped and the symbol combination related to the winning is displayed, a privilege corresponding to the symbol combination is given to the player. As an example of a privilege given to a player, payout of game media (medals, etc.), re-game operation for performing internal lottery processing again without consuming game media, and game media payout opportunities increase. The operation of a bonus game can be mentioned.

  The above-mentioned gaming machine is usually equipped with a main control circuit in which a circuit (main control circuit) for controlling the main gaming operation of the gaming machine such as determination of an internal winning combination, rotation and stop of each reel, determination of presence / absence of winning is implemented. A board and a sub-control board on which a circuit (sub-control circuit) for controlling a rendering operation mainly by displaying an image is mounted. Conventionally, there is known a gaming machine having a function of unidirectionally communicating a command for controlling the operation of the sub control board from the main control board to the sub control board (for example, refer to Patent Document 1). In the gaming machine described in Patent Document 1, since no signal is input from the sub-control board to the main control board, it is possible to prevent a go-to action on the main control board via the sub-control board. Can be increased.

  Conventionally, optical communication using an optical cable has been adopted in order to increase the safety of communication between the main control board and the sub control board. In this case, malfunctions of the control circuit due to external noise can be reduced, and goto action using radio waves can be prevented.

JP 2011-146 A

  As described above, conventionally, various measures for preventing a go-to action for communication between the main control board and the sub-control board have been proposed. However, until now, no measures have been taken to prevent the goto action performed on the signal path from the command input terminal to the sub control circuit in the sub control board.

  The present invention has been made in view of the above circumstances, and an object of the present invention is to prevent a go-to action on a signal path from a command input end to a sub control circuit in the sub control board, thereby further improving security. It is to provide a gaming machine that can be increased.

  In order to solve the above problems, the present invention provides a gaming machine having the following configuration.

A variable display section (for example, three reels 3L, 3C, 3R and three stepping motors 61L, 61C, which will be described later) includes a plurality of display rows in which a plurality of types of symbols are arranged and displays the plurality of types of symbols in a game. 61R),
A main board (e.g., a main control board 31 described later) having a main control section for controlling the operation of the variable display section and transmitting predetermined data (a variety of commands described later) relating to the operation during the game;
A sub board (for example, a sub control board 32 described later) that receives the predetermined data transmitted from the main control unit;
A notification device unit (for example, a sub-device unit 43 described later) that is electrically connected to the sub-board and performs a predetermined effect during the game,
The communication of the predetermined data between the main board and the sub board is a one-way communication from the main board to the sub board,
The sub-board is
An interface circuit to which the predetermined data is input;
A second power supply voltage (for example, a second power supply voltage Vcc2 = 3.3 V described later) having a voltage value different from a first power supply voltage (for example, a first power supply voltage Vcc1 = 5 V described later) supplied to the interface circuit. A sub-control unit that operates, receives the predetermined data via the interface circuit, and controls the operation of the notification device unit based on the predetermined data;
A first voltage monitoring unit that monitors a change in the first power supply voltage supplied to the interface circuit and outputs a signal to the sub-control unit when an abnormality occurs in the first power supply voltage (for example, A third voltage monitoring circuit 93) to be described later;
A second voltage monitoring unit (for example, a second voltage monitoring circuit 92 described later) that monitors a change in the second power supply voltage supplied to the sub-control unit,
The notification unit includes a sub-device that does not share a drive power source with the interface circuit,
The sub-control unit, when the signal is input from the first voltage monitoring unit, performs a predetermined notification by the sub-device.

  In the gaming machine of the present invention, the predetermined notification may be an error notification.

  According to the present invention, as described above, the communication status of the signal path from the command input terminal to the sub control unit (sub control circuit) on the sub board (sub control board) can be monitored. It is possible to prevent a go-to action on the signal path and further increase security.

It is a figure for demonstrating the function flow of the game machine in the 1st Embodiment of this invention. It is a perspective view which shows the external appearance structure of the game machine in the 1st Embodiment of this invention. It is a figure which shows the internal structure of the game machine in the 1st Embodiment of this invention. It is a block diagram which shows the whole structure of the circuit with which the game machine in the 1st Embodiment of this invention is provided. It is a block diagram which shows the internal structure of the sub control circuit in the 1st Embodiment of this invention. It is a main flowchart which shows the process example of the main control circuit of the game machine in the 1st Embodiment of this invention. It is a flowchart which shows the example of the interruption process by control of the main CPU (Central Processing Unit) in the 1st Embodiment of this invention. It is a flowchart which shows the example of the main board | substrate communication task performed by the sub CPU in the 1st Embodiment of this invention. It is a flowchart which shows the example of the production registration task performed by the sub CPU in the 1st Embodiment of this invention. It is a flowchart which shows the example of the production content determination process in the 1st Embodiment of this invention. It is a block diagram which shows the internal structure of the main control board of the game machine in the 1st Embodiment of this invention, and a sub control board. It is a flowchart which shows the example of the interruption process by the sub CPU at the time of the error generation in the 1st Embodiment of this invention. It is a block diagram which shows the internal structure of the main control board of a game machine in the 2nd Embodiment of this invention, and a sub control board. It is a flowchart which shows the example of the interruption process by the sub CPU at the time of the error generation in the 2nd Embodiment of this invention. It is a block diagram which shows the internal structure of the main control board and sub control board of a game machine in the 3rd Embodiment of this invention.

  Hereinafter, pachislot machines showing various embodiments of the gaming machine according to the present invention will be described with reference to the drawings.

<1. First Embodiment>
In the pachislot machine according to the first embodiment of the present invention, an interface circuit (described later) provided in a signal path from the input end of a command transmitted from the main control board to the sub control circuit (sub CPU) in the sub control board. By monitoring the power supply voltage, goto action on the signal path is prevented. Hereinafter, the configuration of the pachislot having such a power supply voltage monitoring function will be described with reference to the drawings. Before that, in the pachislot according to the present embodiment, the pachislot is related to the normal game operation and the rendering operation. An outline of the configuration and an outline of a processing flow of main operations at the time of gaming and production will be described.

[Function flow]
First, with reference to FIG. 1, the functional flow of the pachislot machine according to the first embodiment of the present invention will be described. In the pachislot machine of this embodiment, medals are used as game media for playing games. In addition to medals, for example, coins, game balls, game point data, tokens, or the like can be applied as game media.

  When a player inserts a medal into the pachislot and operates the start lever, one value (hereinafter, random number value) is extracted from random numbers in a predetermined numerical range (for example, 0 to 65535).

  The internal lottery means performs lottery based on the extracted random number value and determines an internal winning combination. By determining the internal winning combination, a combination of symbols that permits display along a winning determination line described later is determined. The types of symbol combinations are those related to “winning” that gives the player benefits such as medal payout, re-game operation, bonus game operation, etc., and other so-called “losing” And are provided.

  Further, when the start lever is operated, a plurality of reels are rotated. After that, when the player presses the stop button corresponding to the predetermined reel, the reel stop control means and the special game stop control means, based on the internal winning combination and the timing when the stop button is pressed, Control to stop rotation.

  The pachislot is basically controlled to stop the rotation of the corresponding reel within a specified time (190 msec) from when the stop button is pressed. In this specification, the number of symbols that move with the rotation of the reel within the specified time is referred to as “the number of sliding pieces”, and when the specified period is 190 msec (maximum delay time), the maximum number (maximum) Set the number of sliding pieces to 4 symbols.

  The reel stop control means, when an internal winning combination permitting display of a symbol combination related to winning is determined, normally, the symbol combination is placed on the winning determination line within a prescribed time of 190 msec (four symbols). The rotation of the reel is stopped so as to display as much as possible. Further, the reel stop control means uses the specified time to stop the rotation of the reel so that the combination of symbols that are not permitted to be displayed by the internal winning combination is not displayed along the winning determination line.

  As described above, when all the rotations of the plurality of reels are stopped, the winning determination means determines whether or not the combination of symbols displayed along the winning determination line is related to winning. . Then, when the winning determination means determines that the combination of symbols related to winning is made, a privilege such as a medal payout is given to the player. In the pachislot, the above-described series of operations are performed as a single game (unit game).

  Also, in the pachislot, among the above-described series of operations, various operations are performed using a video display operation by a liquid crystal display device, a light output operation by various lamps, an audio output operation by a speaker, or a combination of these operations. Production is performed. Such a production operation is performed as follows.

  First, when the start lever is operated, an effect random number value (hereinafter referred to as effect random number value) is extracted separately from the random number value used for determining the internal winning combination. When the effect random number value is extracted, the effect content determination means determines the effect content to be executed this time from lots of effect contents associated with the internal winning combination by lottery.

  When the content of the effect is determined, the effect executing means executes the corresponding effect in conjunction with each opportunity such as the start of reel rotation, the stop of rotation of each reel, or the determination of the presence or absence of a prize. In this way, in the pachislot machine, the player has the opportunity to know or predict the determined internal winning combination (in other words, the combination of symbols to be aimed at) by executing the production contents associated with the internal winning combination. It is possible to improve the player's interest.

[Pachislot structure]
Next, the structure of the pachislot machine according to the present embodiment will be described with reference to FIGS. 2 is a perspective view showing an external structure of the pachislot machine 1 according to the present embodiment, and FIG. 3 is a view showing an internal structure of the pachislot machine 1.

(1) External structure As shown in FIG. 2, the pachi-slot 1 includes a cabinet 1a that houses a reel, a circuit board, and the like, and a front door 1b that is attached to the cabinet 1a so as to be openable and closable. Inside the cabinet 1a, three reels 3L, 3C, 3R (variable display portions) are provided, and the three reels 3L, 3C, 3R are arranged in a direction orthogonal to the rotation direction of the reels (in the example shown in FIG. Arranged in a line along the direction). Hereinafter, the reels 3L, 3C, and 3R are referred to as a left reel 3L, a middle reel 3C, and a right reel 3R, respectively.

  Each reel (display row) has a cylindrical reel body and a translucent sheet material mounted on the peripheral surface (circumferential surface) of the reel body. A plurality of (for example, 21) symbols are continuously drawn on the surface of the sheet material along the circumferential direction of the reel body.

  An image display device 10 composed of, for example, a liquid crystal display device is provided in the approximate center of the front door 1b. The image display device 10 includes a display screen including three symbol display areas 4L, 4C, and 4R. In the present embodiment, video is displayed using the entire display screen including the symbol display areas 4L, 4C, and 4R, and a predetermined effect is executed.

  The three symbol display areas 4L, 4C, and 4R are provided corresponding to the left reel 3L, the middle reel 3C, and the right reel 3R, respectively. As shown in FIG. 2, each symbol display area is provided at a position overlapping with the corresponding reel when viewed from the front (player side), and is positioned in front of the corresponding reel (player side). To be provided. Each symbol display area has a function as a display window, and a symbol drawn on a corresponding reel provided behind the symbol display region can be visually observed through the display window. Hereinafter, the symbol display areas 4L, 4C, and 4R are referred to as a left display window 4L, a middle display window 4C, and a right display window 4R, respectively.

  In the present embodiment, each display window has three symbols arranged in succession among a plurality of types of symbols drawn on the reel when rotation of the corresponding reel provided behind the display window is stopped. Is configured to display. In other words, the upper, middle and lower areas are provided in the frame of each display window, and one symbol can be displayed in each area. Therefore, in this embodiment, symbols can be displayed on the display screen in a 3 × 3 array form. In the present embodiment, a pseudo line set from the left display window 4L to the right display window 4R in the symbol displayed in the 3 × 3 array form is a line for determining whether or not a prize is won. (Hereinafter referred to as a winning determination line).

  For example, a top line connecting the upper area of the left display window 4L, the upper area of the middle display window 4C, and the upper area of the right display window 4R, the lower area of the left display window 4L, the lower area of the middle display window 4C, and the right display window 4R. The bottom line connecting the lower regions, the middle region of the left display window 4L, the middle region of the middle display window 4C, the center line connecting the middle region of the right display window 4R, and the like can be set as the winning determination line. Further, for example, a cross-down line connecting the upper area of the left display window 4L, the middle area of the middle display window 4C, and the lower area of the right display window 4R, the lower area of the left display window 4L, the middle area of the middle display window 4C, and the right A cross-up line or the like connecting the upper area of the display window 4R can also be set as a winning determination line. Note that the winning determination line is arbitrarily set according to, for example, the model of the pachislot machine 1 or the like.

  A 7-segment display 6 including a 7-segment LED (Light Emitting Diode) is provided in the vicinity of a side end in the display screen of the image display device 10. The 7-segment display 6 includes the number of medals inserted in the current game (number of inserted medals), the number of medals to be paid out to the player as a privilege (hereinafter referred to as the number of payouts), and medals deposited inside the pachislot 1. Information such as the number of credits (hereinafter referred to as credits) is digitally displayed.

  Further, the front door 1b is provided with various devices (medal insertion slot 11, bet button 12, settlement button 14, start lever 16, stop buttons 17L, 17C, and 17R) that are to be operated by the player.

  The medal slot 11 is provided for receiving a medal dropped on the pachislot 1 from the outside by the player. The medals accepted through the medal slot 11 are inserted into one game up to a predetermined number (for example, three), and the medals exceeding the predetermined number can be deposited inside the pachislot 1. Yes (so-called credit function).

  The bet button 12 is provided to determine the number of coins to be inserted into one game from medals deposited inside the pachislot 1. The checkout button 14 is provided to pull out medals deposited inside the pachislot 1 to the outside.

  The start lever 16 is provided to start rotation of all reels (3L, 3C, 3R). The stop buttons 17L, 17C, and 17R are provided in association with the left reel 3L, the middle reel 3C, and the right reel 3R, respectively, and each stop button is provided to stop the rotation of the corresponding reel. Hereinafter, the stop buttons 17L, 17C, and 17R are referred to as a left stop button 17L, a middle stop button 17C, and a right stop button 17R, respectively.

  Further, as shown in FIG. 2, the front door 1b is provided with a medal payout outlet 18, a medal tray 19, and the like. The medal payout port 18 guides medals discharged by driving a medal payout device 33 described later to the outside. The medal tray 19 stores medals discharged from the medal payout opening 18.

  Further, as shown in FIG. 2, the front door 1b is provided with a light emitting device 20 configured by, for example, a lamp (LED or the like), for example, audio output devices 21L and 21R configured by a speaker or the like. The light emitting device 20 turns on and off the light in a pattern corresponding to the contents of the effect. The audio output devices 21L and 21R output sound such as sound effects and music corresponding to the contents of the production.

(2) Internal Structure Next, the internal structure of the pachislot machine 1 will be described with reference to FIG. FIG. 3 is a diagram showing a state in which the front door 1b is opened, and shows a structure on the back surface side of the front door 1b and a structure inside the cabinet 1a.

  A main control board 31 (main board) on which a later-described main control circuit 41 (see FIG. 4) is mounted is provided in an upper portion in the cabinet 1a. The main control circuit 41 is a circuit that controls the main operation of the game in the pachislot machine 1 and the flow between the operations, such as determination of an internal winning combination, rotation and stop of each reel, determination of presence / absence of winning. A specific configuration of the main control circuit 41 will be described in detail later.

  Three reels (a left reel 3L, a middle reel 3C, and a right reel 3R) are provided at a substantially central portion in the cabinet 1a. Although not shown in FIG. 3, each reel is connected to a corresponding stepping motor described later (any of stepping motors 61L, 61C, 61R in FIG. 4) via a gear having a predetermined reduction ratio. .

  In the cabinet 1a, a sub-control circuit 42 (see FIGS. 4 and 5) described later is mounted on the side of the left reel 3L opposite to the middle reel 3C (left side in the example shown in FIG. 3). A sub control board 32 (sub board) is provided. The sub-control circuit 42 is a circuit that controls the rendering operation by the image display device 10, the audio output devices 21L and 21R, the light emitting device 20, and the like. A specific configuration of the sub control circuit 42 will be described later in detail.

  A lower portion in the cabinet 1a is provided with a medal payout device 33 (hereinafter referred to as a hopper 33) that can accommodate a large amount of medals and can discharge them one by one. In addition, a power supply device 34 that supplies necessary power to each device included in the pachislot 1 is provided on one side of the hopper 33 (left side in the example shown in FIG. 3) in the cabinet 1a.

  A selector 35 is provided in the lower part of the arrangement area of the display windows (the left display window 4L, the middle display window 4C, and the right display window 4R) on the back side of the front door 1b (the part opposite to the display screen). It is done. The selector 35 is a device for selecting whether or not the material or shape of the medal inserted from the outside through the medal insertion slot 11 is appropriate, and guides the medal determined to be appropriate to the hopper 33. Further, although not shown in FIG. 3, a medal sensor 35 </ b> S (see FIG. 4 to be described later) is provided on the path through which the medal passes in the selector 35.

[Circuit configuration of pachislot]
Next, with reference to FIG.4 and FIG.5, the structure of the main circuits with which the pachislot 1 in this embodiment is provided is demonstrated. FIG. 4 is a block configuration diagram of the entire circuit included in the pachi-slot 1, and FIG. 5 is a block configuration diagram illustrating an internal configuration of the sub control circuit. Although not shown in FIGS. 4 and 5, the pachi-slot 1 of the present embodiment is a voltage monitoring circuit for monitoring the power supply voltages of various circuits mounted on the main control board and the sub control board (FIG. 11 described later). The first voltage monitoring circuit 91 to the third voltage monitoring circuit 93 shown in FIG. The configuration of this voltage monitoring circuit will be described in detail later.

  As shown in FIG. 4, the pachi-slot 1 includes a main control circuit 41, a sub-control circuit 42, and peripheral devices (actuators) electrically connected to these circuits.

(1) Main control circuit The main control circuit 41 is mainly composed of a microcomputer 50 mounted on a circuit board (main control board 31). As other components, the main control circuit 41 includes a clock pulse generation circuit 54, a frequency divider 55, a random number generator 56, a sampling circuit 57, a display drive circuit 64, and a hopper drive circuit 65, as shown in FIG. And a payout completion signal circuit 66.

  The microcomputer 50 includes a main control unit 51 (main CPU), a main ROM (Read Only Memory) 52, and a main RAM (Random Access Memory) 53, which are CPUs.

  The main ROM 52 controls various programs (not shown) such as a control program for various processes (see FIGS. 6 and 7 to be described later) executed by the main control unit 51, an internal lottery table, and the sub control circuit 42. Data and the like for transmitting a command (command) are stored. The main RAM 53 is provided with a storage area (not shown) for storing various data such as an internal winning combination determined by execution of the control program and various flags necessary for control.

  As shown in FIG. 4, a clock pulse generation circuit 54, a frequency divider 55, a random number generator 56 and a sampling circuit 57 are connected to the main control unit 51. The clock pulse generation circuit 54 and the frequency divider 55 generate clock pulses. The main control unit 51 executes a control program based on the generated clock pulse. The random number generator 56 generates a random number in a predetermined range (for example, 0 to 65535). Then, the sampling circuit 57 extracts one value from the generated random numbers.

  Various switches and sensors are connected to the input port of the microcomputer 50. The main control unit 51 receives input signals from various switches and controls operations of peripheral devices such as stepping motors 61L, 61C, 61R.

  The stop switch 17S detects that each of the left stop button 17L, the middle stop button 17C, and the right stop button 17R has been pressed (stop operation) by the player. The start switch 16S detects that the start lever 16 has been operated by the player (start operation). The settlement switch 14S detects that the settlement button 14 has been pressed by the player.

  The medal sensor 35S detects that a medal inserted into the medal insertion slot 11 has passed through the selector 35. The bet switch 12S detects that the bet button 12 has been pressed by the player.

  Peripheral devices whose operations are controlled by the microcomputer 50 include three stepping motors 61L, 61C, 61R (variation display unit), a 7-segment display 6, and a hopper 33. A drive circuit for controlling the operation of each peripheral device is connected to the output port of the microcomputer 50.

  The motor drive circuit 62 controls the drive of the three stepping motors 61L, 61C, 61R provided corresponding to the left reel 3L, the middle reel 3C, and the right reel 3R, respectively. The reel position detection circuit 63 detects, for each reel, a reel index indicating that the reel has made one rotation by an optical sensor having a light emitting unit and a light receiving unit.

  Each of the three stepping motors 61L, 61C, 61R has a configuration in which the momentum is proportional to the number of output pulses, and the rotation axis can be stopped at a specified angle. The driving force of each stepping motor is transmitted to the corresponding reel via a gear having a predetermined reduction ratio. Each time one pulse is output to each stepping motor, the corresponding reel rotates at a constant angle.

  The main control unit 51 detects the reel index of each reel and then counts the number of times a pulse has been output to the corresponding stepping motor, so that the rotation angle of each reel (specifically, the design of the reel Manage the number of rotations).

  Here, the management of the rotation angle of each reel will be specifically described. The number of pulses output to each stepping motor is counted by a pulse counter (not shown) provided in the main RAM 53. Each time the output of a predetermined number of pulses (for example, 16 times) necessary for the rotation of one symbol is counted by the pulse counter, the value of the symbol counter (not shown) provided in the main RAM 53 is set to “1”. "Is added. A symbol counter is provided for each reel. The value of the symbol counter is cleared when the reel index is detected by the reel position detection circuit 63.

  That is, in this embodiment, by managing the value of the symbol counter, it is managed how many symbols have been rotated since the reel index was detected. Therefore, the position of each symbol on each reel is detected with reference to the position where the reel index is detected.

  In the present embodiment, as described above, the maximum number of sliding symbols during the normal game (during bonus non-operation) is determined for four symbols. Therefore, when the left stop button 17L is pressed, the symbols of the left reel 3L located in the area on the winning determination line in the left display window 4L and the symbols existing in the range up to four are displayed on the left. It becomes a symbol that can be stopped in the region of the window 4L.

  A display unit drive circuit 64 included in the main control circuit 41 controls the operation of the 7-segment display 6. The hopper drive circuit 65 controls the operation of the hopper 33. The payout completion signal circuit 66 manages the detection of medals performed by the medal detection unit 33S provided in the hopper 33, and checks whether or not medals discharged from the hopper 33 have reached a predetermined payout number. To do.

(2) Sub-control circuit As shown in FIGS. 4 and 5, the sub-control circuit 42 is connected to the main control circuit 41, and displays the contents of effects based on a command (predetermined data) transmitted from the main control circuit 41. Processes such as determination and execution. Although not shown in FIGS. 4 and 5, in the pachislot machine 1 of the present embodiment, as shown in FIG. 11 described later, the sub control circuit 42 includes an interface circuit 80 mounted on the sub control board 32, and level conversion. It is connected to the main control circuit 41 via a circuit 81.

  In this embodiment, the communication between the main control board and the sub control board is a one-way communication from the main control board to the sub control board, and an optical communication system is adopted as the communication system. That is, in this embodiment, command transmission from the main control board to the sub control board is performed by optical communication.

  As shown in FIG. 5, the sub control circuit 42 basically includes a sub control unit 71 (sub CPU), a sub storage unit 72, an image control unit 73, and an audio control unit 74. The sub storage unit 72 includes a sub ROM 72a and a sub RAM 72b. The image control unit 73 includes a rendering processor 73a, a drawing RAM 73b, and a driver 73c. The audio control unit 74 includes a DSP (Digital Signal Processor) 74a, an audio RAM 74b, an A / D (Analog to Digital) converter 74c, and an amplifier 74d.

  The sub-control unit 71 is constituted by a CPU, and performs video, sound, and light output control according to a control program stored in the sub-ROM 72a in accordance with a command transmitted from the main control circuit 41. The sub ROM 72a basically has a program storage area and a data storage area.

  In the program storage area, various control programs executed by the sub control unit 71 (sub CPU) are stored. The control program stored in the program storage area includes, for example, a main board communication task for controlling communication with the main control circuit 41, a production random number value, and determination of production contents (production data). An effect registration task for performing registration, a drawing control task for controlling display of video by the image display device 10 (liquid crystal display device) based on the determined content of the effect, and control of light output by the light emitting device 20 (lamp) Programs such as a lamp control task for controlling the sound output and a sound control task for controlling sound output by the sound output devices 21L and 21R (speakers).

  In the data storage area, for example, a storage area for storing various data tables, a storage area for storing effect data constituting various effects, a storage area for storing animation data relating to creation of video, and sound data relating to BGM and sound effects And various storage areas such as a storage area for storing lamp data relating to a light on / off pattern.

  The sub RAM 72b has a storage area for registering the determined contents and effects data, a storage area for storing various data such as an internal winning combination transmitted from the main control circuit 41, and the like.

  Further, as shown in FIG. 5, the sub-control circuit 42 is connected to a sub-device unit 43 (notification device unit) including the image display device 10, the audio output devices 21L and 21R, the light-emitting device 20, and the like. The operation of each device (subdevice) in 43 is controlled by the sub-control circuit 42.

  In the present embodiment, the sub control unit 71, the rendering processor 73a, the drawing RAM 73b (including the frame buffer), and the driver 73c create a video according to the animation data specified by the contents of the presentation, and the created video is displayed as an image. The image is displayed by the device 10 (liquid crystal display device). Further, the sub control unit 71, DSP 74a, audio RAM 74b, A / D converter 74c, and amplifier 74d output sounds such as BGM from the sound output devices 21L and 21R (speakers) according to the sound data specified by the contents of the production. Further, the sub-control unit 71 turns on and off the light emitting device 20 (lamp) according to the lamp data specified by the contents of the effect.

[Description of main control circuit operation]
Next, with reference to FIG. 6 and FIG. 7, the contents of main processing executed by the main control unit 51 (main CPU) of the main control circuit 41 using a program will be described.

(1) Pachislot Main Operation Processing by Main Control Unit First, the procedure of main operation processing of the pachislot machine 1 controlled by the main control unit 51 will be described with reference to a main flowchart (hereinafter referred to as main flow) shown in FIG. To do.

  First, when power is turned on to the pachislot machine 1, the main control unit 51 performs initialization processing at the time of power-on (S1). In this initialization process, it is determined whether the backup has been normally performed, whether the setting has been changed appropriately, and the like, and initialization corresponding to the determination result is performed.

  Next, the main control unit 51 performs an initialization process at the end of one game (S2). In this initialization process, the data in the designated storage area in the main RAM 53 is cleared. Note that the designated storage area here is a storage area that needs to be erased for each unit game (one game) such as an internal winning combination storage area or a display combination storage area.

  Next, the main control unit 51 performs medal acceptance / start check processing (S3). In this processing, input checks of the medal sensor 35S and the start switch 16S are performed.

  Next, the main control unit 51 extracts a random number value and stores the extracted random value in a random value storage area provided in the main RAM 53 (S4). When the extracted random number value is stored in the random value storage area, the main control unit 51 performs an internal lottery process (S5). In this process, the internal winning combination is determined by lottery based on a random value.

  Next, the main control unit 51 performs a start command transmission process (S6). In this process, a start command is transmitted from the main control circuit 41 to the sub control circuit 42. Note that the start command includes a parameter for specifying an internal winning combination.

  Next, the main control unit 51 performs a reel rotation start process (S7). In this process, the main control unit 51 requests the start of rotation of all reels. When the start of rotation of all reels is requested, the driving of the three stepping motors 61L, 61C, and 61R is controlled by an interrupt process (see FIG. 12), which will be described later, executed at a constant cycle (1.1173 msec). Then, the rotation of the left reel 3L, the middle reel 3C, and the right reel 3R is started. At this time, each reel is subjected to acceleration control until the rotation speed reaches a predetermined speed, and then controlled so that the predetermined speed is maintained.

  Next, the main control unit 51 performs a reel stop control process (S8). In this process, the rotation of the corresponding reel is stopped based on the timing when the left stop button 17L, the middle stop button 17C, and the right stop button 17R are respectively pressed and the internal winning combination.

  Next, the main control unit 51 performs a winning search process (S9). In this process, the main control unit 51 searches for a combination of symbols displayed on the winning determination line after all of the left reel 3L, the middle reel 3C, and the right reel 3R are stopped, and based on the search result, medal Determine the number of payouts. Specifically, in this process, the symbol combination displayed on the winning determination line is checked against the symbol combination specified in the symbol combination table (not shown), and if both match, The display combination and the number of payouts to be determined are determined.

  Next, the main control unit 51 performs a display command transmission process (S10). In this process, a display command is transmitted from the main control circuit 41 to the sub control circuit 42. The display command includes a parameter for specifying a display combination and the number of medals to be paid out.

  Next, the main control unit 51 performs a medal payout process (S11). In this process, the hopper 33 is driven and the number of credits is updated based on the number of payouts of the display combination determined in S10, and medals are paid out.

  Next, the main control unit 51 performs a bonus end number counter updating process (S12). In this process, the value determined as the medal payout number in S10 is subtracted from the bonus end number counter. The bonus end number counter is a counter for managing the trigger of the bonus end, and is provided in the main RAM 53, for example.

  Next, the main control unit 51 determines whether or not the bonus operating flag is on (S13). The bonus operating flag is stored in, for example, a predetermined storage area of the main RAM 53, and when the bonus operating flag is on, it means that the bonus game is operating.

  In S13, when the main control unit 51 determines that the bonus operating flag is not on (when S13 is NO), the main control unit 51 performs the process of S15 described later.

  On the other hand, when the main control unit 51 determines in S13 that the bonus operating flag is on (when S13 is YES), the main control unit 51 performs a bonus end check process (S14). In this process, the main control unit 51 refers to various counters for managing the end timing of the bonus game, and checks whether or not to end the operation of the bonus game.

  After the process of S14 or when S13 is NO, the main control unit 51 performs a bonus operation check process (S15). In this process, it is mainly checked whether or not to start the bonus game. When the bonus operation check process ends, the main control unit 51 returns the process to S2, and repeats the processes after S2.

(2) Interrupt processing by the main controller (1.1173 msec)
Next, an interrupt process periodically performed by the main control unit 51 will be described with reference to FIG. First, the main control unit 51 saves the register (S21). Next, the main control unit 51 performs an input port check process (S22). In this process, signals input from various switches such as the stop switch 17S are checked.

  Next, the main control unit 51 performs a reel control process (S23). In this process, the main control unit 51 starts rotation of the left reel 3L, the middle reel 3C, and the right reel 3R when the start of rotation of all reels is requested, and thereafter, each reel rotates at a constant speed. The three stepping motors 61L, 61C, 61R are driven and controlled. When the number of sliding symbols is determined, the main control unit 51 updates the symbol counter of the corresponding reel by the number of sliding symbols. Then, the main control unit 51 waits for the updated symbol counter to match the value corresponding to the planned stop position (the symbol at the planned stop position reaches the area on the winning determination line of the display window). The corresponding stepping motor is driven and controlled so that the rotation of the reel to be decelerated and stopped.

  Next, the main control unit 51 performs a lamp and 7-segment driving process (S24). In this process, the main control unit 51 controls the 7-segment display 6 to display the number of payouts and the number of credits. Next, the main control unit 51 performs a register restoration process (S25). After that, the main control unit 51 ends the interrupt process.

[Description of sub-control circuit operation]
Next, contents of main processes (tasks) executed by the sub control unit 71 (sub CPU) of the sub control circuit 42 using a program will be described with reference to FIGS.

(1) Main Board Communication Task First, the main board communication task performed by the sub-control unit 71 will be described with reference to FIG.

  First, the sub-control unit 71 performs reception check of the command transmitted from the main control circuit 41 (S31). Next, when receiving a command, the sub-control unit 71 extracts the type of the received command (S32).

  Next, the sub-control unit 71 determines whether or not a command different from the previous one has been received (S33). In S33, when it is determined that the sub control unit 71 has not received a command different from the previous command (when S33 is NO), the sub control unit 71 returns the process to S31 and repeats the processes after S31.

  On the other hand, when it is determined in S33 that the sub-control unit 71 has received a command different from the previous command (when S33 is YES), the sub-control unit 71 stores the message in the message queue based on the received command. (S34). The message queue is a mechanism for exchanging information between processes. And after the process of S34, the sub-control part 71 returns a process to S31, and repeats the process after S31.

(2) Production Registration Task Next, the production registration task performed by the sub control unit 71 will be described with reference to FIG.

  First, the sub-control unit 71 extracts a message from the message queue (S41). Next, the sub-control unit 71 determines whether there is a message in the message queue (S42). In S42, when the sub-control unit 71 determines that there is no message in the message queue (when S42 is NO), the sub-control unit 71 performs the process of S45 described later.

  On the other hand, when the sub control unit 71 determines in S42 that there is a message in the message queue (when S42 is YES), the sub control unit 71 copies the game information from the message (S43). In this process, for example, various data such as the internal winning combination, the type of reel that has stopped rotating, the display combination, and the game state flag specified by the parameters are copied to a storage area (not shown) provided in the sub RAM 72b. The

  Next, the sub-control unit 71 performs effect content determination processing (S44). In this process, the sub-control unit 71 determines the contents of effects and registers the effect data according to the type of the received command. Details of the effect content determination process will be described later with reference to FIG.

  After the process of S44 or when S42 is NO, the sub-control unit 71 registers animation data (S45). Next, the sub-control unit 71 registers sound data (S46). Next, the sub-control unit 71 registers lamp data (S47). In addition, these registration processes are performed based on the effect data registered in the effect content determination process of S44. And after the process of S47, the sub-control part 71 returns a process to S41, and repeats the process after S41.

(3) Effect Content Determination Process Next, an example of the effect content determination process performed in S44 in the flowchart of the effect registration task (see FIG. 9) will be described with reference to FIG. Note that the flowchart of the effect registration task is not limited to the example illustrated in FIG. 10, and is appropriately changed according to the type of command transmitted from the main control board 31 to the sub control board 32.

  First, the sub-control unit 71 determines whether or not a start command is received (S51).

  When the sub control unit 71 determines in S51 that the start command is being received (when S51 is YES), the sub control unit 71 performs a start command receiving process (S52). In this process, the sub-control unit 71 extracts the effect random number, determines the effect number by lottery based on the internal winning combination, and registers it. Here, the production number is data for designating the content of the production to be executed this time.

  Next, the sub-control unit 71 registers the production data at the start according to the registered production number (S53). The production data is data for designating animation data, sound data, and lamp data. Therefore, when the effect data is registered, the corresponding animation data and the like are determined, and effects such as display of video are executed. Thereafter, the sub control unit 71 ends the effect content determination process, and moves the process to S45 of the effect registration task (see FIG. 9).

  On the other hand, when it is determined in S51 that the sub-control unit 71 is not receiving a start command (when S51 is NO), the sub-control unit 71 determines whether it is receiving a reel stop command (S54). .

  In S54, when it is determined that the sub control unit 71 is receiving the reel stop command (when S54 is YES), the sub control unit 71 determines that the registered production number and the type of the operation stop button are used. The effect data at the time of stop is registered (S55). Thereafter, the sub control unit 71 ends the effect content determination process, and moves the process to S45 of the effect registration task (see FIG. 9).

  On the other hand, when it is determined in S54 that the sub-control unit 71 is not receiving a reel stop command (when S54 is NO), the sub-control unit 71 determines whether it is a display command reception (S56). .

  When the sub control unit 71 determines in S56 that the display command is being received (when S56 is YES), the sub control unit 71 performs the display effect according to the registered effect number and display combination. Data is registered (S57). Thereafter, the sub control unit 71 ends the effect content determination process, and moves the process to S45 of the effect registration task (see FIG. 9).

  On the other hand, when it is determined in S56 that the sub-control unit 71 is not receiving a display command (when S56 is NO), the sub-control unit 71 determines whether or not it is a bonus start command reception (S58). .

  In S58, when it is determined that the sub control unit 71 is receiving a bonus start command (when S58 is YES), the sub control unit 71 registers effect data for starting the bonus (S59). Thereafter, the sub control unit 71 ends the effect content determination process, and moves the process to S45 of the effect registration task (see FIG. 9).

  On the other hand, when the sub control unit 71 determines in S58 that the bonus start command is not received (S58 is NO), the sub control unit 71 determines whether or not it is a bonus end command reception (S60). ). In S60, when the sub-control unit 71 determines that it is not at the time of receiving the bonus end command (when S60 is NO), the sub-control unit 71 ends the effect content determination process, and the process is registered as an effect registration task (see FIG. 9). ) To S45.

  On the other hand, when the sub control unit 71 determines in S60 that the bonus end command is being received (S60 is YES), the sub control unit 71 registers the effect data for the end of the bonus (S61). Thereafter, the sub control unit 71 ends the effect content determination process, and moves the process to S45 of the effect registration task (see FIG. 9).

  In the pachi-slot 1 of the present embodiment, main operations are performed according to the various processing procedures described with reference to FIGS.

[Main control board and sub control board]
As described above, in the pachislot machine 1 of this embodiment, a voltage monitoring circuit for monitoring the power supply voltages of various circuits mounted on the main control board 31 and the sub control board 32 is provided. Here, a configuration example of the main control board 31 and the sub control board 32 including such a voltage monitoring circuit will be described with reference to FIG. FIG. 11 is a schematic block configuration diagram of the main control board 31 and the sub control board 32 in the pachislot machine 1 of the present embodiment. In order to simplify the description, FIG. 11 mainly shows components related to the power supply voltage monitoring operation.

(1) Main Control Board As shown in FIG. 11, the main control board 31 is mounted not only with the main control circuit 41 described with reference to FIG. 4 but also with a first voltage monitoring circuit 91. Are electrically connected to a main control unit 51 in the main control circuit 41.

  The first voltage monitoring circuit 91 monitors the power supply voltage (hereinafter referred to as the first power supply voltage Vcc1) of the main control unit 51 (main CPU), and if an abnormality occurs in the first power supply voltage Vcc1, a reset signal is output. Output to the main control unit 51. Therefore, in order to realize such an operation, the first voltage monitoring circuit 91 is functionally mainly composed of a first voltage monitoring unit 91a and a reset signal output unit 91b.

  The first voltage monitoring unit 91a includes, for example, a comparator or the like, and compares the first power supply voltage Vcc1 of the main control unit 51 with a predetermined threshold voltage (hereinafter referred to as the first threshold voltage Vth1) by the comparator. Thus, the power supply voltage of the main control unit 51 is monitored.

  In the present embodiment, the first power supply voltage Vcc1 (operating voltage) of the main controller 51 (main CPU) is 5 V, and the operable voltage range of the main controller 51 (hereinafter referred to as the operating voltage range) is 4 It is assumed that the voltage is from 5V to 5.5V. In this embodiment, the lower limit value (4.5 V) of the operating voltage of the main control unit 51 is set as the first threshold voltage Vth1. However, the present invention is not limited to this, and the first threshold voltage Vth1 can be appropriately changed according to the operating voltage range of the main controller 51, for example. Further, for example, considering the monitoring accuracy (monitoring error) of the first power supply voltage Vcc1, the first threshold voltage Vth1 is set to a value slightly higher than the lower limit value (specification value) of the operating voltage of the main control unit 51. Also good.

  The reset signal output unit 91b outputs a reset signal to the main control unit 51 based on the monitoring result of the first voltage monitoring unit 91a. Specifically, the reset signal output unit 91b determines that the first power supply voltage Vcc1 is less than or equal to the first threshold voltage Vth1 (4.5V) due to some error event (an abnormality has occurred in the first power supply voltage Vcc1). In the case), the reset signal is output to the reset signal input terminal (input port) of the main control unit 51. As a result, the main control unit 51 is reset.

  The first voltage monitoring circuit 91 can be configured by any circuit as long as it is a circuit that enables the above-described operation. For example, the first voltage monitoring circuit 91 can be configured by a voltage monitoring IC (Integrated Circuit) that has been commercially available. it can.

(2) Sub Control Board As shown in FIG. 11, the sub control board 32 includes not only the sub control circuit 42 described in FIG. 5 but also an interface circuit 80, a level conversion circuit 81, a second voltage monitoring circuit 92, and a second voltage monitoring circuit 92. A three voltage monitoring circuit 93 (voltage monitoring unit) is mounted.

  In the sub control board 32, the interface circuit 80 and the level conversion circuit 81 are provided on a signal path from an input end of a command transmitted from the main control unit 51 to the sub control unit 71 (sub CPU). At this time, the command input terminal is connected to the input terminal of the interface circuit 80, and the output terminal of the interface circuit 80 is connected to the input terminal of the level conversion circuit 81. The output terminal of the level conversion circuit 81 is connected to a predetermined command input terminal of the sub control unit 71. That is, the command transmitted from the main control unit 51 is input to the sub control unit 71 via the interface circuit 80 and the level conversion circuit 81. The second voltage monitoring circuit 92 is electrically connected to the sub control unit 71, and the third voltage monitoring circuit 93 is electrically connected to the interface circuit 80 and the sub control unit 71.

  The interface circuit 80 is an interface circuit including at least a pull-up resistor, and can be configured by, for example, a commercially available interface circuit. As the interface circuit 80, not only a pull-up resistor but also an interface circuit including a damping resistor may be used.

  In the present embodiment, the interface circuit 80 is operated at the same power supply voltage as the main control unit 51 (first power supply voltage Vcc1 = 5.0 V). The drive power supply for the interface circuit 80 may be the same as the drive power supply for the main control unit 51, or may be provided separately from the drive power supply for the main control unit 51.

  The level conversion circuit 81 converts the maximum value (= Vcc1) of the output voltage of the interface circuit 80 into the operating voltage level (Vcc2 described later) of the sub-control unit 71. In the present embodiment, as will be described later, since the operating voltage of the sub-control unit 71 is 3.3V, the level conversion circuit 81 converts the voltage level of 5V to the voltage level of 3.3V. The level conversion circuit 81 can be composed of any circuit as long as it enables such an operation, and can be composed of, for example, a commercially available level conversion circuit.

  The second voltage monitoring circuit 92 monitors the power supply voltage of the sub-control unit 71 (sub CPU) (hereinafter referred to as the second power supply voltage Vcc2), and outputs a reset signal when an abnormality occurs in the second power supply voltage Vcc2. Output to the sub-control unit 71. Therefore, the second voltage monitoring circuit 92 is functionally mainly composed of a second voltage monitoring unit 92a and a reset signal output unit 92b in order to realize such an operation.

  The second voltage monitoring unit 92a includes, for example, a comparator and the like, and the second power supply voltage Vcc2 of the sub-control unit 71 is compared with a predetermined threshold voltage (hereinafter referred to as second threshold voltage Vth2) by the comparator. Thus, the power supply voltage of the sub-control unit 71 is monitored.

  In the present embodiment, the second power supply voltage Vcc2 (operating voltage) of the sub control unit 71 (sub CPU) is 3.3 V, and the operating voltage range of the sub control unit 71 is 3.0 V to 3.6 V. And In this embodiment, the lower limit value (3.0 V) of the operating voltage of the sub-control unit 71 is set as the second threshold voltage Vth2. However, the present invention is not limited to this, and the second threshold voltage Vth2 can be appropriately changed according to the operating voltage range of the sub-control unit 71, for example. For example, in consideration of the monitoring accuracy (monitoring error) of the second power supply voltage Vcc2, the second threshold voltage Vth2 is set to a value slightly higher than the lower limit value (specification value) of the operating voltage of the sub-control unit 71. Also good.

  The reset signal output unit 92b outputs a reset signal to the sub-control unit 71 based on the monitoring result of the second voltage monitoring unit 92a. Specifically, the reset signal output unit 92b has a case where the value of the second power supply voltage Vcc2 becomes equal to or lower than the second threshold voltage Vth2 (3.0V) due to some error event (an abnormality has occurred in the second power supply voltage Vcc2). In the case), a reset signal is output to the reset signal input terminal (input port) of the sub-control unit 71. As a result, the sub-control unit 71 is reset.

  The second voltage monitoring circuit 92 can be configured by any circuit as long as it is a circuit that enables the above-described operation. For example, the second voltage monitoring circuit 92 can be configured by a commercially available voltage monitoring IC.

  The third voltage monitoring circuit 93 monitors the power supply voltage (first power supply voltage Vcc1) of the interface circuit 80, and outputs an interrupt signal to the sub-control unit 71 when an abnormality occurs in the first power supply voltage Vcc1. . Therefore, the third voltage monitoring circuit 93 is functionally mainly composed of a first voltage monitoring unit 93a and an interrupt signal output unit 93b in order to realize such an operation.

  Similar to the first voltage monitoring unit 91a in the first voltage monitoring circuit 91, the first voltage monitoring unit 93a includes, for example, a comparator, and the comparator uses the first power supply voltage Vcc1 and the first threshold voltage Vth1. And the power supply voltage of the interface circuit 80 is monitored.

  The interrupt signal output unit 93b outputs an interrupt signal to the sub control unit 71 based on the monitoring result of the first voltage monitoring unit 93a. Specifically, the interrupt signal output unit 93b has a case where the value of the first power supply voltage Vcc1 becomes equal to or lower than the first threshold voltage Vth1 (4.5V) due to some error event (including a go-to action described later) (first When an abnormality occurs in one power supply voltage Vcc1, an interrupt signal is output to the interrupt signal input terminal (input port) of the sub-control unit 71. In this case, the sub-control unit 71 performs specific interrupt processing such as processing for notifying that an error has occurred and processing for giving a penalty to the game. This specific interrupt process will be described in detail in the operation description of the third voltage monitoring circuit 93 to be described later.

  The configuration of the third voltage monitoring circuit 93 is functionally the same as the configuration of the first voltage monitoring circuit 91, and the voltage level to be monitored is the same. Therefore, in the present embodiment, the third voltage monitoring circuit 93 can be configured by the same circuit as the first voltage monitoring circuit 91, and can be configured by, for example, a commercially available voltage monitoring IC. Note that the present invention is not limited to this, and for example, the third voltage monitoring circuit 93 may be configured by a circuit having an operating characteristic different from that of the first voltage monitoring circuit 91. For example, when the operating voltage range of the interface circuit 80 is different from the operating voltage range of the main control unit 51, the first threshold voltage Vth1 of the third voltage monitoring circuit 93 is different from that of the first voltage monitoring circuit 91. It may be set to a value.

[Method to prevent goto action]
Next, a method for preventing the goto action in the pachi-slot 1 of the present embodiment will be described. As described in the above-mentioned problem, conventionally, no countermeasure has been taken for the goto action performed on the signal path from the command input terminal to the sub control circuit 42 in the sub control board 32. Here, an example of the goto action performed on the signal path will be described.

  Now, in the pachislot machine 1 of the present embodiment, as shown in FIG. 11, among the various sub devices included in the sub device unit 43, the driving power source of the light emitting device 20 (lamp) is shared with the driving power source of the interface circuit 80. Think if you are. In general, the sub device in which the same drive power supply as that of the interface circuit 80 is used is not limited to the light emitting device 20, and differs depending on, for example, the model of the pachislot 1.

  The go-to action performed on the signal path from the command input terminal to the sub control circuit 42 in the sub control board 32 is performed, for example, by short-circuiting the first power supply voltage Vcc1 of the interface circuit 80. However, because of the structure of the pachislot 1, it is difficult to perform the goto action directly on the interface circuit 80, so that the sub-device (light emitting device 20 in the present embodiment) that uses the drive power supply in common with the interface circuit 80 Goto acts are performed. That is, the first power supply voltage Vcc1 of the light emitting device 20 attached to the front door 1b of the pachi-slot 1 is short-circuited, whereby a go-to action is performed on the signal path from the command input terminal to the sub-control circuit 42. .

  Next, the effect when such a gotting action is performed will be described. In the pachislot machine 1 of this embodiment, the sub-control unit 71 (sub-control board 32) receives a command (display command) including information on the display combination related to “replay” from the main control unit 51 (main control board 31). When received three times in succession, a privilege of assist time (hereinafter referred to as “AT”), which is a function of navigating the establishment of a specific small role with a lamp or the like, is given to the player. Further, in the pachislot machine 1 that gives such a privilege, a display command related to “Replay”, a display command related to “Lose”, and a display command related to “Replay” from the main control unit 51 (main control board 31). Suppose that the display commands related to “Replay” are transmitted to the sub-control unit 71 (sub-control board 32) in this order.

  In such a case, when the go-to action is performed at the reception timing of the display command related to “losing” and the first power supply voltage Vcc1 of the interface circuit 80 is short-circuited, the voltage level of the output terminal is changed from 5V to 0V. Thus, the change in the voltage level at the output terminal of the interface circuit 80 is eliminated. This state is the same as when no command is transmitted from the main control unit 51 (main control board 31) to the sub control unit 71 (sub control board 32). That is, a state in which the display command related to “losing” has not been received by the sub-control unit 71 (a state in which the display command related to “losing” has not been transmitted from the main control unit 51) is generated due to the goto action.

  Therefore, when such a got action is performed, the sub-control unit 71 recognizes that the display command related to “replay” has been received three times in succession, and as a result, erroneously assigns AT to the player. (The game state is advantageous to the player).

  However, in the pachislot machine 1 of this embodiment, the third voltage monitoring circuit 93 for monitoring the first power supply voltage Vcc1 of the interface circuit 80 is provided as described above. Then, the third voltage monitoring circuit 93 constantly monitors whether or not the first power supply voltage Vcc1 (= 5V) of the interface circuit 80 has become equal to or lower than the first threshold voltage Vth1 (= 4.5V). Therefore, in this embodiment, the third voltage monitoring circuit 93 can always determine whether or not a go-to action has been performed on the interface circuit 80.

  In the pachislot machine 1 of the present embodiment, for example, when a go-to action is performed on the interface circuit 80 and the first power supply voltage Vcc1 of the interface circuit 80 becomes equal to or lower than the first threshold voltage Vth1, the third voltage The monitoring circuit 93 outputs an interrupt signal to the sub control unit 71.

  When an interrupt signal is input from the third voltage monitoring circuit 93 to the sub-control unit 71, the sub-control unit 71, for example, a process for notifying that an error has occurred or a process for giving a penalty to the game, etc. Perform specific interrupt processing (error processing).

  Here, an interrupt process performed by the sub control unit 71 (sub CPU) when an error occurs will be described with reference to FIG. FIG. 12 shows not only the interrupt process of the sub-control unit 71 when a gossip occurs to the interface circuit 80 but also the interrupt process performed when an abnormality occurs in the second power supply voltage Vcc2 of the sub-control unit 71. The flow is also illustrated. In order to simplify the description, in the interrupt processing flow shown in FIG. 12, signals related to the occurrence of errors other than the interrupt signal from the third voltage monitoring circuit 93 and the reset signal from the second voltage monitoring circuit 92 are sub-signals. Illustration of the flow of interrupt processing of the sub-control unit 71 performed when input to the control unit 71 is omitted.

  In the interrupt process by the sub control unit 71 shown in FIG. 12, first, the sub control unit 71 (sub CPU) determines whether or not the input error occurrence signal is a reset signal input from the second voltage monitoring circuit 92. Is discriminated (S71).

  In S71, when the sub control unit 71 determines that the input signal is a reset signal (when S71 is YES), the sub control unit 71 performs initialization processing (S72). Thereafter, the sub-control unit 71 ends the interrupt process when an error occurs.

  On the other hand, when the sub-control unit 71 determines in S71 that the input signal is not a reset signal (when S71 is NO), the sub-control unit 71 indicates that the input signal related to the error occurrence is the third voltage monitoring circuit 93. It is determined whether or not the interrupt signal is input from (S73).

  In S73, when the sub-control unit 71 determines that the input signal is not an interrupt signal (when S73 is NO), the sub-control unit 71 ends the interrupt process when an error occurs.

  On the other hand, when the sub control unit 71 determines that the input signal is an interrupt signal in S73 (when S73 is YES), the sub control unit 71 performs a specific error process (specific process). (S74). Thereafter, the sub-control unit 71 ends the interrupt process when an error occurs.

  In the process at the time of error in S74, for example, a process for notifying that an error has occurred due to a go-to action (notification for prompting an error check), a process for giving a penalty such as navigation stop, and the like are performed. In the former process, notification may be performed for a predetermined period, or notification is performed until any release operation (for example, reset operation, setting change operation, power on / off operation, etc.) is performed on the pachi-slot 1. You may make it continue. In the case where information indicating that an error has occurred due to a gotting action or the like is continuously notified, the process of S74 is continued until a canceling operation is performed.

  Further, when notification is performed as the error time process, the notification is performed by a sub device that does not share the drive power supply with the interface circuit 80 (a sub device other than the sub device on which the goat action has been performed). Therefore, in the present embodiment, when notification is performed as error processing, notification is performed using the image display device 10 (liquid crystal display device) and / or the audio output devices 21L and 21R (speakers).

  Further, when notification is performed as an error process, error information indicating that an operation such as a goto action has been performed may be simultaneously transmitted to the hall computer of the amusement store.

  In the present embodiment, the voltage monitoring operation by the first voltage monitoring circuit 91, the second voltage monitoring circuit 92, and the third voltage monitoring circuit 93 is a game control operation by the main control unit 51 after the pachislot 1 is started. This is always performed in parallel with the production control operation by the sub-control unit 71, that is, the normal game processing. When a reset signal is input from the second voltage monitoring circuit 92 to the sub-control unit 71, or when an interrupt signal is input from the third voltage monitoring circuit 93 to the sub-control unit 71, FIG. The described interrupt process is performed in preference to the normal game process.

  As described above, in the pachislot machine 1 of the present embodiment, the first power supply voltage Vcc1 of the interface circuit 80 is monitored by the third voltage monitoring circuit 93, and the subcircuit sharing the drive power supply with the interface circuit 80 or the interface circuit 80. When a go-to action is performed on the light emitting device 20 (in this embodiment) and an abnormality occurs in the first power supply voltage Vcc1, the abnormality can be detected immediately. When the abnormality of the first power supply voltage Vcc1 is detected, the sub-control unit 71 performs the various error processing described above. Therefore, in the pachislot machine 1 of the present embodiment, it is possible to prevent the go-to action on the signal path from the command input terminal to the sub-control circuit 42 in the sub-control board 32, and security can be further improved.

<2. Second Embodiment>
Next, a pachislot machine according to a second embodiment of the present invention will be described. In the pachislot machine according to the second embodiment, its functional flow, appearance and internal structure, main control circuit, sub-control circuit and sub-device configuration, and main operation process flow by the main control circuit and sub-control circuit are as follows. These are the same as those in the first embodiment (see FIGS. 1 to 10). Therefore, description of their configuration and processing flow is omitted here.

[Main control board and sub control board]
Also in the pachislot of the present embodiment, various voltage monitoring circuits for monitoring the power supply voltage are provided on each of the main control board and the sub control board as in the first embodiment.

  FIG. 13 is a schematic block configuration diagram of the main control board and the sub control board in the pachi-slot of this embodiment. FIG. 13 mainly shows components related to a power supply voltage monitoring operation in order to simplify the description. Further, the main control board 31 and the sub control board 44 in the pachislot of this embodiment shown in FIG. 13 have the same configuration as the main control board 31 and the sub control board 32 in the pachislot 1 of the first embodiment shown in FIG. Are denoted by the same reference numerals.

  As is clear from a comparison between FIG. 13 and FIG. 11, in the present embodiment, the configuration of the sub control board 44 is different from the configuration of the sub control board 32 of the first embodiment. Other configurations are the same as the corresponding configurations of the first embodiment. Therefore, only the configuration of the sub-control board 44 will be described here, and description of other configurations will be omitted.

  As shown in FIG. 13, the sub control board 44 of the present embodiment includes not only the sub control circuit 42 described in FIG. 5, but also an interface circuit 80, a level conversion circuit 81, and a second voltage monitoring circuit 92 (second Voltage monitoring unit) and a third voltage monitoring circuit 94 (first voltage monitoring unit) are mounted.

  In the present embodiment, the sub-control circuit 42, the interface circuit 80, the level conversion circuit 81, and the second voltage monitoring circuit 92 have the same configuration as the corresponding configuration in the first embodiment. Description of these configurations is omitted. Further, in the present embodiment, the third voltage monitoring circuit 94 is electrically connected to the interface circuit 80 and the second voltage monitoring circuit 92. It is the same as that of embodiment.

  Similar to the first embodiment, the third voltage monitoring circuit 94 monitors the power supply voltage (first power supply voltage Vcc1) of the interface circuit 80, and detects the first power supply voltage by some error event (including the goto action). When an abnormality occurs in Vcc1, a reset signal is output to the sub-control unit 71 via the second voltage monitoring circuit 92. Therefore, the third voltage monitoring circuit 94 is functionally mainly composed of a first voltage monitoring unit 93a and a reset signal output unit 94b in order to realize such an operation.

  As in the first embodiment, the first voltage monitoring unit 93a includes, for example, a comparator, and the first power supply voltage Vcc1 (5V) and the first threshold voltage Vth1 (4.5V) by the comparator. And the first power supply voltage Vcc1 of the interface circuit 80 is monitored.

  The reset signal output unit 94b outputs a reset signal to the sub-control unit 71 via the second voltage monitoring circuit 92 based on the monitoring result of the first voltage monitoring unit 93a. Specifically, when the value of the first power supply voltage Vcc1 becomes equal to or lower than the first threshold voltage Vth1 (4.5V) due to some error event, the reset signal output unit 94b monitors the reset signal as the second voltage monitor. The signal is output to the reset signal input terminal of the sub-control unit 71 via the circuit 92.

  In the present embodiment, as in the first embodiment, the configuration of the third voltage monitoring circuit 94 is functionally the same as the configuration of the first voltage monitoring circuit 91, and the voltage level to be monitored is similar to that of the first voltage monitoring circuit 91. Is the same. Therefore, the third voltage monitoring circuit 94 can be composed of the same circuit as the first voltage monitoring circuit 91, and can be composed of, for example, a commercially available voltage monitoring IC. The present invention is not limited to this. For example, the third voltage monitoring circuit 94 may be configured with a circuit having different operating characteristics from the first voltage monitoring circuit 91. For example, when the operating voltage range of the interface circuit 80 is different from the operating voltage range of the main control unit 51, the first threshold voltage Vth1 of the third voltage monitoring circuit 94 is different from that of the first voltage monitoring circuit 91. It may be set to a value.

  In the present embodiment, similarly to the first embodiment, the second voltage monitoring circuit 92 monitors the power supply voltage (second power supply voltage Vcc2) of the sub-control unit 71, and the second power supply voltage Vcc2 is monitored. If an abnormality occurs, the second voltage monitoring circuit 92 outputs a reset signal to the reset signal input terminal of the sub-control unit 71. That is, in this embodiment, when an abnormality occurs in the first power supply voltage Vcc1 of the interface circuit 80 and / or the second power supply voltage Vcc2 of the sub-control unit 71, the reset signal is sub-controlled from the second voltage monitoring circuit 92. Is output to the unit 71.

  Therefore, the configuration of the second voltage monitoring circuit 92 is substantially a configuration (not shown) including an OR circuit therein, and the reset signal input from the third voltage monitoring circuit 94 and the second voltage monitoring circuit 92. When at least one of the reset signals output from the reset signal output unit 92b is input to the OR circuit, the reset signal is output from the OR circuit to the sub-control unit 71.

  As described above, in the present embodiment, when an abnormality occurs in the first power supply voltage Vcc1 of the interface circuit 80 due to the above-described gore action or the like, the third voltage monitoring circuit 94 interrupts the sub-control unit 71. A reset signal is output instead of a signal. Therefore, in this embodiment, when a go-to action is performed on the signal path from the command input end to the sub control circuit 42 in the sub control board 32, the sub control unit 71 performs the interrupt process. In addition to the above-described specific error processing, initialization processing is performed.

[Method to prevent goto action]
Next, a method for preventing a go-to action performed on a signal path from the command input terminal in the sub control board 32 to the sub control circuit 42 in the present embodiment will be described with reference to FIG.

  FIG. 14 is a flowchart of an interrupt process performed in the sub-control unit 71 when an error occurs due to the above-described goth action or the like. FIG. 14 shows not only the interrupt process of the sub-control unit 71 at the time of occurrence of the above-described goth action, but also the flow of the interrupt process performed when an abnormality occurs in the second power supply voltage Vcc2 of the sub-control unit 71. Also illustrated. In order to simplify the description, in the interrupt processing flow shown in FIG. 14, a signal related to the occurrence of an error other than the reset signal from the third voltage monitoring circuit 94 and / or the second voltage monitoring circuit 92 is sent to the sub-control unit 71. The illustration of the flow of interrupt processing of the sub-control unit 71 when it is input to is omitted.

  As described above, in the present embodiment, when the third voltage monitoring circuit 94 detects that the first power supply voltage Vcc1 of the interface circuit 80 is short-circuited (ie, an abnormality has occurred) due to the gore action, The initialization process based on the reset signal is performed instead of the specific error process based on the interrupt signal performed in the first embodiment. Therefore, the processing flow of the interrupt processing of the sub-control unit 71 in the present embodiment shown in FIG. 14 is the same as the processing based on the interrupt signal in the processing flow of the interrupt processing of the first embodiment shown in FIG. The processing flow is omitted.

  Specifically, in the interrupt processing of this embodiment, first, the sub control unit 71 (sub CPU) determines whether or not the input error generation signal is a reset signal input from the second voltage monitoring circuit 92. Is determined (S81).

  In S81, when the sub control unit 71 determines that the input signal is not a reset signal (when S81 is NO), the sub control unit 71 ends the interrupt process when an error occurs.

  On the other hand, when the sub control unit 71 determines in S81 that the input signal is a reset signal (when S81 is YES), the sub control unit 71 performs an initialization process (S82). Thereafter, the sub-control unit 71 ends the interrupt process when an error occurs.

  In the present embodiment, when an error occurs due to the goto action, the interruption process by the sub-control unit 71 is performed in this way. In the present embodiment as well, the power supply voltage monitoring operation by the first voltage monitoring circuit 91, the second voltage monitoring circuit 92, and the third voltage monitoring circuit 94 is the same as in the first embodiment. Thereafter, it is always performed in parallel with the normal game processing (game control operation by the main control unit 51 and production control operation by the sub control unit 71). When a reset signal is input from the second voltage monitoring circuit 92 to the sub-control unit 71, or when a reset signal is input from the third voltage monitoring circuit 94 via the second voltage monitoring circuit 92, The interrupt process described with reference to FIG. 14 is performed with priority over the normal game process.

  As described above, also in the pachislot of the present embodiment, the first power supply voltage Vcc1 of the interface circuit 80 is monitored by the third voltage monitoring circuit 94 as in the first embodiment, and the first power supply voltage Vcc1 is monitored by, for example, the goth action. If an abnormality (short circuit) occurs in the power supply voltage Vcc1, the abnormality can be detected immediately. When the abnormality of the first power supply voltage Vcc1 is detected, the sub-control unit 71 performs an initialization process. Therefore, also in the pachislot of the present embodiment, it is possible to prevent the goto action on the signal path from the command input end to the sub control circuit 42 in the sub control board 32, as in the first embodiment. Yes, security can be increased.

<3. Third Embodiment>
Next, a pachislot machine according to a third embodiment of the present invention will be described. In the pachislot machine according to the third embodiment, its functional flow, appearance and internal structure, main control circuit, sub-control circuit and sub-device configuration, and main operation process flow by the main control circuit and sub-control circuit are as follows. These are the same as those in the first embodiment (see FIGS. 1 to 10). Therefore, description of their configuration and processing flow is omitted here.

  Also in the pachislot of the present embodiment, various voltage monitoring circuits for monitoring the power supply voltage are provided on each of the main control board and the sub control board as in the first embodiment.

  FIG. 15 is a schematic block configuration diagram of the main control board and the sub control board in the pachi-slot of this embodiment. FIG. 15 mainly shows components related to a power supply voltage monitoring operation in order to simplify the description. Further, the main control board 31 and the sub control board 45 in the pachislot of this embodiment shown in FIG. 15 have the same configuration as the main control board 31 and the sub control board 44 in the pachislot of the second embodiment shown in FIG. Are denoted by the same reference numerals.

  As is clear from comparison between FIG. 15 and FIG. 13, in this embodiment, the configuration of the sub control board 45 is different from the configuration of the sub control board 44 of the second embodiment. Other configurations are the same as the corresponding configurations of the second embodiment. Therefore, only the configuration of the sub-control board 45 will be described here, and description of other configurations will be omitted.

  As shown in FIG. 15, the sub control board 45 of the present embodiment includes not only the sub control circuit 42 described in FIG. 5 but also an interface circuit 80, a level conversion circuit 81, a second voltage monitoring circuit 92 (a second voltage monitoring circuit 92). A voltage monitoring unit), a third voltage monitoring circuit 94 (first voltage monitoring unit), and an OR circuit 95 (reset signal output unit).

  In the present embodiment, the sub control circuit 42, the interface circuit 80, and the level conversion circuit 81 have the same configuration as that of the first embodiment, and therefore, the description of these configurations is omitted here. The connection relationship between these circuits is the same as that of the first embodiment.

  Similar to the first embodiment, the second voltage monitoring circuit 92 is electrically connected to the sub control unit 71 and monitors the power supply voltage (second power supply voltage Vcc2) of the sub control unit 71. The internal configuration of the second voltage monitoring circuit 92 can be configured in the same manner as the second voltage monitoring circuit 92 of the first embodiment, and the second voltage monitoring circuit 92 is conventionally commercially available, for example. It can be composed of a voltage monitoring IC. The second voltage monitoring circuit 92 is connected to one input terminal of the OR circuit 95. When the value of the second power supply voltage Vcc2 becomes equal to or lower than the second threshold voltage Vth2 due to some error event, the OR circuit 95 A reset signal is output to one of the input terminals.

  As in the first embodiment, the third voltage monitoring circuit 94 is electrically connected to the interface circuit 80 and monitors the power supply voltage (first power supply voltage Vcc1) of the interface circuit 80. The internal configuration of the third voltage monitoring circuit 94 can be configured in the same manner as the third voltage monitoring circuit 94 of the second embodiment, and the third voltage monitoring circuit 94 is commercially available, for example. It can be composed of a voltage monitoring IC. Further, the third voltage monitoring circuit 94 is connected to the other input terminal of the OR circuit 95, and the value of the first power supply voltage Vcc1 becomes equal to or lower than the first threshold voltage Vth1 due to some error event (including the above-mentioned gore action). In this case, a reset signal is output to the other input terminal of the OR circuit 95.

  The output terminal of the OR circuit 95 is connected to the reset signal input terminal of the sub-control unit 71. The OR circuit 95 outputs a reset signal to the sub-control unit 71 when a reset signal is input from the second voltage monitoring circuit 92 and / or the third voltage monitoring circuit 94. In the second embodiment, the OR circuit is included in the second voltage monitoring circuit 92. However, in the present embodiment, the OR circuit is separately provided outside the second voltage monitoring circuit 92. is there.

  In the pachislot of this embodiment having the above-described configuration, when an abnormality occurs in the first power supply voltage Vcc1 of the interface circuit 80 and / or the second power supply voltage Vcc2 of the sub-control unit 71, the reset signal is sub-controlled from the OR circuit 95. Is output to the unit 71. That is, in this embodiment, as in the second embodiment, the third voltage monitoring circuit 94 indicates that the first power supply voltage Vcc1 of the interface circuit 80 has been short-circuited (because an abnormality has occurred) due to the gore action. If detected, a reset signal is input to the sub-control unit 71 to perform initialization processing. Therefore, the processing flow of the interrupt processing of the sub control unit 71 performed when an error occurs in the present embodiment is the same as the flow of interrupt processing of the second embodiment shown in FIG.

  As described above, also in the pachislot of this embodiment, the first power supply voltage Vcc1 of the interface circuit 80 is monitored by the third voltage monitoring circuit 94 as in the first and second embodiments. Thus, when an abnormality (short circuit) occurs in the first power supply voltage Vcc1, the abnormality can be detected immediately. When the abnormality of the first power supply voltage Vcc1 is detected, the sub control unit 71 performs an initialization process. Therefore, also in the pachislot of this embodiment, as in the first and second embodiments, a go-to action on the signal path from the command input end to the sub control circuit 42 in the sub control board 32 is prevented. Can increase security.

  In the various embodiments described above, a pachislot machine has been described as an example of a gaming machine, but the present invention is not limited to this. The technology of the present invention can be applied to, for example, pachinko machines and other game machines, and the same effect can be obtained.

  DESCRIPTION OF SYMBOLS 1 ... Pachi slot (game machine), 3L ... Left reel, 3C ... Middle reel, 3R ... Right reel, 4L ... Left display window, 4C ... Middle display window, 4R ... Right display window, 10 ... Image display device, 17L ... Left Stop button, 17C ... Middle stop button, 17R ... Right stop button, 20 ... Light emitting device, 21L, 21R ... Audio output device, 31 ... Main control board, 32, 44, 45 ... Sub control board, 41 ... Main control circuit, 42 ... sub control circuit, 43 ... sub device unit, 51 ... main control unit, 71 ... sub control unit, 72 ... sub storage unit, 73 ... image control unit, 74 ... audio control unit, 80 ... interface circuit, 81 ... level Conversion circuit 91 ... first voltage monitoring circuit 92 ... second voltage monitoring circuit 93, 94 ... third voltage monitoring circuit 95 ... OR circuit

Claims (2)

A variable display unit including a plurality of display columns in which a plurality of types of symbols are arranged, and variably displaying the plurality of types of symbols during a game;
A main board having a main control unit for controlling the operation of the variable display unit and transmitting predetermined data related to an operation during a game;
A sub-board for receiving the predetermined data transmitted from the main control unit;
An informing device that is electrically connected to the sub-board and performs a predetermined effect during the game,
The communication of the predetermined data between the main board and the sub board is a one-way communication from the main board to the sub board,
The sub-board is
An interface circuit to which the predetermined data is input;
It operates with a second power supply voltage having a voltage value different from the first power supply voltage supplied to the interface circuit, receives the predetermined data via the interface circuit, and performs the notification based on the predetermined data A sub-control unit for controlling the operation of the device unit;
A first voltage monitoring unit that monitors a change in the first power supply voltage supplied to the interface circuit and outputs a signal to the sub-control unit when an abnormality occurs in the first power supply voltage;
A second voltage monitoring unit that monitors a change in the second power supply voltage supplied to the sub-control unit,
The notification unit includes a sub-device that does not share a drive power source with the interface circuit,
The sub-control unit, when the signal is input from the first voltage monitoring unit, performs a predetermined notification by the sub-device. The gaming machine according to claim 1, wherein the predetermined notification is an error notification.

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