JP2014139974A - Power mosfet manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve the problem in buried epitaxial growth based on a full-mask residual scheme, a full-mask removal scheme, and a simple combination thereof, that the full-mask residual scheme, if an overgrowth layer of buried epitaxial growth is thick, causes a crystal defect to occur in the vicinity of surface due to a difference in thermal expansion coefficient between a trench processing hard mask and an Si substrate, that the full-mask removal scheme has difficulty in eliminating, by polishing, a thickness variation in the wafer surface caused by buried epitaxial growth, and that the simple combination scheme is incapable of sufficient flattening, etc. depending on its implementation.SOLUTION: In the present method for manufacturing a power MOSFET, buried epitaxial growth is executed while a trench processing hard mask film remains in a scribe region, and then the hard mask film is subjected to primary polishing as a stopper, and then secondary polishing is executed while the hard mask film is removed.

Description

  The present application relates to a method of manufacturing a semiconductor integrated circuit device (or a semiconductor device), and can be applied to, for example, a manufacturing process of a power semiconductor device.

  Japanese Unexamined Patent Publication No. 2010-118536 (Patent Document 1) relates to a buried epitaxial growth for forming a super junction in a manufacturing process of a power semiconductor device. In the first example, a cap film made of a silicon oxide film is formed on the surface of all the trenches in the cell region and on the surface of the silicon substrate around the target (Target). In this state, a technique of performing CMP (Chemical Mechanical Polishing) after performing buried epitaxial growth is disclosed. In this example, in order to leave the cap film around the target, only a part of the over-epitaxial layer is removed by CMP, and then dry etch-back for Si is performed to remove the remaining over-epitaxial layer. It has been removed. On the other hand, in the second example, after forming a trench using the silicon oxide film as a mask, a cap film composed of the silicon oxide film is left in the recess portion around the target, and in this state, buried epitaxial growth is performed. A technique for removing all of the overepitaxial layer by performing CMP after execution is disclosed.

  Japanese Unexamined Patent Publication No. 2011-249634 (Patent Document 2) relates to buried epitaxial growth for forming a super junction in a manufacturing process of a power semiconductor device. There is disclosed a technique in which a trench for forming a super junction is formed, embedded epitaxial growth is performed in a state where all trench processing hard mask films such as a silicon oxide film are left, and then the surface is planarized. Yes. Here, the planarization of the surface is performed by first performing the first CMP process using the trench processing hard mask film as a stopper, then removing the hard mask film by wet etching or the like, and then performing the second CMP process. A CMP process is executed.

  Japanese Unexamined Patent Application Publication No. 2009-224606 (Patent Document 3) relates to buried epitaxial growth for forming a super junction in a manufacturing process of a power semiconductor device. There is disclosed a technique of performing CMP after performing buried epitaxial growth in a state in which a trench for forming a super junction is formed and the trench processing hard mask film is completely removed.

JP 2010-118536 A JP 2011-249634 A JP 2009-224606 A

  For buried epitaxial growth, basically, a method of executing buried epitaxial growth while leaving almost all of the trench processing hard mask (referred to as “full-surface mask remaining method”), and a state where almost all of the trench processing hard mask is removed. There are a method of executing buried epitaxial growth (referred to as “entire mask removal method”) and a simple combination of these methods.

  With regard to these, the following has been clarified by the study of the present inventors. That is, the full-surface mask remaining method can absorb the thickness variation by polishing using the trench processing hard mask as a polishing stopper even when the variation of the buried epitaxial growth rate in the wafer is large. On the other hand, when the thickness of the overgrown epitaxial growth layer is increased, crystal defects are generated near the surface due to the difference in thermal expansion coefficient between the trench processing hard mask and the silicon substrate. Further, the depth of the crystal defect becomes deeper in proportion to the thickness of the overgloss layer.

  On the other hand, in the whole surface mask removal method, such crystal defects do not occur in principle, but it is difficult to eliminate the thickness variation in the wafer surface caused by the buried epitaxial growth by polishing.

  Furthermore, as a simple combination method, for example, after performing buried epitaxial growth with the trench processing hard mask remaining only in the scribe region, the planarization is first planarized by polishing using the trench processing hard mask as a stopper, and then dry. There is a method of performing secondary planarization by etch back. However, this method has a problem in that the flattening cannot be sufficiently performed because the secondary flattening is performed by dry etching back.

  Further, as another simple combination method, for example, after performing the buried epitaxial growth with the trench processing hard mask remaining only in the recess portion of the scribe region, the trench processing hard mask is used as a stopper to polish directly. There is a method of flattening. However, this method has a problem of requiring a process such as forming a relatively large recess in the scribe region.

  Means for solving such problems will be described below, but other problems and novel features will become apparent from the description of the present specification and the accompanying drawings.

  An outline of representative ones of the embodiments disclosed in the present application will be briefly described as follows.

  That is, the outline of an embodiment of the present application is that, in a power MOSFET manufacturing method, after performing buried epitaxial growth in a state where a hard mask film for trench processing is present in a hard mask remaining region of a scribe region, the hard mask film is stopped as a stopper. As a result, the secondary polishing is performed with the hard mask film removed.

  The effects obtained by the representative ones of the embodiments disclosed in the present application will be briefly described as follows.

  That is, according to one embodiment of the present application, it is possible to reduce the occurrence of crystal defects in the cell region while ensuring flatness without complicating the process.

Whole surface top view of wafer for explaining the manufacturing process in the method of manufacturing a power MOSFET (cell peripheral SJ termination type) according to an embodiment of the present application, the wafer at the time of device completion, the chip region, the interrelation between each part inside and outside, and the like It is. 1 is an enlarged plan view of a single chip region and its periphery in FIG. 1 (almost at the time of completion of the device, but the metal source electrode and the like are removed in order to make the super junction structure and the like easier to see). FIG. 3 is an enlarged plan view of a chip corner peripheral cutout region R1 of FIGS. 1 and 2. FIG. 3 is a top view of a wafer showing a relationship between a hard mask remaining region and a cell region in a trench formation process substantially corresponding to FIG. 2 (however, a structure such as an alignment mark region is omitted); FIG. 5 is a top view of a wafer showing a state of alignment mark regions omitted in FIG. 4. The cell region (or super junction formation region) and the scribe region (alignment mark) of the wafer during the manufacturing process (alignment mark forming step) for explaining the wafer process and the like in the method of manufacturing the power MOSFET according to the embodiment of the present application. FIG. 3 is a cross-sectional view (corresponding to the XX ′ cross-section of FIG. 2) of a region. A cell region (or super junction formation region) of a wafer in the middle of a manufacturing process (lower trench hard mask film forming step for trench etching) for explaining a wafer process and the like in the method of manufacturing a power MOSFET according to the one embodiment of the present application, and It is sectional drawing (corresponding to XX 'section of Drawing 2) of a scribe field (including an alignment mark field). Cell region (or super junction formation region) and scribe of a wafer in the middle of a manufacturing process (lower trench hard mask processing step) for explaining a wafer process and the like in the method of manufacturing a power MOSFET according to the one embodiment of the present application It is sectional drawing (corresponding to XX 'section of Drawing 2) of a field (including an alignment mark field). The cell region (or super junction formation region) of the wafer during the manufacturing process (upper layer hard mask film forming step for trench etching) for explaining the wafer process and the like in the method of manufacturing the power MOSFET of the one embodiment of the present application, and It is sectional drawing (corresponding to XX 'section of Drawing 2) of a scribe field (including an alignment mark field). Cell region (or super junction formation region) and scribe of wafer during manufacturing process (upper layer hard mask processing step for trench etching) for explaining a wafer process and the like in the method of manufacturing a power MOSFET according to the embodiment of the present application It is sectional drawing (corresponding to XX 'section of Drawing 2) of a field (including an alignment mark field). The cell region (or super junction formation region) and scribe region (alignment mark region) of the wafer during the manufacturing process (trench etching step) for explaining the wafer process and the like in the method of manufacturing the power MOSFET according to the embodiment of the present application. 3 is a cross-sectional view (corresponding to the XX ′ cross-section of FIG. 2). FIG. 14 is a plan view of the cell region in the step of FIG. 13 (corresponding to the active cell cutout region R2 of FIG. 2). Cell region (or super junction formation region) and scribe of a wafer in the middle of a manufacturing process (upper layer hard mask removal step for trench etching) for explaining a wafer process and the like in the method of manufacturing a power MOSFET according to the embodiment of the present application It is sectional drawing (corresponding to XX 'section of Drawing 2) of a field (including an alignment mark field). A cell region (or super junction formation region) and a scribe region (alignment mark region) of a wafer in the middle of a manufacturing process (buried epitaxial growth step) for explaining a wafer process and the like in the method of manufacturing a power MOSFET according to the embodiment of the present application. 3 is a cross-sectional view (corresponding to the XX ′ cross-section of FIG. 2). The cell region (or super junction formation region) and scribe region (alignment region) of the wafer during the manufacturing process (first CMP step) for explaining the wafer process and the like in the method of manufacturing the power MOSFET according to the embodiment of the present application. 3 is a cross-sectional view (including a mark region) (corresponding to the XX ′ cross-section of FIG. 2). The cell region (or super junction formation region) and scribe of the wafer during the manufacturing process (trench etch lower hard mask removing step) for explaining the wafer process and the like in the method of manufacturing the power MOSFET according to the embodiment of the present application. It is sectional drawing (corresponding to XX 'section of Drawing 2) of a field (including an alignment mark field). The cell region (or super junction formation region) and the scribe region (alignment region) of the wafer during the manufacturing process (second CMP step) for explaining the wafer process and the like in the method of manufacturing the power MOSFET according to the embodiment of the present application. 3 is a cross-sectional view (including a mark region) (corresponding to the XX ′ cross-section of FIG. 2). 2 in the active cell cutout region R2 of FIG. 2 during the manufacturing process (P-type body region introducing step) for explaining the wafer process and the like in the method of manufacturing the power MOSFET according to the embodiment of the present invention. It is a corresponding device sectional view. 2 in the active cell cutout region R2 of FIG. 2 during the manufacturing process (polysilicon film forming step) for explaining the wafer process and the like in the method of manufacturing the power MOSFET according to the embodiment of the present invention. It is a corresponding device sectional view. XX ′ of the active cell cutout region R2 in FIG. 2 during the manufacturing process (gate processing and N + type source region introducing step) for explaining the wafer process and the like in the method of manufacturing the power MOSFET according to the embodiment of the present application. It is device sectional drawing which respond | corresponds substantially to a cross section. 2 in the active cell cutout region R2 of FIG. 2 during the manufacturing process (contact groove formation and P + type body contact region introducing step) for explaining the wafer process and the like in the method of manufacturing the power MOSFET of the one embodiment of the present application. FIG. 10 is a device cross-sectional view substantially corresponding to the X ′ cross-section. XX ′ in the active cell cutout region R2 in FIG. 2 during the manufacturing process (plug embedding and surface metal film forming step) for explaining the wafer process and the like in the method of manufacturing the power MOSFET according to the embodiment of the present application. It is device sectional drawing which respond | corresponds substantially to a cross section. XX ′ cross section of active cell cutout region R2 in FIG. 2 during the manufacturing process (final passivation film formation and processing step) for explaining the wafer process and the like in the method of manufacturing the power MOSFET according to the embodiment of the present application. FIG. In the XX ′ cross section of the active cell cutout region R2 in FIG. 2 during the manufacturing process (back surface metal electrode film forming step) for explaining the wafer process and the like in the method of manufacturing the power MOSFET according to the embodiment of the present application. FIG. 4 is a device cross-sectional view that substantially corresponds. The entire chip periphery of FIG. 4 for explaining a device structure in the method of manufacturing the power MOSFET according to the embodiment of the present application, in particular, a modified example relating to the formation range of the super junction structure (superjunction forming method limited in the cell region) It is a top view of the wafer corresponding to cut-out region R3. The figure for demonstrating the modification (superjunction formation area | region-buffer layout layout between superjunction formation area | regions) regarding the device structure in the manufacturing method of the power MOSFET of the said one Embodiment of this application especially the formation range of a super junction structure, etc. 4 is a top view of a wafer corresponding to a whole chip cutting area R3 of 4 chips. FIG. The entire chip periphery in FIG. 4 for explaining a device structure in the method of manufacturing a power MOSFET according to the embodiment of the present invention, in particular, a modification (formation method for limiting the entire surface of the chip region) regarding the formation range of the super junction structure. It is a top view of the wafer corresponding to cut-out region R3. FIG. 4 is a view for explaining a modification (a whole chip region and external peripheral limited super junction formation method) relating to a device structure, particularly a super junction structure formation range, etc. in the method of manufacturing a power MOSFET according to the embodiment of the present application. It is a top view of the wafer corresponding to the chip peripheral whole cutout region R3. FIG. 9 is a device cross-sectional view corresponding to FIG. 8 for describing a wafer process and the like related to Modification Example 1 (Stripe Hard Mask Thinning Method) related to a hard mask layout in a cell region in the method for manufacturing a power MOSFET according to the embodiment of the present application; . 8 is a device cross-sectional view corresponding to FIG. 8 for explaining a wafer process and the like related to Modification Example 1 (Stripe Hard Mask Thinning Method) related to the hard mask layout in the cell region in the method for manufacturing the power MOSFET according to the embodiment of the present application. Etching lower layer hard mask processing step). FIG. 10 is a device cross-sectional view substantially corresponding to FIG. 10 for explaining the wafer process and the like related to Modification Example 1 (Stripe Hard Mask Thinning Method) in the cell region hard mask layout in the method of manufacturing the power MOSFET according to the embodiment of the present application. The upper layer hard mask processing step for trench etching). In the process of FIG. 33 corresponding to FIG. 12 for explaining the wafer process and the like regarding the modification 1 (stripe hard mask thinning method) related to the hard mask layout in the cell region in the method of manufacturing the power MOSFET according to the embodiment of the present application. FIG. 3 is a plan view of a cell region (corresponding to an active cell cutout region R2 in FIG. 2). Device sectional view (trench) corresponding to FIG. 13 for explaining the wafer process and the like related to Modification Example 1 (Stripe Hard Mask Thinning Method) related to the hard mask layout in the cell region in the method of manufacturing the power MOSFET according to the embodiment of the present application. Etching upper layer hard mask removing step). 14 is a device cross-sectional view corresponding to FIG. 14 (embedding) for explaining a wafer process and the like related to Modification Example 1 (Stripe Hard Mask Thinning Method) in the cell region hard mask layout in the method of manufacturing the power MOSFET according to the embodiment of the present application. Epitaxial growth step). FIG. 15 is a device cross-sectional view corresponding to FIG. 15 for explaining the wafer process and the like related to Modification Example 1 (Stripe Hard Mask Thinning Method) related to the hard mask layout in the cell region in the method of manufacturing the power MOSFET according to the embodiment of the present application. 1 CMP step). Device sectional view (trench) corresponding to FIG. 16 for explaining a wafer process and the like related to Modification Example 1 (Stripe Hard Mask Thinning Method) in the cell region hard mask layout in the method of manufacturing the power MOSFET according to the embodiment of the present application. Etching lower layer hard mask removing step). FIG. 17 is a device sectional view corresponding to FIG. 17 for explaining the wafer process and the like related to Modification Example 1 (Stripe Hard Mask Thinning Method) related to the hard mask layout in the cell region in the method of manufacturing the power MOSFET according to the embodiment of the present application. 2 CMP step). The top view of the cell area | region in the trench etch process corresponding to FIG. 12 for demonstrating the modification 2 (island hard mask laying system) regarding the hard mask layout in a cell area | region in the manufacturing method of power MOSFET of the said one Embodiment of this application (Corresponding to the active cell cutout region R2 in FIG. 2). The top view of the cell area | region in the trench etch process corresponding to FIG. 12 for demonstrating the modification 3 (island hard mask thinning-out system) regarding the hard mask layout in a cell area | region in the manufacturing method of power MOSFET of the said one Embodiment of this application (Corresponding to the active cell cutout region R2 in FIG. 2). It is a device principal part perspective view for demonstrating the modification (LDMOSFET) regarding the device structure in the manufacturing method of power MOSFET of the said one Embodiment of this application. It is a process block flowchart for demonstrating the outline of the manufacturing method of the power MOSFET of the said one Embodiment of this application. FIG. 5 is a top view of a wafer corresponding to a whole chip peripheral cutout region R3 of FIG. 4 for providing a supplementary explanation regarding a wafer whole surface super junction formation method.

[Outline of Embodiment]
First, an outline of a typical embodiment of the invention disclosed in the present application will be described.

1. A power MOSFET manufacturing method including the following steps:
(A) preparing a semiconductor wafer having an on-substrate epitaxial layer on the first main surface side and having the first conductivity type substrate layer on the second main surface side;
(B) forming a hard mask film on the first main surface of the semiconductor wafer;
(C) patterning the hard mask film;
(D) forming a plurality of trenches in the first main surface of the semiconductor wafer using the patterned hard mask film as a mask;
(E) After the step (d), the hard mask film is formed on the hard mask film remaining area of the scribe area adjacent to each of a large number of chip areas arranged in a lattice pattern on the first main surface. Removing the hard mask film so as to remain as a CMP stop film;
(F) With the CMP stop film in the scribe region, the first main surface of the semiconductor wafer has a second conductivity type opposite to the first conductivity type by buried epitaxial growth. Depositing a buried epitaxy layer;
(G) After the step (f), performing a first CMP process on the first main surface of the semiconductor wafer using the CMP stop film as a CMP stopper;
(H) a step of removing the CMP stop film after the step (g);
(I) A step of performing a second CMP process on the first main surface of the semiconductor wafer after the step (h).

2. In the method of manufacturing a power MOSFET according to item 1, the step (b) includes the following substeps:
(B1) forming a first insulating film on the first main surface of the semiconductor wafer;
(B2) removing the first insulating film so as to leave the first insulating film as a residual insulating film in the hard mask film residual region;
(B3) After the substep (b2), forming a second insulating film that forms the hard mask film together with the residual insulating film on the first main surface of the semiconductor wafer.

  3. 3. In the method for manufacturing a power MOSFET according to item 1 or 2, the hard mask film remaining region includes an alignment mark region.

  4). 4. The method for manufacturing a power MOSFET according to Item 2 or 3, wherein the first insulating film is a silicon nitride insulating film, and the second insulating film is a silicon oxide insulating film.

  5. 5. In the method of manufacturing a power MOSFET according to any one of Items 1 to 4, the polishing amount of the second CMP process is smaller than the polishing amount of the first CMP process.

  6). 6. In the method for manufacturing a power MOSFET according to any one of Items 1 to 5, in the second CMP process, both the epitaxy layer on the substrate and the buried epitaxy layer are polished.

7). A power MOSFET manufacturing method including the following steps:
(A) preparing a semiconductor wafer having an on-substrate epitaxial layer on the first main surface side and having the first conductivity type substrate layer on the second main surface side;
(B) forming a hard mask film on the first main surface of the semiconductor wafer;
(C) patterning the hard mask film;
(D) forming a plurality of trenches in the first main surface of the semiconductor wafer using the patterned hard mask film as a mask;
(E) After the step (d), on the first main surface, a first hard mask film residual region inside each of a large number of chip regions arranged in a lattice pattern, and the chip regions Removing the hard mask film so as to leave the hard mask film as a CMP stop film in a second hard mask film remaining region of each scribe region adjacent to each other;
(F) In a state where the CMP stop film is in each chip region and the scribe region, a second conductivity type opposite to the first conductivity type is formed by buried epitaxial growth on the first main surface of the semiconductor wafer. Depositing a buried epitaxy layer having a conductivity type;
(G) After the step (f), performing a first CMP process on the first main surface of the semiconductor wafer using the CMP stop film as a CMP stopper;
(H) a step of removing the CMP stop film after the step (g);
(I) A step of performing a second CMP process on the first main surface of the semiconductor wafer after the step (h).

  8). In the power MOSFET manufacturing method according to the item 7, the first hard mask film residual region is also provided in a cell region in each chip region.

9. Item 9. The method for manufacturing a power MOSFET according to Item 7 or 8, wherein the step (b) includes the following substeps:
(B1) forming a first insulating film on the first main surface of the semiconductor wafer;
(B2) removing the first insulating film so as to leave the first insulating film as a residual insulating film in the first hard mask film residual region and the second hard mask film residual region;
(B3) After the substep (b2), forming a second insulating film that forms the hard mask film together with the residual insulating film on the first main surface of the semiconductor wafer.

  10. 10. The method for manufacturing a power MOSFET according to any one of Items 7 to 9, wherein the second hard mask film remaining region includes an alignment mark region.

  11. In the method for manufacturing a power MOSFET according to Item 9 or 10, the first insulating film is a silicon nitride insulating film, and the second insulating film is a silicon oxide insulating film.

  12 12. In the method of manufacturing a power MOSFET according to any one of Items 7 to 11, the polishing amount of the second CMP process is smaller than the polishing amount of the first CMP process.

  13. 13. The method for manufacturing a power MOSFET according to any one of Items 8 to 12, wherein the first hard mask film remaining region has a stripe shape in the cell region.

  14 13. The method for manufacturing a power MOSFET according to any one of Items 8 to 12, wherein the first hard mask film residual region has an island shape in the cell region.

  15. 14. In the method of manufacturing a power MOSFET according to item 13, an interval between the stripe-like first hard mask film residual regions is about 10 to 100 micrometers.

  16. 15. In the method for manufacturing a power MOSFET according to item 14, the interval between the island-like first hard mask film remaining regions is about 10 to 100 micrometers.

17. A power MOSFET manufacturing method including the following steps:
(A) having a first conductivity type on-substrate epitaxy layer on the first main surface side and having a second conductivity type substrate layer opposite to the first conductivity type on the second main surface side; Preparing a semiconductor wafer;
(B) forming a hard mask film on the first main surface of the semiconductor wafer;
(C) patterning the hard mask film;
(D) forming a plurality of trenches in the first main surface of the semiconductor wafer using the patterned hard mask film as a mask;
(E) After the step (d), the hard mask film is formed on the hard mask film remaining area of the scribe area adjacent to each of the plurality of chip areas arranged in a lattice pattern on the first main surface. Removing the hard mask film so as to remain as a CMP stop film;
(F) depositing a buried epitaxy layer having the second conductivity type by buried epitaxial growth on the first main surface of the semiconductor wafer in a state where the CMP stop film is in the scribe region;
(G) After the step (f), performing a first CMP process on the first main surface of the semiconductor wafer using the CMP stop film as a CMP stopper;
(H) a step of removing the CMP stop film after the step (g);
(I) A step of performing a second CMP process on the first main surface of the semiconductor wafer after the step (h).

18. Item 18. The method for manufacturing a power MOSFET according to Item 17, wherein the step (b) includes the following substeps:
(B1) forming a first insulating film on the first main surface of the semiconductor wafer;
(B2) removing the first insulating film so as to leave the first insulating film as a residual insulating film in the hard mask film residual region;
(B3) After the substep (b2), forming a second insulating film that forms the hard mask film together with the residual insulating film on the first main surface of the semiconductor wafer.

  19. 19. In the method of manufacturing a power MOSFET according to item 17 or 18, the hard mask film remaining region includes an alignment mark region.

  20. 20. In the method for manufacturing a power MOSFET according to Item 18 or 19, the first insulating film is a silicon nitride insulating film, and the second insulating film is a silicon oxide insulating film.

[Description format, basic terms, usage in this application]
1. In the present application, the description of the embodiment may be divided into a plurality of sections for convenience, if necessary, but these are not independent from each other unless otherwise specified. Each part of a single example, one part is the other part of the details, or part or all of the modifications. Moreover, as a general rule, the same part is not repeated. In addition, each component in the embodiment is not indispensable unless specifically stated otherwise, unless it is theoretically limited to the number, and obviously not in context.

  Further, in the present application, the term “semiconductor device” mainly refers to various transistors (active elements) alone, or a device in which resistors, capacitors, etc. are integrated on a semiconductor chip or the like (for example, a single crystal silicon substrate). (Including a package having one or more of these chips). Here, as a representative of various transistors, a MISFET (Metal Insulator Semiconductor Effect Transistor) typified by a MOSFET (Metal Oxide Field Effect Transistor) can be exemplified. In the present application, a power semiconductor element is targeted, but the “power semiconductor element” mainly means various semiconductor elements that handle power of 5 watts or more, such as a power MOSFET, an IGBT (Insulated Gate Bipolar Transistor), and a power. It refers to a diode, a composite element including at least one of these, and the like.

  Power MOSFETs can be classified into horizontal power MOSFETs (generally called “LDMOSFETs”) and vertical power MOSFETs (generally called “Vertical MOSFETs”). The vertical power MOSFET is further classified into a planar type and a trench type. In the present application, the planar type is mainly described as an example, but the same applies to the trench type as well. Needless to say, it can be applied.

  2. Similarly, in the description of the embodiment and the like, the material, composition, etc. may be referred to as “X consisting of A”, etc., except when clearly stated otherwise and clearly from the context, except for A It does not exclude what makes an element one of the main components. For example, as for the component, it means “X containing A as a main component”. For example, “silicon member” is not limited to pure silicon, but also includes SiGe alloys, other multi-component alloys containing silicon as a main component, and members containing other additives. Needless to say.

  Similarly, “silicon oxide film”, “silicon oxide insulating film” and the like are not only relatively pure undoped silicon oxide but also other silicon oxide as main components. Including membrane. For example, a silicon oxide insulating film doped with impurities such as TEOS-based silicon oxide (TEOS-based silicon oxide), PSG (phosphorus silicon glass), BPSG (borophosphosilicate glass) is also a silicon oxide film. In addition to a thermal oxide film and a CVD oxide film, a coating system film such as SOG (Spin On Glass) or nano-clustering silica (NSC) is also a silicon oxide film or a silicon oxide insulating film. In addition, a low-k insulating film such as FSG (Fluorosilicate Glass), SiOC (Silicon Oxide silicide), carbon-doped silicon oxide (OSD), or OSG (Organosilicate Glass) is similarly used. It is a membrane. Further, a silica-based Low-k insulating film (porous insulating film, including “porous” or “porous”) including a hole in a member similar to these is also a silicon oxide film or silicon oxide. It is a system insulating film.

  In addition to silicon oxide insulating films, silicon nitride insulating films that are commonly used in the semiconductor field include silicon nitride insulating films. Materials belonging to this system include SiN, SiCN, SiNH, SiCNH, and the like. Here, “silicon nitride” includes both SiN and SiNH unless otherwise specified. Similarly, “SiCN” includes both SiCN and SiCNH, unless otherwise specified.

  3. “Wafer” usually refers to a single crystal silicon wafer on which a semiconductor integrated circuit device (same as a semiconductor device and an electronic device) is formed, but an insulating substrate such as an epitaxial wafer, an SOI substrate, an LCD glass substrate and the like. Needless to say, a composite wafer such as a semiconductor layer is also included.

  4). The figure, position, attribute, and the like are preferably illustrated, but it is needless to say that the present invention is not strictly limited to this unless it is clearly indicated otherwise and the context clearly does not. Therefore, for example, “square” includes a substantially square, “orthogonal” includes a case where the two are substantially orthogonal, and “match” includes a case where the two substantially match. The same applies to “parallel” and “right angle”. Therefore, for example, a deviation of about 10 degrees from perfect parallel belongs to parallel.

  In addition, for a certain region, “whole”, “whole”, “whole area”, and the like include cases of “substantially whole”, “substantially general”, “substantially whole area”, and the like. Therefore, for example, 80% or more of a certain area can be referred to as “whole”, “whole”, and “whole area”. The same applies to “all circumferences”, “full lengths”, and the like.

  Further, regarding the shape of a certain object, “rectangular” includes “substantially rectangular”. Therefore, for example, if the area of the portion different from the rectangle is less than about 20% of the whole, it can be said to be a rectangle. In this case, the same applies to “annular” and the like. In this case, when the annular body is divided, a portion obtained by interpolating or extrapolating the divided element portion is a part of the annular body.

  Also, with regard to periodicity, “periodic” includes almost periodic, and for each element, for example, if the deviation of the period is less than about 20%, each element can be said to be “periodic”. . Furthermore, if what is out of this range is, for example, less than about 20% of all the elements to be periodic, it can be said to be “periodic” as a whole.

  Note that the definitions in this section are general, and when there are different definitions in the following individual descriptions, priority is given to the individual descriptions for this part. However, the definition, provisions, etc. of this section are still valid for parts that are not stipulated in the individual description part, unless explicitly denied.

  5. In addition, when a specific number or quantity is mentioned, a numerical value exceeding that specific number will be used unless specifically stated otherwise, unless theoretically limited to that number, or unless otherwise clearly indicated by the context. There may be a numerical value less than the specific numerical value.

  6). In general, a super junction structure is formed by inserting columnar or plate-like column regions of opposite conductivity type into a semiconductor region of a certain conductivity type at approximately equal intervals so that charge balance is maintained. In this application, when referring to the “super junction structure” by the trench fill method, in principle, a plate region of an opposite conductivity type is formed in a semiconductor region of a certain conductivity type (usually a plate shape, although it is bent or refracted). The “column area” of (good) is inserted at approximately equal intervals so that the charge balance is maintained. In the embodiment, a description will be given of a P-type column region formed in parallel at equal intervals on an N-type semiconductor layer (for example, a drift region).

  There are roughly three types of methods for introducing this super junction structure: multi-epitaxial method, trench insulating film embedding method, and trench fill method (buried epitaxial method, trench filling method, autofill method or trench epitaxial method). Embedding method). Among these, the multi-epitaxial method in which epitaxial growth and ion implantation are repeated many times is expensive because the process is complicated due to the high degree of freedom of process and design. The trench insulating film embedding method is such that after oblique ion implantation into the trench, the trench is embedded with a CVD (Chemical Vapor Deposition) insulating film, which is simpler in terms of process, but between the source and drain by the area of the trench. It is disadvantageous in terms of area regarding on-resistance (Ron). In contrast, the trench fill method has a relatively low degree of freedom in process and design due to restrictions on the growth conditions of buried epitaxial growth, but has an advantage that the process is simple.

  With respect to the super junction structure, “orientation” means that the P-type column or N-type column constituting the super junction structure is viewed two-dimensionally corresponding to the main surface of the chip (parallel to the main surface of the chip or wafer). The longitudinal direction).

  Note that the super junction structure is not limited to the power MOSFET, but is almost as it is or necessary change in the drift region (or the corresponding region or main current path) of all power semiconductor devices (for example, power diodes). And can be applied.

  In the present application, not only the epitaxial layer portion that becomes a current path when a power semiconductor device such as a power MOSFET is in an on state, but also a periphery that contributes to maintaining a reverse breakdown voltage when the power semiconductor device is in an off state. The epitaxial layer portion (including the P-type column region and the N-type column region) is referred to as a drift region.

  7). In the present application, when a crystal plane is displayed as, for example, (100), the equivalent crystal plane is included. Similarly, when the crystal orientation is displayed as <100>, <110>, etc., it shall include the equivalent crystal orientation.

  7). In the present application, the “epitaxy layer on the substrate” refers to a layer formed by epitaxial growth on a relatively flat substrate. On the other hand, the “embedded epitaxy layer” refers to embedding a recess by epitaxial growth on a surface with relatively ruggedness that is deeper than the average groove width.

  Further, the “chip area” refers to an area to be a chip when the wafer is separated into individual chips. On the other hand, the “scribe region” refers to a portion that is removed by dicing or the like.

  Further, the “hard mask film” is an etching resistant mask film other than a resist film that is not used as a mask simultaneously with the resist film. The “hard mask film remaining region” refers to a region where the hard mask film remains after the trench forming hard mask film is partially removed after the trench is formed. On the other hand, the “hard mask removal region” is a portion where the hard mask film should be removed when part of the trench forming hard mask film is removed after the trench formation.

[Details of the embodiment]
The embodiment will be further described in detail. In the drawings, the same or similar parts are denoted by the same or similar symbols or reference numerals, and description thereof will not be repeated in principle.

  In the accompanying drawings, hatching or the like may be omitted even in a cross section when it becomes complicated or when the distinction from the gap is clear. In relation to this, when it is clear from the description etc., the contour line of the background may be omitted even if the hole is planarly closed. Furthermore, even if it is not a cross section, it may be hatched to clearly indicate that it is not a void.

  In addition, as a prior patent application disclosing the power MOSFET using the super junction structure or the like, for example, Japanese Unexamined Patent Publication No. 2011-108906, Japanese Unexamined Patent Publication No. 2011-146429, Japanese Unexamined Patent Publication No. 2011-216687, Japanese Special Application No. 2012-13030 (Japan filing date January 25, 2012), Japanese Patent Application No. 2013-384 (Japan filing date January 7, 2013), and the like.

1. Description of manufacturing steps in a method of manufacturing a power MOSFET (cell peripheral SJ termination type) according to an embodiment of the present application, and a wafer, a chip region at the time of device completion, a mutual relationship between internal and external parts (mainly FIGS. 1 to 5) )
In this example, a planar power MOSFET manufactured on a silicon-based semiconductor substrate and having a source-drain breakdown voltage of about 600 volts will be described in detail. (The planar power MOSFET is the same in the following sections. However, it is needless to say that it can also be applied to power MOSFETs and other devices having other breakdown voltage values.

  The chip size described here is mainly about 3 to 10 mm square, but it goes without saying that the size situation is arbitrary. The planar shape of the chip will be mainly described as being square, but it is needless to say that it may be rectangular.

  FIG. 1 shows a manufacturing process in a method for manufacturing a power MOSFET (cell peripheral SJ termination type) according to an embodiment of the present application, a wafer at the time of device completion, a chip region, a mutual relationship between internal and external parts, and the like. FIG. FIG. 2 is an enlarged plan view of the single chip region of FIG. 1 and its periphery (almost at the time of device completion, but the metal source electrode and the like are removed in order to make the super junction structure and the like easier to see). FIG. 3 is an enlarged plan view of the chip corner peripheral cutout region R1 of FIGS. FIG. 4 is a top view of the wafer showing the relationship between the hard mask remaining region and the cell region etc. in the trench formation process in a portion substantially corresponding to FIG. 2 (however, the structure of the alignment mark region etc. is omitted). FIG. 5 is a top view of the wafer showing the state of the alignment mark region omitted in FIG. Based on these, the manufacturing process in the method of manufacturing a power MOSFET (cell peripheral SJ termination type) according to an embodiment of the present application, the wafer at the time of completion of the device, the chip region, the interrelation between the respective parts inside and outside, and the like will be described.

  FIG. 1 shows the layout of the chip region 2 and the like on the device main surface 1a of the wafer 1 (assuming a 200φ wafer and a chip size of about 3 mm square, the actual number of chips is about 100 times this. However, the size of the chip is exaggerated for convenience of illustration). As shown in FIG. 1, the front side main surface 1a (device main surface, source side main surface, i.e., first main surface) of the wafer 1 has a large number of chip regions 2 or regions to be chip regions substantially in a matrix. These are separated from each other by a scribe region 32 (X direction scribe region 32x, Y direction scribe region 32y) orthogonally intersecting the X direction and the Y direction. In this example, the crystal plane of the front main surface 1a of the wafer 1 is, for example, (100), and the crystal orientation in the direction of the notch 9 is, for example, <100> or <110> (of course, as necessary. Other crystal planes and crystal orientations may also be used).

  The overall planar layout of the upper surface of the chip 2 (chip region) (corresponding to the front main surface 1a of the wafer 1) when the device is almost completed is shown in FIG. 2 (for easy viewing, the metal layer in the chip inner region is removed. Show). As shown in FIG. 2, the chip 2 (2a) has a substantially square shape or a rectangular shape (rectangular shape) close to it, a guard ring 10 is provided in the chip peripheral area 20, and an active cell area 4 is provided in the center. (Cell area). Needless to say, this does not exclude the elongated rectangular chip. In the active cell region 4, a polysilicon film (gate electrode) 21 having a multiple connection structure (a sheet shape having a number of identical openings) is provided, and the entire active cell region 4 and a predetermined area of the chip peripheral region 20 are provided. In this area, P-type column areas 6 constituting a super junction structure are spread. Needless to say, the planar structure of the gate electrode may be a single connection if necessary. Here, the scribe region 32 is provided with an alignment mark region 5 in which an alignment mark 8 (8y) is provided. Further, around the cell region 4, a cell region external peripheral super junction formation region 39 is provided. In this example, the cell region 4 and the cell region external peripheral super junction formation region 39 include a super junction. A formation region 36 is formed. Further, in this example, as far as the chip region 2 is concerned, a portion that is not the super junction formation region 36 is a super junction non-formation region 37. In this example, the super junction formation region 36 does not exist outside the chip region 2. In this example, an example in which the alignment mark area 5 is provided inside the scribe area 32, that is, an example in which the alignment mark area 5 is completely removed by dicing or the like is shown. Needless to say, a part of the chip region 2 may be provided.

  The chip corner peripheral cutout region R1 of FIGS. 1 and 2 is shown in FIG. As shown in FIG. 3, a P + type body contact region 27 is provided in the active cell region 4 of the chip region 2a, and a large number of N type silicon epitaxy layers 1e from the active cell region 4 to the chip peripheral region 20 are provided. P-type column region 6 is formed. The P-type column region 6 and the N-type column region 7 (N-type silicon epitaxy layer 1e) between them constitute a super junction structure. The chip area 2a is adjacent to the chip area 2b with the Y-direction scribe area 32y in between and the chip area 2c with the X-direction scribe area 32x in between, and the chip area 2a has an intersection area between the scribe areas 32x and 32y. It is adjacent to the region 2d. In both scribe regions 32x and 32y, an alignment mark region 5 for forming an alignment mark 8 for aligning the super junction structure and the subsequent process layer (for example, 36 micrometers x 32 micrometers) The degree of which can be illustrated). An X-direction alignment mark 8x is provided in the alignment mark area 5 of the X-direction scribe area 32x, and a Y-direction alignment mark 8y is provided in the Y-direction scribe area 32y.

  Next, the single chip region 2a after the removal of the hard mask film portion after the trench formation, which is the main part of the wafer process in the method for manufacturing the power MOSFET according to the embodiment of the present application, and its periphery (chip regions 2b, 2c, FIG. 4 shows an outline of the situation of the upper surface of the wafer 1 in 2d, 2e, 2f, 2g, 2h, 2i and the scribe region 32). As shown in FIG. 4, in this example, the super junction formation region 36 extends over the entire cell region 4 and its periphery. That is, a super junction structure is also provided in the junction termination region. From the definition of each region, a portion other than the super junction formation region 36 is a super junction non-formation region 37. The super junction non-formation region 37 roughly corresponds to the hard mask remaining region 38 as it is (meaning that the peripheral portion of the alignment mark region 5 is excluded). Further, almost the entire scribe region 32 is a hard mask residual region 38b (second hard mask residual region) in the scribe region, and the chip region 2 other than the super junction formation region 36 is a hard mask residual region 38a in the chip region. (First hard mask residual region). Such a layout of the super junction formation region and the hard mask residual region is effective in securing junction termination characteristics.

  Next, FIG. 5 shows an enlarged plan view of the peripheral portion (alignment mark region peripheral cutout region R4 in FIG. 3) of the alignment mark region 5 excluded in FIG. As shown in FIG. 5, the ring-shaped edge portion of the alignment mark region 5 is a hard mask removal region 40, and the entire other alignment mark region 5 and the scribe region 32 outside the alignment mark region 5. The whole (excluding the TEG pattern region and other alignment mark regions) is a hard mask residual region 38b (second hard mask residual region).

2. Explanation of wafer process and the like in the method of manufacturing the power MOSFET according to the embodiment of the present application (mainly FIGS. 6 to 24)
An example of a wafer process corresponding to the device structure described in Section 1 is shown below. However, it goes without saying that the following process is an example, and various changes can be made.

  Since the dimensions, film thicknesses, etc. of the respective parts shown in section 1 and section 2 are basically not different even in section 3 and below, they will not be repeatedly described in principle unless otherwise different.

  FIG. 6 is a wafer cell region (or super junction formation region) and scribe region in the middle of the manufacturing process (alignment mark forming step) for explaining the wafer process and the like in the method of manufacturing a power MOSFET according to the embodiment of the present application. It is sectional drawing (corresponding to XX 'section of Drawing 2) (including an alignment mark field). FIG. 7 shows the cell region (or super junction formation) of the wafer in the middle of the manufacturing process (lower trench hard mask film forming step for trench etching) for explaining the wafer process and the like in the method of manufacturing the power MOSFET according to the embodiment of the present application. 3 is a cross-sectional view (corresponding to the XX ′ cross section in FIG. 2) of the region) and the scribe region (including the alignment mark region). FIG. 8 shows a cell region (or super junction formation region) of a wafer in the middle of a manufacturing process (a lower layer hard mask processing step for trench etching) for explaining a wafer process and the like in the method of manufacturing a power MOSFET according to the embodiment of the present application. ) And a scribe region (including an alignment mark region) (corresponding to the XX ′ cross section in FIG. 2). FIG. 9 shows the cell region (or super junction formation) of the wafer during the manufacturing process (upper layer hard mask film forming step for trench etching) for explaining the wafer process and the like in the method of manufacturing the power MOSFET according to the embodiment of the present application. 3 is a cross-sectional view (corresponding to the XX ′ cross section in FIG. 2) of the region) and the scribe region (including the alignment mark region). FIG. 10 is a cell region (or super junction formation region) of a wafer in the middle of a manufacturing process (upper layer hard mask processing step for trench etching) for explaining a wafer process and the like in the method of manufacturing a power MOSFET according to the embodiment of the present application. ) And a scribe region (including an alignment mark region) (corresponding to the XX ′ cross section in FIG. 2). FIG. 11 shows a wafer cell region (or a super junction formation region) and a scribe region (in the middle of a manufacturing process (trench etching step)) for explaining a wafer process and the like in the method of manufacturing a power MOSFET according to the embodiment of the present application. FIG. 6 is a cross-sectional view (corresponding to the XX ′ cross-section of FIG. 2) of the alignment mark region). FIG. 12 is a plan view of the cell region in the step of FIG. 13 (corresponding to the active cell cutout region R2 of FIG. 2). FIG. 13 is a cell region (or super junction formation region) of a wafer in the middle of the manufacturing process (upper layer hard mask removing step for trench etching) for explaining the wafer process and the like in the method of manufacturing a power MOSFET according to the embodiment of the present application. ) And a scribe region (including an alignment mark region) (corresponding to the XX ′ cross section in FIG. 2). FIG. 14 shows a wafer cell region (or super junction formation region) and a scribe region (in the process of buried epitaxial growth) in the middle of a manufacturing process for explaining a wafer process and the like in the method of manufacturing a power MOSFET according to the embodiment of the present application. FIG. 6 is a cross-sectional view (corresponding to the XX ′ cross-section of FIG. 2) of the alignment mark region). 15 shows a wafer cell region (or super junction formation region) and scribe in the middle of a manufacturing process (first CMP step) for explaining a wafer process and the like in the method of manufacturing a power MOSFET according to the embodiment of the present application. It is sectional drawing (corresponding to XX 'section of Drawing 2) of a field (including an alignment mark field). FIG. 16 is a cell region (or super junction formation region) of a wafer in the middle of a manufacturing process (lower trench hard mask removal step) for explaining a wafer process and the like in the method of manufacturing a power MOSFET according to the embodiment of the present application. ) And a scribe region (including an alignment mark region) (corresponding to the XX ′ cross section in FIG. 2). FIG. 17 is a wafer cell region (or super junction formation region) and scribe in the middle of a manufacturing process (second CMP step) for explaining a wafer process and the like in the method of manufacturing a power MOSFET according to the embodiment of the present application. It is sectional drawing (corresponding to XX 'section of Drawing 2) of a field (including an alignment mark field). 18 is a cross-sectional view taken along line XX ′ of the active cell cutout region R2 in FIG. 2 during the manufacturing process (P-type body region introducing step) for explaining the wafer process and the like in the method of manufacturing the power MOSFET according to the embodiment of the present application. It is device sectional drawing which respond | corresponds substantially to a cross section. FIG. 19 is a cross-sectional view taken along line XX ′ of the active cell cutout region R2 of FIG. 2 during the manufacturing process (polysilicon film forming step) for explaining the wafer process and the like in the method of manufacturing the power MOSFET according to the embodiment of the present application. It is device sectional drawing which respond | corresponds substantially to a cross section. FIG. 20 shows an X of the active cell cutout region R2 in FIG. 2 during the manufacturing process (gate processing and N + type source region introduction step) for explaining the wafer process and the like in the method of manufacturing the power MOSFET according to the embodiment of the present application. FIG. 10 is a device sectional view substantially corresponding to a −X ′ section. 21 shows the active cell cutout region R2 in FIG. 2 during the manufacturing process (contact groove formation and P + type body contact region introducing step) for explaining the wafer process and the like in the method of manufacturing the power MOSFET according to the embodiment of the present application. FIG. 6 is a device cross-sectional view substantially corresponding to a cross section of XX ′. FIG. 22 shows an X of the active cell cutout region R2 in FIG. 2 during the manufacturing process (plug embedding and surface metal film forming step) for explaining the wafer process and the like in the method of manufacturing the power MOSFET according to the embodiment of the present application. FIG. 10 is a device sectional view substantially corresponding to a −X ′ section. FIG. 23 is a cross-sectional view of the active cell cutout region R2 in FIG. 2 during the manufacturing process (final passivation film formation and processing step) for explaining the wafer process and the like in the method of manufacturing the power MOSFET according to the embodiment of the present application. FIG. 10 is a device cross-sectional view substantially corresponding to the X ′ cross-section. FIG. 24 is a cross-sectional view taken along line XX in the active cell cutout region R2 of FIG. 'It is a device sectional view substantially corresponding to the section. Based on these, the wafer process and the like in the method of manufacturing the power MOSFET of the one embodiment of the present application will be described.

First, as shown in FIG. 6, for example, a wafer 1 is prepared in which an N-type silicon epitaxy layer 1e (an epitaxy layer on a substrate) is formed on the surface 1a side of an N + type silicon single crystal substrate portion 1s (substrate layer). . Here, the diameter of the wafer is described as being about 200 millimeters, for example, but the diameter of the wafer may be about 150 millimeters, about 300 millimeters, or others. In addition, the thickness of the wafer is described as being about 700 micrometers, for example, but may be an appropriate thickness (a preferable range is a range of about 300 to 1200 micrometers) as necessary. Regarding the impurity doping of the substrate portion 1 s of the wafer, for example, an N + silicon single crystal substrate doped with antimony on the order of 10 ¹⁸ to 10 ¹⁹ / cm ³ can be exemplified as a preferable example. The thickness of the epitaxy layer on the substrate is, for example, about 50 micrometers when the breakdown voltage is about 600 volts. Next, an alignment mark forming resist film 15 is formed on almost the entire surface of the wafer 1 on the surface 1a side by, for example, coating. Next, the resist film 15 for alignment mark formation is patterned by, for example, ordinary lithography, and the wafer 1 is subjected to anisotropic dry etching using, for example, a halogen-based etching gas as a mask. An alignment mark 8 (for example, a width of about 2 micrometers and a depth of about 5 micrometers) is formed on the surface 1a. Thereafter, the alignment mark forming resist film 15 that has become unnecessary is removed by, for example, ashing. 6 to 17, the cell region 4 is shown on the left side of the drawing. However, in this example, this portion may be used as the super junction formation region 36.

  Next, as shown in FIG. 7, for example, a silicon nitride film (for example, a thickness) is formed as a lower layer hard mask 11 f for trench etching by CVD (Chemical Vapor Deposition) or the like on almost the entire surface on the surface 1 a side of the wafer 1. Is about 500 nm). Note that a silicon oxide film (for example, a thickness of about 100 nm) or the like may be formed as a base film of the silicon nitride film (effective in preventing peeling).

  Next, as shown in FIG. 8, a trench etch lower hard mask processing resist film 31 is formed on almost the entire surface 1a side of the wafer 1 by, for example, coating. Next, for example, by patterning the resist film 31 for processing the lower layer hard mask for trench etching by ordinary lithography or the like, and using it as a mask, anisotropic dry etching is performed using, for example, a fluorocarbon-based etching gas or the like. Thus, the lower layer hard mask 11f for trench etching is patterned. Thereafter, the resist film 31 for processing the lower hard mask for trench etching that has become unnecessary is removed by, for example, ashing.

  Next, as shown in FIG. 9, as an upper hard mask 11s for trench etching, for example, by CVD or the like, for example, a silicon oxide film (for example, the thickness is 1.. (About 0 micrometer) is formed. Thus, in this example, the trench etch hard mask 11 (hard mask film) is constituted by the trench etch lower hard mask 11f and the trench etch upper hard mask 11s.

  Next, as shown in FIG. 10, an upper hard mask processing resist film 33 for trench etching is formed on almost the entire surface on the surface 1a side of the wafer 1 by, for example, coating. Next, the resist film 33 for processing the upper hard mask for trench etching is patterned by, for example, ordinary lithography, and anisotropic dry etching is performed by using, for example, a fluorocarbon-based etching gas as a mask. Thus, the upper layer hard mask 11s for trench etching is patterned. After that, the resist film 33 for processing the upper hard mask for trench etching that has become unnecessary is removed by, for example, ashing.

  Next, as shown in FIG. 11, the surface of the wafer 1 is subjected to anisotropic dry etching using the patterned trench etching hard mask 11 as an etching resistant mask, for example, using a halogen-based etching gas or the like. A trench 12 for embedding a P-type column region (for example, a depth of about 55 micrometers and a width of about 4 micrometers) is formed in 1a. It is desirable that the P-type column region burying trench 12 reaches the N-type silicon single crystal substrate 1s. However, even if they have not reached, they need only be close.

  Next, as shown in FIGS. 12 and 13, the upper layer hard mask 11s for trench etching is removed by, for example, wet etching using a hydrofluoric acid-based etching solution or the like. That is, the hard mask film is removed so as to leave the hard mask film as a CMP stop film in the hard mask film remaining area of the scribe area adjacent to each of a large number of chip areas arranged in a lattice pattern. Thereby, a hard mask removal region 40 is formed in the cell region 4. As shown here, when the entire wafer is viewed, the CMP stop film remains in a lattice pattern, so that variations in the amount of overgloss can be absorbed by subsequent CMP processing. Further, since the hard mask film has a double structure and is formed of films having different properties (mainly a silicon nitride insulating film and a silicon oxide insulating film), there is an advantage that the etching process in the middle is simplified. Furthermore, since the remaining hard mask film covers almost the entire alignment mark region, the integrity of the alignment mark can be maintained even in a process such as buried epitaxial growth.

  Next, as shown in FIG. 14, a buried epitaxial layer 14 is formed by performing buried epitaxial growth on almost the entire surface of the wafer 1 on the surface 1a side. At this time, the overgloss amount can be exemplified as a preferable value of about 5 micrometers, for example.

  Next, as shown in FIG. 15, a first CMP (Chemical Mechanical Polishing) process is performed on the surface 1a side of the wafer 1 using the trench etch hard mask 11 (11f) as a CMP stop film. The amount of polishing at this time is, for example, about 4.5 micrometers.

  Next, as shown in FIG. 16, for example, the trench etching hard mask 11 (11f) is removed by wet etching (or, of course, dry etching) using a silicon nitride film etchant such as hot phosphoric acid. At this point, the step on the upper surface 1a of the wafer is, for example, about 0.5 micrometers.

Next, as shown in FIG. 17, by performing a second CMP process, both the buried epitaxy layer 14 and the on-substrate epitaxy layer 1e are polished to flatten the surface. The amount of polishing at this time is, for example, about 1.5 micrometers. Thus, the polishing amount of the second CMP process is smaller than the polishing amount of the first CMP. This is because in the second CMP process, planarization is achieved with a polishing amount that is about three times the remaining step after the first CMP.
Although the two-stage CMP process is not essential, as described above, by executing the CMP process in two stages, each buried epitaxy layer 14 in the cell region 4 is more than performed in one stage. There is a merit that it becomes easy to make the polishing amount uniform. That is, when the CMP process is performed in only one stage, the polishing amount of the buried epitaxy layer 14 in the cell region 4 particularly in the central portion tends to be larger than that in the peripheral portion in the cell region 4. Therefore, there is a possibility that the characteristics of the MOSFETs vary within the cell region 4.

  As a result, a P-type column region 6 and an N-type column region 7 are formed. Hereinafter, the process will be described using only the cell region 4 (specifically, the active cell cutout region R2 in FIG. 17) as an example.

As shown in FIG. 18, a P-type body region introducing silicon oxide film 18 is formed on almost the entire surface 1a of the wafer 1 by, for example, thermal oxidation. Next, the P-type body region introduction resist film 17 is applied and patterned (for example, by normal lithography), and the patterned resist film 17 is used as a mask to perform P-type body region 16 ( (P-type channel region) is introduced (the ion species is boron, for example, and the concentration is, for example, about 10 ¹⁷ / cm ³ ). Thereafter, the P-type body region introducing resist film 17 that has become unnecessary is removed by, for example, ashing, and the P-type body region introducing silicon oxide film 18 is wet etched using, for example, a hydrofluoric acid-based etching solution. Etc. (or dry etching may be used).

  Next, as shown in FIG. 19, a gate oxide film 19 (for example, about 100 nm thick) is formed on the surface 1a of the semiconductor wafer 1 by thermal oxidation (for example, wet oxidation at 950 degrees Celsius). Further, a gate polysilicon film 21 (for example, a phosphorus-doped polysilicon film having a thickness of about 500 nm) is formed by, for example, low pressure CVD (Chemical Vapor Deposition). As wafer cleaning before gate oxidation, for example, the first cleaning liquid, that is, ammonia: hydrogen peroxide: pure water = 1: 1: 5 (volume ratio), and the second cleaning liquid, that is, hydrochloric acid: hydrogen peroxide: Wet cleaning can be applied using pure water = 1: 1: 6 (volume ratio).

Next, as shown in FIG. 20, the gate electrode processing resist film 22 is used for dry etching (for example, polysilicon is SF ₆ , O ₂ etching gas, and the oxide film is CHF ₃ , CF ₄ etching, for example. The gate electrode 21 is patterned by executing (gas) (for example, by ordinary lithography). Subsequently, the N + source region 23 and the like are introduced (the ionic species is, for example, arsenic and the concentration is, for example, on the order of 10 ²⁰ / cm ³ ). Thereafter, the resist film 22 that is no longer needed is entirely removed.

Next, as shown in FIG. 21, a PSG (Phospho-Silicate-Glass) film 24 (interlayer insulating film) having a thickness of about 900 nm is formed on almost the entire surface 1a of the semiconductor wafer 1 by CVD or the like. (An SOG film may be overlaid and planarized). Subsequently, a source contact groove opening resist film 25 is formed on the surface 1a of the semiconductor wafer 1 (for example, by ordinary lithography), and anisotropic dry etching is performed using the resist film 25 as a mask, thereby forming the source contact groove. The source contact trench 26 is extended into the substrate by opening the layer 26 and anisotropically etching the surface of the silicon substrate, for example. Of course, such etching of the substrate is not essential. Thereafter, a P + body contact region 27 is introduced into the bottom of the source contact trench 26 (contact hole) by ion implantation (for example, BF ₂ ) (concentration is, for example, about 10 ¹⁹ / cm ³ ). Thereafter, the resist film 25 that is no longer needed is entirely removed.

  Next, as shown in FIG. 22, a tungsten plug 28 is embedded in the source contact groove 26 through, for example, a titanium-based barrier metal film. Subsequently, for example, an aluminum-based metal layer is formed by sputtering or the like and patterned (for example, by ordinary lithography) to form the metal source electrode 29, the guard ring electrode 10 (FIG. 2), and the like. Although an example in which the tungsten plug 28 is used is shown here, it goes without saying that the aluminum-based metal layer may be directly formed by sputtering through a barrier metal or the like.

  Next, as shown in FIG. 23, for example, a final passivation film 34 such as an inorganic final passivation film or an organic inorganic final passivation film is formed as an upper layer, and a source pad opening 43 or the like is opened (for example, normally By lithography.) As the final passivation film 34, in addition to a single layer film such as an inorganic final passivation film or an organic inorganic final passivation film, an organic inorganic final passivation film or the like may be laminated on a lower inorganic final passivation film. good.

  Next, as shown in FIG. 24, for example, backgrinding is performed on the back surface 1b of the wafer 1, and the initial thickness of the wafer (the thickness of only the substrate portion, for example, about 700 micrometers). ) Is reduced to about 200 to 20 micrometers if necessary. Next, the back metal electrode 30 is formed on the back surface 1b (the surface of the drain region 35) of the wafer 1 by sputtering film formation or the like.

  Thereafter, the wafer 1 is divided into chip regions 2 by, for example, blade dicing or the like (laser dicing, laser grooving, or a combination of these and blade dicing may be used). As a result, the scribe region 32 is removed, and the wafer 1 becomes a large number of chips 2.

3. Description of various modifications relating to the device structure in the method of manufacturing the power MOSFET according to the embodiment of the present application, particularly the formation range of the super junction structure (mainly FIGS. 25 to 28)
In this section, various modified examples of the range of the super junction formation region 36 and the hard mask remaining region 38 related to the entire chip peripheral cutout region R3 in FIG. Since the basic structure and process are the same as those described in Sections 1 and 2 (basic example: standard cell region peripheral superjunction termination method), only different parts will be described below in principle.

  FIG. 25 is a diagram illustrating a device structure in the method of manufacturing a power MOSFET according to the embodiment of the present invention, in particular, a modification example regarding the formation range of the super junction structure (super-junction forming method limited in the cell region). It is a top view of the wafer corresponding to the chip peripheral whole cutout region R3. FIG. 26 illustrates a device structure in the method of manufacturing a power MOSFET according to the embodiment of the present invention, in particular, a modification example regarding the formation range of the superjunction structure (superjunction formation region-hard mask residual region buffered layout). FIG. 5 is a top view of the wafer corresponding to the entire chip cutting area R3 in FIG. FIG. 27 shows a device structure in the method of manufacturing a power MOSFET according to the embodiment of the present invention, in particular, a modified example relating to the formation range of the superjunction structure (a superjunction forming method limited to the entire chip region). It is a top view of the wafer corresponding to the chip peripheral whole cutout region R3. FIG. 28 is a view for explaining a device structure in the method for manufacturing a power MOSFET according to the embodiment of the present invention, in particular, a modification example regarding the formation range of the super junction structure (chip region entire surface and external peripheral limited super junction formation method). FIG. 5 is a top view of a wafer corresponding to the entire chip periphery cutout region R3 of FIG. 4. Based on these, various modifications relating to the device structure in the method of manufacturing the power MOSFET according to the embodiment of the present application, in particular, the formation range of the super junction structure, and the like will be described.

(1) Description of the super junction formation method within the cell region (mainly FIG. 25):
In this example, as shown in FIG. 25, unlike the standard cell region peripheral super-junction termination method (FIG. 4), the super junction formation region 36 is not provided outside the cell region 4 in principle. The outside is a hard mask residual region 38 in almost the whole area except for an exceptional part. Such a layout is effective when the junction termination structure is constructed mainly by a field plate or the like.

(2) Description of the buffer type layout between the super junction formation region and the hard mask residual region (mainly FIG. 26):
In this example, as shown in FIG. 26, the superjunction forming region 36 (that is, the cell region external peripheral superjunction) is also provided outside the cell region 4 as in the standard cell region peripheral superjunction termination method (FIG. 4). A formation region 39) is provided. However, unlike the standard cell region peripheral superjunction termination method (FIG. 4), the buffer region 42, that is, the superjunction non-formation region 37, is formed between the superjunction formation region 36 and the hard mask residual region 38. A portion that is not the residual region 38 is provided.

  As described above, by providing the buffer region 42, that is, the super junction non-formation region 37 but the hard mask residual region 38 between the super junction formation region 36 and the hard mask residual region 38, the hard mask is provided. The influence of crystal defects generated in the remaining region 38 can be prevented from reaching the super junction forming region 36 in the vicinity.

  The provision of such a buffer region 42 can be applied not only in the case of FIG. 4 (the layout after specific application is FIG. 26) but also in the case of FIG. 25, FIG. 27, FIG. .

(3) Description of the chip region entire surface limited super junction formation method (mainly FIG. 27):
In this example, as shown in FIG. 27, the superjunction forming region 36 (that is, the cell region external peripheral superjunction) is also provided outside the cell region 4 as in the standard cell region peripheral superjunction termination method (FIG. 4). A formation region 39) is provided. However, unlike the standard cell region peripheral super junction termination method (FIG. 4), the cell region external peripheral super junction formation region 39 extends over almost the entire chip region 2. Therefore, in this example, the hard mask remaining area 38 coincides with the scribe area 32 except for an exceptional part. Such a layout is effective when it is desired to make the embedding characteristics uniform in the chip region.

(4) Description of the superjunction forming method for the entire chip area and external peripheral area (mainly FIG. 28):
In this example, as shown in FIG. 28, it is similar to the example of FIG. 27 (chip region whole surface limited super junction formation method), but unlike that, the super junction formation region 36 is also located outside the chip region 2. Some are spreading. Therefore, in this example, the hard mask remaining region 38 is substantially the entire portion of the scribe region 32 that is not the super junction formation region 36. Such a layout is effective when it is desired to make the embedding characteristics uniform even at the end of the chip region. Here, “substantially” means excluding exceptional parts (the same applies to other parts).

  As a modification, there is a case where the super junction formation region 36 covers almost the entire region of the wafer 1 (wafer full surface super junction formation method). The handling of such an example will be described in section 7.

  Further, the various modifications described in this section and the wafer whole surface superjunction formation method described in section 7 are not only applicable to the examples described in sections 1 and 2, but also examples described in other sections (for example, Needless to say, the present invention can also be applied to the example described in Section 4).

4). Explanation of wafer process and the like related to modification 1 (stripe hard mask thinning method) related to the hard mask layout in the cell region in the method of manufacturing the power MOSFET according to the embodiment of the present application (mainly FIGS. 29 to 37)
In all of the examples described so far, in principle, the hard mask remaining region 38 is not disposed in the super junction formation region 36. However, in this section, the super junction formation region 36 is also partially included. (In the sense that it does not remain), a hard mask residual area 38 is provided.

  In this example, most of the basic parts are the same as those described so far, so only the different parts will be described in principle below. This is the same in the next section.

  FIG. 29 is a device cross-sectional view corresponding to FIG. 8 for explaining the wafer process and the like related to Modification Example 1 (Stripe Hard Mask Thinning Method) related to the hard mask layout in the cell region in the method of manufacturing the power MOSFET according to the embodiment of the present application. FIG. FIG. 30 is a device cross-sectional view corresponding to FIG. 8 for explaining the wafer process and the like related to Modification Example 1 (Stripe Hard Mask Thinning Method) related to the hard mask layout in the cell region in the method of manufacturing the power MOSFET according to the embodiment of the present application. It is a figure (lower trench hard mask process for trench etching). FIG. 31 is a device substantially corresponding to FIG. 10 for explaining the wafer process and the like related to Modification Example 1 (Stripe Hard Mask Thinning Method) related to the hard mask layout in the cell region in the method of manufacturing the power MOSFET according to the embodiment of the present application. It is sectional drawing (the upper layer hard mask process for trench etching). FIG. 32 is a diagram corresponding to FIG. 33 for explaining the wafer process and the like related to the modification 1 (stripe hard mask thinning method) related to the hard mask layout in the cell region in the method of manufacturing the power MOSFET according to the embodiment of the present application. FIG. 6 is a plan view of a cell region in the step (corresponding to an active cell cutout region R2 in FIG. 2). FIG. 33 is a device cross-sectional view corresponding to FIG. 13 for explaining the wafer process and the like related to Modification Example 1 (Stripe Hard Mask Thinning Method) related to the hard mask layout in the cell region in the method of manufacturing the power MOSFET according to the embodiment of the present application. It is a figure (upper layer hard mask removal process for trench etching). FIG. 34 is a device cross-sectional view corresponding to FIG. 14 for explaining the wafer process and the like related to Modification Example 1 (Stripe Hard Mask Thinning Method) related to the hard mask layout in the cell region in the method for manufacturing the power MOSFET according to the embodiment of the present application. It is a figure (buried epitaxial growth process). FIG. 35 is a device cross-sectional view corresponding to FIG. 15 for explaining the wafer process and the like related to Modification Example 1 (Stripe Hard Mask Thinning Method) related to the hard mask layout in the cell region in the method of manufacturing the power MOSFET according to the embodiment of the present application. It is a figure (1st CMP process). FIG. 36 is a device cross-sectional view corresponding to FIG. 16 for explaining a wafer process and the like related to Modification Example 1 (Stripe Hard Mask Thinning Method) related to the hard mask layout in the cell region in the method of manufacturing the power MOSFET according to the embodiment of the present application. It is a figure (lower layer hard mask removal process for trench etching). FIG. 37 is a device cross-sectional view corresponding to FIG. 17 for explaining a wafer process and the like related to Modification Example 1 (Stripe Hard Mask Thinning Method) related to the hard mask layout in the cell region in the method of manufacturing the power MOSFET according to the embodiment of the present application. It is a figure (2nd CMP process). Based on these, a wafer process and the like related to Modification Example 1 (Stripe Hard Mask Thinning Method) related to the hard mask layout in the cell region in the method of manufacturing the power MOSFET according to the embodiment of the present application will be described.

  In the section 2, after the processing described with reference to FIGS. 6 and 7, as shown in FIG. 29, the resist film for processing the lower layer hard mask for trench etching, for example, by coating or the like on almost the entire surface on the surface 1a side of the wafer 1. 31 is deposited. Next, for example, by patterning the resist film 31 for processing the lower layer hard mask for trench etching by ordinary lithography or the like, and using it as a mask, anisotropic dry etching is performed using, for example, a fluorocarbon-based etching gas or the like. Thus, the lower layer hard mask 11f for trench etching is patterned. Thereafter, the resist film 31 for processing the lower hard mask for trench etching that has become unnecessary is removed by, for example, ashing.

  Next, as shown in FIG. 30, for example, a silicon oxide film is formed as an upper hard mask 11 s for trench etching, for example, by CVD or the like on almost the entire surface 1 a side of the wafer 1. Thus, in this example, the trench etch hard mask 11 (hard mask film) is constituted by the trench etch lower hard mask 11f and the trench etch upper hard mask 11s. Next, an upper hard mask processing resist film 33 for trench etching is formed on almost the entire surface on the surface 1a side of the wafer 1 by, for example, coating. Next, the upper resist layer 33 for trench etching is patterned by, for example, ordinary lithography.

  Next, as shown in FIG. 31, by performing anisotropic dry etching using a patterned trench etching upper hard mask processing resist film 33 as a mask, for example, using a fluorocarbon-based etching gas, trenches are formed. The upper hard mask 11s for etching is patterned. After that, the resist film 33 for processing the upper hard mask for trench etching that has become unnecessary is removed by, for example, ashing. Next, anisotropic dry etching is performed using the patterned trench etch hard mask 11 as an etching-resistant mask, for example, using a halogen-based etching gas or the like, so that a P-type column region is formed on the surface 1a of the wafer 1. A buried trench 12 is formed.

  Next, as shown in FIGS. 32 and 33, the upper hard mask 11s for trench etching is removed, for example, by wet etching using a hydrofluoric acid-based etching solution or the like. As a result, the hard mask removal region 40 and the hard mask residual region 38 a (first hard mask residual region) in the chip region 2 are also formed in the cell region 4. Here, as the stripe thinning-out interval Ls, for example, about 15 micrometers (the range is about 10 to 100 micrometers) can be exemplified as a preferable one. Here, an example in which the hard mask residual regions 38a are arranged every other region between the trenches 12 is shown, but the hard mask residual regions 38a may be arranged every other plurality.

  As described above, the interval between the first hard mask film residual regions in the stripe shape is about 10 micrometers to 100 micrometers, which is sufficiently shorter than the dimensions of the cell area or the like (super junction formation area). This is effective for ensuring flatness in a region or the like (super junction formation region).

  As shown here, when the entire wafer is viewed, the CMP stop film remains in a lattice shape (cell regions and the like are stripes). Absorption can be achieved by CMP treatment. Further, since the hard mask film has a double structure and is formed of films having different properties (mainly a silicon nitride insulating film and a silicon oxide insulating film), there is an advantage that the etching process in the middle is simplified. Furthermore, since the remaining hard mask film covers almost the entire alignment mark region, the integrity of the alignment mark can be maintained even in a process such as buried epitaxial growth.

  Next, as shown in FIG. 34, the buried epitaxial layer 14 is formed by performing buried epitaxial growth on almost the entire surface on the surface 1 a side of the wafer 1. At this time, the overgloss amount can be exemplified as a preferable value of about 5 micrometers, for example.

  Next, as shown in FIG. 35, a first CMP (Chemical Mechanical Polishing) process is performed on the surface 1a side of the wafer 1 using the trench etch hard mask 11 (11f) as a CMP stop film. The amount of polishing at this time is, for example, about 4.5 micrometers.

  Next, as shown in FIG. 36, the trench etching hard mask 11 (11f) is removed by, for example, wet etching (or, of course, dry etching) using a silicon nitride film etchant such as hot phosphoric acid. At this point, the step on the upper surface 1a of the wafer has a value of about 0.5 micrometers or less, for example. This is because there is a CMP stop film also in the cell region and the like, and the macro region is uniformly present in the portion (corresponding to being distributed almost periodically).

  Next, as shown in FIG. 37, by performing a second CMP process, both the buried epitaxy layer 14 and the on-substrate epitaxy layer 1e are polished to flatten the surface. As a result, a P-type column region 6 and an N-type column region 7 are formed. There is a high possibility that the polishing amount at this time is sufficient, for example, about 1.5 micrometers or less. Thus, the polishing amount of the second CMP process is smaller than the polishing amount of the first CMP. This is because in the second CMP process, planarization is achieved with a polishing amount that is about three times the remaining step after the first CMP.

  Hereinafter, the process will be described using only the cell region 4 (active cell cutout region R2 in FIG. 37) as an example.

  The subsequent processing is the same as that described with reference to FIGS. 18 to 24 in section 2.

5. Description of Modification Example 2 (Island Hard Mask Spreading Method) and Modification Example 3 (Island Hard Mask Thinning Method) related to the hard mask layout in the cell region in the method of manufacturing the power MOSFET according to the embodiment of the present application (mainly FIG. 38 and FIG. (Fig. 39)
The striped hard mask thinning method described in section 4 (for example, FIG. 32) and the modifications described below will be described in the basic examples described in sections 1 and 2, and sections 3, 6, 7, etc. Needless to say, the present invention can be applied to each modification.

  In this example, since most of the basic parts are the same as those described so far (for example, the part described in section 4), only different parts will be described below in principle.

  FIG. 38 is a cell region in a trench etch process corresponding to FIG. 12 for explaining a modification 2 (island hard mask laying method) in the cell region hard mask layout in the method of manufacturing the power MOSFET according to the embodiment of the present application. FIG. 6 is a plan view (corresponding to the active cell cutout region R2 in FIG. 2). FIG. 39 is a cell region in a trench etch process corresponding to FIG. 12 for explaining a third modification (island hard mask thinning method) related to the hard mask layout in the cell region in the method for manufacturing the power MOSFET of the one embodiment of the present application. FIG. 6 is a plan view (corresponding to the active cell cutout region R2 in FIG. 2). Based on these, the second modification (island hard mask laying method) and the third modification (island hard mask thinning method) relating to the hard mask layout in the cell region in the method of manufacturing the power MOSFET according to the one embodiment of the present application will be described. .

(1) Description of the island hard mask spread method (mainly FIG. 38):
In the example of FIG. 32, with respect to the stripe-shaped region, the portion where the hard mask residual region 38a (first hard mask residual region) of the chip region is provided is thinned out. On the other hand, in this example, as shown in FIG. 38, the hard mask residual region 38a of the chip region in each stripe-shaped region in the vertical direction, for example, for every predetermined section. The portion where the (first hard mask residual region) is provided is thinned out. Here, the island thinning-out interval Lb can be exemplified by a preferable value of, for example, about 15 micrometers (the range is about 10 to 100 micrometers). As described above, the distance between the island-shaped first hard mask film remaining regions is about 10 to 100 μm, which is sufficiently shorter than the size of the cell region or the like (super junction formation region). Etc. (superjunction forming region) is effective in ensuring flatness.

  Further, the island length Li can be exemplified as a preferable value of, for example, about 200 micrometers (the range is about 100 to 500 micrometers).

(2) Description of the island hard mask thinning method (mainly FIG. 39):
In this example, as shown in FIG. 39, the example of FIG. 32 and the example of FIG. 38 are combined. That is, for each chip, a portion of the chip area where the hard mask residual area 38a (first hard mask residual area) is provided is thinned out, and at the same time, each stripe-shaped area is vertically fixed, for example, in a constant direction. In each of the sections, a portion where the hard mask residual region 38a (first hard mask residual region) of the chip region is provided is thinned out.

  Here, as the stripe thinning-out interval Ls, for example, about 15 micrometers (the range is about 10 to 100 micrometers) can be exemplified as a preferable one. As described above, the interval between the first hard mask film residual regions in the stripe shape is about 10 micrometers to 100 micrometers, which is sufficiently shorter than the dimensions of the cell area or the like (super junction formation area). This is effective for ensuring flatness in a region or the like (super junction formation region). Here, an example in which the hard mask residual regions 38a are arranged every other region between the trenches 12 is shown, but the hard mask residual regions 38a may be arranged every other plurality.

  Furthermore, the island thinning-out interval Lb can be exemplified by a preferable value of, for example, about 15 micrometers (the range is about 10 to 100 micrometers). As described above, the distance between the island-shaped first hard mask film remaining regions is about 10 to 100 μm, which is sufficiently shorter than the size of the cell region or the like (super junction formation region). Etc. (superjunction forming region) is effective in ensuring flatness.

  Further, the island length Li can be exemplified as a preferable value of, for example, about 200 micrometers (the range is about 100 to 500 micrometers).

6). Description of Modified Example (LDMOSFET) Regarding Device Structure in Power MOSFET Manufacturing Method of One Embodiment of the Present Application (Mainly FIG. 40)
Up to this point, the application to the vertical power MOSFET has been mainly described, but in this section, an application example to the horizontal power MOSFET will be described.

  FIG. 40 is a perspective view of the main part of the device for explaining a modification (LDMOSFET) relating to the device structure in the method of manufacturing a power MOSFET according to the embodiment of the present application. Based on this, a modified example (LDMOSFET) related to the device structure in the method of manufacturing a power MOSFET according to the embodiment of the present application will be described. Since an LDMOSFET is usually formed on a P-type substrate, it is suitable for integration on the same chip as a CMOS integrated circuit.

  First, an outline of the device structure will be described. As shown in FIG. 40, the chip 2 on which the LDMOSFET is formed (the chip area of the wafer 1 before the division) is formed on, for example, a P-type silicon single crystal substrate portion 1p (substrate layer). An N-type silicon epitaxy layer 1e (epitaxy layer on the substrate) is formed on the surface 1a side of the P-type silicon single crystal substrate portion 1p, and the gate insulating film 19 is formed on the surface via a gate insulating film 19, for example. A silicon film 21 (gate electrode) is provided. A P-type body region 16 (P-type channel region) is provided under the gate electrode 21 and on the N-type silicon epitaxy layer 1 e on one side thereof, and the surface region thereof is along the gate electrode 21. N + type source region 23 is provided. The P type body region 16 and the N + type source region 23 form, for example, a so-called double diffusion structure. Further, a P + type body contact region 27 is provided on the surface of the P type body region 16 so as to be in contact with the N + type source region 23.

  On the other hand, columnar N-type buffer regions 41a, 41b, 41c, 41d, 41e are provided below the N-type silicon epitaxy layer 1e on the other side of the gate electrode 21, and N on the N-type buffer region 41e. An N + type drain region 35 is provided on the surface of the type silicon epitaxy layer 1e. On the surface of the N-type silicon epitaxy layer 1 e between the N + -type drain region 35 and the P-type body region 16, a super junction structure composed of a columnar P-type column region 6 and an N-type column region 7 is provided. This region is a super junction formation region 36.

  An example of the device manufacturing process will be briefly described as follows. That is, first, a P-type single crystal silicon wafer 1p is prepared. Next, an N-type substrate epitaxy layer 1e is formed partly on almost the entire surface of the P-type single crystal silicon wafer 1p, and each N-type buffer region 41a, 41b, 41c, The impurity concentrations of 41d and 41e are adjusted. Thereafter, the epitaxial layer 1e on the N-type substrate is formed to the top. Next, for example, as shown in FIG. 11 and the like, a P-type column region embedding trench 12 is formed, and the P-type column region 6 is embedded therein, for example, as in FIGS. Next, in the same manner as in FIG. 20, the gate electrode 21 is processed, and using this as a mask, the P-type body region 16 and the N + type source region 23 are introduced by the double diffusion method. For example, the N + type drain region 35 is introduced simultaneously with the N + type source region 23, for example. Further, the P + type body contact region 27 is introduced before or after the introduction thereof.

  Here, the embedding of the P-type column region 6 has been specifically described mainly with the method described in sections 1 and 2, but it goes without saying that the method described in other portions may be used.

7). Supplementary explanation about the above-described embodiment (including modifications) and general consideration (mainly FIGS. 41 and 42)
FIG. 41 is a process block flow diagram for explaining the outline of the method of manufacturing the power MOSFET according to the embodiment of the present application. FIG. 42 is a top view of the wafer corresponding to the entire chip peripheral cutout region R3 of FIG. 4 for supplementary explanation regarding the wafer whole surface super junction forming method. Based on these, a supplementary explanation regarding the above-described embodiment (including modifications) and a general consideration will be given.

(1) Technical issues in superjunction structure formation technology by buried epitaxial growth:
The superjunction structure forming method by the buried epitaxial growth method is generally roughly divided into a full mask remaining method and a full mask removal method. A CMP stop film is useful in order to absorb the film thickness variation of the buried epitaxial growth by polishing. On the other hand, the CMP stop film causes crystal defects during buried epitaxial growth.

  According to a study by the present inventors regarding the entire surface mask remaining method, when the overgrowth amount of the buried epitaxy layer increases, the surface expansion due to the difference in thermal expansion coefficient between the hard mask film (CMP stop film) and silicon occurs. Crystal defects occur in the vicinity. It has also been clarified that the depth of this defect increases in proportion to the amount of overgloss. In addition, since the crystal defects cause deterioration of the breakdown voltage between the source and the drain with respect to device characteristics, it is necessary to polish the silicon surface (not only the buried epitaxy layer) to be removed. Polishing with a thickness exceeding the level necessary for conversion is required.

  On the other hand, according to a study by the inventors of the present invention regarding the entire surface mask removal method, since there is no hard mask film (CMP stop film) during buried epitaxial growth, crystal defects do not occur, but film thickness variation in buried epitaxial growth occurs. It is difficult to absorb this by polishing.

(2) Description of outline of manufacturing method of power MOSFET of one embodiment of the present application (mainly FIG. 41):
Therefore, the outline of the method of manufacturing the power MOSFET according to the embodiment of the present application is as follows. That is, by leaving the trench forming hard mask film in the scribe region or the like, while avoiding the generation of crystal defects in the cell region or the like, the buried epitaxial growth is performed by the first CMP process using the remaining hard mask film as the CMP stop film. In the second CMP process after the remaining hard mask film is removed, final planarization and defect removal can be performed.

  Specifically, as shown in FIG. 41, a wafer 1 having the same conductivity type substrate epitaxy layer (for example, see FIG. 6) is prepared (same conductivity type epitaxy substrate preparation step 101). Next, a trench etching hard mask 11 (for example, see FIG. 9) is formed on the first main surface 1a of the wafer 1 (for example, see FIG. 6) (hard mask film forming step 102). Next, the hard mask 11 (see, for example, FIG. 10) is patterned (hard mask film processing step 103). Next, a trench 12 (see, for example, FIG. 11) is formed using the patterned hard mask 11 (trench formation step 104). Next, the hard mask 11 is partially removed so as to leave the hard mask 11 in the hard mask remaining region 38 (for example, see FIG. 4) of the scribe region 32 (for example, see FIG. 13) (hard mask film partial removal). Step 105). Next, buried epitaxial growth is performed to form a buried epitaxy layer 14 (for example, see FIG. 14) in the trench 12 or the like (buried epitaxial growth step 106). Next, using the remaining hard mask 11 as a CMP stop film (see, for example, FIG. 15), a first CMP process is performed on the first main surface 1a side of the wafer 1 (first CMP step 107). ). Next, the remaining hard mask 11 (for example, see FIG. 16) is removed (CMP stop film removal step 108). Next, a second CMP process (for example, see FIG. 17) is performed on the first main surface 1a side of the wafer 1 (second CMP step 109). In FIG. 41, between the blocks connected by a broken line, the mutual context is arbitrary except when logically or technically defined.

(3) Description of other outlines and the like of the method of manufacturing the power MOSFET according to the embodiment of the present application (mainly refer to FIG. 4):
The examples described in Section 1 and Section 2 can also be described as follows. That is, as shown in FIG. 4, the super junction formation region 36 is a part of the chip region 2, and the entire super junction non-formation region 37 including a part of the chip region 2 and the entire scribe region 32 is hard masked. This is a residual region 38.

(4) Description of outline of each example of sections 4 and 5 (refer mainly to FIG. 32, FIG. 38 and FIG. 39):
Similar to subsection (3), a comprehensive outline of each example of sections 4 and 5 will be described. That is, in the super junction formation region 36, the region where the hard mask is formed is divided into the hard mask remaining region 38 and the hard mask removal region 40 according to a substantially constant periodic structure.

(5) Supplementary explanation on the method of forming the entire wafer super junction (mainly FIG. 42):
As described in the subsection (4) of section 3 with respect to FIG. 28 (superjunction formation method for the entire chip area and external peripheral limited superjunction), the superjunction formation area 36 can be extended to the outside of the chip area 2. Is expanded to the limit, it is also possible to make the super junction forming region 36 almost the entire wafer. FIG. 42 corresponds to this example (wafer whole surface super junction forming method). In this case, since the super junction non-formation region 37 does not substantially exist, the examples described in the sections 4 and 5 and their modifications can be applied. Such a layout is effective when it is desired that the embedding characteristics and the like are uniform over the entire wafer, thereby ensuring uniformity at the end of the chip.

8). Summary The invention made by the present inventor has been specifically described based on the embodiments. However, the present invention is not limited thereto, and it goes without saying that various changes can be made without departing from the scope of the invention.

  For example, in the above-described embodiment, the planar type MOS structure has been specifically described as an example. However, the present invention is not limited thereto, and it goes without saying that the present invention can be applied to a trench type gate structure. . In addition, the layout of the gate of the MOSFET is shown as an example in which the gates are arranged in stripes parallel to the pn column. However, the gates can be arranged in a direction orthogonal to the pn column, arranged in a lattice, or various applications.

  In the above embodiment, the N channel device is mainly formed on the upper surface of the N epitaxial layer on the N + silicon single crystal substrate. However, the present invention is not limited to this, and P + silicon is used. A P channel device may be formed on the upper surface of the P epitaxial layer on the single crystal substrate.

  In the above-described embodiment, the power MOSFET has been specifically described as an example. However, the present invention is not limited thereto, and it goes without saying that the present invention can also be applied to a power device having a super junction structure, that is, a diode or the like. . Needless to say, the present invention can also be applied to a semiconductor integrated circuit device incorporating these power MOSFETs and diodes.

1 Wafer (semiconductor substrate)
1a Front side main surface of wafer (device main surface, that is, first main surface)
1b Wafer backside main surface 1e N type silicon epitaxy layer (epitaxy layer on substrate)
1p P-type silicon single crystal substrate (substrate layer)
1s N + type silicon single crystal substrate (substrate layer)
2, 2a, 2b, 2c, 2d, 2e, 2f, 2g, 2h, 2i Chip region 4 Cell region 5 Alignment mark region 6 P-type column region 7 N-type column region 8 Alignment mark 8x X-direction alignment mark 8y Y-direction alignment Mark 9 Notch 10 Guard ring 11 Trench etch hard mask 11f Trench etch lower hard mask 11s Trench etch upper hard mask 12 P-type column region buried trench 14 Buried epitaxy layer 15 Alignment mark forming resist film 16 P-type body region (P-type channel region)
17 P-type body region introducing resist film 18 P-type body region introducing silicon oxide film 19 Gate insulating film 20 Chip peripheral region 21 Polysilicon film (gate electrode)
22 Gate electrode processing resist film 23 N + type source region 24 Interlayer insulating film 25 Contact groove forming resist film 26 Contact groove (contact hole)
27 P + type body contact region 28 Tungsten plug 29 Metal source electrode 30 Back surface metal electrode 31 Resist film for trench etching lower layer hard mask processing 32 Scribe region 32x X direction scribe region 32y Y direction scribe region 33 For trench etch upper layer hard mask processing Resist film 34 Final passivation film 35 N + type drain region 36 Super junction formation region 37 Super junction non-formation region 38 Hard mask residual region 38a Hard mask residual region of chip region (first hard mask residual region)
38b Hard mask residual region in scribe region (second hard mask residual region)
39 Cell region external peripheral super junction formation region 40 Hard mask removal region 41a, 41b, 41c, 41d, 41e N-type buffer region 42 Buffer region 43 Source pad opening 101 Same conductivity type epitaxy substrate preparation step 102 Hard mask film formation step 103 Hard mask film processing step 104 Trench formation step 105 Hard mask film partial removal step 106 Embedded epitaxial growth step 107 First CMP step 108 CMP stop film removal step 109 Second CMP step Lb Island thinning interval Li island length Ls Stripe thinning interval R1 Chip corner peripheral cutout region R2 Active cell cutout region R3 Chip peripheral full cutout region R4 Alignment mark region peripheral cutout region R5 Alignment mark Area corner cutout area

Claims (20)

A power MOSFET manufacturing method including the following steps:
(A) preparing a semiconductor wafer having an on-substrate epitaxial layer on the first main surface side and having the first conductivity type substrate layer on the second main surface side;
(B) forming a hard mask film on the first main surface of the semiconductor wafer;
(C) patterning the hard mask film;
(D) forming a plurality of trenches in the first main surface of the semiconductor wafer using the patterned hard mask film as a mask;
(E) After the step (d), the hard mask film is formed on the hard mask film remaining area of the scribe area adjacent to each of a large number of chip areas arranged in a lattice pattern on the first main surface. Removing the hard mask film so as to remain as a CMP stop film;
(F) With the CMP stop film in the scribe region, the first main surface of the semiconductor wafer has a second conductivity type opposite to the first conductivity type by buried epitaxial growth. Depositing a buried epitaxy layer;
(G) After the step (f), performing a first CMP process on the first main surface of the semiconductor wafer using the CMP stop film as a CMP stopper;
(H) a step of removing the CMP stop film after the step (g);
(I) A step of performing a second CMP process on the first main surface of the semiconductor wafer after the step (h). 2. The method of manufacturing a power MOSFET according to claim 1, wherein the step (b) includes the following sub-steps:
(B1) forming a first insulating film on the first main surface of the semiconductor wafer;
(B2) removing the first insulating film so as to leave the first insulating film as a residual insulating film in the hard mask film residual region;
(B3) After the substep (b2), forming a second insulating film that forms the hard mask film together with the residual insulating film on the first main surface of the semiconductor wafer.     3. The method of manufacturing a power MOSFET according to claim 2, wherein the hard mask film remaining region includes an alignment mark region.     4. The method of manufacturing a power MOSFET according to claim 3, wherein the first insulating film is a silicon nitride insulating film, and the second insulating film is a silicon oxide insulating film.     5. The method of manufacturing a power MOSFET according to claim 4, wherein the polishing amount of the second CMP process is smaller than the polishing amount of the first CMP process.     6. The method of manufacturing a power MOSFET according to claim 5, wherein in the second CMP process, both the epitaxy layer on the substrate and the buried epitaxy layer are polished. A power MOSFET manufacturing method including the following steps:
(A) preparing a semiconductor wafer having an on-substrate epitaxial layer on the first main surface side and having the first conductivity type substrate layer on the second main surface side;
(B) forming a hard mask film on the first main surface of the semiconductor wafer;
(C) patterning the hard mask film;
(D) forming a plurality of trenches in the first main surface of the semiconductor wafer using the patterned hard mask film as a mask;
(E) After the step (d), on the first main surface, a first hard mask film residual region inside each of a large number of chip regions arranged in a lattice pattern, and the chip regions Removing the hard mask film so as to leave the hard mask film as a CMP stop film in a second hard mask film remaining region of each scribe region adjacent to each other;
(F) In a state where the CMP stop film is in each chip region and the scribe region, a second conductivity type opposite to the first conductivity type is formed by buried epitaxial growth on the first main surface of the semiconductor wafer. Depositing a buried epitaxy layer having a conductivity type;
(G) After the step (f), performing a first CMP process on the first main surface of the semiconductor wafer using the CMP stop film as a CMP stopper;
(H) a step of removing the CMP stop film after the step (g);
(I) A step of performing a second CMP process on the first main surface of the semiconductor wafer after the step (h).     8. The method of manufacturing a power MOSFET according to claim 7, wherein the first hard mask film residual region is also provided in a cell region in each chip region. 9. The method for manufacturing a power MOSFET according to claim 8, wherein the step (b) includes the following sub-steps:
(B1) forming a first insulating film on the first main surface of the semiconductor wafer;
(B2) removing the first insulating film so as to leave the first insulating film as a residual insulating film in the first hard mask film residual region and the second hard mask film residual region;
(B3) After the substep (b2), forming a second insulating film that forms the hard mask film together with the residual insulating film on the first main surface of the semiconductor wafer.     10. The method of manufacturing a power MOSFET according to claim 9, wherein the second hard mask film residual region includes an alignment mark region.     11. The method of manufacturing a power MOSFET according to claim 10, wherein the first insulating film is a silicon nitride insulating film, and the second insulating film is a silicon oxide insulating film.     12. The method of manufacturing a power MOSFET according to claim 11, wherein a polishing amount of the second CMP process is smaller than a polishing amount of the first CMP process.     13. The method of manufacturing a power MOSFET according to claim 12, wherein the first hard mask film remaining region has a stripe shape in the cell region.     13. The method for manufacturing a power MOSFET according to claim 12, wherein the first hard mask film residual region has an island shape in the cell region.     14. The method of manufacturing a power MOSFET according to claim 13, wherein an interval between the stripe-like first hard mask film residual regions is about 10 micrometers to 100 micrometers.     15. The method of manufacturing a power MOSFET according to claim 14, wherein an interval between the island-like first hard mask film residual regions is about 10 micrometers to 100 micrometers. A power MOSFET manufacturing method including the following steps:
(A) having a first conductivity type on-substrate epitaxy layer on the first main surface side and having a second conductivity type substrate layer opposite to the first conductivity type on the second main surface side; Preparing a semiconductor wafer;
(B) forming a hard mask film on the first main surface of the semiconductor wafer;
(C) patterning the hard mask film;
(D) forming a plurality of trenches in the first main surface of the semiconductor wafer using the patterned hard mask film as a mask;
(E) After the step (d), the hard mask film is formed on the hard mask film remaining area of the scribe area adjacent to each of the plurality of chip areas arranged in a lattice pattern on the first main surface. Removing the hard mask film so as to remain as a CMP stop film;
(F) depositing a buried epitaxy layer having the second conductivity type by buried epitaxial growth on the first main surface of the semiconductor wafer in a state where the CMP stop film is in the scribe region;
(G) After the step (f), performing a first CMP process on the first main surface of the semiconductor wafer using the CMP stop film as a CMP stopper;
(H) a step of removing the CMP stop film after the step (g);
(I) A step of performing a second CMP process on the first main surface of the semiconductor wafer after the step (h). 18. The method of manufacturing a power MOSFET according to claim 17, wherein the step (b) includes the following substeps:
(B1) forming a first insulating film on the first main surface of the semiconductor wafer;
(B2) removing the first insulating film so as to leave the first insulating film as a residual insulating film in the hard mask film residual region;
(B3) After the substep (b2), forming a second insulating film that forms the hard mask film together with the residual insulating film on the first main surface of the semiconductor wafer.     19. The method for manufacturing a power MOSFET according to claim 18, wherein the hard mask film remaining region includes an alignment mark region.     20. The method of manufacturing a power MOSFET according to claim 19, wherein the first insulating film is a silicon nitride insulating film, and the second insulating film is a silicon oxide insulating film.

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