CN105047700B - A kind of preparation method of light break-through IGBT device - Google Patents
A kind of preparation method of light break-through IGBT device Download PDFInfo
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
- H01L29/66333—Vertical insulated gate bipolar transistors
- H01L29/66348—Vertical insulated gate bipolar transistors with a recessed gate
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/063—Reduced surface field [RESURF] pn-junction structures
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Abstract
The present invention relates to power semiconductor field, discloses a kind of preparation method of light break-through IGBT device.IGBT device made from the preparation method, N-type carrier accumulation layer and P+ type floating Rotating fields are gathered, with high-breakdown-voltage, on the basis of the advantages such as low forward conduction voltage drop and turn-off power loss are low, can also be by setting between the 2nd P+ doped layers and gate oxide in the interval and simultaneously the N+ of row pattern adulterates block layer and collets Rotating fields of being staggered, significantly increase the resistance value of internal emitter integrated resistor, effectively suppress the increase of internal saturation current, and then extend the short-circuit safety operation area of IGBT device, it can avoid producing heavy current impact, ensure the working life of device.
Description
Technical field
The present invention relates to power semiconductor field, in particular it relates to a kind of preparation method of light break-through IGBT device.
Background technology
IGBT（Insulated Gate Bipolar Transistor, insulated gate bipolar transistor）Be one kind be by
BJT (Bipolar Junction Transistor, double pole triode) and MOS（Metal-Oxid-Semicon-ductor,
Insulating gate type field effect tube）The compound full-control type voltage driven type power semiconductor of composition, set have MOSFE（Metal-
Oxide-Semiconductor Field-Effect Transistor, metal-oxide half field effect transistor）High input impedance and
GTR（Giant Transistor, power transistor）Both low conduction voltage drops the advantages of, have driving power small and saturation pressure
The characteristics of reduction, DC voltage is generally applicable to as 600V and the converter system of the above such as alternating current generator, frequency converter, switch electricity
The fields such as source, lighting circuit, Traction Drive.
In order to further excavate the potentiality of IGBT structure, IGBT's experienced from punch structure to non-punch structure,
Then the differentiation of light punch structure is arrived.A kind of cellular section of the light punch IGBT device of second generation as shown in Figure 1, due to
P+ type floating layer and N-type carrier storage Rotating fields are gathered, can make IGBT device that there is high-breakdown-voltage, low forward conduction pressure
The advantage such as low with turn-off power loss drops, but because N-type carrier accumulation layer is thicker（Generally 5 microns）, with N- substrate layers
The NN- types hole barrier of formation is therefore higher, will assemble under the conductance modulation effect in forward conduction, at NN- knots substantial amounts of
Hole so that the inside saturation current of device will also increase considerably, therefore the short circuit safety of this light punch IGBT device
Workspace is smaller, and IGBT device is easily damaged under heavy current impact.
A kind of the problem of punch IBGT devices light for the above-mentioned second generation, it is desirable to provide new light punch IBGT devices
And preparation method, IGBT device can be made in the base with high-breakdown-voltage, low forward conduction voltage drop and the advantages such as turn-off power loss is low
On plinth, the increase of internal saturation current can be suppressed, extend its short-circuit safety operation area, so as to effectively avoid producing high current punching
Hit, it is ensured that the working life of IGBT device.
The content of the invention
The problem of punch IBGT devices light for the foregoing second generation, the invention provides a kind of novel light break-through IGBT devices
Part and preparation method, IGBT device can be made with high-breakdown-voltage, low forward conduction voltage drop and the advantages such as turn-off power loss is low
On the basis of, the increase of internal saturation current can be suppressed, extend its short-circuit safety operation area, so as to effectively avoid producing high current
Impact, it is ensured that the working life of IGBT device.
The technical solution adopted by the present invention, a kind of novel light break-through IGBT device is on the one hand provided, including several are in
The cellular of parallel-connection structure, it is characterised in that the lower surface connection colelctor electrode of the cellular, and collector electrode metal is sequentially provided with upwards
Contact layer, the first P+ doped layers, N-type cushion and N- substrate layers；The upper surface of the cellular connects emitter stage and grid respectively,
Emitter metal contact layer, the 2nd P+ doped layers, P- doped layers and N-type carrier is sequentially provided with downwards in the lower section of emitter stage to deposit
Reservoir, it is sequentially provided with gate metal contact layer, the trench gate being made up of polysilicon gate and gate oxide downwards in the lower section of grid
Structure and P+ type floating layer；The emitter metal contact layer is between two gate metal contact layers and is arranged at intervals, described
2nd P+ doped layers, P- doped layers and N-type carrier accumulation layer between two trench gate structures, and the 2nd P+ doped layers with
Several N+ doping block layers and collets layer side by side are provided between gate oxide, the N+ doping block layers and collets layer are staggered
It is intervally arranged, and is to be connected with height, with wide rectangular parallelepiped structure, the N-type carrier accumulation layer with N- substrate layers, the P+
Type floating layer is located at trench gate structure bottom and is connected respectively with gate oxide and N- substrate layers.In the cellular of the IGBT device
In structure, on the one hand the N-type carrier accumulation layer coordinates with N- substrate layers, can cause to lean in N- substrate layers in forward conduction
The hole concentration of nearly emitter stage side increases, and reduces the forward conduction voltage drop and turn-off power loss of device, while the P+ type floating
Layer can improve the electric field concentration effect of groove grid bottom, effectively reduce peak-peak electric field, greatly improve the breakdown voltage of device, from
And make IGBT device that there is high-breakdown-voltage, low forward conduction voltage drop and the advantages such as turn-off power loss is low；On the other hand, it is compared to
It is existing, adulterate Rotating fields in the N+ of strip, set between the 2nd P+ doped layers and gate oxide described between being staggered
Every and simultaneously N+ doping block layers and collets Rotating fields of row pattern, the internal emitter integrated resistor to be formed can be made to flow effect base
In the case that this is constant, its guide flow cross section is smaller, and average resistivity is higher, is integrated so as to significantly increase internal emitter
The resistance value of resistance, effectively suppresses the increase of internal saturation current, and then extends the short-circuit safety operation area of IGBT device, can
Avoid producing heavy current impact, it is ensured that the working life of device.
The technical solution adopted by the present invention, a kind of preparation method of light break-through IGBT device is on the other hand provided, it is special
Sign is, including step is as follows：S101. n type single crystal silicon piece of the selection with N- doped substrates, and pre-processed；S102. it is right
Silicon chip carries out two-sided phosphorus doping technique, and N-type cushion is generated in silicon chip bottom, and N-type carrier accumulation layer is generated in silicon chip top layer；
S103. the mask boron doping process of one side is carried out to silicon chip upper surface, in the top of N-type carrier accumulation layer generation P- doping
Layer；S104. one side mask etch process is carried out to silicon chip upper surface, runs through P- doped layers and N-type current-carrying in the generation of silicon chip top layer
The grid groove of sub- accumulation layer；S105. the mask boron doping process of one side is carried out to silicon chip upper surface, is generated in grid trench bottom epitaxial region
P+ type floating layer；S106. the oxidation technology of one side is carried out to silicon chip upper surface, gate oxide is generated in grid groove, is then passed through
Masked-deposition technique fills polysilicon into grid groove, forms the polysilicon gate in channel form；S107. silicon chip upper surface is carried out single
The mask phosphorus doping technique in face, N+ doped layers are generated on the top of P- doped layers；S108. two-sided boron is carried out to silicon chip and adulterates work
Skill, the first P+ doped layers are generated in the bottom of N-type cushion, and the 2nd P+ doped layers are generated in the centre position of N+ doped layers；
S109. one side mask etch process is carried out to silicon chip upper surface, mixed in the N+ between the 2nd P+ doped layers and gate oxide
The interval trough of several mistakes side by side is generated in diamicton, titanium dioxide is then filled to each interval trough by masked-deposition technique
Silicon, wrong collets layer side by side between formation；S110. two-sided metal deposition process is carried out to silicon chip, is generated respectively in upper surface
In spaced apart emitter metal contact layer and gate metal contact layer, collector electrode metal contact layer is generated in lower surface.According to
According to abovementioned steps, you can obtain novel light break-through IGBT device provided by the present invention, it is with high-breakdown-voltage, low forward direction
On the basis of the advantages such as conduction voltage drop and turn-off power loss are low, it can effectively suppress the increase of internal saturation current, and then extend
The short-circuit safety operation area of IGBT device, avoid producing heavy current impact, it is ensured that the working life of device.
Specifically, also comprise the following steps in the step S102：Phosphorus doping technique is masked to silicon chip upper surface, and
N-type carrier accumulation layer is generated using thermal diffusion mode.
Specifically, also comprise the following steps in the step S103：Mixed in the mask boron that one side is carried out to silicon chip upper surface
Ion implanting mode is used in general labourer's skill, generation doping area is more than the P- doped layers of N-type carrier accumulation layer doping area.
Specifically, comprise the following steps in the step S108：The mask boron that one side is carried out to silicon chip upper surface adulterates work
Skill, and it is less than the of N+ doped layers doping area in the centre position of N+ doped layers generation doping area using ion implanting mode
Two P+ doped layers.
Specifically, also comprise the following steps in the step S110：The mask aluminium conjunction of one side is carried out to the upper surface of silicon chip
Golden depositing operation, emitter metal contact layer is generated in the top of the 2nd P+ doped layers, and grid is generated in the top of polysilicon gate
Metal contact layer.
To sum up, using a kind of novel light break-through IGBT device provided by the present invention and preparation method, IGBT device can be made
Gather N-type carrier accumulation layer and P+ type floating Rotating fields, with high-breakdown-voltage, low forward conduction voltage drop and turn-off power loss
On the basis of low advantage, additionally it is possible to by setting between the 2nd P+ doped layers and gate oxide in the interval and side by side of being staggered
The N+ doping block layers and collets Rotating fields of shape, significantly increase the resistance value of internal emitter integrated resistor, effectively in suppression
The increase of portion's saturation current, and then the short-circuit safety operation area of IGBT device is extended, it can avoid producing heavy current impact, it is ensured that device
The working life of part.
Brief description of the drawings
In order to illustrate more clearly about the embodiment of the present invention or technical scheme of the prior art, below will be to embodiment or existing
There is the required accompanying drawing used in technology description to be briefly described, it should be apparent that, drawings in the following description are only this
Some embodiments of invention, for those of ordinary skill in the art, on the premise of not paying creative work, can be with
Other accompanying drawings are obtained according to these accompanying drawings.
Fig. 1 is a kind of cellular section schematic diagram of the light punch IGBT device of existing second generation.
Fig. 2 is the cellular section schematic diagram of novel light break-through IGBT device provided in an embodiment of the present invention.
Fig. 3 is the cellular floor map of novel light break-through IGBT device provided in an embodiment of the present invention.
Fig. 4 is the preparation method flow chart of novel light break-through IGBT device provided in an embodiment of the present invention.
Fig. 5 is the IGBT device section schematic diagram shown in step S101 in preparation method provided in an embodiment of the present invention.
Fig. 6 is the IGBT device section schematic diagram shown in step S102 in preparation method provided in an embodiment of the present invention.
Fig. 7 is the IGBT device section schematic diagram shown in step S103 in preparation method provided in an embodiment of the present invention.
Fig. 8 is the IGBT device section schematic diagram shown in step S104 in preparation method provided in an embodiment of the present invention.
Fig. 9 is the IGBT device section schematic diagram shown in step S105 in preparation method provided in an embodiment of the present invention.
Figure 10 is the IGBT device section schematic diagram shown in step S106 in preparation method provided in an embodiment of the present invention.
Figure 11 is the IGBT device section schematic diagram shown in step S107 in preparation method provided in an embodiment of the present invention.
Figure 12 is the IGBT device section schematic diagram shown in step S108 in preparation method provided in an embodiment of the present invention.
Figure 13 is the IGBT device section schematic diagram shown in step S110 in preparation method provided in an embodiment of the present invention.
In above-mentioned accompanying drawing：1st, collector electrode metal contact layer 2, the first P+ doped layers 3, N-type cache layer 4, N- substrate layers
5th, N-type carrier accumulation layer 6, P- doped layers 7, N+ doping blocks layer 8, collets layer 9, the 2nd P+ doped layers 10, emitter stage
Metal contact layer 11, gate metal contact layer 12, polysilicon gate 13, gate oxide 14, P+ type floating layer.
Embodiment
Hereinafter with reference to accompanying drawing, novel light break-through IGBT device provided by the invention is described in detail by way of example
And preparation method.Herein it should be noted that being used to help understand the present invention for the explanation of these way of example, but not
Form limitation of the invention.
Various technologies described herein can be used for but be not limited to power semiconductor field, can be also used for other
Similar field.
The terms "and/or", only a kind of incidence relation for describing affiliated partner, expression may have three kinds of passes
System, for example, A and/or B, can be represented：Individualism A, individualism B, while tri- kinds of situations of A and B, the terms be present
" or/and " it is another affiliated partner relation of description, expression may have two kinds of relations, for example, A or/and B, can be represented：It is single
A solely be present, two kinds of situations of individualism A and B, in addition, character "/" herein, it is a kind of to typically represent forward-backward correlation object
"or" relation.
Embodiment one, Fig. 2 show the cellular section schematic diagram for the novel light break-through IGBT device that the present embodiment provides, figure
3 show the cellular floor map for the novel light break-through IGBT device that the present embodiment provides.The novel light break-through IGBT devices
Part, including several are in the cellular of parallel-connection structure, the lower surface of the cellular connects colelctor electrode, and is sequentially provided with colelctor electrode upwards
Metal contact layer 1, the first P+ doped layers 2, N-type cushion 3 and N- substrate layers 4；The upper surface of the cellular connects transmitting respectively
Pole and grid, it is sequentially provided with emitter metal contact layer 10, the 2nd P+ doped layers 9, P- doped layers 6 downwards in the lower section of emitter stage
With N-type carrier accumulation layer 5, gate metal contact layer 11 is sequentially provided with downwards in the lower section of grid, by polysilicon gate 12 and grid
The trench gate structure and P+ type floating layer 14 that oxide layer 13 forms；The emitter metal contact layer 10 is located at two gate metals and connect
Between contact layer 11 and it is arranged at intervals, the 2nd P+ doped layers 9, P- doped layers 6 and the N-type carrier accumulation layer 5 are located at two grooves
Between grid structure, and several N+ doping blocks layers 7 and insulation side by side are provided between the 2nd P+ doped layers 9 and gate oxide 13
Block layer 8, the N+ doping blocks layer 7 and collets layer 8 are staggered and are intervally arranged, and be same height, with wide rectangular parallelepiped structure, described
N-type carrier accumulation layer 5 is connected with N- substrate layers 4, the P+ type floating layer 14 be located at trench gate structure bottom and respectively with grid
Oxide layer 13 is connected with N- substrate layers 4.
In the structure cell of the IGBT device, on the one hand the N-type carrier accumulation layer 5 and N- substrate layers 4 coordinate,
A NN- type hole barrier is formed, under the conductance modulation effect in forward conduction so that exist in N- substrate layers 4 a large amount of empty
Cave, and the NN- types hole barrier formed will prevent hole from flowing to P- doped layers 6, and assemble substantial amounts of hole at NN- knots, make
Obtain the hole concentration in N- substrate layers 4 close to emitter stage side to increase, so as to optimize the Electric Field Distribution of first intracellular, reduce chip
Forward conduction voltage drop and turn-off power loss, while the P+ type floating layer can improve the electric field concentration effect of groove grid bottom, effectively
Reduce peak-peak electric field, the breakdown voltage of device is greatly improved, so that IGBT device has high-breakdown-voltage, low forward
The advantages such as logical pressure drop and turn-off power loss are low；On the other hand, be compared to it is existing, adulterate Rotating fields in the N+ of strip, the
What is set between two P+ doped layers 9 and gate oxide 13 is described in interval and the simultaneously N+ doping block layer 7 and collets of row pattern of being staggered
8 structure of layer, can making the internal emitter integrated resistor to be formed, its guide flow cross section is more in the case where stream effect is basically unchanged
Small, average resistivity is higher, so as to significantly increase the resistance value of internal emitter integrated resistor, effectively suppresses internal saturation
The increase of electric current, and then the short-circuit safety operation area of IGBT device is extended, it can avoid producing heavy current impact, it is ensured that device
Working life.
Further specifically, not less than 0.3 times N+ of the length of the collets layer 8 adulterates the length of block layer 7 and is not more than
The length of 0.6 times of N+ doping blocks layer 7.The length lower limit of the collets layer 8 is restricted in craft precision, and its higher limit needs true
The stream effect of internal emitter integrated resistor is protected, therefore as optimization, in the present embodiment, the length of the collets layer 8
The length of block layer 7 is adulterated for 0.5 times of N+.
Specifically, the length-width ratio of the N+ doping blocks layer 7 is 3:2.
Specifically, N+ doping block layer 7 and absolutely of the local connection of the emitter metal contact layer 10 positioned at its down either side
Edge block layer 8.
Specifically, the depth of the trench gate structure is more than the 2nd P+ doped layers 9, P- doped layers 6 and N-type carrier storage
The thickness sum of 5 three of layer and no more than 1 micron.Planar gate structure is compared to, the trench gate structure can improve device
On state characteristic, reduce conducting resistance, for this, its lower limit need to be more than the 2nd P+ doped layers 9, P- doped layers 6 and N-type carrier
The thickness sum of the three of accumulation layer 5, so that trench gate structure can run through downwards N-type carrier accumulation layer 5；It is simultaneously because internal
Saturation current density and the depth of trench gate structure present relationships of increase function, therefore the depth of trench gate structure is also unsuitable excessive,
As an example, in the present embodiment, in the 2nd P+ doped layers 9, P- doped layers 6 and the thickness of the three of N-type carrier accumulation layer 5
It is 8.5 microns to spend sum（The thickness sum of 2nd P+ doped layers 9 and P- doped layers 6 is 3.5 microns, N-type carrier accumulation layer 5
Thickness be 5 microns）In the case of, the depth of the trench gate structure is 9 microns.
The novel light break-through IGBT device that above-described embodiment provides, has the advantages that：（1）N-type current-carrying is gathered
Sub- accumulation layer and P+ type floating Rotating fields, make IGBT device have high-breakdown-voltage, low forward conduction voltage drop and turn-off power loss low
The advantages that；（2）By setting between the 2nd P+ doped layers and gate oxide in the interval and simultaneously the N+ of row pattern adulterates block of being staggered
Layer and collets Rotating fields, significantly increase the resistance value of internal emitter integrated resistor, effectively suppress internal saturation current
Increase, and then extend the short-circuit safety operation area of IGBT device, can avoid producing heavy current impact, it is ensured that the work of device
Life-span.
Embodiment two, Fig. 4 show the preparation method flow chart for the novel light break-through IGBT device that the present embodiment provides, figure
5 show that the IGBT device section schematic diagram shown in step S101, Fig. 6 show this reality in the preparation method that the present embodiment provides
The IGBT device section schematic diagram shown in step S102 in the preparation method of example offer is applied, Fig. 7 shows what the present embodiment provided
IGBT device section schematic diagram in preparation method shown in step S103, Fig. 8 are shown in the preparation method that the present embodiment provides
IGBT device section schematic diagram shown in step S104, Fig. 9 show step S105 institutes in the preparation method that the present embodiment provides
The IGBT device section schematic diagram shown, Figure 10 show the IGBT devices shown in step S106 in the preparation method that the present embodiment provides
Part section schematic diagram, Figure 11 show the IGBT device section signal shown in step S107 in the preparation method that the present embodiment provides
Figure, Figure 12 show that the IGBT device section schematic diagram shown in step S108, Figure 13 show in the preparation method that the present embodiment provides
IGBT device section schematic diagram shown in step S110 in the preparation method of the present embodiment offer has been provided.Embodiment two is as a kind of
The preparation method of novel light break-through IGBT device described by embodiment one, including step are as follows.
S101. n type single crystal silicon piece of the selection with N- doped substrates, and pre-processed.
In the step S101, it is necessary first to according to the targeted breakdown voltage of IGBT device and target forward conduction voltage drop
N type single crystal silicon piece of the demand selection with suitable N- doping concentrations and thickness, then passes through acid, alkali, deionized water ultrasonic wave
Matting, n type single crystal silicon substrate surface is chemically treated, the n type single crystal silicon piece finally obtained is as shown in Figure 5.
S102. two-sided phosphorus doping technique is carried out to silicon chip, N-type cushion is generated in silicon chip bottom, N is generated in silicon chip top layer
Type carrier accumulation layer.
The step S102 to the phosphorus doping target area of silicon chip upper surface as shown in fig. 6, due to being only doped, therefore
Need first to generate mask layer in silicon chip upper surface, and after allowing mask layer to cover non-phosphorus doping target area, can just carry out two-sided phosphorus
Doping process.Simultaneously because to generate deeper N-type cushion and N-type carrier accumulation layer（Shown in embodiment one
, it is necessary to generate the N-type carrier storage layer of 8.5 micron thickness in IGBT device, and N-type cushion is then deeper）, be compared to from
Sub- injection mode, phosphorus doping technique is more suitable using thermal diffusion mode, and not only doping depth is deeper, and doping concentration is more equal
It is even.Therefore specifically, also comprising the following steps in the step S102：Phosphorus doping technique is masked to silicon chip upper surface, and
N-type carrier accumulation layer is generated using thermal diffusion mode.
S103. the mask boron doping process of one side is carried out to silicon chip upper surface, is generated on the top of N-type carrier accumulation layer
P- doped layers.
The step S103 is as shown in fig. 7, need also exist for first covering non-boron doping mesh in silicon chip upper surface generation mask layer
Region is marked, due to the N-type carrier accumulation layer of lower section being completely covered in order to ensure the P- doped layers of generation, mask layer does not cover
Boron doping target area have to be larger than and cover in step S102 the unlapped phosphorus doping target area of mask layer institute.While by
It is shallower in the doping depth of P- doped layers（In the IGBT device that embodiment one is shown, the P- of 3.5 micron thickness need to be only generated
Doped layer, to ensure that final N-type carrier accumulation layer has 5 microns of thickness）, in order to save preparation time, as
Optimization, in the present embodiment, also comprise the following steps in the step S103：The mask boron of one side is being carried out to silicon chip upper surface
Ion implanting mode is used in doping process, generation doping area is more than the P- doped layers of N-type carrier accumulation layer doping area.
S104. one side mask etch process is carried out to silicon chip upper surface, runs through P- doped layers and N-type in the generation of silicon chip top layer
The grid groove of carrier accumulation layer.
The step S104 as shown in figure 8, the depth of the grid groove be less than the doping depth of N-type carrier accumulation layer with
1 micron of sum, so that subsequent step realizes the trench gate structure described by embodiment one.
S105. the mask boron doping process of one side is carried out to silicon chip upper surface, is floated in grid trench bottom epitaxial region generation P+ type
Dead level.
Then the step S105 passes through as shown in figure 9, the mask layer in silicon chip upper surface covers non-slotted region
The boron doping process of ion implanting mode, you can rapidly and accurately generate P+ type floating layer in grid trench bottom epitaxial region.
S106. the oxidation technology of one side is carried out to silicon chip upper surface, gate oxide is generated in grid groove, then passes through mask
Depositing operation fills polysilicon into grid groove, forms the polysilicon gate in channel form.
The step S106 is as shown in Figure 10, and after gate oxide is generated, in silicon chip upper surface, generation covers non-slotted area
The mask layer in domain, polysilicon is filled into grid groove finally by chemical vapour deposition technique, obtain the polysilicon gate in channel form.
S107. the mask phosphorus doping technique of one side is carried out to silicon chip upper surface, in the top of P- doped layers generation N+ doping
Layer.
The step S107 is as shown in figure 11, and due to the thickness of thin of N+ doped layers, doping concentration is high, used after mask from
The phosphorus doping technique of sub- injection mode can quickly generate the N+ doped layers of high concentration.
S108. two-sided boron doping process is carried out to silicon chip, the first P+ doped layers are generated in the bottom of N-type cushion, in N
The centre position of+doped layer generates the 2nd P+ doped layers.
The step S108 is as shown in figure 12, and the no-coverage of mask layer is the intermediate region of N+ doped layers, using from
The phosphorus doping technique of sub- injection mode is that can obtain the 2nd P+ doped layers that are positioned at N+ doped layers centre position and being high concentration.
S109. one side mask etch process is carried out to silicon chip upper surface, positioned at the 2nd P+ doped layers and gate oxide it
Between N+ doped layers in generate the interval trough of several mistakes side by side, then filled by masked-deposition technique to each interval trough
Silica, wrong collets layer side by side between formation.
In the step S109, the etching depth of the interval trough requires identical with the thickness of N+ doped layers, to isolate
N+ doping block layers independent side by side are formed, used depositing operation is identical with the depositing operation used in step 106 in addition,
It is in be staggered interval and the simultaneously N+ doping block layers of row pattern and insulation so as to obtain described by embodiment one for chemical vapour deposition technique
Block Rotating fields.
S110. two-sided metal deposition process is carried out to silicon chip, is generated respectively in spaced apart emitter stage in upper surface
Metal contact layer and gate metal contact layer, collector electrode metal contact layer is generated in lower surface.
The step S110 is as shown in figure 13, and first in silicon chip upper surface, generation can make emitter metal contact layer and grid gold
Belong to the mask layer of contact layer isolation, then using the aluminium alloy depositing operation of chemical vapour deposition technique, you can obtain embodiment one
Three kinds of described metal contact layers.Specifically, also comprise the following steps in the step S110：The upper surface of silicon chip is carried out
The mask aluminium alloy depositing operation of one side, emitter metal contact layer is generated in the top of the 2nd P+ doped layers, in polysilicon gate
Top generation gate metal contact layer.
The preparation method for the novel light break-through IGBT device that above-described embodiment provides, by this method except that can be implemented
Described by example one outside IGBT device, also have the advantages that：For different doping demands, using suitable doping work
Skill, the IGBT device guaranteed both quality and quantity can be quickly obtained, have good directive function to the technique productions of IGBT device.
As described above, it can preferably realize the present invention.For a person skilled in the art, according to the religion of the present invention
Lead, design various forms of novel light break-through IGBT devices and preparation method and do not need performing creative labour.Do not departing from
These embodiments are changed in the case of the principle and spirit of the present invention, changes, replace, integrating and modification still falls within this hair
Bright protection domain.
Claims (5)
1. a kind of preparation method of light break-through IGBT device, it is characterised in that as follows including step：
S101. n type single crystal silicon piece of the selection with N- doped substrates, and pre-processed；
S102. two-sided phosphorus doping technique is carried out to silicon chip, N-type cushion is generated in silicon chip bottom, carried in silicon chip top layer generation N-type
Flow sub- accumulation layer；
S103. the mask boron doping process of one side is carried out to silicon chip upper surface, generation P- mixes on the top of N-type carrier accumulation layer
Diamicton；
S104. one side mask etch process is carried out to silicon chip upper surface, runs through P- doped layers and N-type current-carrying in the generation of silicon chip top layer
The grid groove of sub- accumulation layer；
S105. the mask boron doping process of one side is carried out to silicon chip upper surface, P+ type floating layer is generated in grid trench bottom epitaxial region；
S106. the oxidation technology of one side is carried out to silicon chip upper surface, gate oxide is generated in grid groove, then passes through masked-deposition
Technique fills polysilicon into grid groove, forms the polysilicon gate in channel form；
S107. the mask phosphorus doping technique of one side is carried out to silicon chip upper surface, N+ doped layers are generated on the top of P- doped layers；
S108. two-sided boron doping process is carried out to silicon chip, the first P+ doped layers is generated in the bottom of N-type cushion, is mixed in N+
The centre position of diamicton generates the 2nd P+ doped layers；
S109. one side mask etch process is carried out to silicon chip upper surface, in the N between the 2nd P+ doped layers and gate oxide
The interval trough of several mistakes side by side is generated in+doped layer, dioxy is then filled to each interval trough by masked-deposition technique
SiClx, wrong collets layer side by side between formation；
S110. two-sided metal deposition process is carried out to silicon chip, is generated respectively in spaced apart emitter metal in upper surface
Contact layer and gate metal contact layer, collector electrode metal contact layer is generated in lower surface.
2. the preparation method of a kind of light break-through IGBT device as claimed in claim 1, it is characterised in that in the step S102
Also comprise the following steps：
Phosphorus doping technique is masked to silicon chip upper surface, and N-type carrier accumulation layer is generated using thermal diffusion mode.
3. the preparation method of a kind of light break-through IGBT device as claimed in claim 2, it is characterised in that in the step S103
Also comprise the following steps：
Ion implanting mode is used in the mask boron doping process for carrying out one side to silicon chip upper surface, generation doping area is more than
N-type carrier accumulation layer adulterates the P- doped layers of area.
4. the preparation method of a kind of light break-through IGBT device as claimed in claim 1, it is characterised in that in the step S108
Comprise the following steps：
The mask boron doping process of one side is carried out to silicon chip upper surface, and uses ion implanting mode in the interposition of N+ doped layers
Put the 2nd P+ doped layers that generation doping area is less than N+ doped layers doping area.
5. the preparation method of a kind of light break-through IGBT device as claimed in claim 1, it is characterised in that in the step S110
Also comprise the following steps：
The mask aluminium alloy depositing operation of one side is carried out to the upper surface of silicon chip, emitter stage is generated in the top of the 2nd P+ doped layers
Metal contact layer, gate metal contact layer is generated in the top of polysilicon gate.
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