CN106684131B

CN106684131B - Power device and manufacturing method thereof

Info

Publication number: CN106684131B
Application number: CN201510760045.3A
Authority: CN
Inventors: 刘国友; 覃荣震; 黄建伟; 张泉; 朱利恒; 戴小平
Original assignee: Zhuzh Csr Times Electric Co ltd
Current assignee: Zhuzhou CRRC Times Electric Co Ltd; Zhuzhou CRRC Times Semiconductor Co Ltd
Priority date: 2015-11-10
Filing date: 2015-11-10
Publication date: 2020-05-15
Anticipated expiration: 2035-11-10
Also published as: CN106684131A

Abstract

The invention discloses a power device and a manufacturing method thereof, wherein the power device comprises: the power device comprises an N trap, an N-substrate, a P-base region, a polysilicon gate, an N + source region, a P + ohmic contact region, an emitter metal electrode and a gate oxide layer, wherein the power device adopts a trench gate structure. The power device further comprises a P trap, wherein an N + source region, a P-base region, the N trap and the P trap are sequentially arranged from top to bottom, and the P trap surrounds the bottom of the groove gate structure. The electric field intensity at the bottom of the groove is reduced by accelerating the depletion of carriers of the N well when the power device is turned off. The invention can solve the technical problem of the reduction of the withstand voltage characteristic of the device caused by the high-concentration N well, and the technical problems of high cost, large process difficulty and small doping concentration adjustment range of the conventional manufacturing process of the P well, so that the device can still keep good withstand voltage characteristic under the high-concentration N well, thereby optimizing the contradiction relationship between the power consumption and the withstand voltage of the device.

Description

Power device and manufacturing method thereof

Technical Field

The invention relates to the technical field of power semiconductors, in particular to an Insulated Gate Bipolar Transistor (IGBT) power device and a manufacturing method thereof.

Background

In the prior art, in order to optimize the on-state voltage drop and turn-off loss of a power device and reduce the power consumption of the device, a Carrier Storage Layer (hole blocking Layer) structure is generally adopted, and the structure is also called as an "N-Enhancement Layer" and a "Carrier Storage N Layer" (N-type Carrier Storage Layer). As shown in fig. 1, the IGBT based on the carrier storage layer planar gate structure is provided with an N-enhancement layer 13 surrounding the P-base region, wherein 8 is an emitter metal electrode, and 12 is a collector metal electrode. The applicant applies for the structure on the 07 th 12 th 2012 and discloses the structure on the 13 th 03 th 2013, and the structure is disclosed in the chinese invention patent "a planar gate type IGBT chip" with the publication number CN 102969351B. As shown in fig. 2, in the IGBT based on the trench gate structure of the carrier storage layer, an N well (N-type carrier storage layer 17) is disposed below the P-base region to surround the P-base region, and a hole barrier is formed at this position, so that the extraction of holes by the emitter electrode in the on state is blocked, and the injection of electrons into the emitter electrode is increased, thereby enhancing the conductivity modulation effect at this position and reducing the on-state voltage drop. In the figure, 4 is a polysilicon gate, 8 is an emitter metal electrode, 12 is a collector metal electrode, and 17 is an N-type carrier storage layer. The applicant applies for the structure on the 07 th 12 th 2012 and the 13 th 03 th 2013, and discloses the structure in the 'trench gate type IGBT chip' of the chinese invention application with the publication number CN 102969350A. Since this structure does not rely on increasing hole injection from the back collector, the back hole injection efficiency can be optimized and the turn-off loss of the device can be further reduced. In the structure shown in fig. 2, a metal barrier layer 14 is surrounded on the upper portion of the gate oxide layer 9, and a P + diffusion layer 15 and an emitter layer 16 are disposed between the two trenches.

Generally, the doping concentration of the N well is higher than that of the N-substrate, and as the doping concentration of the N well is increased, the on-state voltage drop of the power device can be further reduced. However, as the concentration of the N-well increases, the voltage endurance of the device decreases, because the high concentration of the N-well affects the carrier depletion rate of the device in the off state, resulting in the concentration of the electric field at the bottom of the trench (as shown in fig. 3, 4 and 5), and thus high electric field strength is generated, which affects the voltage endurance of the device.

Disclosure of Invention

In view of the above, an object of the present invention is to provide a power device and a method for manufacturing the same, which can solve the technical problem of the decrease of the withstand voltage characteristic of the device caused by the high-concentration N well, so that the device can still maintain a good withstand voltage characteristic under the high-concentration N well, thereby optimizing the contradiction between the power consumption and the withstand voltage of the device.

In order to achieve the above object, the present invention specifically provides a technical implementation scheme of a power device, where the power device includes: the power device comprises an N trap, an N-substrate, a P-base region, a polysilicon gate, an N + source region, a P + ohmic contact region, an emitter metal electrode and a gate oxide layer, wherein the power device adopts a trench gate structure. The power device further comprises a P trap, wherein an N + source region, a P-base region, the N trap and the P trap are sequentially arranged from top to bottom, and the P trap surrounds the bottom of the groove gate structure.

Preferably, the peak doping concentration of the P-well is located at the bottom of the trench.

Preferably, the P-well reduces the electric field strength at the bottom of the trench by accelerating the depletion of carriers of the N-well when the power device is turned off.

Preferably, the doping concentration of the P-well is higher than that of the N-well.

Preferably, the doping concentration curves of the P-well and the N-well are connected.

Preferably, when the power device adopts a trench gate structure of an effective gate, two P wells located at the bottom of the effective gate are separated from each other.

Preferably, when the trench gate structure of the power device includes an effective gate and two or more dummy gates disposed at two sides of the effective gate, two P wells located at the bottom of the effective gate are separated from each other, the P wells located at the bottoms of the dummy gates and the effective gate adjacent to each other are separated from each other or connected to each other, and the P wells located at the bottoms of the two dummy gates adjacent to each other are separated from each other or connected to each other.

The invention specifically provides a technical implementation scheme of the manufacturing method of the power device, and the manufacturing method of the power device comprises the following steps:

s101: manufacturing an N well on the basis of the N-substrate;

s102: manufacturing a P-base region on the N trap;

s103: manufacturing a groove on the basis of the previous step;

s104: injecting a P well through the groove to form a P well;

s105: carrying out gate oxide layer manufacturing and polysilicon filling in the groove;

s106: manufacturing an N + source electrode region between the two grooves;

s107: and finishing the subsequent process.

The invention also provides another technical implementation scheme of the manufacturing method of the power device, and the manufacturing method of the power device comprises the following steps when the distance between the effective grid electrodes is equal to the distance between the adjacent dummy grid and the effective grid electrode:

s111: p well manufacturing is carried out on the basis of the N-substrate;

s101: on the basis of the previous step, N-well manufacturing is carried out;

s102: manufacturing a P-base region on the N trap;

s103: manufacturing a groove on the basis of the previous step;

s106: manufacturing an N + source electrode region between the two grooves;

s107: and finishing the subsequent process.

Preferably, step S101 further includes:

s1011, manufacturing a sacrificial oxide layer on the front surface of the device on the basis of the N-substrate through high-temperature oxidation, wherein the thickness of the sacrificial oxide layer is 100 Å -600 Å;

s1012: coating a layer of photoresist on the sacrificial oxide layer, then carrying out exposure, and removing the photoresist above the device effective area to form an N-well injection window;

s1013: carrying out N-type ion implantation, and removing the residual photoresist on the surface of the device;

s1014: performing high-temperature drive to finally form an N well, wherein the doping concentration of the N well is 1e16/cm³And the junction depth of the N well is 3-8 mu m below the magnitude level.

Preferably, step S111 further includes:

s1111, manufacturing a sacrificial oxide layer on the front surface of the device on the basis of the N-substrate through high-temperature oxidation, wherein the thickness of the sacrificial oxide layer is 100 Å -600 Å;

s1112: coating a layer of photoresist on the sacrificial oxide layer, then carrying out exposure, and removing the photoresist above the device effective area to form a P well injection window;

s1113: performing P-type ion implantation, and removing the residual photoresist on the surface of the device;

s1114: performing high-temperature drive to finally form a P well, wherein the doping concentration of the P well is 1e16/cm³And the junction depth of the P well is 3-8 mu m below the magnitude level.

Preferably, step S102 further includes:

s1021: manufacturing a sacrificial oxide layer on the N well through high-temperature oxidation, wherein the thickness of the sacrificial oxide layer is 100-600A;

s1022: coating a layer of photoresist on the sacrificial oxide layer, then exposing, and removing the photoresist on the active region of the device

Photoresist to form a P-base region injection window;

s1023: performing P-type ion implantation, removing the residual photoresist on the surface of the device, and removing the residual photoresist on the surface of the device;

s1024: performing high-temperature propulsion to finally form a P-base region, wherein the doping concentration of the P-base region is 1e17/cm³Above the magnitude, the junction depth of the P-base region is 3-8 μm.

Preferably, step S103 further includes:

s1031: carrying out etching window modeling: coating a layer of photoresist, and then carrying out exposure and photoresist removal to form a groove etching window;

s1032: and etching the groove until the target depth is greater than or equal to the junction depth of the N trap.

Preferably, the step S104 further includes:

s1041: performing P-type ion implantation on the active region of the device;

s1042: and carrying out high-temperature propulsion to form a P well, wherein the doping concentration of the P well is higher than that of the N well.

Preferably, the step S105 further includes:

s1051: carrying out high-temperature oxidation to grow a gate oxide layer on the inner wall of the groove, wherein the thickness of the gate oxide layer is 0.1-0.5 mu m;

s1052: depositing polycrystalline silicon, wherein the polycrystalline silicon fills the inside of the groove;

s1053: n-type doping is carried out on the polysilicon, and the doping concentration is 1e19/cm³Magnitude above;

the step S1053 further includes:

firstly, N-type ion implantation is carried out, then doping is realized through high-temperature propulsion, and an oxide layer is formed on the surface of the polycrystalline silicon after the propulsion.

Preferably, the step S106 further includes:

s1061: carrying out etching window modeling: coating a layer of photoresist, and then carrying out exposure and photoresist removal to form an N + source region injection window;

s1062: performing N-type ion implantation, and removing the residual photoresist;

s1063: performing high-temperature drive to form an N + source region with the doping concentration of 1e19/cm³And the junction depth of the N + source region is more than or equal to 1 μm.

The invention specifically provides a third technical implementation scheme of the manufacturing method of the power device, and the manufacturing method of the power device comprises the following steps:

s201: manufacturing a P-base region on the basis of the N-substrate;

s202: etching a groove on the basis of the previous step;

s203: injecting an N well through the groove to form an N well;

s204: continuing to etch the groove until reaching the target depth;

s205: injecting a P well through the groove to form a P well;

s206: carrying out gate oxide layer manufacturing and polysilicon filling in the groove;

s207: manufacturing an N + source electrode region between the two grooves;

s208: and finishing the subsequent process.

The present invention further provides a fourth technical implementation of the manufacturing method of the power device, and the manufacturing method of the power device includes the following steps when the distance between the effective gates is equal to the distance between the dummy gate and the effective gate adjacent to each other:

s211: p well manufacturing is carried out on the basis of the N-substrate;

s201: on the basis of the previous step, P-base region manufacturing is carried out;

s202: etching a groove on the basis of the previous step;

s203: injecting an N well through the groove to form an N well;

s204: continuing to etch the groove until reaching the target depth;

s207: manufacturing an N + source electrode region between the two grooves;

s208: and finishing the subsequent process.

Preferably, the step S201 further includes:

s2011, manufacturing a sacrificial oxide layer on the front surface of the device on the basis of an N-substrate through high-temperature oxidation, wherein the thickness of the sacrificial oxide layer is 100 Å -600 Å;

s2012: coating a layer of photoresist on the sacrificial oxide layer, then carrying out exposure, and removing the photoresist above the device effective region to form a P-base region injection window;

s2013: performing P-type ion implantation, and removing the residual photoresist on the surface of the device;

s2014: performing high-temperature propulsion to finally form the P-base region, wherein the doping concentration of the P-base region is 1e17/cm³Above the magnitude, the junction depth of the P-base region is 3-8 μm.

Preferably, the step S211 further includes:

s2111, manufacturing a sacrificial oxide layer on the front surface of the device on the basis of the N-substrate through high-temperature oxidation, wherein the thickness of the sacrificial oxide layer is 100 Å -600 Å;

s2112: coating a layer of photoresist on the sacrificial oxide layer, then carrying out exposure, and removing the photoresist above the device effective area to form a P well injection window;

s2113: performing P-type ion implantation, and removing the residual photoresist on the surface of the device;

s2114: performing high-temperature drive to finally form the P well, wherein the doping concentration of the P well is 1e16/cm³And the junction depth of the P well is 3-8 mu m below the magnitude level.

Preferably, the step S202 further includes:

s2021: carrying out etching window modeling: coating a layer of photoresist, and then carrying out exposure and photoresist removal to form a groove etching window;

s2022: and etching the groove until reaching a first depth which is greater than or equal to the junction depth of the P-base region.

Preferably, the step S203 further includes:

s2031: carrying out N-type ion implantation on the whole device;

s2032: performing high-temperature drive to form an N well, wherein the doping concentration of the N well is 1e14/cm³～1e17/cm³Is less than 3 μm, the junction depth of the N-well is within the order of magnitude of (d).

Preferably, the step S204 further includes:

s2041: carrying out etching window modeling: coating a layer of photoresist, and then carrying out exposure and photoresist removal to form a groove etching window;

s2042: and etching the groove until reaching a second depth, wherein the second depth is the design depth of the groove, and the design depth of the groove is between 4 and 8 mu m.

Preferably, the step S205 further includes:

and carrying out P-type ion implantation on the active region of the device, wherein the doping concentration of the P trap is lower than that of the N + source region.

Preferably, the step S206 further includes:

s2061: carrying out high-temperature oxidation to grow a gate oxide layer on the inner wall of the groove, wherein the thickness of the gate oxide layer is 0.1-0.5 mu m;

s2062: depositing polycrystalline silicon, wherein the polycrystalline silicon fills the inside of the groove;

s2063: n-type doping is carried out on the polysilicon, and the doping concentration is 1e19/cm³Above the order of magnitude.

The step S2063 further includes:

Preferably, the step S207 further includes:

s2071: carrying out etching window modeling: coating a layer of photoresist, and then carrying out exposure and photoresist removal to form an N + source region injection window;

s2072: performing N-type ion implantation, and removing the residual photoresist;

s2073: performing high-temperature drive to form an N + source region with the doping concentration of 1e19/cm³And the junction depth of the N + source region is more than or equal to 1 μm.

By implementing the technical scheme of the power device and the manufacturing method thereof provided by the invention, the power device has the following beneficial effects:

(1) the invention improves the voltage resistance of the high-concentration N-well trench gate power device and optimizes the contradiction relationship between the on-state voltage drop (power consumption) and the voltage resistance of the IGBT;

(2) the process cost of the P well is lower than that of the high-energy ion implantation process;

(3) the P-well diffusion process does not influence the concentration and junction depth of the N-well, the P-base region and the N + source region, and reduces the complexity and difficulty of the process;

(4) the invention utilizes the groove to carry out self-alignment injection without adding a photoetching plate;

(5) the concentration of the P trap is easy to adjust, and the adjusting window range is large.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below. It is obvious that the drawings in the following description are only some embodiments of the invention, and that for a person skilled in the art, other embodiments can be obtained from these drawings without inventive effort.

FIG. 1 is a schematic cross-sectional structure diagram of a power device based on a carrier storage layer planar gate structure in the prior art;

FIG. 2 is a schematic cross-sectional view of a prior art power device based on a carrier storage layer trench gate structure;

FIG. 3 is a schematic diagram of the internal electric field distribution of a prior art trench-gate power device;

FIG. 4 is a graph of electric field strength at a tangent line C4 in FIG. 3;

FIG. 5 is a graph of the electric field intensity at the tangent to C3 and C5 in FIG. 3;

FIG. 6 is a schematic cross-sectional view of one embodiment of a power device of the present invention;

FIG. 7 is a schematic diagram of the doping concentration profile at the tangent line A-A' of the cross-sectional structure of the device of FIG. 6 according to the present invention;

FIG. 8 is a schematic diagram of an N-well fabrication step performed in one embodiment of a method for fabricating a power device according to the present invention;

FIG. 9 is a schematic diagram of a P-base region fabrication step performed in one embodiment of a method for fabricating a power device of the present invention;

FIG. 10 is a schematic diagram of a trench forming step performed in one embodiment of a method for forming a power device of the present invention;

FIG. 11 is a schematic diagram of a P-well implantation step performed in one embodiment of a method for fabricating a power device according to the present invention;

FIG. 12 is a schematic diagram of a gate oxide layer formation and polysilicon filling step performed in one embodiment of a method for forming a power device according to the present invention;

fig. 13 is a schematic diagram illustrating a step of forming an N + source region according to an embodiment of the method for forming a power device of the present invention;

FIG. 14 is a schematic diagram of a subsequent processing step performed in one embodiment of a method for fabricating a power device of the present invention;

FIG. 15 is a schematic illustration of a P-base region fabrication step performed in another embodiment of a method for fabricating a power device of the present invention;

fig. 16 is a schematic diagram of a trench manufacturing step performed in another embodiment of the method for manufacturing a power device of the present invention;

fig. 17 is a schematic diagram of an N-well implantation step in another embodiment of the method for manufacturing a power device of the present invention;

FIG. 18 is a schematic diagram of a high temperature drive-in and N-well formation step in another embodiment of a method for fabricating a power device of the present invention;

FIG. 19 is a schematic diagram of a second trench etching step performed in another embodiment of the method for fabricating a power device of the present invention;

fig. 20 is a schematic diagram of a P-well implantation step in another embodiment of the method for fabricating a power device of the present invention;

FIG. 21 is a schematic diagram of a gate oxide layer formation and polysilicon filling step performed in another embodiment of a method for forming a power device according to the present invention;

fig. 22 is a schematic diagram illustrating a step of forming an N + source region in another embodiment of the method for forming a power device of the present invention;

FIG. 23 is a schematic diagram illustrating a subsequent processing step performed in another embodiment of a method for fabricating a power device according to the present invention;

fig. 24 is a schematic cross-sectional view of another embodiment of a power device of the present invention;

fig. 25 is a schematic cross-sectional view of a third embodiment of the power device of the present invention;

fig. 26 is a schematic cross-sectional structure of a power device with dimensions indicated in a third embodiment of the present invention;

fig. 27 is a schematic cross-sectional view of a fourth embodiment of the power device of the present invention;

FIG. 28 is a schematic diagram showing the effect of diffusion junction depth of a P-well on electric field strength in the present invention;

FIG. 29 is a graph showing the effect of diffusion junction depth of a P-well on the on-state voltage drop in the present invention;

FIG. 30 is an enlarged, fragmentary view of FIG. 29 of the present invention;

FIG. 31 is a graph illustrating the effect of doping concentration of a P-well on the on-state voltage drop in the present invention;

FIG. 32 is an enlarged partial schematic view of FIG. 31 in accordance with the invention;

FIG. 33 is a schematic diagram showing the effect of doping concentration of P-well on voltage resistance in the present invention;

FIG. 34 is an enlarged, fragmentary view of FIG. 33 of the present invention;

fig. 35 is an enlarged view of a portion of a structure of a portion a of fig. 18;

in the figure: the transistor comprises a 1-N trap, a 2-N substrate, a 3-P-base region, a 4-polysilicon gate, a 5-N + source region, a 6-P trap, a 7-P + ohmic contact region, an 8-emitter metal electrode, a 9-gate oxide layer, a 10-photoresist, an 11-sacrificial oxide layer, a 12-collector metal electrode, a 13-N-enhancement layer, a 14-metal barrier layer, a 15-P + diffusion layer, a 16-emitter layer, a 17-N type carrier storage layer, a 20-effective grid and a 30-false grid.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention. It is to be understood that the described embodiments are merely a few embodiments of the invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

Referring to fig. 6 to fig. 35, a power device and a method for manufacturing the same according to an embodiment of the present invention are shown, and the present invention will be further described with reference to the drawings and the embodiment.

Example 1:

as shown in fig. 6, an embodiment of a power device includes: the power device comprises an N trap 1, an N-substrate 2, a P-base region 3, a polysilicon gate 4, an N + source region 5, a P + ohmic contact region 7, an emitter metal electrode 8 and a gate oxide layer 9, wherein the power device adopts a trench gate structure. The trench gate structure includes a conventional gate (effective gate) structure and a dummy gate structure, and the trench gate structure in this embodiment adopts the conventional gate structure. The P-base region 3, the N trap 1 and the N-substrate 2 are sequentially arranged from top to bottom. A P-base region 3, an N + source region 5, a P + ohmic contact region 7 and an emitter metal electrode 8 are formed on the upper portion of the N trap 1 between the two grooves, wherein the P-base region 3 is located on the upper portion of the N trap 1, the emitter metal electrode 8 is located in the middle between the two grooves, and the P + ohmic contact region 7 is located on the lower portion of the emitter metal electrode 8. The N + source region 5 is positioned at the upper part of the P-base region 3 and positioned at two sides of the emitter metal electrode 8. The trench further comprises a polysilicon gate 4 and a gate oxide layer 9 located outside the polysilicon gate 4. The front surface of the device comprises four times of doping, and in a cross-sectional view of a power device structure, an N + source region 5, a P-base region 3, an N trap 1 and a P trap 6 are sequentially arranged from top to bottom. The power device further comprises a P-well 6, wherein the P-well 6 surrounds the bottom of the trench gate structure. The P-well 6 has a peak doping concentration at the bottom of the trench to facilitate the implementation of this solution.

The P-well 6 reduces the electric field strength at the trench bottom by accelerating the depletion of carriers of the N-well 1 when the power device is off (in a withstand voltage state). Meanwhile, the doping concentration of the P well 6 is higher than that of the N well 1, so that the carriers of the N well 1 are completely exhausted in the pressure resistance process, and the pressure resistance performance of the device is optimal.

As shown in fig. 7, the doping concentration curves of the P-well 6 and the N-well 1 are connected, if the doping concentration curves of the P-well 6 and the N-well 1 are separated, the optimum voltage withstand of the device cannot be realized, and if the doping concentration curves of the two are crossed, the optimum on-state voltage drop of the device cannot be realized.

When the power device adopts a trench gate structure of an effective gate, two P wells 6 positioned at the bottom of the effective gate are separated, and an electronic path is provided when the device is conducted. The P-wells 6 are separated, that is, the P-wells 6 under two adjacent effective gates are isolated and not contacted with each other, that is, an electronic path is provided when the device is turned on, so that electrons injected from the emitter metal electrode 8 can enter the N-substrate 2 of the device (device) to participate in conductance modulation.

In order to improve the voltage endurance capability of the power device based on the high-concentration N well 1, in the present embodiment, a P well structure is introduced at the bottom of the trench, so that when the device is turned off (in a voltage endurance state), the depletion of N well carriers is accelerated, the electric field strength near the bottom of the trench is reduced, and the voltage endurance capability of the device is improved. The technical scheme described in embodiment 1 of the present invention solves the technical problem of the decrease in the withstand voltage characteristic of the device due to the high-concentration N-well, and solves the technical problems of high cost, large process difficulty, small doping concentration adjustment range, and the like of the conventional manufacturing process of the P-well, so that the device can still maintain a good withstand voltage characteristic under the high-concentration N-well, thereby optimizing the contradiction between the power consumption and the withstand voltage of the device.

Example 2:

the on-state voltage drop of the trench gate type IGBT decreases with the increase of the doping concentration of the N well (carrier storage layer) 1, but the increase of the doping concentration of the N well 1 is disadvantageous to the withstand voltage of the device, and the main weak point is the position of the trench bottom. However, the fabrication process of the P-well 6 has many difficulties, such as:

to realize a P-well structure, a high-energy ion implantation process may be used, but this may result in higher process costs. Meanwhile, the peak value of the doping concentration of the P-well 6 manufactured by the high-energy ion implantation process is limited, and a high-concentration P-well structure is difficult to obtain. In addition, a conventional diffusion process may also be employed, but the conventional diffusion process requires four diffusion dopings of the P-well 6, the N-well 1, the P-base region 3, and the N + source region 5 in sequence. This requires four diffusions within a few microns of junction depth, which is very difficult to process and difficult to co-optimize for four dopings, which will eventually result in a small concentration adjustment window for the P-well.

As shown in fig. 8 to 14, in an embodiment of the method for manufacturing the power device according to embodiment 1, the N-well 1 is manufactured by a conventional diffusion method, and the method includes the following steps:

s101: the N trap 1 is manufactured on the basis of an N-substrate 2, the whole device (silicon wafer) is injected by adopting a conventional diffusion method, and a high-temperature propelling process is carried out.

Step S101 further includes the following processes:

s1011: a sacrificial oxide layer (SiO) is formed on the front surface of the device on the basis of the N-substrate 2 by high-temperature oxidation₂Silicon dioxide) 11, the thickness of the sacrificial oxide layer 11 is 100 Å -600 Å, preferably 300 Å;

s1012: coating a layer of photoresist 10 on the sacrificial oxide layer 11, then carrying out exposure, and removing the photoresist 10 above the device effective area (cellular area) to form an N-well injection window;

s1013: performing N-type ion implantation, and removing the residual photoresist 10 on the surface of the device;

s1014: performing high temperature drive (diffusion process) to form N well 1, wherein the doping concentration of N well 1 is 1e16/cm³Of less than the order of magnitude, preferably 1e15/cm³The junction depth of the N well 1 is 3 μm to 8 μm, preferably 5 μm.

S102: and (3) manufacturing a P-base region 3 on the N trap 1, and doping and high-temperature propelling the P-base region 3 according to a conventional diffusion method.

Step S102 further includes the following processes:

s1021, manufacturing a sacrificial oxide layer 11 on the N well 1 (the front surface of the device) through high-temperature oxidation, wherein the thickness of the sacrificial oxide layer 11 is 100 Å -600 Å, preferably 300 Å;

s1022: a layer of photoresist 10 is coated on the sacrificial oxide layer 11, then exposure is carried out, and the upper part of the active area of the device is removed

A photoresist 10 (on the front side of the device) forms a P-base region injection window;

s1023: performing P-type ion implantation, removing the residual photoresist 10 on the surface of the device, and removing the residual photoresist on the surface of the device

A photoresist 10;

s1024: performing high-temperature propulsion (diffusion process) to finally form the P-base region 3, wherein the doping concentration of the P-base region 3 is 1e17/cm³Of order of magnitude or more, preferably 1e17/cm³The junction depth of the P-base region 3 is 3 μm to 8 μm, preferably 4 μm.

S103: and on the basis of the previous step, making a groove, including making a groove etching window and etching.

Step S103 further includes the following processes:

s1031: carrying out etching window modeling: coating a layer of photoresist 10, and then carrying out exposure and photoresist removal to form a groove etching window;

s1032: and etching the groove until the target depth is greater than or equal to the junction depth of the N well 1.

S104: p-well implantation is performed through the trench to form a P-well 6. Since the doping concentration of the P-well 6 is lower than that of the N + source region 5, a P-well implantation photolithography plate is not required, and the whole device wafer can be implanted. At this time, the high temperature advance may not be performed first, but the advance may be completed by using a high temperature process of a subsequent process.

Step S104 further includes the following processes:

s1041: carrying out P-type ion implantation on an active area (cellular area) of the device;

s1042: and performing high-temperature drive (diffusion process) to form a P well 6, wherein the doping concentration of the P well 6 is higher than that of the N well 1.

S105: and manufacturing a gate oxide layer 9 and filling polycrystalline silicon in the groove.

Step S105 further includes the following processes:

s1051: carrying out high-temperature oxidation to grow a layer of gate oxide layer 9 on the inner wall of the groove, wherein the thickness of the gate oxide layer 9 is 0.1-0.5 μm, preferably 0.1 μm;

s1052: performing polycrystalline silicon (Poly) deposition, wherein the polycrystalline silicon fills the inner part of the groove;

s1053: carrying out N-type doping on the polysilicon with the doping concentration of 1e19/cm³Of order of magnitude or more, preferably 1e20/cm³。

Step S1053 further includes the following processes:

S106: an N + source region 5 is formed between the two trenches, including N + source region implantation window formation, implantation and high temperature drive-in.

Step S106 further includes the following processes:

s1061: carrying out etching window modeling: coating a layer of photoresist 10, and then carrying out exposure and photoresist removal to form an N + source region injection window;

s1062: performing N-type ion implantation, and removing the residual photoresist 10;

s1063: performing high temperature drive to form an N + source region 5, wherein the doping concentration of the N + source region 5 is 1e19/cm³Of order of magnitude or more, preferably 1e20/cm³The junction depth of the N + source region 5 is 1 μm or less, preferably 0.5 μm.

S107: the fabrication of the P-well 6, the N-well 1, the P-base region 3, and the N + source region 5 is completed, and the subsequent process is consistent with the conventional fabrication process. Conventional processes in this section may be referred to specifically as: CN102945804B Chinese invention patent and other related manufacturing methods in the prior art.

In the specific embodiment 2 of the invention, the P-well structure is realized by the process of diffusion after groove etching, the diffusion doping of the P-well 6 is completed after the rest three times of diffusion, a photoetching plate is not required to be additionally added, and the process cost is lower than that of high-energy ion implantation. Meanwhile, the process difficulty is greatly reduced compared with that of the conventional four-time diffusion, the three-time doping concentration is not influenced, the three-time doping concentration is not required to be cooperatively optimized, the concentration of the P well 6 is very easy to adjust, and the adjusting window is large.

Example 3:

as shown in fig. 15 to 23, another specific embodiment of the method for manufacturing a power device according to embodiment 1 includes the following steps:

s201: and manufacturing the P-base region 3 on the basis of the N-substrate 2, and doping and high-temperature propelling the P-base region 3 according to a conventional diffusion method.

Step S201 further includes the following processes:

s2011, manufacturing a sacrificial oxide layer 11 on the front surface of the device on the basis of the N-substrate 2 through high-temperature oxidation, wherein the thickness of the sacrificial oxide layer 11 is 100 Å -600 Å, preferably 300 Å;

s2012: coating a layer of photoresist 10 on the sacrificial oxide layer 11, then carrying out exposure, and removing the photoresist 10 above an effective region (cellular region) of the device to form a P-base region injection window;

s2013: performing P-type ion implantation, and removing the residual photoresist 10 on the surface of the device;

s2014: performing high-temperature propulsion (diffusion process) to finally form the P-base region 3, wherein the doping concentration of the P-base region 3 is 1e17/cm³Of order of magnitude or more, preferably 1e17/cm³The junction depth of the P-base region 3 is 3 μm to 8 μm, preferably 3 μm.

S202: on the basis of the previous step, groove etching is carried out, wherein the groove etching comprises groove etching window manufacturing and etching, and the etching is carried out to the position of the peak concentration (first depth a) of the N well 1.

Step S202 further includes the following processes:

s2021: carrying out etching window modeling: coating a layer of photoresist 10, and then carrying out exposure and photoresist removal to form a groove etching window;

s2022: and etching the groove until the first depth a is larger than or equal to the junction depth of the P-base region 3.

S203: an N-well implant is performed through the trench. Since the concentration of the N-well 1 is lower than that of the N + source region 5 and is a shallow junction implant, the entire wafer (device) can be directly implanted without a reticle. Then, high temperature drive is performed to form an N well 1.

Step S203 further includes the following processes:

s2031: the whole device is implanted with N-type ions, and the whole silicon wafer (device) can be implanted without photoetching;

s2032: performing high temperature drive (diffusion process) to form N well 1, the doping concentration of N well 1 depends on design, but the concentration range can be large, and is generally 1e14/cm³～1e17/cm³In the order of magnitude range of (1 e 17/cm), preferably 1e17/cm³The junction depth of the N-well 1 is less than 3 μm, preferably 2 μm. Which is not possible with the conventional processes of the prior art.

S204: the trench etch is continued to the target depth.

Step S204 further includes the following processes:

s2041: carrying out etching window modeling: coating a layer of photoresist 10, and then carrying out exposure and photoresist removal to form a groove etching window;

s2042: the trench etching is performed until a second depth b, which is the designed depth of the trench, which is between 4 μm and 8 μm, preferably 6 μm.

S205: p-well implantation is performed through the trench to form a P-well 6. Since the doping concentration of the P-well 6 is lower than that of the N + source region 5, a P-well implantation photolithography plate is not required to be provided, and the whole silicon wafer can be implanted. At this time, the high temperature advance may not be performed first, but the advance may be completed by using a high temperature process of a subsequent process.

Step S205 further includes the following process:

and performing P-type ion implantation on the active region (cellular region) of the device, wherein the doping concentration of the P well 6 is lower than that of the N + source region 5. Here, instead of performing the high temperature advance, the advance is performed by a subsequent high temperature process (a high temperature process for the fabrication of the gate oxide layer 9).

S206: and manufacturing a gate oxide layer 9 and filling polycrystalline silicon in the groove.

Step S206 further includes:

s2061: carrying out high-temperature oxidation to grow a layer of gate oxide layer 9 on the inner wall of the groove, wherein the thickness of the gate oxide layer 9 is 0.1-0.5 μm, preferably 0.1 μm;

s2062: performing polycrystalline silicon (Poly) deposition, wherein the polycrystalline silicon fills the inner part of the groove;

s2063: carrying out N-type doping on the polysilicon with the doping concentration of 1e19/cm³Of order of magnitude or more, preferably 1e20/cm³。

Step S2063 further includes the following process:

S207: an N + source region 5 is formed between the two trenches, including N + source region implantation window formation, implantation and high temperature drive-in.

Step S207 further includes the following process:

s2071: carrying out etching window modeling: coating a layer of photoresist 10, and then carrying out exposure and photoresist removal to form an N + source region injection window;

s2072: performing N-type ion implantation, and removing the residual photoresist 10;

s2073: performing high temperature drive to form an N + source region 5, wherein the doping concentration of the N + source region 5 is 1e19/cm³Of order of magnitude or more, preferably 1e20/cm³The junction depth of the N + source region 5 is 1 μm or less, preferably 0.5 μm.

S208: the fabrication of the P-well 6, the N-well 1, the P-base region 3, and the N + source region 5 is completed, and the subsequent process is consistent with the conventional fabrication process. Conventional processes in this section may be referred to specifically as: CN102945804B Chinese invention patent and other related manufacturing methods in the prior art.

In the present embodiment, the distance L between the two trench centers of the trench gate structure is less than or equal to 2 μm to ensure that a high concentration of the N-well 1 can be achieved. In the embodiment, the N-well 1 is formed by lateral diffusion, and the too wide trench spacing is difficult to ensure that a laterally continuous N-well structure is realized under the condition of a small N-well junction depth.

In the present embodiment, the concentration of the N-well 1 is greater than the conventional concentration, and the doping concentration of the N-well 1 manufactured by the conventional process is usually 1e15/cm³Of no more than 1e16/cm³Magnitude. The doping concentration of the N-well 1 in the present embodiment can usually exceed 1e16/cm³In order of magnitude of 1e17/cm³Of the order of magnitude, even 1e18/cm³Magnitude.

In this embodiment, the concentration peak of the N well 1 is located at the first depth a of the trench, which is convenient for the power device to adopt the manufacturing process of diffusion doping after etching. The first depth a is equal to or slightly larger than the sum of the junction depth c of the P-base region 3 and the junction depth of the single-side diffusion of the N-well 1, so as to ensure the high-concentration doping of the N-well 1 and the concentration adjustment without influencing the P-base region 3. As shown in fig. 35, a is the first depth, c is the junction depth of the P-base region 3, d is the junction depth of the N-well 1, and e is the single-side diffusion junction depth of the N-well 1. When the first depth a = the junction depth c of the P-base region 3 + the single-side diffusion junction depth e of the N-well 1, the P-base region 3 is connected (connected) to the N-well 1. When the first depth a is larger than the junction depth c of the P-base region 3 + the single-side diffusion junction depth e of the N-well 1, the P-base region 3 is separated from (isolated from) the N-well 1.

Example 4:

when the trench gate structure of the power device comprises the effective gate 20 and more than two dummy gates 30 arranged at two sides of the effective gate 20, the P-well 6 at the bottom of the dummy gate 30 is separated from or connected with the P-well 6 at the bottom of the effective gate 20 adjacent to the dummy gate 30, and the P-well 6 at the bottom of the dummy gate 30 is separated from or connected with the P-well 6 at the bottom of another dummy gate 30 adjacent to the dummy gate 30. In embodiment 1 of the present invention, the P wells 6 at the bottom of the trenches of the conventional gate (effective gate) are separated from each other (providing an electronic path when the device is turned on), but in this embodiment, the P wells 6 at the bottom of the trenches of the dummy gate 30 are not limited and may be separated from each other, connected to each other, or intersected. The dummy gate 30 can be either floating or grounded in electrical connection. The floating is that the polysilicon in the dummy gate 30 is not extracted and is surrounded by a gate oxide layer (SiO)₂) And (4) surrounding. The grounding means that the polysilicon in the dummy gate 30 is extracted to the surface of the device to be connected with the emitter metal electrode 8 of the device. And the polysilicon in the effective gate 20 is led out to the surface of the device and connected with the gate electrode of the device. The N + source region 5 is not provided on either side of the dummy gate 30, and therefore the emitter metal electrode 8 is not provided on either side thereof. In terms of process implementation, the manufacturing method of the dummy gate 30 is the same as the manufacturing method of the effective gate 20, and the difference is that in the process of leading out the gate, the effective gate 20 is led out to the gate electrode of the device, and the dummy gate 30 is floated (not led out) or led out to the emitter metal electrode 8 of the device.

The dummy gate 30 can reduce the saturation current, and since the total channel width of the device is reduced, the saturation current can be reduced, and the short-circuit capability of the device can be adjusted. Meanwhile, due to the addition of the dummy gate 30, namely a field plate structure is arranged in the device, an electric field close to the surface of the device is pushed into the device, the problem of electric field concentration at the bottom of the effective gate 20 is solved, and the voltage resistance of the device is further improved.

As shown in fig. 24, for the case that the P wells 6 at the bottom of the dummy gate 30 are separated from each other, the manufacturing process can be as in

embodiments

2 and 3.

As shown in fig. 25, for the case that the dummy gate 30 and the trench lower P well 6 are connected to each other, the following two ways are needed.

As shown in fig. 26, if the distance L1 between two adjacent effective gates 20 (i.e., the distance between the centers of two adjacent effective gates 20) is greater than the distance L2 between an effective gate 20 and any adjacent other dummy gate 30 (i.e., the distance between the center of an effective gate 20 and the center of any adjacent other dummy gate 30) in a cell structure, i.e., L1 > L2, the manufacturing methods described in

embodiments

2 and 3 can still be used. By controlling the diffusion time of the P well 6, the connection of the P well 6 at the bottom of the dummy gate 30 can be realized, and the P well 6 at the bottom of the effective gate 20 is ensured to be separated. As shown in fig. 27, when the distance L1 between two adjacent effective gates 20 is greater than the distance L2 between an effective gate 20 and an adjacent dummy gate 30, and the distance L3 between two dummy gates 30 adjacent to each other (i.e., the distance between the centers of two dummy gates 30 adjacent to each other), i.e., L1 > L2= L3, the manufacturing methods described in embodiment 2 and embodiment 3 may still be adopted.

If L1 (the distance between two adjacent effective gates 20) = L2 (the distance between an effective gate 20 and an adjacent dummy gate 30) = L3 (the distance between two dummy gates 30 adjacent to each other) within one cell, the manufacturing methods described in

embodiments

2 and 3 cannot be employed, but the manufacturing methods of

embodiments

5 and 6 described below must be employed. First, the process of forming the P-well 6 is performed, and then other processes are performed, otherwise the P-wells 6 on the left and right sides are connected together, there is no isolation between the two effective gates 20, and thus no electron path can be formed.

Example 5:

an embodiment of the method for manufacturing a power device as described in embodiment 4 above, when the distance between the effective gates is equal to the distance between the dummy gate and the effective gate adjacent to the dummy gate, the method includes the following steps:

s111: p well 6 is made (diffused) on the basis of N-substrate 2;

s101: on the basis of the previous step, manufacturing an N well 1;

s102: manufacturing a P-base region 3 on the N trap 1;

s103: manufacturing a groove on the basis of the previous step;

s105: manufacturing a gate oxide layer 9 and filling polycrystalline silicon in the groove;

s106: manufacturing an N + source region 5 between the two grooves;

s107: and finishing the subsequent process.

Step S111 further includes the following processes:

s1111, manufacturing a sacrificial oxide layer 11 on the front surface of the device on the basis of the N-substrate 2 through high-temperature oxidation, wherein the thickness of the sacrificial oxide layer 11 is 100 Å -600 Å, preferably 300 Å;

s1112: coating a layer of photoresist 10 on the sacrificial oxide layer 11, then carrying out exposure, and removing the photoresist 10 above the device effective area (cellular area) to form a P-well injection window;

s1113: performing P-type ion implantation, and removing the residual photoresist 10 on the surface of the device;

s1114: performing high temperature drive (diffusion process) to form P well 6, wherein the doping concentration of P well 6 is 1e16/cm³Of less than the order of magnitude, preferably 1e15/cm³The junction depth of the P well 6 is 3 μm to 8 μm, preferably 8 μm.

Steps S101, S102, S103, S105, S106, and S107 in this embodiment are the same as steps S101, S102, S103, S105, S106, and S107 in embodiment 2.

Example 6:

another specific embodiment of the method for manufacturing a power device as described in embodiment 4 above, when the distance between the effective gates is equal to the distance between the dummy gate and the effective gate adjacent to the dummy gate, the method includes the following steps:

s211: manufacturing a P well 6 on the basis of the N-substrate 2;

s201: on the basis of the previous step, making a P-base region 3;

s202: etching a groove on the basis of the previous step;

s203: performing N-well injection through the groove to form an N-well 1;

s204: continuing to etch the groove until reaching the target depth;

s206: manufacturing a gate oxide layer 9 and filling polycrystalline silicon in the groove;

s207: manufacturing an N + source region 5 between the two grooves;

s208: and finishing the subsequent process.

Step S211 further includes the following processes:

s2111, manufacturing a sacrificial oxide layer 11 on the front surface of the device on the basis of the N-substrate 2 through high-temperature oxidation, wherein the thickness of the sacrificial oxide layer 11 is 100 Å -600 Å, preferably 300 Å;

s2112: coating a layer of photoresist 10 on the sacrificial oxide layer 11, then carrying out exposure, and removing the photoresist 10 above the device effective area to form a P well injection window;

s2113: performing P-type ion implantation, and removing the residual photoresist 10 on the surface of the device;

s2114: performing high temperature drive to finally form a P well 6, wherein the doping concentration of the P well 6 is 1e16/cm³Of less than the order of magnitude, preferably 1e16/cm³The junction depth of the P well 6 is 3 μm to 8 μm, preferably 8 μm.

Steps S201, S202, S203, S204, S206, S207 and S208 in this embodiment are the same as steps S201, S202, S203, S204, S206, S207 and S208 in embodiment 3.

As shown in fig. 28, 29 and 30, the influence of the diffusion junction depth of the P-well 6 on the on-state voltage drop and the withstand voltage of the device (device) is reflected. The structure of the P-well 6 can reduce the electric field intensity at the bottom of the trench of the power device, and the distance between the P-well 6 and the N-well 1 is reduced (1 x junction depth, 2x junction depth, 4x junction depth), which helps to reduce the electric field intensity, namely: the diffusion junction depth of the P-well 6 is increased, which is more favorable for reducing the electric field strength at the bottom of the trench of the device, as shown in fig. 28, which is the influence of the diffusion junction depth of the P-well 6 on the electric field strength, wherein C3: y =5um, Vce = 1800V.

The addition of the P-well 6 increases the on-state voltage drop of the device. When the junction depth of the P-well 6 is small (1 × junction depth) (the P-well 6 is separated from the N-well 1), the voltage drop is not as large as it would be without the P-well 6. As the junction depth of the P-well 6 increases until just after (2 x junction depth), the effect on the device on-state voltage drop increases, i.e., the on-state voltage drop increases. When the P-well 6 intersects the N-well 1 (4 x junction depth), the on-state voltage drop of the device increases more. I.e., the greater the diffusion junction depth of the P-well 6, the greater the on-state voltage drop of the device, as shown in fig. 29 and 30. Therefore, it can be concluded that the larger the diffusion junction depth of the P-well 6 is, the better the voltage endurance of the device is, but the larger the on-state voltage drop is.

As shown in fig. 31 to 34, the influence of the concentration change of the P well 6 on the on-state voltage drop and the withstand voltage of the device is reflected. Wherein, as shown in fig. 31 and 32, the doping concentration of the P-well 6 has an influence on the device voltage resistance, and the increase of the concentration of the P-well 6 slightly increases the on-state voltage drop of the device, but the increase is not large. As shown in fig. 31 and 32, the influence of the doping concentration of the P-well 6 on the on-state voltage drop of the device is small (slightly increased) and the influence of the concentration increase of the P-well 6 on the withstand voltage of the device is small. Therefore, it can be concluded that the concentration variation (within a certain range) of the P-well 6 has little influence on both the on-state voltage drop and the voltage resistance of the device, i.e. the doping concentration variation range of the P-well 6 is large.

By implementing the technical scheme of the power device and the manufacturing method thereof described in the specific embodiment of the invention, the following technical effects can be produced:

(1) the power device and the manufacturing method thereof described in the specific embodiment of the invention improve the voltage withstanding performance of the high-concentration N-well trench gate power device, and optimize the contradiction relationship between the on-state voltage drop (power consumption) and the voltage withstanding of the IGBT;

(2) the power device and the manufacturing method thereof described in the specific embodiment of the invention have the advantages that the process cost of the P well is lower than that of the high-energy ion implantation process;

(3) the power device and the manufacturing method thereof described in the embodiment of the invention have the advantages that the P-well diffusion process does not affect the concentration and junction depth of the N-well, the P-base region and the N + source region, and the process complexity and difficulty are reduced;

(4) the power device and the manufacturing method thereof described in the specific embodiment of the invention use the groove to perform self-aligned injection without adding a photolithography plate;

(5) the power device and the manufacturing method thereof described in the specific embodiment of the invention have the advantages that the concentration of the P well is easy to adjust, and the adjusting window range is large.

The embodiments in the present description are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other.

The foregoing is merely a preferred embodiment of the invention and is not intended to limit the invention in any manner. Although the present invention has been described with reference to the preferred embodiments, it is not intended to be limited thereto. Those skilled in the art can make many possible variations and modifications to the disclosed embodiments, or equivalent modifications, without departing from the spirit and scope of the invention, using the methods and techniques disclosed above. Therefore, any simple modification, equivalent replacement, equivalent change and modification made to the above embodiments according to the technical essence of the present invention are still within the protection scope of the technical solution of the present invention.

Claims

1. A method for manufacturing a power device is characterized in that when the distance between effective grid electrodes is equal to the distance between a false grid and the effective grid electrode which are adjacent to each other, the method comprises the following steps:

s111: p well manufacturing is carried out on the basis of the N-substrate;

s101: on the basis of the previous step, N-well manufacturing is carried out;

s102: manufacturing a P-base region on the N trap;

s103: manufacturing a groove on the basis of the previous step;

s106: manufacturing an N + source electrode region between the two grooves;

s107: and finishing the subsequent process.

2. The method for manufacturing a power device according to claim 1, wherein the step S111 further comprises:

s1114: performing high-temperature drive to finally form the P well, wherein the doping concentration of the P well is 1e16/cm³And the junction depth of the P well is 3-8 mu m below the magnitude level.

3. The method for manufacturing a power device according to claim 1 or 2, wherein the step S102 further comprises:

s1021, manufacturing a sacrificial oxide layer on the N well through high-temperature oxidation, wherein the thickness of the sacrificial oxide layer is 100 Å -600 Å;

Photoresist to form a P-base region injection window;

s1023: performing P-type ion implantation, removing the residual photoresist on the surface of the device, and removing the residual photoresist on the surface of the device

Gluing;

s1024: performing high-temperature propulsion to finally form the P-base region, wherein the doping concentration of the P-base region is 1e17/cm³Above the magnitude, the junction depth of the P-base region is 3-8 μm.

4. The method for manufacturing a power device according to claim 3, wherein the step S103 further comprises:

s1032: and etching the groove until the target depth is reached, wherein the target depth is greater than or equal to the junction depth of the N trap.

5. The method for manufacturing a power device according to claim 4, wherein the step S105 further comprises:

the step S1053 further includes:

6. The method for manufacturing a power device according to claim 4 or 5, wherein the step S106 further comprises:

7. A method for manufacturing a power device is characterized by comprising the following steps:

s201: manufacturing a P-base region on the basis of the N-substrate;

s202: etching a groove on the basis of the previous step;

s203: injecting an N well through the groove to form an N well;

s204: continuing to etch the groove until reaching the target depth;

s205: injecting a P well through the groove to form a P well;

s207: manufacturing an N + source electrode region between the two grooves;

s208: and finishing the subsequent process.

8. The method for manufacturing a power device according to claim 7, wherein the step S201 further comprises:

9. The method for manufacturing a power device according to claim 8, wherein the step S202 further comprises:

10. The method for manufacturing a power device according to claim 9, wherein the step S203 further comprises:

s2031: carrying out N-type ion implantation on the whole device;

11. The method for manufacturing a power device according to claim 10, wherein the step S204 further comprises:

12. The method for manufacturing a power device according to claim 7, wherein the step S205 further comprises:

13. The method for manufacturing a power device according to claim 10, 11 or 12, wherein the step S206 further comprises:

s2063: n-type doping is carried out on the polysilicon, and the doping concentration is 1e19/cm³Magnitude above;

the step S2063 further includes:

14. The method according to claim 13, wherein the step S207 further comprises:

15. A method for manufacturing a power device is characterized in that when the distance between effective grid electrodes is equal to the distance between two adjacent dummy grids and the effective grid electrodes, the method comprises the following steps:

s211: p well manufacturing is carried out on the basis of the N-substrate;

s202: etching a groove on the basis of the previous step;

s203: injecting an N well through the groove to form an N well;

s204: continuing to etch the groove until reaching the target depth;

s207: manufacturing an N + source electrode region between the two grooves;

s208: and finishing the subsequent process.

16. The method for manufacturing a power device according to claim 15, wherein the step S211 further comprises:

17. The method for manufacturing a power device according to claim 16, wherein the step S202 further comprises:

18. The method for manufacturing a power device according to claim 17, wherein the step S203 further comprises:

s2031: carrying out N-type ion implantation on the whole device;

19. The method for manufacturing a power device according to claim 18, wherein the step S204 further comprises:

20. The method for manufacturing a power device according to claim 15, wherein the step S205 further comprises:

21. The method for manufacturing a power device according to claim 18, 19 or 20, wherein the step S206 further comprises:

the step S2063 further includes:

22. The method of manufacturing a power device according to claim 21, wherein the step S207 further comprises:

23. A power device fabricated according to the method of any one of claims 1 to 22, comprising: the power device is characterized by further comprising a P trap, wherein the N + source region, the P-base region, the N trap and the P trap are sequentially arranged from top to bottom, and the P trap surrounds the bottom of a groove of the groove gate structure; when the trench gate structure of the power device comprises an effective gate and more than two dummy gates arranged at two sides of the effective gate, two P wells positioned at the bottom of the effective gate are separated, the P wells positioned at the bottoms of the dummy gates and the effective gate which are adjacent to each other are separated or connected, and the P wells positioned at the bottoms of the two dummy gates which are adjacent to each other are separated or connected.