JP5872621B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a technique that is effective when applied to a cell peripheral layout technique or a high breakdown voltage technique in a semiconductor device (or semiconductor integrated circuit device) and a method for manufacturing the semiconductor device (or semiconductor integrated circuit device).

Japanese Patent Application Publication No. 2007-116190 (Patent Document 1) or US Patent Publication No. 2005-098826 (Patent Document 2) Super-manufactured by a multi-epitaxy method or a trench insulating film embedding method (intra-trench ion implantation method) Various structures have been disclosed for the layout around the cell region of a power MOSFET (Metal Oxide Semiconductor Field Effect Transistor) having a junction structure. For example, a P ^- resurf region, a ring-shaped peripheral P-type drift region by a multi-epitaxy method, a linear peripheral P-type drift region of a vertical arrangement by a trench insulating film embedding method, and a linear peripheral P-type of a divided vertical / parallel arrangement Drift region and the like.

JP 2007-116190 A US Patent Publication No. 2005-098826

  With respect to the drift region of a power MOSFET or the like, the development of a high breakdown voltage FET or the like having a low on-resistance has been an important issue while avoiding the limitations due to the conventional silicon limit. Therefore, various methods for introducing a super junction structure having alternately a relatively high concentration Slab-like N-type column and P-type column in the drift region have been developed. There are roughly three types of methods for introducing this super junction structure: a multi-epitaxial method, a trench insulating film embedding method, and a trench fill method (trench filling method or trench epitaxial embedding method). ) Among these, the multi-epitaxial method in which epitaxial growth and ion implantation are repeated many times is expensive because the process is complicated due to the high degree of freedom of process and design. In the trench insulating film embedding method, after oblique ion implantation into the trench, the trench is embedded with a CVD (Chemical Vapor Deposition) insulating film, which is simpler in terms of process, but is disadvantageous in terms of area by the area of the trench. It becomes.

  On the other hand, the trench fill method has a merit that the process is simple although the degree of freedom of process and design is relatively low due to the limitation of the growth conditions of buried epitaxial growth. Accordingly, the inventors of the present application have examined device structures such as power MOSFETs and mass production regarding the high breakdown voltage & low on-resistance by the trench fill method, and it has become clear that there are the following problems. It was. That is, in the super junction structure, since the concentration of the main body cell portion (active region) is relatively high, the conventional peripheral termination structure (junction edge termination structure) or the resurf structure (reduced surface field) is used. It is difficult to ensure a breakdown voltage equal to or higher than that of the cell portion in the peripheral portion (peripheral region, junction termination region).

  The present invention has been made to solve these problems.

  An object of the present invention is to provide a semiconductor device such as a solid active element having a high breakdown voltage and a low on-resistance.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  The following is a brief description of an outline of typical inventions disclosed in the present application.

  That is, one invention of the present application is a semiconductor device including a power MOSFET having a super-junction structure formed by a trench fill method in a cell portion, and the drift region around the cell portion is along each side thereof. A super-junction structure having a proper orientation is provided.

  The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

  That is, in a semiconductor device including a power MOSFET having a super-junction structure formed by a trench fill method in a cell portion, a super-junction having an orientation along each side of the drift region around the cell portion. Since the structure is provided, it is possible to effectively prevent a decrease in breakdown voltage around the cell portion.

It is the whole chip plane layout figure in the device structure (two-dimensional resurf structure) of power MOSFET which is an example of the semiconductor device of one embodiment of this application. FIG. 3 is an enlarged plan layout view of a chip corner portion CR including an upper right end portion of a cell portion in a power MOSFET device structure (two-dimensional resurf structure) that is an example of a semiconductor device according to an embodiment of the present application; FIG. 3 is a cross-sectional view of a main part of the device corresponding to the A-A ′ cross section of FIG. 2 in a device structure (two-dimensional resurf structure) of a power MOSFET which is an example of a semiconductor device according to an embodiment of the present application; FIG. 3 is a cross-sectional view of a principal part of the device corresponding to the B-B ′ cross section of FIG. 2 in a device structure (two-dimensional resurf structure) of a power MOSFET that is an example of a semiconductor device according to an embodiment of the present application; It is a device principal part cross-section process flow figure (the hard mask film | membrane patterning process for P type column trench formation) of the wafer process in the manufacturing method of the semiconductor device of one embodiment of this application. It is a device principal part cross-section process flow figure (P type column trench formation process) of the wafer process in the manufacturing method of the semiconductor device of one embodiment of this application. It is a device principal part section process flow figure (P type buried epitaxial layer formation process) of a wafer process in a manufacturing method of a semiconductor device of one embodiment of this application. It is a device principal part cross-section process flow figure (CMP process to a P type buried epitaxial layer) of the wafer process in the manufacturing method of the semiconductor device of one embodiment of this application. It is a device principal part section process flow figure (P-type RESURF area | region introduction process) of the wafer process in the manufacturing method of the semiconductor device of one embodiment of this application. It is a device principal part cross-section process flow figure (P-type resurf area | region introduction resist film removal process) of the wafer process in the manufacturing method of the semiconductor device of one embodiment of this application. It is a device principal part cross-section process flow figure (gate polysilicon film formation process) of the wafer process in the manufacturing method of the semiconductor device of one embodiment of this application. It is a device principal part cross-section process flow figure (gate electrode patterning process) of the wafer process in the manufacturing method of the semiconductor device of one embodiment of this application. It is a device principal part cross-section process flow figure (P-type well area | region introduction process) of the wafer process in the manufacturing method of the semiconductor device of one embodiment of this application. It is a device principal part cross-section process flow figure (P-type well area | region introduction resist film removal process) of the wafer process in the manufacturing method of the semiconductor device of one embodiment of this application. It is a device principal part cross-section process flow figure (N + source region introduction | transduction process) of the wafer process in the manufacturing method of the semiconductor device of one embodiment of this application. It is a device principal part cross-section process flow figure (interlayer insulation film formation process) of the wafer process in the manufacturing method of the semiconductor device of one embodiment of this application. It is a device principal part cross-section process flow figure (source contact hole opening process) of the wafer process in the manufacturing method of the semiconductor device of one embodiment of this application. It is a device principal part section process flow figure (P + contact formation process to P type well field) of a wafer process in a manufacturing method of a semiconductor device of one embodiment of this application. FIG. 10 is an enlarged plan layout diagram of a chip corner portion CR including an upper right end portion of a cell portion in a power MOSFET device structure (three-dimensional resurf structure) which is an example of a semiconductor device according to another embodiment of the present application. FIG. 20 is a cross-sectional view of a principal part of a device corresponding to the A-A ′ cross section of FIG. 19 in a device structure (three-dimensional resurf structure) of a power MOSFET which is an example of a semiconductor device of another embodiment of the present application; FIG. 20 is a cross-sectional view of a principal part of a device corresponding to the B-B ′ cross section of FIG. 19 in a device structure (three-dimensional resurf structure) of a power MOSFET which is an example of a semiconductor device of another embodiment of the present application; Device main part schematic cross section substantially corresponding to FIG. 4, FIG. 21, etc. for explaining a modification (stepped shape) of the P-surface RESURF layer in each device structure of the power MOSFET of the semiconductor device of each embodiment of the present application FIG. FIG. 2 of a modified example (simple refraction type) of a super junction planar structure in a peripheral corner region in a power MOSFET device structure (two-dimensional resurf structure) as an example of a semiconductor device according to an embodiment of the present application FIG. 6 is an enlarged plan layout view of a chip corner portion CR including a cell portion upper right end corresponding to FIG. FIG. 2 is a modified example of a super junction plane structure of a peripheral corner region in a device structure (two-dimensional resurf structure) of a power MOSFET that is an example of a semiconductor device according to an embodiment of the present invention (cut off of a refractive part). 2 is an enlarged plan layout view of a chip corner portion CR including a right upper end portion of a cell portion corresponding to the above. The figure of the modification (super P type column type) of the super junction (Super Junction) plane structure of a peripheral corner area in the power MOSFET device structure (two-dimensional resurf structure) which is an example of the semiconductor device of one embodiment of this application It is an enlarged plan layout view of the chip corner portion CR including the upper right end portion of the cell portion corresponding to 2 etc. This corresponds to FIG. 3 and the like for additional explanation about application of a field plate to a device structure (two-dimensional resurf structure) of a power MOSFET which is an example of a semiconductor device according to an embodiment of the present application. FIG. 3 is a cross-sectional view of a main part of the device (substantially corresponding to the cross section AA ′ of FIG. 2). This corresponds to FIG. 4 and the like for additional explanation about application of a field plate to a device structure (two-dimensional resurf structure) of a power MOSFET which is an example of a semiconductor device according to an embodiment of the present application. FIG. 3 is a cross-sectional view of the main part of the device (corresponding substantially to the cross section BB ′ of FIG. 2). Corresponding to FIG. 20 and the like for additional explanation about application of a field plate to a device structure (three-dimensional resurf structure) of a power MOSFET which is an example of a semiconductor device of another embodiment of the present application FIG. 20 is a cross-sectional view of a principal part of the device (substantially corresponding to the cross section AA ′ of FIG. 19). Corresponding to FIG. 21 and the like for additional explanation about the application of a field plate to a device structure (three-dimensional RESURF structure) of a power MOSFET which is an example of a semiconductor device of another embodiment of the present application FIG. 20 is a cross-sectional view of the principal part of the device (substantially corresponding to the BB ′ cross-section of FIG. 19). Application of a floating field ring or a field limiting ring to a device structure (two-dimensional resurf structure) of a power MOSFET which is an example of a semiconductor device according to an embodiment of the present application FIG. 3 is an enlarged plan layout diagram of a chip corner portion CR including a cell portion upper right end portion corresponding to FIG. Application of a floating field ring or a field limiting ring to a device structure (two-dimensional resurf structure) of a power MOSFET which is an example of a semiconductor device according to an embodiment of the present application FIG. 3 is a cross-sectional view of a main part of the device corresponding to FIG. 3 and the like (substantially corresponding to the cross section AA ′ of FIG. 2) for additional explanation of the device. Application of a floating field ring or a field limiting ring to a device structure (two-dimensional resurf structure) of a power MOSFET which is an example of a semiconductor device according to an embodiment of the present application FIG. 5 is a cross-sectional view of a principal part of the device corresponding to FIG. Corresponding to FIG. 19 and the like for additional explanation about application of a field plate to a device structure (three-dimensional RESURF structure) of a power MOSFET which is an example of a semiconductor device of another embodiment of the present application FIG. 5 is an enlarged plan layout view of a chip corner portion CR including a cell portion upper right end portion to be performed. Corresponding to FIG. 20 and the like for additional explanation about application of a field plate to a device structure (three-dimensional resurf structure) of a power MOSFET which is an example of a semiconductor device of another embodiment of the present application FIG. 20 is a cross-sectional view of a principal part of the device (substantially corresponding to the cross section AA ′ of FIG. 19). Corresponding to FIG. 21 and the like for additional explanation about the application of a field plate to a device structure (three-dimensional RESURF structure) of a power MOSFET which is an example of a semiconductor device of another embodiment of the present application FIG. 20 is a cross-sectional view of the principal part of the device (substantially corresponding to the BB ′ cross-section of FIG. 19).

[Outline of Embodiment]
First, an outline of a typical embodiment of the invention disclosed in the present application will be described.

1. Semiconductor devices including:
(A) a semiconductor chip having a first main surface provided with a source electrode of a power MOSFET and a second main surface provided with a drain electrode of the power MOSFET;
(B) provided in a substantially central portion on the first main surface, and in a substantially rectangular cell region, a peripheral side region provided along each side of the cell region, and each corner portion of the cell region Peripheral corner area provided;
(C) a drift region of a first conductivity type provided in substantially the entire surface of the cell region, each peripheral side region, and each peripheral corner region on the first main surface side of the semiconductor chip;
(D) a first super-junction structure provided in the drift region and substantially over the entire cell region and having a first orientation;
(E) substantially the same as the first super-junction structure provided in the drift region of each peripheral side region on both sides of the cell region in a direction orthogonal to the first orientation of the first super-junction structure. Second and third super-junction structures having the same length and orientation;
(F) An orientation that is provided in the drift region of each peripheral side region on both sides of the cell region in the first orientation direction of the first super junction structure and is substantially orthogonal to the first super junction structure. Fourth and fifth super-junction structures having:

  2. In the semiconductor device according to the item 1, the first to fifth super-junction structures are based on a trench epitaxial filling method.

3. The semiconductor device according to item 1 or 2 further includes the following:
(G) A substantially L-shaped column group that connects each pair of columns constituting the second to fifth super-junction structures in each peripheral corner region.

  4). In the semiconductor device according to the item 3, each of the substantially L-shaped column groups presents a continuous figure that is refracted substantially at a right angle in the middle.

  5. In the semiconductor device according to the item 3, each of the substantially L-shaped column group presents a pair of continuous figures having an orthogonal orientation separated in the middle.

  6). 4. In the semiconductor device according to the item 3, each of the substantially L-shaped column group includes a pair of continuous figures having mutually perpendicular orientations separated in the middle, and an auxiliary placed near the outside of the closest part. It consists of a column.

  7). 7. In the semiconductor device according to any one of 1 to 6, in the surface region of the drift region on the first main surface side, at least a part of each peripheral side region or each peripheral corner region includes the cell. A surface resurf region is provided so as to surround the region.

  8). 8. In the semiconductor device according to any one of 1 to 7, a field plate extends above a part of the surface RESURF region.

  9. 9. The semiconductor device according to claim 1, wherein the cell is a surface region of the drift region on the first main surface side, wherein at least a part of each peripheral side region or each peripheral corner region includes the cell. One or more floating field rings are provided to surround the region.

  10. 10. The semiconductor device according to any one of 1 to 9, wherein the surface resurf region is divided into a plurality of regions.

11. Semiconductor devices including:
(A) a semiconductor chip having a first main surface provided with a source electrode of a power MOSFET and a second main surface provided with a drain electrode of the power MOSFET;
(B) provided in a substantially central portion on the first main surface, and in a substantially rectangular cell region, a peripheral side region provided along each side of the cell region, and each corner portion of the cell region Peripheral corner area provided;
(C) a drift region of a first conductivity type provided in substantially the entire surface of the cell region, each peripheral side region, and each peripheral corner region on the first main surface side of the semiconductor chip;
(D) a first super-junction structure provided in the drift region and substantially over the entire cell region and having a first orientation;
(E) The drift region of each peripheral side region on both sides of the cell region in the first orientation direction of the first super junction structure has substantially the same orientation as the first super junction structure. Second and third super junction structures;
(F) provided in the drift region of each peripheral side region on both sides of the cell region in a direction orthogonal to the first orientation of the first super junction structure, and substantially the same as the first super junction structure Fourth and fifth super-junction structures having orthogonal orientations.

  12 12. In the semiconductor device according to the item 11, the second and third super junction structures are connected to the first super junction structure.

  13. In the semiconductor device according to the item 11 or 12, the first to fifth super-junction structures are based on a trench epitaxial burying method.

  14 14. In the semiconductor device as described above in any one of 11 to 13, the fourth and fifth super-junction structures are provided so as to surround each peripheral corner region.

  15. 15. The semiconductor device according to any one of 11 to 14, wherein the cell is a surface region of the drift region on the first main surface side, and at least part of each peripheral side region or each peripheral corner region. A surface resurf region is provided so as to surround the region.

  16. 16. In the semiconductor device as described above in any one of 11 to 15, a field plate extends above a part of the surface RESURF region.

  17. 17. In the semiconductor device according to any one of 11 to 16, in the surface region of the drift region on the first main surface side, at least a part of each peripheral side region or each peripheral corner region includes the cell. One or more floating field rings are provided to surround the region.

  18. In the semiconductor device according to any one of items 11 to 17, the surface resurf region is divided into a plurality of regions.

19. A method for manufacturing a semiconductor device, the semiconductor device comprising:
(A) a semiconductor chip region on a wafer having a first main surface provided with a source electrode of a power MOSFET and a second main surface provided with a drain electrode of the power MOSFET;
(B) provided in a substantially central portion on the first main surface, and in a substantially rectangular cell region, a peripheral side region provided along each side of the cell region, and each corner portion of the cell region Peripheral corner area provided;
(C) a drift region of a first conductivity type provided in substantially the entire surface of the cell region, each peripheral side region, and each peripheral corner region on the first main surface side of the semiconductor chip;
(D) a first super-junction structure provided in the drift region and substantially over the entire cell region and having a first orientation;
(E) substantially the same as the first super-junction structure provided in the drift region of each peripheral side region on both sides of the cell region in a direction orthogonal to the first orientation of the first super-junction structure. Second and third super-junction structures having the same length and orientation;
(F) An orientation that is provided in the drift region of each peripheral side region on both sides of the cell region in the first orientation direction of the first super junction structure and is substantially orthogonal to the first super junction structure. Fourth and fifth super-junction structures having:
Here, in the manufacturing method, the first to fifth super junction structures are formed by a trench epitaxial filling method.

20. A method for manufacturing a semiconductor device, the semiconductor device comprising:
(A) a semiconductor chip region on a wafer having a first main surface provided with a source electrode of a power MOSFET and a second main surface provided with a drain electrode of the power MOSFET;
(B) provided in a substantially central portion on the first main surface, and in a substantially rectangular cell region, a peripheral side region provided along each side of the cell region, and each corner portion of the cell region Peripheral corner area provided;
(C) a drift region of a first conductivity type provided in substantially the entire surface of the cell region, each peripheral side region, and each peripheral corner region on the first main surface side of the semiconductor chip;
(D) a first super-junction structure provided in the drift region and substantially over the entire cell region and having a first orientation;
(E) Provided in connection with the first super junction structure in the drift region of each peripheral side region on both sides of the cell region in the first orientation direction of the first super junction structure. Second and third super junction structures having substantially the same length and orientation as the first super junction structure;
(F) provided in the drift region of each peripheral side region on both sides of the cell region in a direction orthogonal to the first orientation of the first super junction structure, and substantially the same as the first super junction structure Fourth and fifth super junction structures having orthogonal orientations;
Here, in the manufacturing method, the first to fifth super junction structures are formed by a trench epitaxial filling method.

  Next, an outline of another embodiment of the invention disclosed in the present application will be described.

1. Semiconductor devices including:
(A) a semiconductor chip having a first main surface provided with a source electrode of a power MOSFET and a second main surface provided with a drain electrode of the power MOSFET;
(B) a substantially rectangular cell region provided in a substantially central portion on the first main surface, and a cell peripheral region surrounding the cell region;
(C) a drift region of a first conductivity type provided in substantially the entire surface of the cell region and the cell peripheral region on the first main surface side of the semiconductor chip;
(D) a first super-junction structure provided in the drift region and substantially over the entire cell region and having a first orientation;
(E) substantially the same as the first super junction structure provided in the drift region of the cell peripheral region on both sides of the cell region in a direction orthogonal to the first orientation of the first super junction structure. Second and third super-junction structures having the same length and orientation;
(F) a fourth provided in the drift region in the cell peripheral region other than the portion where the second and third super junction structures are provided, and having an orientation substantially orthogonal to the first super junction structure; And a fifth super junction structure,
Here, the first to fifth super-junction structures are based on the trench epitaxial filling method.

  2. 2. The semiconductor device according to claim 1, wherein a surface resurf region is provided so as to surround the cell region in at least a part of the cell peripheral region, which is a surface region of the drift region on the first main surface side. It has been.

  3. In the semiconductor device of the above item 2, a field plate extends above a part of the surface RESURF region.

  4). 4. In the semiconductor device according to the item 2 or 3, the surface region of the drift region on the first main surface side, wherein at least a part of the cell peripheral region surrounds the cell region. Floating field rings are provided.

  5. 5. In the semiconductor device according to any one of 2 to 4, the surface resurf region is divided into a plurality of regions.

6). Semiconductor devices including:
(A) a semiconductor chip having a first main surface provided with a source electrode of a power MOSFET and a second main surface provided with a drain electrode of the power MOSFET;
(B) a substantially rectangular cell region provided in a substantially central portion on the first main surface, and a cell peripheral region surrounding the cell region;
(C) a drift region of a first conductivity type provided in substantially the entire surface of the cell region and the cell peripheral region on the first main surface side of the semiconductor chip;
(D) a first super-junction structure provided in the drift region and substantially over the entire cell region and having a first orientation;
(E) Provided in connection with the first super junction structure in the drift region of the cell peripheral region on both sides of the cell region in the first orientation direction of the first super junction structure. Second and third superjunction structures having substantially the same orientation as the first superjunction structure;
(F) a fourth provided in the drift region in the cell peripheral region other than the portion where the second and third super junction structures are provided, and having an orientation substantially orthogonal to the first super junction structure; And a fifth super junction structure,
Here, the first to fifth super-junction structures are based on the trench epitaxial filling method.

  7). 7. The semiconductor device according to claim 6, wherein a surface resurf region is provided in at least a part of the cell peripheral region so as to surround the cell region, in the surface region of the drift region on the first main surface side. It has been.

  8). 8. In the semiconductor device according to item 7, a field plate extends above a part of the surface RESURF region.

  9. 9. In the semiconductor device according to the item 7 or 8, the surface region of the drift region on the first main surface side, wherein at least a part of the cell peripheral region surrounds the cell region. Floating field rings are provided.

  10. In the semiconductor device according to any one of 7 to 9, the surface RESURF region is divided into a plurality of regions.

11. Semiconductor devices including:
(A) a semiconductor chip having a first main surface provided with a source electrode of a power MOSFET and a second main surface provided with a drain electrode of the power MOSFET;
(B) a substantially rectangular cell region provided in a substantially central portion on the first main surface, and a cell peripheral region surrounding the cell region;
(C) a drift region of a first conductivity type provided in substantially the entire surface of the cell region and the cell peripheral region on the first main surface side of the semiconductor chip;
(D) a first super-junction structure provided in the drift region and substantially over the entire cell region and having a first orientation;
(E) substantially the same as the first super junction structure provided in the drift region of the cell peripheral region on both sides of the cell region in a direction orthogonal to the first orientation of the first super junction structure. Second and third super-junction structures having the same length and orientation;
(F) Provided in the drift region of the cell peripheral region other than the portion where the second and third super junction structures are provided and the peripheral corner regions, and substantially orthogonal to the first super junction structure Fourth and fifth super-junction structures having orientation;
(G) In each peripheral corner region, a substantially L-shaped column group interconnecting each pair of columns constituting the second to fifth super-junction structures;
Here, the first to fifth super-junction structures are based on the trench epitaxial filling method.

  12 In the semiconductor device according to the item 11, each of the substantially L-shaped column groups presents a continuous figure that is refracted at a substantially right angle in the middle.

  13. 12. In the semiconductor device according to the item 11, each of the substantially L-shaped column group presents a pair of continuous figures having an orthogonal orientation separated in the middle.

  14 12. In the semiconductor device according to the item 11, each of the substantially L-shaped column group includes a pair of continuous figures having mutually orthogonal orientations separated in the middle, and an auxiliary placed near the outside of the closest part. It consists of a column.

  15. 15. In the semiconductor device as described above in any one of 11 to 14, the surface region of the drift region on the first main surface side so that at least a part of the cell peripheral region surrounds the cell region. A surface resurf region is provided.

  16. 16. In the semiconductor device as described above in 15, the field plate extends above a part of the surface resurf region.

  17. Item 15. The semiconductor device according to item 15 or 16, wherein at least part of the cell peripheral region is a surface region of the drift region on the first main surface side so as to surround the cell region. Floating field rings are provided.

  18. 18. In the semiconductor device as described above in any one of 15 to 17, the surface resurf region is divided into a plurality of regions.

19. A method for manufacturing a semiconductor device, the semiconductor device comprising:
(A) a semiconductor chip region on a wafer having a first main surface provided with a source electrode of a power MOSFET and a second main surface provided with a drain electrode of the power MOSFET;
(B) a substantially rectangular cell region provided in a substantially central portion on the first main surface, and a cell peripheral region surrounding the cell region;
(C) a drift region of a first conductivity type provided in substantially the entire surface of the cell region and the cell peripheral region on the first main surface side of the semiconductor chip region;
(D) a first super-junction structure provided in the drift region and substantially over the entire cell region and having a first orientation;
(E) substantially the same as the first super junction structure provided in the drift region of the cell peripheral region on both sides of the cell region in a direction orthogonal to the first orientation of the first super junction structure. Second and third super-junction structures having the same length and orientation;
(F) a fourth provided in the drift region in the cell peripheral region other than the portion where the second and third super junction structures are provided, and having an orientation substantially orthogonal to the first super junction structure; And a fifth super junction structure,
Here, in the manufacturing method, the first to fifth super junction structures are formed by a trench epitaxial filling method.

20. A method for manufacturing a semiconductor device, the semiconductor device comprising:
(A) a semiconductor chip region on a wafer having a first main surface provided with a source electrode of a power MOSFET and a second main surface provided with a drain electrode of the power MOSFET;
(B) a substantially rectangular cell region provided in a substantially central portion on the first main surface, and a cell peripheral region surrounding the cell region;
(C) a drift region of a first conductivity type provided in substantially the entire surface of the cell region and the cell peripheral region on the first main surface side of the semiconductor chip region;
(D) a first super-junction structure provided in the drift region and substantially over the entire cell region and having a first orientation;
(E) Provided in connection with the first super junction structure in the drift region of the cell peripheral region on both sides of the cell region in the first orientation direction of the first super junction structure. Second and third super junction structures having substantially the same length and orientation as the first super junction structure;
(F) a fourth provided in the drift region in the cell peripheral region other than the portion where the second and third super junction structures are provided, and having an orientation substantially orthogonal to the first super junction structure; And a fifth super junction structure,
Here, in the manufacturing method, the first to fifth super junction structures are formed by a trench epitaxial filling method.

[Description format, basic terms, usage in this application]
1. In the present application, the description of the embodiment may be divided into a plurality of sections for convenience, if necessary, but these are not independent from each other unless otherwise specified. Each part of a single example, one part is the other part of the details, or part or all of the modifications. Moreover, as a general rule, the same part is not repeated. In addition, each component in the embodiment is not indispensable unless specifically stated otherwise, unless it is theoretically limited to the number, and obviously not in context.

  Further, in the present application, the term “semiconductor device” mainly refers to various transistors (active elements) alone, or a device in which resistors, capacitors, etc. are integrated on a semiconductor chip or the like (for example, a single crystal silicon substrate). Say. Here, as a representative of various transistors, a MISFET (Metal Insulator Semiconductor Effect Transistor) typified by a MOSFET (Metal Oxide Field Effect Transistor) can be exemplified. At this time, typical examples of various single transistors include power MOSFETs and IGBTs (Insulated Gate Bipolar Transistors).

  2. Similarly, in the description of the embodiment and the like, the material, composition, etc. may be referred to as “X consisting of A”, etc., except when clearly stated otherwise and clearly from the context, except for A It does not exclude what makes an element one of the main components. For example, as for the component, it means “X containing A as a main component”. For example, “silicon member” is not limited to pure silicon, but also includes SiGe alloys, other multi-component alloys containing silicon as a main component, and members containing other additives. Needless to say. Similarly, “silicon oxide film”, “silicon oxide insulating film”, etc. are not only relatively pure undoped silicon oxide (FS), but also FSG (Fluorosilicate Glass), TEOS-based silicon oxide ( Thermal oxide films such as TEOS-based silicon oxide), SiOC (Silicon Oxicarbide) or carbon-doped silicon oxide or OSG (Organosilicate glass), PSG (Phosphorus Silicate Glass), BPSG (Borophosphosilicate Glass), CVD Oxide film, SOG (Spin ON Glass), nano-clustering silica (Nano-Clustering Silica: NCS), etc., coating system silicon oxide, silica-based low-k insulating film (porous) with pores introduced in the same material Needless to say, it includes a composite insulating film and other silicon-based insulating films having these as main components.

  In addition to silicon oxide insulating films, silicon nitride insulating films that are commonly used in the semiconductor field include silicon nitride insulating films. Materials belonging to this system include SiN, SiCN, SiNH, SiCNH, and the like. Here, “silicon nitride” includes both SiN and SiNH unless otherwise specified. Similarly, “SiCN” includes both SiCN and SiCNH, unless otherwise specified.

  Note that SiC has similar properties to SiN, but SiON is often rather classified as a silicon oxide insulating film.

  3. Similarly, suitable examples of graphics, positions, attributes, and the like are given, but it is needless to say that the present invention is not strictly limited to those cases unless explicitly stated otherwise, and unless otherwise apparent from the context.

  4). In addition, when a specific number or quantity is mentioned, a numerical value exceeding that specific number will be used unless specifically stated otherwise, unless theoretically limited to that number, or unless otherwise clearly indicated by the context. There may be a numerical value less than the specific numerical value.

  5. “Wafer” usually refers to a single crystal silicon wafer on which a semiconductor device (same as a semiconductor integrated circuit device and an electronic device) is formed, but an insulating substrate such as an epitaxial wafer, an SOI substrate, an LCD glass substrate, and the like. Needless to say, a composite wafer such as a semiconductor layer is also included.

  6). In general, a super-junction structure is formed by inserting column-type or plate-type column regions of opposite conductivity type into a semiconductor region of a certain conductivity type at substantially equal intervals so as to maintain charge balance. In this application, when referring to the “super-junction structure” by the trench-fill method, in principle, a certain conductive type semiconductor region has a plate shape of an opposite conductivity type (usually a plate shape but bent or refracted). May be inserted at substantially equal intervals so that the charge balance is maintained. In the embodiment, a case where P-type columns are formed in parallel at equal intervals on an N-type semiconductor layer (for example, a drift region) will be described.

  With respect to the super junction structure, “orientation” means that the P-type column or N-type column constituting the super junction structure is viewed two-dimensionally corresponding to the main surface of the chip (the main surface of the chip or wafer). In the plane parallel to).

  In the present application, regarding a resurf (Reduced Surface Field) structure or a junction edge termination structure, a junction edge extension or a surface resurf region (specifically, a resurf-type (specifically, a resurf-type)) is used. "Region") refers to a region of the same conductivity type formed in the surface region of the drift region and connected to the end of the P-type body region (P-type well region) constituting the channel region and having a lower impurity concentration. . Usually, it is formed in a ring shape so as to surround the cell portion. A field plate is a conductive film pattern connected to a source potential or an equivalent potential, and extends above the surface (device surface) of the drift region via an insulating film. The part surrounding the cell part in a ring shape. Furthermore, the floating field ring or the field limiting ring is separated from the P-type body region (P-type well region) on the surface of the drift region (device surface). An impurity region or a group of impurity regions having the same conductivity type and a similar concentration and surrounding a cell portion in a ring shape in a single or multiple manner.

[Details of the embodiment]
The embodiment will be further described in detail. In the drawings, the same or similar parts are denoted by the same or similar symbols or reference numerals, and description thereof will not be repeated in principle.

  In the accompanying drawings, hatching or the like may be omitted even in a cross section when it becomes complicated or when the distinction from the gap is clear. In relation to this, when it is clear from the description etc., the contour line of the background may be omitted even if the hole is planarly closed. Furthermore, even if it is not a cross section, it may be hatched to clearly indicate that it is not a void.

  For the convenience of illustration, the number of P-type columns shown in each figure is about 3 or 5 for the peripheral side region, etc., but may actually exceed about 10 in some cases. The example shown here will be described by taking an example with a breakdown voltage of about several hundred volts. In the following example, a product having a breakdown voltage of about several hundred volts (for example, 600 volts) will be described as an example.

1. Description of power MOSFET device structure (two-dimensional resurf structure) as an example of a semiconductor device according to an embodiment of the present application (mainly FIGS. 1 to 4)
Although the super junction structure is one of the RESURF structures, the RESURF structure described in this section is an explanation of the RESURF structure for the P-type surface layer formed on the surface of the bulk superjunction structure in the cell peripheral region. Since the P-type column extends in parallel to the corresponding side of the cell region in the cell peripheral region, the electric field direction applied to the depletion layer extending to the P-type surface layer has two other degrees of freedom. In other words, this type of resurf structure is called a two-dimensional resurf structure because it has a front direction from the back of the substrate and an internal direction from the chip edge to the device main surface.

  Next, the role of the two-dimensional RESURF structure will be described. In the trench fill method, since the buried epitaxial growth for forming the P column is performed by one epitaxial growth in both the cell region and the cell peripheral region, the impurity concentration of the P column is equal in both the cell region and the cell peripheral region. Therefore, the charge balance between the cell region and the cell peripheral region can be controlled by the P column width. As for the charge balance, the cell column and the cell peripheral region have the same P column width so that the breakdown voltage is not significantly reduced in the cell peripheral region as compared with the cell region, and the cell region and the cell peripheral region have the same charge balance. It is necessary to keep. However, by adjusting the charge balance of the bulk superjunction structure as described above, the breakdown voltage equal to or higher than that of the cell region cannot be obtained in the cell peripheral region. This is because the depletion layer includes peripheral side regions 4a, 4b, 4c, 4d adjacent to the four sides of the P-type well region 7 and the cell region 3, and peripheral corner regions corresponding to the corner portions of the chip 2 therebetween. This is because it terminates in a region sandwiched between 5a, 5b, 5c, and 5d, and the electric field concentrates in the vicinity of the end portion of the P-type well region 7. Therefore, the number of equipotential lines passing through to the N column surface is adjusted by providing a P-type surface RESURF region 8 on the surface of the peripheral region. When a bias is applied to the drain electrode 1b, the bulk superjunction begins to be depleted from the cell region, and the bulk superjunction structure in the peripheral region is also depleted radially from the cell region. At this time, if there is no P-type surface resurf region, the depletion layer terminated around the P-type well region 7 is depleted from the inside of the device main surface to the chip edge direction by the P-type surface resurf region. Extend. The P-type surface RESURF region can be designed so that the number of equipotential lines can evenly escape to the chip surface from the inside of the device main surface to the chip edge direction by appropriately controlling the impurity concentration. As a result, a breakdown voltage equal to or higher than that of the cell region can be secured in the cell peripheral region.

  FIG. 1 is a plan layout diagram of the entire chip in a device structure (two-dimensional resurf structure) of a power MOSFET which is an example of a semiconductor device according to an embodiment of the present application. FIG. 2 is an enlarged plan layout view of the chip corner portion CR including the upper right end portion of the cell portion in the power MOSFET device structure (two-dimensional resurf structure) which is an example of the semiconductor device according to the embodiment of the present application. FIG. 3 is a cross-sectional view of a principal part of the device corresponding to the A-A ′ cross section of FIG. 2 in the device structure (two-dimensional resurf structure) of the power MOSFET which is an example of the semiconductor device according to the embodiment of the present application. FIG. 4 is a cross-sectional view of a principal part of the device corresponding to the B-B ′ cross section of FIG. 2 in the device structure (two-dimensional RESURF structure) of the power MOSFET which is an example of the semiconductor device according to the embodiment of the present application. Based on these, a device structure (two-dimensional resurf structure) of a power MOSFET that is an example of a semiconductor device according to an embodiment of the present application will be described.

  As shown in FIG. 1 to FIG. 4 (mainly FIG. 1), the device main surface 1a (on the back surface 1b of the chip 1) of the semiconductor chip 2 (chip region, which is described here as an example of 3 mm square). The layout viewed from the (opposite surface) side is a substantially rectangular (square or rectangular) cell region (cell portion) 3 in the center, a ring-shaped cell peripheral region surrounding it, and the end of the chip 2 on the outer side. It consists of a ring-shaped tip end region and the like. The cell region 3 includes a linear repetitive gate electrode 9 which is a main part of the power MOSFET, and a P-type well region 7 (P-type body region) provided in the surface region of the N epitaxial layer 1e (drift region) so as to surround it. ), A super-junction structure composed of a large number of P-type columns 6i (that is, a first super-junction structure having a first orientation, a column thickness of about 4 micrometers, a column interval of about 6 micrometers), and the like. It is configured. The cell peripheral area includes peripheral side areas 4a, 4b, 4c and 4d adjacent to the four sides of the cell area 3, and peripheral corner areas 5a, 5b, 5c and 5d corresponding to the corner portions of the chip 2 therebetween. It is configured. In the chip end region, a ring-shaped N + channel stopper 18 and a ring-shaped guard ring electrode 11 (aluminum-based metal electrode) connected thereto are provided so that an undesired channel is not formed at the chip end. ing. A plurality of P-type columns 6b and 6d are provided in the N epitaxial layer 1e (drift region) of the peripheral side regions 4b and 4d in the peripheral region of the cell, similarly to the P-type column 6i (that is, the first The second and third super-junction structures having the following orientation: Column thickness of about 4 micrometers, column spacing of about 6 micrometers, distance from the end of the column belonging to the first super-junction structure For example, about 3 micrometers). The orientation and length of these P-type columns 6b and 6d are almost the same as those of the P-type column 6i. Of the cell peripheral areas, areas other than these, that is, an area connecting the peripheral side area 4a and the pair of peripheral corner areas 5a and 5b, and a peripheral side area 4c and the pair of peripheral corner areas 5c and 5d are connected. The N epitaxial layer 1e (drift region) in the region is provided with a plurality of P-type columns 6a and 6c (that is, fourth and fifth super junction structures having an orientation orthogonal to the first orientation). Is). The orientations of these P-type columns 6a and 6c are substantially orthogonal to the P-type column 6i.

  Next, details of the layout and the relationship with the vertical structure will be described based on FIG. 2 in which the chip corner portion CR including the upper right end portion of the cell portion in FIG. 1 is enlarged. This layout is line symmetric with respect to the center line (vertical and horizontal) of the chip and is subject to rotation by 180 degrees with respect to the center of the chip (extracting electrodes, source pads, gate pads, etc. do not necessarily have this objectivity. If the vicinity of one corner is described, it is almost equivalent to substantially explaining the entire chip 2. Therefore, in the following, the planar layout will be described mainly by taking the vicinity of the upper right part of the chip 2 as an example.

FIG. 3 shows the AA ′ cross section of FIG. As shown in FIG. 3, an N epitaxial layer 1e (drift region) is provided on an N + silicon single crystal substrate 1s, and P-type columns 6a and 6i are provided so as to penetrate vertically therethrough. A P + contact region 15 is provided in the P-type well region 7 (P-type body region) on the surface of the epitaxial layer 1e, to which a metal source electrode 14 is connected via a barrier metal or the like. Yes. A P-type surface RESURF region 8 having a lower concentration than that of the P-type well region 7 (impurity peak concentration is, for example, about 2 × 10 ¹⁶ / cm ³ , and its depth is usually higher than that of the P-type well region 7. Although it is shallow, the applicable range is about 10% to 150% of the depth) as an extension, and extends to, for example, the vicinity of the outermost P-type column. A field insulating film 16 or the like is provided on the surface of the N epitaxial layer 1e, and a gate electrode 9 (gate / polysilicon film) or the like is provided therein. In the chip end region, an N + channel stopper 18 and a ring-shaped guard ring electrode 11 connected to the N + channel stopper 18 are provided. In addition to these, a semiconductor region 12 corresponding to the P + body contact region of the chip edge portion. , Etc. are regions formed at the same time when impurities are introduced into the cell portion 3, and function as a channel stop or the like together with the N + channel stopper 18, the guard ring electrode 11, and the like.

  FIG. 4 shows a B-B ′ cross section of FIG. 2. As shown in FIG. 4, a gate insulating film 19 is provided below the gate polysilicon film 9, and an N + source region 21 is provided on the surface of the P-type body region 7 on both sides of the gate electrode 9. .

  Here, returning to FIG. 2, the necessity of such a layout will be described. In an element having a super-junction structure in the cell region 3, the on-resistance can be lowered while ensuring a vertical breakdown voltage (so-called bulk breakdown voltage). However, since the breakdown voltage of the entire device is rather determined at the peripheral portion, it is necessary to introduce a super junction structure also in the cell peripheral region. Since the depletion layer spreads in the cell peripheral region is almost radial with the cell region 3 as the center, in order to ensure a high breakdown voltage, the corresponding property is required. On the other hand, in the trench fill method, the planar shape of the P-type columns 6a, 6b, 6c, and 6d is limited to a figure composed of sides orthogonal to each other due to limitations due to the characteristics of epitaxial growth. The degree of freedom in which the depletion layer of the surface RESURF layer extends is determined by the electric field component applied to the depletion layer. That is, the electric field component is composed of two components in the front direction from the back of the substrate and the internal direction of the device main surface from the chip edge, and this type of resurf structure is called a two-dimensional resurf structure. The objectivity of the two-dimensional RESURF structure and the P-type column is the same in the peripheral side regions 4a, 4b, 4c, and 4d. Therefore, in the cell peripheral region, with respect to the P-type surface resurf structure, it is efficient to basically configure only the two-dimensional resurf structure to maintain the breakdown voltage of the cell peripheral region. Strictly speaking, in the peripheral corner regions 5a, 5b, 5c, and 5d, since the depletion layer itself is spread in a manner different from the target property of the peripheral side regions 4a, 4b, 4c, and 4d, a very high breakdown voltage is obtained. It doesn't matter unless it is required.

  Further improvements in the super junction structure in the peripheral corner areas 5a, 5b, 5c, 5d will be further described in section 5.

2. Description of essential parts of wafer process in manufacturing method of semiconductor device of one embodiment of the present application (mainly FIGS. 5 to 17)
In this section, a process corresponding to the structure of section 1 will be described. However, since these steps are basically common to other structures, the following description will not be repeated for other structures.

  FIG. 5 is a cross-sectional process flow diagram of a principal part of a wafer process (a hard mask film patterning step for forming a trench for a P-type column) in the method for manufacturing a semiconductor device according to an embodiment of the present application. FIG. 6 is a cross-sectional process flow diagram (P-type column trench forming process) of the device main part of the wafer process in the semiconductor device manufacturing method according to the embodiment of the present application. FIG. 7 is a cross-sectional process flow diagram of a principal part of a wafer process (P-type buried epitaxial layer forming step) in the method of manufacturing a semiconductor device according to the embodiment of the present application. FIG. 8 is a cross-sectional process flow diagram of a principal part of a wafer process in the method of manufacturing a semiconductor device according to the embodiment of the present application (planarization process to a P-type buried epitaxial layer). FIG. 9 is a cross-sectional process flow diagram of a principal part of a wafer process (P-type RESURF region introduction step) in the method of manufacturing a semiconductor device according to the embodiment of the present application. FIG. 10 is a cross-sectional process flow diagram of a principal part of a wafer process in the semiconductor device manufacturing method according to the embodiment of the present application (resist film removal process for introducing a P-type RESURF region). FIG. 11 is a cross-sectional process flow diagram (gate polysilicon film forming step) of the device main part of the wafer process in the semiconductor device manufacturing method according to the embodiment of the present application. FIG. 12 is a cross-sectional process flow diagram (gate electrode patterning step) of the principal part of the wafer process in the semiconductor device manufacturing method according to the embodiment of the present application. FIG. 13 is a cross-sectional process flow diagram of a principal part of a wafer process (P-type well region introducing step) in the method of manufacturing a semiconductor device according to the embodiment of the present application. FIG. 14 is a cross-sectional process flow diagram of a principal part of a wafer process (P-type well region diffusion step) in the method of manufacturing a semiconductor device according to the embodiment of the present application. FIG. 15 is a cross-sectional process flow diagram of an essential part of a wafer process (N + source region introduction step) in the method of manufacturing a semiconductor device according to the embodiment of the present application. FIG. 16 is a cross-sectional process flow diagram of an essential part of a wafer process (interlayer insulating film forming step) in the method of manufacturing a semiconductor device according to the embodiment of the present application. FIG. 17 is a cross-sectional process flow diagram (source contact hole opening process) of the principal part of the wafer process in the method of manufacturing a semiconductor device according to the embodiment of the present application. FIG. 18 is a cross-sectional process flow diagram of a principal part of a wafer process in a method for manufacturing a semiconductor device according to an embodiment of the present application (P + contact formation process to a P-type well region). Based on these, the main part of the wafer process in the method of manufacturing a semiconductor device according to an embodiment of the present application will be described.

First, as shown in FIG. 5, for example, N + silicon single crystal substrate 1s doped with antimony (for example, on the order of 10 ¹⁸ to 10 ¹⁹ / cm ³ ) (here, for example, a 200φ wafer, the wafer diameter is 150φ) , 300φ or 450φ), for example, a semiconductor wafer formed with a phosphorus-doped N epitaxial layer 1e having a thickness of about 45 micrometers (drift region, concentration is on the order of, for example, 10 ¹⁵ / cm ³ ). Prepare 1 On the device surface 1a (main surface opposite to the back surface 1b) of the semiconductor wafer 1, a P-type column trench forming hard mask film 31 made of, for example, P-TEOS (plasma-tetraethylorthosilicate) or the like is formed.

  Next, as shown in FIG. 6, by using the P-type column trench forming hard mask film 31 as a mask, the N epitaxial layer 1e and the like are dry-etched to form the P-type column trench 32. Subsequently, the unnecessary hard mask film 31 is removed.

Next, as shown in FIG. 7, buried epitaxial growth is performed on the P-type column trench 32 to form a P-type buried epitaxial layer 33 (concentration on the order of, for example, 10 ¹⁵ / cm ³ ). .

  Next, as shown in FIG. 8, the P-type buried epitaxial layer 33 outside the P-type column trench 32 is removed and the surface 1a of the semiconductor wafer 1 is flattened by a flattening step, for example, CMP (Chemical Mechanical Polishing). Turn into. Here, the super junction structure as shown in FIG. 8 may be formed by a multi-epitaxial method in addition to the trench fill method.

  Next, as shown in FIG. 9, a silicon oxide film 16 is formed on almost the entire surface 1a of the semiconductor wafer 1 by thermal oxidation, and a P-type RESURF region introduction resist film 22 is formed thereon by lithography. To do. Subsequently, using the P-type RESURF region introduction resist film 22 as a mask, the P-type surface RESURF region 8 is introduced by ion implantation (for example, boron). Thereafter, as shown in FIG. 10, the resist film 22 that is no longer needed is entirely removed.

  Next, as shown in FIG. 11, a gate oxide film 19 is formed on the surface 1a of the semiconductor wafer 1 by thermal oxidation (for example, wet oxidation at 950 degrees Celsius), on which the gate polysilicon film 9 is formed. Is formed by, for example, low pressure CVD (Chemical Vapor Deposition). As wafer cleaning before gate oxidation, for example, the first cleaning liquid, that is, ammonia: hydrogen peroxide: pure water = 1: 1: 5 (volume ratio), and the second cleaning liquid, that is, hydrochloric acid: hydrogen peroxide: Wet cleaning can be applied using pure water = 1: 1: 6 (volume ratio).

  Next, as shown in FIG. 12, the gate electrode 9 is patterned by dry etching.

Next, as shown in FIG. 13, a P-type well region introducing resist film 23 is formed by lithography. Subsequently, the P-type well region 7 (P-type body region) is introduced by ion implantation using the P-type well region introducing resist film 23 as a mask (concentration is, for example, about 10 ¹⁷ / cm ³ ). Thereafter, as shown in FIG. 14, the resist film 23 that is no longer needed is entirely removed.

Subsequently, as shown in FIG. 15, an N + source region introduction resist film 24 is formed by lithography, and using the resist film 24 as a mask, ion implantation (for example, arsenic) is used to form the N + source region 21 and the N + channel region at the chip edge portion. A semiconductor region 18 or the like corresponding to the stopper region is introduced (concentration is, for example, on the order of 10 ²⁰ / cm ³ ). Thereafter, the resist film 24 that is no longer needed is entirely removed.

  Next, as shown in FIG. 16, a PSG (Phospho-Silicate-Glass) film 25 (interlayer insulating film) is formed on almost the entire surface 1a of the semiconductor wafer 1 by CVD or the like (the SOG film is overlaid on the upper side). Flattening).

  Next, as shown in FIG. 17, a source contact hole opening resist film 26 is formed on the surface 1a of the semiconductor wafer 1, and using this as a mask, the source contact hole 27 and the like are formed by dry etching. To open. Subsequently, the resist film 26 that is no longer needed is entirely removed.

Thereafter, as shown in FIG. 18, after etching the silicon substrate, P + body contact regions 12 and 15 are introduced by ion implantation (for example, BF ₂ ) (concentration is, for example, on the order of 10 ¹⁹ / cm ³ ). degree). Further, as shown in FIGS. 3, 4 and others (for example, FIGS. 20 to 22, 26 to 29, 31, 32, 34 and 35), an aluminum-based metal layer is sputtered through a barrier metal film such as TiW. The metal source electrode 14, the guard ring electrode 11, and the like are formed by patterning and patterning.

3. Description of a device structure (three-dimensional resurf structure) of a power MOSFET which is an example of a semiconductor device according to another embodiment of the present application (mainly FIGS. 19 to 21)
In the RESURF structure described in this section, since the P-type column extends perpendicularly to the corresponding side of the cell region in the cell peripheral region, the degree of freedom in the direction of the electric field applied to the depletion layer extending to the P-type surface layer Since this has three degrees of freedom, that is, a direction parallel to the corresponding side of the cell region, a surface direction from the back of the substrate, and an internal direction of the device main surface from the chip edge, this type of resurf structure is This is called a three-dimensional resurf structure. Since the basic configuration of the device is almost the same as that in section 1, in principle, only different parts will be described below (the same applies to the following sections).

  FIG. 19 is an enlarged plan layout view of the chip corner portion CR including the upper right end portion of the cell portion in the power MOSFET device structure (three-dimensional resurf structure) as an example of the semiconductor device of another embodiment of the present application. FIG. 20 is a cross-sectional view of a principal part of the device corresponding to the A-A ′ cross section of FIG. 19 in the device structure (three-dimensional resurf structure) of a power MOSFET which is an example of a semiconductor device according to another embodiment of the present application. FIG. 21 is a cross-sectional view of a principal part of the device corresponding to the B-B ′ cross section of FIG. 19 in the device structure (three-dimensional resurf structure) of a power MOSFET which is an example of a semiconductor device according to another embodiment of the present application. Based on these, a device structure (three-dimensional resurf structure) of a power MOSFET that is an example of a semiconductor device according to another embodiment of the present application will be described.

  As shown in FIG. 19 to FIG. 21, the layout of the semiconductor chip 2 (chip area) viewed from the device main surface 1a (the surface opposite to the back surface 1b of the chip 1) is a substantially rectangular (square or rectangular) cell area. (Cell portion) 3, a ring-shaped cell peripheral region surrounding the cell portion, and a ring-shaped chip end region constituting the end portion of the chip 2 on the outside thereof. The cell region 3 includes a linear repetitive gate electrode 9 which is a main part of the power MOSFET, and a P-type well region 7 (P-type body region) provided in the surface region of the N epitaxial layer 1e (drift region) so as to surround it. ), A super-junction structure (that is, a first super-junction structure having a first orientation) composed of a large number of P-type columns 6i. The cell peripheral area includes peripheral side areas 4a, 4b (4c, 4d) adjacent to the four sides of the cell area 3, and peripheral corner areas 5a, 5b (5c, 5d) corresponding to the corner portions of the chip 2 between them. ). In the chip end region, a ring-shaped N + channel stopper 18 and a ring-shaped guard ring electrode 11 (aluminum-based metal electrode) connected thereto are provided so that an undesired channel is not formed at the chip end. ing.

  In the N epitaxial layer 1e (drift region) of the peripheral side region 4b and the peripheral corner region 5b in the cell peripheral region, a plurality of P-type columns 6b are provided in the same manner as the P-type column 6i (that is, the first 4th and 5th super-junction structures having an orientation perpendicular to the orientation of 1). A plurality of P-type columns obtained by extending the P-type column 6i in the cell region as they are are provided in the other regions of the cell peripheral region, that is, in the N epitaxial layer 1e (drift region) in the peripheral side region 4a. (Ie, second and third super junction structures having substantially the same orientation as the first orientation).

  FIG. 20 shows the A-A ′ cross section of FIG. 19. As shown in FIG. 20, an N epitaxial layer 1e (drift region) is provided on an N + silicon single crystal substrate 1s, and a P-type column 6i is provided so as to penetrate vertically therethrough. In the P-type well region 7 (P-type body region) on the surface of the epitaxial layer 1e, an N + contact region 15 is provided, to which a metal source electrode 14 is connected via a barrier metal or the like. Yes. A P-type surface RESURF region 8 having a lower concentration than that is provided as an extension in the P-type well region 7 and extends, for example, to the vicinity of the outermost P-type column. A field insulating film 16 or the like is provided on the surface of the N epitaxial layer 1e, and a gate electrode 9 (gate / polysilicon film) or the like is provided therein. In the chip end region, an N + channel stopper 18 and a ring-shaped guard ring electrode 11 connected to the N + channel stopper 18 are provided. In addition to these, a semiconductor region 12 corresponding to the P + body contact region of the chip edge portion. Is a region formed at the same time when impurities are introduced into the cell portion 3, and acts as a channel stop or the like as a whole together with the N + channel stopper 18, the guard ring electrode 11, and the like.

  FIG. 21 shows a B-B ′ cross section of FIG. 19. As shown in FIG. 21, a gate insulating film 19 is provided below the gate polysilicon film 9, and an N + source region 21 is provided on the surface of the P-type body region 7 on both sides of the gate electrode 9. . A P-type column 6b is provided so as to penetrate the drift region 1e vertically.

4). Description of Modification of Surface RESURF Layer in Each Device Structure of Power MOSFET of Semiconductor Device of Each Embodiment of the Present Application (Mainly FIG. 22)
The surface resurf layer described in each section is not essential for each example, but when applied, it has the effect of preventing a decrease in breakdown voltage when combined with other resurf structures. It goes without saying that the divided surface RESURF layer described in this section can be applied to each surface RESURF layer described in another example.

  FIG. 22 is a device component substantially corresponding to FIG. 4, FIG. 21 and the like for explaining a modified example (step shape) of the P-surface RESURF layer in each device structure of the power MOSFET of the semiconductor device of each embodiment of the present application. FIG. Based on this, a modification of the surface RESURF layer in each device structure of the power MOSFET of the semiconductor device of each embodiment of the present application will be described.

  As shown in FIG. 22, the feature of this example is that the P-type surface RESURF region 8 is divided into a plurality of regions 8a, 8b, 8c (divided P-type RESURF regions). Each divided P-type RESURF region 8a, 8b, 8c is set to be higher in density than 8b, 8c at 8a near the end of the chip where electric field concentration is likely to occur. Also, the diffusion layer depth of the P-RESURF layer can be set shallow from the end of the chip to the chip edge direction. By doing in this way, there exists a merit which can hold | maintain a high proof pressure with a comparatively small area compared with the case of a single surface resurf area | region.

5). Description of Modification of Super Junction Planar Structure of Peripheral Corner Region in Power MOSFET Device Structure (2-D Resurf Structure) which is an Example of Semiconductor Device of One Embodiment of the Present Application (Mainly from FIG. 23 25)
The corner correction structure described in this section prevents the relative breakdown voltage drop based on the imperfection of the super junction structure in the peripheral corner area. Of course, it is not essential. However, the application has an advantage that a relatively high breakdown voltage can be secured in a relatively small cell peripheral region. The two-dimensional resurf structure is particularly effective because it tends to require a relatively large area around the cell (because of the small degree of spatial freedom) in order to secure the same breakdown voltage as the three-dimensional resurf structure.

  FIG. 23 shows a modification (simple refraction type) of a super junction plane structure in a peripheral corner region in a power MOSFET device structure (two-dimensional resurf structure) as an example of a semiconductor device according to an embodiment of the present application. FIG. 3 is an enlarged plan layout view of a chip corner portion CR including a cell portion upper right end corresponding to FIG. 2 and the like. FIG. 24 is a modified example of a super junction plane structure of a peripheral corner region in a device structure (two-dimensional resurf structure) of a power MOSFET which is an example of a semiconductor device according to an embodiment of the present application (cut off type of refraction part). FIG. 3 is an enlarged plan layout diagram of a chip corner portion CR including an upper right end portion of a cell portion corresponding to FIG. FIG. 25 shows a modification of the super junction planar structure of the peripheral corner region in the device structure (two-dimensional resurf structure) of the power MOSFET which is an example of the semiconductor device according to the embodiment of the present application (auxiliary P type column type). 3) is an enlarged plan layout view of the chip corner portion CR including the upper right end portion of the cell portion corresponding to FIG. Based on these, a modification of the super junction planar structure of the peripheral corner region in the device structure (two-dimensional resurf structure) of the power MOSFET which is an example of the semiconductor device according to the embodiment of the present application will be described.

  FIG. 23 shows a first modification (simple refraction type). As shown in FIG. 23, unlike FIG. 2, the P-type columns 6 in the cell peripheral region are connected in a ring shape. That is, the P-type columns 6 a and 6 b in the peripheral side regions 4 a and 4 b are connected to each other by the substantially L-shaped column group 20. This structure is very simple and suitable for the process. However, there is a risk that the charge balance (excess and deficient portions of P-type charge appear near the refraction part) may be slightly disturbed around the refraction part. There is an example shown in FIG. 24 or FIG. 25 in which this point is further improved.

  FIG. 24 shows a second modification (refractive section cutting type). As shown in FIG. 24, compared to FIG. 23, the P-type columns 6a and 6b are cut off near the refracting portion. In this example, the normality is very simple and the process is excellent, but there is a tendency that the P-type charge is insufficient around the refractive part.

  FIG. 25 shows a third modification (auxiliary P-type column type). As shown in FIG. 25, compared with FIG. 23, the refracted portions of the P-type columns 6a and 6b are cut off (auxiliary P-type column in the peripheral corner region, that is, the auxiliary column 10), and slightly in the diagonal direction of the chip 2 The layout is shifted. Thereby, it is possible to maintain a good charge balance.

6). Description of application of field plate (mainly, FIG. 26 and FIG. 27) to a device structure (two-dimensional RESURF structure) of a power MOSFET which is an example of a semiconductor device according to an embodiment of the present application
In this example, the source metal electrode is extended to the outside to form a field plate. However, the metal electrode is connected to the floating field ring described in sections 8 and 9, and is connected to the outer insulating film. It may be stretched to form a field plate. It goes without saying that the field plates described here are applicable to the examples in sections 1, 4, 5 and 8.

  FIG. 26 is an additional diagram for explaining the application of a field plate to a device structure (two-dimensional RESURF structure) of a power MOSFET which is an example of a semiconductor device according to an embodiment of the present application. FIG. 3 is a cross-sectional view of a principal part of the device (corresponding substantially to the cross section AA ′ in FIG. 2). FIG. 27 is a diagram for additional explanation of application of a field plate to a device structure (two-dimensional RESURF structure) of a power MOSFET which is an example of a semiconductor device according to an embodiment of the present application. FIG. 3 is a cross-sectional view of a principal part of the device (corresponding substantially to the BB ′ cross section of FIG. 2) corresponding to FIG. Based on these, application of a field plate to a device structure (two-dimensional RESURF structure) of a power MOSFET which is an example of a semiconductor device according to an embodiment of the present application will be described.

  In this example, as shown in FIGS. 26 and 27, the metal source electrode 14 is extended above the P − -type surface RESURF region 8, and this portion is used as the field plate 28. The field plate 28 serves to alleviate unwanted electric field concentration in the vicinity of the end portion of the P-type well region 7.

7). Description of application of field plate (Field Plate) to power MOSFET device structure (three-dimensional RESURF structure) which is an example of a semiconductor device according to another embodiment of the present application (mainly FIG. 28 and FIG. 29)
In this example, the source metal electrode is extended to the outside to form a field plate. However, the metal electrode is connected to the floating field ring described in sections 8 and 9, and is connected to the outer insulating film. It may be stretched to form a field plate. It goes without saying that the field plates described here are applicable to the examples in sections 3 and 9.

  FIG. 28 is a diagram for additional explanation of application of a field plate to a device structure (three-dimensional resurf structure) of a power MOSFET which is an example of a semiconductor device according to another embodiment of the present application. FIG. 20 is a cross-sectional view of a principal part of the device (corresponding substantially to the cross section AA ′ in FIG. 19). FIG. 29 is a diagram for additional explanation of application of a field plate to a device structure (three-dimensional resurf structure) of a power MOSFET which is an example of a semiconductor device according to another embodiment of the present application. FIG. 20 is a cross-sectional view of an essential part of the device (corresponding substantially to the BB ′ cross section of FIG. 19). Based on these, application of a field plate (Field Plate) to a device structure (three-dimensional resurf structure) of a power MOSFET which is an example of a semiconductor device according to another embodiment of the present application will be described.

  Similar to Section 6, in this example, as shown in FIGS. 28 and 29, the metal source electrode 14 is extended above the P-type surface RESURF region 8 to use that portion as the field plate 28. ing. The field plate 28 serves to alleviate unwanted electric field concentration in the vicinity of the end portion of the P-type well region 7.

8). Application of a floating field ring or a field limiting ring to a device structure (two-dimensional resurf structure) of a power MOSFET which is an example of a semiconductor device according to an embodiment of the present application Explanation (mainly FIGS. 30 to 32)
It goes without saying that the field plate described here is applicable to the examples of sections 1, 4, 5 and 6.

  FIG. 30 shows a floating field ring or a field limiting ring to a device structure (two-dimensional resurf structure) of a power MOSFET which is an example of a semiconductor device according to an embodiment of the present application. 3 is an enlarged plan layout diagram of the chip corner portion CR including the upper right end portion of the cell portion corresponding to FIG. FIG. 31 shows a floating field ring or a field limiting ring to a device structure (two-dimensional resurf structure) of a power MOSFET which is an example of a semiconductor device according to an embodiment of the present application. 3 is a cross-sectional view of an essential part of the device corresponding to FIG. 3 and the like (substantially corresponding to the AA ′ cross-section of FIG. 2) for additional explanation of application of (). FIG. 32 shows a floating field ring or a field limiting ring to a device structure (two-dimensional resurf structure) of a power MOSFET which is an example of a semiconductor device according to an embodiment of the present application. FIG. 5 is a cross-sectional view of a main part of the device corresponding to FIG. 4 and the like (substantially corresponding to the BB ′ cross-section of FIG. 2) for additional explanation of application of (). Based on these, a floating field ring or a field limiting ring (Field field) to the device structure (two-dimensional resurf structure) of the power MOSFET which is an example of the semiconductor device according to the embodiment of the present application. The application of (Limiting Ring) will be described.

  In this example, as shown in FIGS. 30 to 32, the P-type column 6 and the P-type surface RESURF region 8 are substantially aligned with the P-type columns 6, 6a, 6b, 6c, and 6d near the cell region 3. Providing P-type surface impurity regions 29a, 29b, 29c (floating field rings) having a higher concentration has the advantage of promoting the growth of the depletion layer and dispersing the electric field concentration. The floating field rings 29a, 29b and 29c usually use the same impurity region as that of the P-type well region 7.

9. Floating Field Ring or Field Limiting Ring to Device Structure (Three-dimensional Resurf Structure) of Power MOSFET which is an Example of Semiconductor Device of Other Embodiment of this Application Application explanation (mainly FIGS. 33 to 35)
It goes without saying that the field plates described here are applicable to the examples in sections 3 and 7.

  FIG. 33 is a diagram for additional explanation of application of a field plate to a device structure (three-dimensional RESURF structure) of a power MOSFET which is an example of a semiconductor device according to another embodiment of the present application. 2 is an enlarged plan layout view of a chip corner portion CR including a right upper end portion of a cell portion corresponding to the above. FIG. 34 is a diagram for additional explanation of application of a field plate to a device structure (three-dimensional resurf structure) of a power MOSFET which is an example of a semiconductor device according to another embodiment of the present application. FIG. 20 is a cross-sectional view of a principal part of the device (corresponding substantially to the cross section AA ′ in FIG. 19). FIG. 35 is a diagram for additional explanation of the application of a field plate to a device structure (three-dimensional resurf structure) of a power MOSFET which is an example of a semiconductor device according to another embodiment of the present application. FIG. 20 is a cross-sectional view of an essential part of the device (corresponding substantially to the BB ′ cross section of FIG. 19). Based on these, a floating field ring or a field limiting ring to a device structure (three-dimensional resurf structure) of a power MOSFET which is an example of a semiconductor device of another embodiment of the present application ( Application of Field Limiting Ring) will be described.

  In this example, as shown in FIGS. 33 to 35, P-type surface impurity regions 29a having a higher concentration than the P-type column 6 and the P-type surface RESURF region 8 along the outer periphery of the P-type well region 7 are provided. Providing 29b and 29c (floating field ring) has the advantage of promoting the growth of the depletion layer and dispersing the electric field concentration. The floating field rings 29a, 29b and 29c usually use the same impurity region as that of the P-type well region 7.

10. Summary The invention made by the present inventor has been specifically described based on the embodiments. However, the present invention is not limited thereto, and it goes without saying that various changes can be made without departing from the scope of the invention.

  For example, in the above-described embodiment, the planar type MOS structure is specifically described as an example. However, the present invention is not limited thereto, and the trench type gate structure such as a U-MOSFET is exactly the same. Needless to say, it can be applied. In addition, the layout of the MOSFET is shown as an example in which stripes are arranged in parallel to the pn column. However, the MOSFET can be arranged in a direction orthogonal to the pn column, arranged in a lattice, or various applications.

  In the above embodiment, the N channel device is mainly formed on the upper surface of the N epitaxial layer on the N + silicon single crystal substrate. However, the present invention is not limited to this, and P + silicon is used. A P channel device may be formed on the upper surface of the N epitaxial layer on the single crystal substrate.

  In the above-described embodiment, the power MOSFET has been specifically described as an example. However, the present invention is not limited thereto, and the power device having a super junction structure, that is, a diode, a bipolar transistor, or the like is used. It goes without saying that is also applicable. Needless to say, the present invention can also be applied to a semiconductor integrated circuit device incorporating these power MOSFETs, diodes, bipolar transistors and the like.

  Furthermore, in the above-described embodiment, the trench fill method has been specifically described as a method for forming the super junction structure. However, the present invention is not limited thereto, and for example, a multi-epitaxial method may be used. Needless to say, it can be applied.

1 Semiconductor wafer 1a Wafer device surface (usually source side)
1b Wafer back side (usually drain side)
1e N epitaxial layer (drift region)
1s N + silicon single crystal substrate 2 chips (chip area)
3 Cell area (cell part)
4a, 4b, 4c, 4d Peripheral side region (in the cell peripheral region) 5a, 5b, 5c, 5d Peripheral corner region (in the cell peripheral region) 6, 6a, 6b, 6c, 6d P-type column in the peripheral side region 6i cell Region P-type column 7 P-type well region (P-type body region)
8, 8a, 8b, 8c P-type surface resurf region (divided P-type resurf region)
9 Gate electrode (gate polysilicon film)
10 Auxiliary P-type column (auxiliary column) in the peripheral corner area
11 Guard ring electrode 12 Semiconductor region corresponding to P + body contact region of chip edge portion 14 Metal source electrode 15 P + contact region (P + body contact region)
16 Field insulating film, etc. 18 Semiconductor region (N + channel stopper) corresponding to N + source / drain region of chip edge portion
19 Gate insulating film 20 Substantially L-shaped column group 21 N + source region 22 Resist film for introducing P-type RESURF region 23 Resist film for introducing P-type well region 24 N + Source region introducing resist film 25 Interlayer insulating film 26 Source contact Resist film for hole opening 27 Source contact hole 28 Field plate part 29a, 29b, 29c Floating field ring (field limiting ring)
31 P-type column trench formation hard mask film 32 P-type column trench 33 P-type buried epitaxial layer CR Chip corner portion including upper right end of cell portion

Claims (10)

A semiconductor substrate having a first end, a second end facing the first end, a third end, and a fourth end facing the third end;
A source electrode of a power MOSFET provided on the first main surface of the semiconductor substrate;
A drain electrode of the power MOSFET provided on a second main surface of the semiconductor substrate opposite to the first main surface;
A cell region provided on the first main surface;
A first peripheral side region provided between the cell region and the first edge;
A second peripheral side region provided between the cell region and the second end side;
A third peripheral side region provided between the cell region and the third end side;
A fourth peripheral side region provided between the cell region and the fourth end side;
A drift region of a first conductivity type formed in the semiconductor substrate and provided in the cell region and the first to fourth peripheral side regions;
A second conductivity type formed in the drift region of the first peripheral side region, extending in a first direction from the third end side to the fourth end side, and opposite to the first conductivity type; A plurality of configured first columns;
A plurality of second columns formed in the drift region of the second peripheral side region, extending in the first direction, and configured of the second conductivity type;
A plurality of thirds formed in the drift region of the third peripheral side region, extending in a second direction from the first end side toward the second end side, and configured by the second conductivity type; Columns,
A plurality of fourth columns formed in the drift region of the fourth peripheral side region, extending in the second direction, and configured of the second conductivity type;
A plurality of fifth columns formed in the drift region of the cell region, extending in the first direction, and configured of the second conductivity type;
The third peripheral side region is provided between the first peripheral side region, the second peripheral side region, and the cell region and the third end side,
The fourth peripheral side region is provided between the first peripheral side region, the second peripheral side region, and the cell region and the fourth end side,
In the cell region, the well region of the second conductivity type is formed on the surface of the drift region on the first main surface side and the surface of the fifth column,
A source region of the first conductivity type electrically connected to the source electrode is formed in the well region;
In the first to fourth peripheral side regions, the surface of the drift region on the first main surface side and the surface of the first to fourth columns are electrically connected to the well region so as to surround the cell region. A resurf region of the second conductivity type is provided ,
The impurity region having a higher impurity concentration than the RESURF region and the second conductivity type is formed at a position in contact with the RESURF region, the drift region, and the first to fourth columns.
The impurity region is formed along a direction in which the first and second columns extend in the first and second peripheral side regions, and the third region in the third and fourth peripheral side regions. And the fourth column is formed along the extending direction .   2. The semiconductor device according to claim 1, wherein the plurality of first to fifth columns are not integrated with each other and are physically separated by the drift region.   3. The semiconductor device according to claim 1, wherein the source electrode is disposed between the first to fourth end sides and the RESURF region so as to surround the first to fourth peripheral side regions. The guard ring electrode of the same layer is formed.   4. The semiconductor device according to claim 1, wherein an impurity concentration of the RESURF region is lower than an impurity concentration of the well region.   5. The semiconductor device according to claim 1, wherein a junction depth of the RESURF region is shallower than a junction depth of the well region.   6. The semiconductor device according to claim 1, wherein a field plate having the same potential as that of the source electrode is formed above the RESURF region. 7. The semiconductor device according to claim 1, wherein a junction depth of the impurity region is deeper than a junction depth of the RESURF region . The semiconductor device according to claim 1, wherein a plurality of the impurity regions are formed,
One of the plurality of impurity regions is in contact with one of the plurality of first columns;
One of the plurality of impurity regions is in contact with one of the plurality of second columns,
One of the plurality of impurity regions is in contact with one of the plurality of third columns;
One of the plurality of impurity regions is formed in contact with one of the plurality of fourth columns . 9. The semiconductor device according to claim 1, wherein the first conductivity type is an N type, and the second conductivity type is a P type . 10. The semiconductor device according to claim 1, wherein each of the plurality of first to fifth columns is configured by an epitaxial layer being embedded in a trench formed in the drift region. Yes .

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