JP2015046627A - Method for manufacturing semiconductor integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve the problem that, from result of study of a problem about a device structure such as a power MOSFET and mass production thereof, concerning high breakdown voltage and low on-resistance or the like using an epitaxy trench filling system, following problems was revealed a p-type column region does not become an ideal rectangular parallelepiped but become a narrower reverse trapezoidal shape as it goes downward further, and concentration distribution becomes thinner at a lower part, thereby the breakdown voltage cannot be obtained unexpectedly.SOLUTION: In a semiconductor device containing a power MOSFET section having a super junction structure formed in an active cell section by a trench philharmonic system, a base epitaxy layer is made as a multilevel structure having high impurity concentration in an upper part.

Description

  The present invention relates to a technique effective when applied to a device structure, a manufacturing process, and the like of a power semiconductor device (or a semiconductor integrated circuit device).

  Japanese Patent Application Laid-Open No. 2008-124346 (Patent Document 1) or US Pat. No. 7,642,597 (Patent Document 2) uses a multi-epitaxy method or an epitaxy trench filling method. An example of a power MOSFET (Metal Oxide Field Effect Transistor) having a semi-junction (Semi-Super Junction) structure in which a super junction structure is introduced partway through the drift region is disclosed. In this example, by forming an impurity profile in the P-type column region constituting the semi-superjunction structure so that the impurity concentration gradually decreases from the top to the bottom, the lower end of the buried field plate (Trench Field Plate) is formed. It is explained that the electric field concentration in the part is relaxed and high breakdown voltage characteristics and low on-resistance are achieved.

  Japanese Unexamined Patent Application Publication No. 2004-119611 (Patent Document 3) discloses an example of a power MOSFET having a semi-superjunction structure manufactured mainly using a multi-epitaxy method. In this example, an impurity profile in which the impurity concentration gradually increases from the upper side to the lower side is formed in the N-type column region constituting the semi-superjunction structure, so that the space between the N-type column region and the P-type column region is increased. There is an explanation to reduce the breakdown voltage caused by the charge imbalance.

  Japanese Patent Laid-Open No. 2008-258442 (Patent Document 4) or US Patent Publication No. 2008-246079 (Patent Document 5) discloses a power MOSFET having a semi-superjunction structure manufactured mainly using a multi-epitaxy method. An example is disclosed. In this example, a high impurity profile is formed in the central portion in the N-type column region and the P-type column region constituting the semi-superjunction structure, so that depletion at the upper and lower ends is facilitated, and the electric field at the portion is increased. An explanation is given to alleviate concentration.

  Japanese Patent Application Laid-Open No. 2008-91450 (Patent Document 6) or US Patent Publication No. 2008-237774 (Patent Document 7) discloses a power MOSFET having a semi-superjunction structure manufactured mainly using a multi-epitaxy method. An example is disclosed. In this example, by forming an impurity profile in the N-type column region and the P-type column region constituting the semi-superjunction structure so that the impurity concentration decreases stepwise from the upper side to the lower side, high breakdown voltage characteristics and It is explained that a low on-resistance is realized.

  Japanese Patent Laid-Open No. 2007-300034 (Patent Document 8) or US Patent Publication No. 2008-17897 (Patent Document 9) discloses a power MOSFET having a semi-superjunction structure that is mainly manufactured using an epitaxy trench filling method. An example is disclosed. In this example, the widths of the N-type column region and the P-type column region constituting the semi-superjunction structure are made different vertically (specifically, the width below the P-type column region is reduced), thereby There is an explanation that the diffusion of boron below is suppressed and the increase of the on-resistance is prevented.

  In Japanese Unexamined Patent Publication No. 2006-66421 (Patent Document 10) or US Pat. No. 7,420,245 (Patent Document 11), a super junction structure is introduced so as to penetrate the drift region, which is manufactured using a multi-epitaxy method. An example of a power MOSFET having a so-called Full-Super Junction structure (or simply referred to as “super-junction structure”) is disclosed. In this example, the N-type column region and the P-type column region constituting the super junction structure are each divided into two upper and lower sections, and the upper section is made high so that the N-type column region and the P-type column region are separated from each other. It is described that the breakdown voltage reduction due to the charge imbalance between the mold column regions is reduced.

JP 2008-124346 A U.S. Pat. No. 7,642,597 JP 2004-119611 A JP 2008-258442 A US Patent Publication No. 2008-246079 JP 2008-91450 A US Patent Publication No. 2008-237774 JP 2007-300034 A US Patent Publication No. 2008-17897 JP 2006-66421 A U.S. Pat. No. 7,420,245

  For drift regions such as power MOSFETs, the development of high breakdown voltage FETs with low on-resistance (for example, source drain breakdown voltage of about 650 volts or more) and the like is an important issue, avoiding the limitations due to the conventional silicon limit (Silicon Limit). ing. Therefore, various methods have been developed for introducing a super junction structure having alternately a relatively high concentration slab-like N-type column region and P-type column region in the drift region. There are roughly three types of methods for introducing this super junction structure, namely, a multi-epitaxy method, a trench insulating film embedding method, and an epitaxial trench filling method (trench fill method or trench epitaxy embedding method). Among these, the multi-epitaxy method in which epitaxial growth and ion implantation are repeated many times is expensive because the process becomes complicated due to the high degree of freedom in process and design. The trench insulating film embedding method is such that after oblique ion implantation into the trench, the trench (groove for embedding the P-type column region) is embedded with a CVD (Chemical Vapor Deposition) insulating film, and the process is simpler. The area is disadvantageous by the area of the trench.

  In contrast, the epitaxy trench filling method is to form a trench in the base epitaxial layer (referred to as “base epitaxy layer”), and embed and form a column region of opposite conductivity type therein by buried epitaxial growth. Although the degree of freedom of process and design is relatively low due to restrictions on the growth conditions of buried epitaxial growth, there is an advantage that the process is simple. Accordingly, the inventors of the present application have examined device structures such as power MOSFETs and mass production related to high breakdown voltage & low on-resistance by the epitaxial trench filling method, and it has become clear that there are the following problems. It was. That is, the P-type column region is not an ideal rectangular parallelepiped, and has a narrow inverted trapezoidal shape at the bottom, and the concentration distribution becomes thin at the bottom, so that a withstand voltage cannot be obtained unexpectedly.

  The present invention has been made to solve these problems.

  An object of the present invention is to provide a semiconductor device such as a power-type solid active element having a high breakdown voltage and a low on-resistance.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  The following is a brief description of an outline of typical inventions disclosed in the present application.

  That is, according to one aspect of the present invention, in a semiconductor device (power MOSFET, IGBT, etc.) including a power MOSFET portion having a superjunction structure formed by a trench fill method in an active cell portion, the upper side of the base epitaxy layer has an impurity concentration. It has a high multi-stage structure (including a two-stage structure).

  The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

  That is, in a semiconductor device including a power MOSFET portion having a super junction structure formed by a trench fill method in an active cell portion, a base epitaxy (Base Epitaxy) layer has a multistage structure (including a two-stage structure) with a high impurity concentration above. By doing so, it is possible to reduce the unbalance of the impurity concentration above and below the column.

1 is an overall top view of a semiconductor chip according to a first embodiment (common to the respective embodiments) of the present application. FIG. 2 is an enlarged plan view of an internal structure corresponding to an active cell end portion and a chip peripheral region cutout portion R1 in FIG. FIG. 3 is a device cross-sectional view corresponding to the A-A ′ cross section of FIGS. 1 and 2. FIG. 2 is an enlarged plan view of an internal structure corresponding to an active cell center cutout portion R2 in FIG. FIG. 3 is a device cross-sectional view corresponding to the B-B ′ cross section of FIGS. 1 and 2. FIG. 5 is an explanatory diagram of a charge distribution corresponding to a half pitch of the super junction structure of the drift region in the active cell region (the left side is an impurity region structure in the semiconductor substrate, the center is each charge distribution in the y direction, the right side is the y direction) Distribution of the absolute value of the electric field strength). FIG. 4 is a device sectional view showing a process flow corresponding to the device section of FIG. 3 (P-type column groove opening hard mask film patterning step). FIG. 4 is a device sectional view showing a process flow corresponding to the device section in FIG. 3 (P-type column groove opening step). FIG. 4 is a device cross-sectional view (epitaxy trench filling step) showing a process flow corresponding to the device cross-section of FIG. 3. FIG. 4 is a device cross-sectional view (planarization step) illustrating a process flow corresponding to the device cross-section of FIG. 3. FIG. 4 is a device sectional view showing a process flow corresponding to the device section in FIG. 3 (P-type RESURF region introducing step). FIG. 4 is a device cross-sectional view (field insulating film etching step) showing a process flow corresponding to the device cross-section of FIG. 3. FIG. 4 is a device sectional view showing a process flow corresponding to the device section in FIG. 3 (P-type body region introduction step). FIG. 4 is a device cross-sectional view (gate oxidation process) illustrating a process flow corresponding to the device cross-section of FIG. 3. FIG. 4 is a device cross-sectional view (gate polysilicon film forming step) showing a process flow corresponding to the device cross-section of FIG. 3. FIG. 4 is a device sectional view showing a process flow corresponding to the device section in FIG. 3 (gate polysilicon film patterning step). FIG. 4 is a device cross-sectional view (N + type source region introduction step) showing a process flow corresponding to the device cross section of FIG. 3. FIG. 4 is a device cross-sectional view (interlayer insulating film forming step) showing a process flow corresponding to the device cross-section of FIG. 3. FIG. 4 is a device cross-sectional view (contact hole forming step) showing a process flow corresponding to the device cross-section of FIG. 3. FIG. 4 is a device sectional view showing a process flow corresponding to the device section in FIG. 3 (P + type body contact region introducing step). FIG. 4 is a device cross-sectional view (aluminum-based metal electrode forming step) showing a process flow corresponding to the device cross-section of FIG. 3. FIG. 6 is a device sectional view showing a process flow corresponding to the device section in FIG. 5 (P-type column groove opening hard mask film patterning step). FIG. 6 is a device sectional view showing a process flow corresponding to the device section in FIG. 5 (P-type column groove opening step). FIG. 6 is a device cross-sectional view (epitaxy trench filling step) showing a process flow corresponding to the device cross-section of FIG. 5. FIG. 6 is a device cross-sectional view (planarization step) illustrating a process flow corresponding to the device cross-section of FIG. 5. FIG. 6 is a device sectional view showing a process flow corresponding to the device section in FIG. 5 (P-type body region introduction step). FIG. 6 is a device cross-sectional view (gate oxidation process) illustrating a process flow corresponding to the device cross-section of FIG. 5. FIG. 6 is a device cross-sectional view (gate polysilicon film forming step) showing a process flow corresponding to the device cross-section of FIG. 5. FIG. 6 is a device sectional view showing a process flow corresponding to the device section in FIG. 5 (gate polysilicon film patterning step). FIG. 6 is a device cross-sectional view (N + type source region introduction step) showing a process flow corresponding to the device cross section of FIG. 5. FIG. 6 is a device cross-sectional view (interlayer insulating film forming step) illustrating a process flow corresponding to the device cross-section of FIG. 5. FIG. 6 is a device cross-sectional view (contact hole forming step) illustrating a process flow corresponding to the device cross-section of FIG. 5. FIG. 6 is a device sectional view showing a process flow corresponding to the device section in FIG. 5 (P + type body contact region introducing step). FIG. 6 is a device cross-sectional view (aluminum-based metal electrode forming step) showing a process flow corresponding to the device cross-section of FIG. 5. FIG. 3 is a device cross-sectional view (second embodiment) corresponding to the B-B ′ cross-section of FIGS. 1 and 2. 35 is an explanatory diagram of a charge distribution corresponding to a half pitch of the super junction structure in the drift region in the active cell region shown in FIG. 35 (the impurity region structure in the semiconductor substrate on the left side, each charge distribution in the center in the y direction, and the right side in the y direction) Distribution of the absolute value of the electric field strength). FIG. 3 is a device cross-sectional view (third embodiment) corresponding to the B-B ′ cross-section of FIGS. 1 and 2. 37 is an explanatory diagram of a charge distribution corresponding to a half pitch of the super junction structure in the drift region in the active cell region shown in FIG. 37 (the impurity region structure in the semiconductor substrate on the left side, each charge distribution in the y direction, and the right side in the y direction) Distribution of the absolute value of the electric field strength). FIG. 4 is a device cross-sectional view (fourth embodiment) corresponding to the B-B ′ cross section of FIGS. 1 and 2. 39 is an explanatory diagram of a charge distribution corresponding to a half pitch of the super junction structure of the drift region in the active cell region shown in FIG. 39 (the impurity region structure in the semiconductor substrate on the left side, each charge distribution in the center in the y direction, and the right side in the y direction) Distribution of the absolute value of the electric field strength). FIG. 40 is a device cross-sectional view (P-type column groove opening hard mask film patterning step) showing a process flow (fourth embodiment) corresponding to the device cross section of FIG. 39; FIG. 40 is a device sectional view showing a process flow (fourth embodiment) corresponding to the device section in FIG. 39 (oblique ion implantation step into an N-type column region); FIG. 40 is a device sectional view (epitaxy trench filling process) showing a process flow (fourth embodiment) corresponding to the device section in FIG. 39; FIG. 40 is a device cross-sectional view (planarization step) illustrating a process flow (fourth embodiment) corresponding to the device cross-section of FIG. 39; FIG. 3 is a device sectional view corresponding to the B-B ′ section in FIGS. 1 and 2 (a trench type power MOSFET which is a modification of the first embodiment); FIG. 46 is a device cross-sectional view (P-type column groove opening hard mask film patterning step) showing a process flow (trench-type power MOSFET which is a modification of the first embodiment) corresponding to the device cross-section of FIG. 45; FIG. 46 is a device cross-sectional view (P-type column groove opening step) showing a process flow (trench-type power MOSFET which is a modification of the first embodiment) corresponding to the device cross-section of FIG. 45. FIG. 46 is a device cross-sectional view (epitaxy trench filling process) showing a process flow (trench power MOSFET which is a modification of the first embodiment) corresponding to the device cross-section of FIG. 45. FIG. 46 is a device cross-sectional view (planarization step) illustrating a process flow (trench-type power MOSFET that is a modification of the first embodiment) corresponding to the device cross-section of FIG. 45. FIG. 46 is a device cross-sectional view (insulating film hard mask removal step) illustrating a process flow (trench-type power MOSFET which is a modification of the first embodiment) corresponding to the device cross-section of FIG. 45; FIG. 46 is a device cross-sectional view (trench etch insulating film formation step) illustrating a process flow (trench power MOSFET which is a modification of the first embodiment) corresponding to the device cross-section of FIG. 45; 46 is a device cross-sectional view (trench etch insulating film formation anisotropic etch-back step) showing a process flow corresponding to the device cross-section of FIG. 45 (trench power MOSFET which is a modification of the first embodiment); FIG. FIG. 46 is a device cross-sectional view (gate trench etch process) showing a process flow corresponding to the device cross-section of FIG. 45 (trench power MOSFET which is a modification of the first embodiment). FIG. 46 is a device sectional view (gate oxidation step) showing a process flow (trench type power MOSFET which is a modification of the first embodiment) corresponding to the device section in FIG. 45; FIG. 46 is a device cross-sectional view (gate polysilicon film formation step) illustrating a process flow (trench type power MOSFET which is a modification of the first embodiment) corresponding to the device cross-section of FIG. 45; FIG. 46 is a device cross-sectional view (gate polysilicon film patterning step) illustrating a process flow (trench power MOSFET which is a modification of the first embodiment) corresponding to the device cross-section of FIG. 45; FIG. 46 is a device cross-sectional view (N + type source region introduction step) illustrating a process flow corresponding to the device cross section of FIG. 45 (a trench power MOSFET that is a modification of the first embodiment). FIG. 46 is a device cross-sectional view (interlayer insulating film formation step) illustrating a process flow (trench-type power MOSFET which is a modification of the first embodiment) corresponding to the device cross-section of FIG. 45. FIG. 46 is a device cross-sectional view (contact hole forming step) showing a process flow (trench type power MOSFET which is a modification of the first embodiment) corresponding to the device cross-section of FIG. 45. FIG. 46 is a device cross-sectional view (P + type body contact region introduction step) showing a process flow corresponding to the device cross section of FIG. 45 (trench type power MOSFET which is a modification of the first embodiment); FIG. 46 is a device cross-sectional view (aluminum-based metal electrode formation step) illustrating a process flow corresponding to the device cross-section of FIG. 45 (a trench type power MOSFET that is a modification of the first embodiment). FIG. 3 is a device cross-sectional view corresponding to the B-B ′ cross-section of FIGS. 1 and 2 (a trench type power MOSFET which is a modification of the second embodiment). FIG. 6 is a device cross-sectional view corresponding to the B-B ′ cross-section of FIGS. 1 and 2 (a trench type power MOSFET that is a modification of the third embodiment). FIG. 6 is a device sectional view corresponding to the B-B ′ section in FIGS. 1 and 2 (a trench type power MOSFET which is a modification of the fourth embodiment);

[Outline of Embodiment]
First, an outline of a typical embodiment of the invention disclosed in the present application will be described.

1. Semiconductor devices including:
(A) a semiconductor chip having a first main surface and a second main surface, on which a power MOSFET is formed;
(B) a source electrode of the power MOSFET provided on the first main surface side of the semiconductor chip;
(C) a drift region of the power MOSFET provided in the surface on the first main surface side of the semiconductor chip and having the first conductivity type;
(D) a plurality of trenches provided so as to penetrate the drift region from the first main surface side of the semiconductor chip;
(E) a plurality of second conductivity type column regions embedded in the plurality of trenches by epitaxial growth and having a second conductivity type opposite to the first conductivity type;
(F) a plurality of first conductivity type column regions having the first conductivity type which are between the plurality of second conductivity type column regions and constitute a super junction structure with them;
Here, each of the plurality of first conductivity type column regions includes the following:
(F1) a lower layer region having a first impurity concentration;
(F2) An upper layer region between the lower layer region and the first main surface and having a second impurity concentration that is higher than the first impurity concentration.

  2. In the semiconductor device of the item 1, the drift region is usually an epitaxy layer.

3. 3. In the semiconductor device according to item 1 or 2, each of the plurality of first conductivity type column regions further includes:
(F3) An intermediate layer region between the lower layer region and the upper layer region and having a third impurity concentration intermediate between the first impurity concentration and the second impurity concentration.

  4). 4. In the semiconductor device according to any one of items 1 to 3, when the first impurity concentration is based on the assumption that the first conductivity type column region is a single region, The first conductivity type column region has a concentration that maintains a charge balance.

  5. In the semiconductor device according to the item 1 or 2, the first impurity concentration is set such that when the first conductivity type column region is a single region, the second conductivity type column region and the first conductivity The concentration is lower than the concentration maintaining the charge balance with the mold column region.

  6). In the semiconductor device according to any one of 1 to 5, the concentration of the upper layer region is increased by ion implantation of the impurity having the first conductivity type.

  7). 7. In the semiconductor device according to any one of items 1 to 6, the semiconductor chip includes a silicon-based member as a main component.

  8). 8. The semiconductor device according to any one of 1 to 7, wherein the first conductivity type is an N type.

  9. 9. In the semiconductor device as described above in any one of 1 to 8, the semiconductor chip constitutes a single or composite power system active device.

  10. 10. In the semiconductor device as described above in any one of 1 to 9, the semiconductor chip constitutes a power MOSFET single device.

  11. 11. In the semiconductor device as described above in any one of 1 to 10, the power MOSFET is a planar type.

  12 11. The semiconductor device according to any one of 1 to 10, wherein the power MOSFET is a trench type.

  13. 13. In the semiconductor device as described above in any one of 1 to 12, the second conductivity type column region has an inverted trapezoidal shape having a wide width on the first main surface side.

  14 14. In the semiconductor device according to any one of Items 1, 2, and 4 to 13, the thickness of the lower layer region is larger than the thickness of the upper layer region.

  15. 14. In the semiconductor device according to any one of items 1, 2, and 4 to 13, the thickness of the lower layer region is smaller than the thickness of the upper layer region.

16. 16. The semiconductor device according to any one of items 1 to 15, further including:
(G) a second conductivity type body region having the second conductivity type formed in a surface region of the drift region on the first main surface side of the semiconductor chip and constituting a channel region of the power MOSFET;
(H) a gate insulating film formed on the surface of the second conductivity type body region on the first main surface side of the semiconductor chip;
(I) A gate electrode whose main component is a polysilicon film formed on the opposite side of the second conductivity type body region across the gate insulating film.

  17. In the semiconductor device of the item 16, the introduction of the second conductivity type body region is performed prior to the formation of the polysilicon film.

18. Semiconductor devices including:
(A) a semiconductor chip having a first main surface and a second main surface, on which a power MOSFET is formed;
(B) a source electrode of the power MOSFET provided on the first main surface side of the semiconductor chip;
(C) a drift region of the power MOSFET provided in the surface on the first main surface side of the semiconductor chip and having the first conductivity type;
(D) A plurality of second conductivity type column regions provided so as to penetrate the drift region from the first main surface side of the semiconductor chip and having a second conductivity type opposite to the first conductivity type. ;
(E) a plurality of first conductivity type column regions having the first conductivity type which are between the plurality of second conductivity type column regions and constitute a super junction structure with them;
(F) a second conductivity type body region having the second conductivity type formed in a surface region of the drift region on the first main surface side of the semiconductor chip and constituting a channel region of the power MOSFET;
(G) a gate insulating film formed on the surface of the second conductivity type body region on the first main surface side of the semiconductor chip;
(H) a gate electrode mainly comprising a polysilicon film formed on the opposite side of the second conductivity type body region across the gate insulating film;
Here, the introduction of the second conductivity type body region is performed prior to the formation of the polysilicon film.

19. In the semiconductor device of the item 18, each of the plurality of first conductivity type column regions includes the following:
(E1) a lower layer region having a first impurity concentration;
(E2) An upper layer region between the lower layer region and the first main surface and having a second impurity concentration higher than the first impurity concentration. In the semiconductor device of the item 18 or 19, the drift region is usually an epitaxy layer.

[Description format, basic terms, usage in this application]
1. In the present application, the description of the embodiment may be divided into a plurality of sections for convenience, if necessary, but these are not independent from each other unless otherwise specified. Each part of a single example, one part is the other part of the details, or part or all of the modifications. Moreover, as a general rule, the same part is not repeated. In addition, each component in the embodiment is not indispensable unless specifically stated otherwise, unless it is theoretically limited to the number, and obviously not in context.

  Furthermore, in the present application, the term “semiconductor device” mainly refers to various transistors (active elements) alone, or a resistor, a capacitor, etc., including a semiconductor chip (eg, a silicon-based member such as a single crystal silicon substrate). It refers to a single or composite power active device (generally a device capable of handling a power of several watts or more) integrated on a substrate (a device having a shape such as a rectangular plate). Here, as a representative of various transistors, a MISFET (Metal Insulator Semiconductor Effect Transistor) typified by a MOSFET (Metal Oxide Field Effect Transistor) can be exemplified. At this time, typical examples of various single transistors include power MOSFETs and IGBTs (Insulated Gate Bipolar Transistors).

  Note that power MOSFETs (IGBTs are basically the same) are roughly classified into vertical types and horizontal types, and these vertical power MOSFETs are further divided into a planar type and a trench type. In the present application, a planar power MOSFET and a trench power MOSFET will be specifically described.

  2. Similarly, in the description of the embodiment and the like, the material, composition, etc. may be referred to as “X consisting of A”, etc., except when clearly stated otherwise and clearly from the context, except for A It does not exclude what makes an element one of the main components. For example, as for the component, it means “X containing A as a main component”. For example, “silicon member” is not limited to pure silicon, but also includes SiGe alloys, other multi-component alloys containing silicon as a main component, and members containing other additives. Needless to say. Similarly, “silicon oxide film”, “silicon oxide insulating film”, etc. are not only relatively pure undoped silicon oxide (FS), but also FSG (Fluorosilicate Glass), TEOS-based silicon oxide ( Thermal oxide films such as TEOS-based silicon oxide), SiOC (Silicon Oxicarbide) or carbon-doped silicon oxide or OSG (Organosilicate glass), PSG (Phosphorus Silicate Glass), BPSG (Borophosphosilicate Glass), CVD Oxide film, SOG (Spin ON Glass), nano-clustering silica (Nano-Clustering Silica: NCS) and other coating-type silicon oxide, silica-based low-k insulating film (porous insulating) Needless to say, a film) and a composite film with other silicon-based insulating films including these as main constituent elements are included.

  In addition to silicon oxide insulating films, silicon nitride insulating films that are commonly used in the semiconductor field include silicon nitride insulating films. Materials belonging to this system include SiN, SiCN, SiNH, SiCNH, and the like. Here, “silicon nitride” includes both SiN and SiNH unless otherwise specified. Similarly, “SiCN” includes both SiCN and SiCNH, unless otherwise specified.

  Note that SiC has similar properties to SiN, but SiON is often rather classified as a silicon oxide insulating film.

  3. Similarly, suitable examples of graphics, positions, attributes, and the like are given, but it is needless to say that the present invention is not strictly limited to those cases unless explicitly stated otherwise, and unless otherwise apparent from the context.

  4). In addition, when a specific number or quantity is mentioned, a numerical value exceeding that specific number will be used unless specifically stated otherwise, unless theoretically limited to that number, or unless otherwise clearly indicated by the context. There may be a numerical value less than the specific numerical value.

  5. “Wafer” usually refers to a single crystal silicon wafer on which a semiconductor device (same as a semiconductor integrated circuit device and an electronic device) is formed, but an insulating substrate such as an epitaxial wafer, an SOI substrate, an LCD glass substrate, and the like. Needless to say, a composite wafer such as a semiconductor layer is also included.

  6). In general, a super junction structure is formed by inserting columnar or plate-like column regions of opposite conductivity type into a semiconductor region of a certain conductivity type at approximately equal intervals so that charge balance is maintained. In this application, when referring to the “super junction structure” by the trench fill method, in principle, a plate region of an opposite conductivity type is formed in a semiconductor region of a certain conductivity type (usually a plate shape, although it is bent or refracted). The “column area” of (good) is inserted at approximately equal intervals so that the charge balance is maintained. In the embodiment, a case where P-type columns are formed in parallel at equal intervals on an N-type semiconductor layer (for example, a drift region) will be described.

  In the present application, regarding a resurf (Reduced Surface Field) structure or a junction edge termination structure, a junction edge extension or a surface resurf area (specifically, a “P-type resurf”). Refers to a region of the same conductivity type that is formed in the surface region of the drift region and is connected to the end portion of the P-type body region (P-type well region) constituting the channel region and having a lower impurity concentration. Usually, it is formed in a ring shape so as to surround the cell portion. In the present application, the N type is referred to as a “first conductivity type” and the P type is referred to as a “second conductivity type”.

[Details of the embodiment]
The embodiment will be further described in detail. In the drawings, the same or similar parts are denoted by the same or similar symbols or reference numerals, and description thereof will not be repeated in principle.

  In the accompanying drawings, hatching or the like may be omitted even in a cross section when it becomes complicated or when the distinction from the gap is clear. In relation to this, when it is clear from the description etc., the contour line of the background may be omitted even if the hole is planarly closed. Furthermore, even if it is not a cross section, it may be hatched to clearly indicate that it is not a void.

  For the convenience of illustration, the number of P-type columns shown in each figure is about 3 or 5 for the peripheral side region, etc., but may actually exceed about 10 in some cases. The example shown here will be described by taking an example with a breakdown voltage of about several hundred volts. In the following example, a product having a withstand voltage of about several hundred volts (specifically, for example, 200 volts or 600 volts) will be described as an example.

  An example of a prior patent application that discloses a power MOSFET using a super junction structure is, for example, Japanese Patent Application No. 2009-263600 (Japanese filing date November 19, 2009).

  The following embodiment is basically a super junction structure in a vertical power device using a trench filling method in a drift region (in principle, it is difficult to form buried epitaxial regions by trench filling in multiple layers vertically). Introducing an epitaxial wafer (a normal non-buried epitaxy layer) epitaxy layer (ie, a normal or base epitaxy layer) is pre-multilayered (upper concentration is high) or selected as a single layer upward The high breakdown voltage is intended to be realized by providing a plurality of peaks in the electric field intensity distribution in the drift region by doping impurities in a high concentration layer. The total number of the multilayer structures is usually about 2 to 5 due to process limitations, but the concentration may be changed continuously.

  Viewed from another aspect, the structure shown here makes the base epitaxy layer multi-layered with the inevitable charge imbalance that comes from the fact that the column region is not an ideal rectangular parallelepiped and the cross section becomes trapezoidal or inverted trapezoidal. This is to compensate. That is, taking the case of the N-type base epitaxy layer as an example, the N-type column region becomes a trapezoid, the P-type column region becomes an inverted trapezoid, and the concentration is lowered below the P-type column region by diffusion by heat treatment in the buried epitaxy process. Progresses. Therefore, as it is, the horizontal plane density of the charge amount is monotonously increasing and decreasing monotonously from top to bottom, and the charge balance can be achieved only at the center, so the electric field strength distribution is a horizontal triangle and the withstand voltage is ideal. Compared to the rectangular distribution, it is greatly reduced. Thus, in each example shown here, the N-type column region is multilayered (including continuous changes; however, a finite layer is easier to create), so that the electric field strength distribution has a plurality of peaks, thereby obtaining a rectangular shape. It is close to the distribution. However, even in the case of the rectangular distribution, creating a high electric field region in the vicinity of the upper and lower ends is disadvantageous in terms of pressure resistance, so it is preferable to place a peak in the inner region.

1. Explanation of the device structure (N + / N type two-stage normal epitaxy system) of the planar power MOSFET which is an example of the semiconductor device according to the first embodiment of the present application (mainly FIGS. 1 to 6)
In this example, a planar power MOSFET manufactured on a silicon-based semiconductor substrate and having a source-drain breakdown voltage of about 600 volts will be described in detail. (The planar power MOSFET is the same in the following sections. However, it is needless to say that it can also be applied to power MOSFETs and other devices having other breakdown voltage values.

  FIG. 1 is an overall top view of a semiconductor chip (silicon-based member chip) according to a first embodiment (common to each embodiment) of the present application. FIG. 2 is an enlarged plan view of the internal structure corresponding to the active cell end portion and chip peripheral region cutout portion R1 in FIG. FIG. 3 is a device cross-sectional view corresponding to the cross section AA ′ of FIGS. 1 and 2 (The shape of the P-type column region is actually an inverted trapezoidal shape. Usually, the inclination of the side surface from the vertical is normal. Is about 89 to 89.5 degrees). FIG. 4 is an enlarged plan view of the internal structure corresponding to the active cell central cutout R2 in FIG. FIG. 5 is a device cross-sectional view corresponding to the B-B ′ cross section of FIGS. 1 and 2. 6 is an explanatory diagram of a charge distribution corresponding to a half pitch of the super junction structure of the drift region in the active cell region shown in FIG. 5 (the left side is an impurity region structure in a semiconductor substrate, the center is each charge distribution in the y direction, and the right side is (distribution of absolute value of electric field strength in y direction). Based on these, the device structure (N + / N type two-stage normal epitaxy system) of the planar type power MOSFET which is an example of the semiconductor device according to the first embodiment of the present application will be described.

  First, the overall layout of a chip (single or composite power system active device) will be described with reference to FIG. As shown in FIG. 1, a guard ring 3 is provided on the periphery of the chip 2, and a gate metal electrode 4 is provided on the inner side thereof. The center portion of the chip 2 is occupied by the source metal electrode 5, and an active cell region 6 is formed in almost the portion below the source metal electrode 5.

  Next, FIG. 2 shows an enlarged plan view of the semiconductor substrate surface region under the source metal electrode 5 in the cell edge portion and chip peripheral region cutout portion R1 of the chip 2 shown in FIG. As shown in FIG. 2, an outermost peripheral P + type region 7 is formed outside the guard ring 3 and is usually connected to a drain potential via an N + type channel stopper region 8. A region inside the guard ring 3 is divided into an active cell region 6 and an edge termination region 15 (cell peripheral region). In the N-type silicon epitaxial layer 1n of these regions, P-type is alternately and periodically. A column region 9 and an N-type column region 10 are provided. In the surface layer portion of the edge termination region 15, a P-type resurf region 14 (of course, these are not essential) is provided to alleviate electric field concentration on the surface. On the other hand, a polysilicon gate electrode 11 is disposed on the surface of the semiconductor substrate in the active cell region 6, and a P-type body constituting a channel region or the like so as to partially overlap the polysilicon gate electrode 11. Region 12 is provided.

  Next, FIG. 3 shows a device sectional view corresponding to the section A-A ′ of FIG. 2. As shown in FIG. 3, a semiconductor substrate 1 on which this device is formed has an N + type single crystal silicon substrate 1s (on the back surface 1b side of the semiconductor substrate 1), an N type lower layer silicon epitaxial layer 1t and an N type upper layer silicon epitaxial layer. Two normal epitaxy layers 1n made of 1d are formed. Therefore, the N-type upper layer column region 10d constituting the N-type column region 10 is a part of the N-type upper layer silicon epitaxial layer 1d, and similarly, the N-type lower layer column region 10t constituting the N-type column region 10 is This is a part of the N-type lower silicon epitaxial layer 1t. A field insulating film 16 and a gate insulating film 21 are provided on the surface 1 a side of the semiconductor substrate 1, and a polysilicon gate electrode 11 is provided on the gate insulating film 21. An interlayer insulating film 17 is provided so as to cover the field insulating film 16 and the polysilicon gate electrode 11, and an N + type is formed in a surface region on the surface 1 a side of the semiconductor substrate 1 in a self-aligning manner with the polysilicon gate electrode 11. A source region 19 is provided (note that the N + type channel stopper region 8 is usually formed simultaneously with this step). A P + type body contact region 18 is provided in the surface region on the surface 1a side of the semiconductor substrate 1 corresponding to the contact hole opened in the interlayer insulating film 17 around the polysilicon gate electrode 11. The outermost peripheral P + type region 7 is usually formed simultaneously with this step. Further, a guard ring 3 and a source metal electrode 5 composed of a barrier metal film and an aluminum-based metal electrode film are formed on the interlayer insulating film 17, and a P-type body at the end of the active cell region 6 is formed. From the vicinity of the outer edge of the region 12 to the outside is a cell peripheral region 15.

  Next, FIG. 4 shows an enlarged plan view of the semiconductor substrate surface region under the cell center cutout portion R2 of the chip 2 shown in FIG. As shown in FIG. 4, the active cell region 6 is laid out with a translational property (periodicity) in the lateral direction, and each includes a plurality of linear or belt-like P-type column regions 9, N-type column regions 10, P-type body region 12, polysilicon gate electrode 11 and the like are repeatedly provided.

  Next, FIG. 5 shows a B-B ′ cross section in FIG. 4. As shown in FIG. 5, the semiconductor substrate 1 has an N-type silicon epitaxial layer 1n (in the function as a device, a drift region 30) on an N + type single crystal silicon substrate 1s. Are periodically embedded with a plurality of P-type column regions 9 therethrough. The N-type silicon epitaxial layer 1n between the P-type column regions 9 functions as an N-type column region 10, and each N-type column region 10 includes an N-type lower layer column region 10t and an N-type upper layer column region 10d. Has been. In this example, the impurity concentration of the N-type lower layer column region 10t is a concentration that maintains a charge balance with the P-type column region 9 (this donor concentration is expressed as “Nd”, but corresponds to the concentration notation other than the column). Is not set). On the other hand, the impurity concentration in the N-type upper column region 10d is slightly higher than the impurity concentration in the N-type lower column region 10t (this donor concentration is expressed as “Nd +”, but corresponds to the concentration notation other than the column). Is not set). Note that the impurity concentration Na of the P-type column region 9 is normally set constant. However, in reality, the lower part tends to become thinner due to the heat treatment time.

Next, FIG. 6 shows an electrical structure of the semiconductor substrate 1 in the cell structure of FIG. In FIG. 6, the left side of the figure is an impurity structure (half pitch of repetition period), the center is charge distribution (half pitch of repetition period), and the right side is electric field intensity distribution (P-type column region 9 and N-type column region 10. The absolute value of the electric field intensity in the vicinity of the boundary and in the vicinity of the extension line). As shown in FIG. 6, the width Lp, y of the P-type column region 9 is a taper shape that becomes narrower toward the lower side, and the width Ln, y of the N-type column region 10 is conversely the upper side. It has a tapered shape that becomes thinner. As a result, the donor distribution Qn (y) and the acceptor in the minimum target unit region (left side in FIG. 6) between the vertical center plane of the P-type column region 9 that is a symmetry plane and the vertical center plane of the N-type column region 10 that is close to the symmetry plane. Distribution Qp (y) (where the area surrounded by the polygonal line and the Y-axis is the total amount Qn of donors and the total amount Qp of acceptors) is as shown in the center of FIG. That is, it can be seen that there are two points where the charge balance can be accurately obtained. Correspondingly, as shown on the right side of FIG. 6, two local maximum points (vertices) appear in the distribution of the electric field strength E corresponding to these two points. For this reason, compared with the case where there is one vertex (that is, the case where the N-type column region 10 is formed of one concentration region), the source / drain breakdown voltage V _B (the area of the portion surrounded by the broken line and the Y axis) is reduced. Can be improved.

2. Description of essential parts of wafer process in manufacturing method of semiconductor device of first embodiment of the present application (mainly FIGS. 7 to 21 and FIGS. 22 to 34)
In this section, the main part of the wafer processing process will be described by taking an example of the device cross section of FIG.

  FIG. 7 is a device sectional view showing a process flow corresponding to the device section in FIG. 3 (P-column groove opening hard mask film patterning step). FIG. 8 is a device sectional view showing a process flow corresponding to the device section in FIG. 3 (P-type column groove opening step). FIG. 9 is a device sectional view (epitaxy trench filling process) showing a process flow corresponding to the device section of FIG. FIG. 10 is a device sectional view (planarization step) showing a process flow corresponding to the device section in FIG. FIG. 11 is a device cross-sectional view (P-type RESURF region introducing step) showing a process flow corresponding to the device cross-section of FIG. FIG. 12 is a device cross-sectional view (field insulating film etching step) showing a process flow corresponding to the device cross-section of FIG. FIG. 13 is a device sectional view (P-type body region introducing step) showing a process flow corresponding to the device section in FIG. 3. FIG. 14 is a device sectional view (gate oxidation process) showing a process flow corresponding to the device section in FIG. FIG. 15 is a device cross-sectional view (gate polysilicon film forming step) showing a process flow corresponding to the device cross-section of FIG. FIG. 16 is a device sectional view (gate polysilicon film patterning step) showing a process flow corresponding to the device section in FIG. FIG. 17 is a device sectional view (N + type source region introduction step) showing a process flow corresponding to the device section in FIG. 3. 18 is a device cross-sectional view (interlayer insulating film forming step) showing a process flow corresponding to the device cross-section of FIG. FIG. 19 is a device sectional view (contact hole forming step) showing a process flow corresponding to the device section in FIG. FIG. 20 is a device sectional view showing a process flow corresponding to the device section in FIG. 3 (P + type body contact region introducing step). FIG. 21 is a device cross-sectional view (aluminum-based metal electrode forming step) showing a process flow corresponding to the device cross-section of FIG. 3. FIG. 22 is a device sectional view showing a process flow corresponding to the device section in FIG. 5 (P-type column groove opening hard mask film patterning step). FIG. 23 is a device sectional view showing a process flow corresponding to the device section in FIG. 5 (P-type column groove opening step). 24 is a device cross-sectional view (epitaxy trench filling step) showing a process flow corresponding to the device cross-section of FIG. FIG. 25 is a device sectional view (planarization step) showing a process flow corresponding to the device section in FIG. 5. 26 is a device cross-sectional view (P-type body region introducing step) showing a process flow corresponding to the device cross-section of FIG. FIG. 27 is a device sectional view (gate oxidation process) showing a process flow corresponding to the device section in FIG. 5. FIG. 28 is a device sectional view (gate polysilicon film forming step) showing a process flow corresponding to the device section in FIG. 5. FIG. 29 is a device sectional view showing a process flow corresponding to the device section in FIG. 5 (gate polysilicon film patterning step). FIG. 30 is a device sectional view showing a process flow corresponding to the device section in FIG. 5 (N + type source region introducing step). FIG. 31 is a device sectional view (interlayer insulating film forming step) showing a process flow corresponding to the device section in FIG. 5. FIG. 32 is a device sectional view (contact hole forming step) showing a process flow corresponding to the device section in FIG. 5. 33 is a device sectional view showing a process flow corresponding to the device section in FIG. 5 (P + type body contact region introducing step). FIG. 34 is a device sectional view (aluminum-based metal electrode formation step) showing a process flow corresponding to the device section in FIG. 5. Based on these, the main part of the wafer process in the manufacturing method of the semiconductor device according to the first embodiment of the present application will be described.

First, as shown in FIGS. 7 and 22, for example, an N + silicon single crystal substrate 1s doped with antimony (for example, about 10 ¹⁸ to 10 ¹⁹ / cm ³ ) (here, for example, a 200φ wafer, a wafer diameter) May be 150φ, 300φ or 450φ), for example, a phosphorus-doped N epitaxial layer 1n having a thickness of about 50 μm (a region to be a drift region as a device, with a concentration of, for example, 10 ¹⁵ / cm ³ When the thickness of the N-type lower silicon epitaxial layer 1t is about 30 micrometers and the phosphorus concentration is about ³ × 10 ¹⁵ / cm ³ , the thickness of the N-type upper silicon epitaxial layer 1d is about 20 micrometers and the phosphorus concentration Is formed to be about 4 × 10 ¹⁵ / cm ³ ) A conductor wafer 1 is prepared. On the device surface 1a of the semiconductor wafer 1 (the main surface opposite to the back surface 1b), a P-type column trench forming hard mask film 22 made of, for example, P-TEOS (plasma-tetraethylorthosilicate) or the like is formed. Here, the width Wn of the N-type column region at the patterning level is, for example, about 6 micrometers, and the width Wp of the P-type column region is, for example, about 4 micrometers (that is, the pitch of the super junction is About 10 micrometers).

Next, as shown in FIGS. 8 and 23, a hard mask film 22 for forming a trench for a P-type column (for example, a plasma TEOS film or a silicon nitride film, or a laminated film thereof having a thickness of, for example, 1 N epitaxial layer 1n or the like is anisotropically dry etched (gas atmosphere is, for example, a mixed atmosphere of Ar, SF ₆ , O ₂ , etching depth, etc.) The P-type column trench 23 can be formed by, for example, about 50 micrometers. Subsequently, the hard mask film 22 that has become unnecessary is removed.

Next, as shown in FIGS. 9 and 24, buried epitaxial growth is performed on the P-type column trench 23, and a P-type buried epitaxial layer 24 (the boron concentration is, for example, about 5 × 10 ¹⁵ / cm ³ ). Form. Here, examples of the source gas for buried epitaxial growth include silicon tetrachloride, trichlorosilane, dichlorosilane, and monosilane. As the processing pressure, for example, about 10 kPa to 110 kPa can be exemplified as a suitable range.

  Next, as shown in FIGS. 10 and 25, the P-type buried epitaxial layer 24 outside the P-type column trench 23 is removed by a planarization process, for example, CMP (Chemical Mechanical Polishing), and the surface of the semiconductor wafer 1 is also removed. 1a is flattened.

Next, as shown in FIG. 11, a silicon oxide film 16 (a field oxide film having a thickness of about 350 nm, for example) is formed on almost the entire surface 1a of the semiconductor wafer 1 by thermal oxidation. Then, a P-type RESURF region introduction resist film 25 is formed by lithography. Subsequently, using the P-type RESURF region introduction resist film 25 as a mask, ion implantation (for example, the dopant is boron, for example, the dose is about 1 × 10 ¹¹ to 1 × 10 ¹² / cm ² , and the implantation energy is, for example, P-type surface RESURF region 14 is introduced by about 200 keV. Thereafter, the resist film 25 that is no longer needed is entirely removed.

  Next, as shown in FIG. 12, a field insulating film processing resist film 26 is formed on the field oxide film 16 by lithography, and using this as a mask, the edge portion of the chip, the active cell region 6 and the like are exposed. Thereafter, the resist film 26 that is no longer needed is entirely removed.

Next, as shown in FIGS. 13 and 26, a P-type body region introducing resist film 27 is formed on the surface 1a of the semiconductor wafer 1 by lithography, and is used as a mask for ion implantation (the dopant is boron). Thus, the P-type body region 12 is introduced. This ion implantation is performed, for example, in the following two steps. As a first step, for example, it is implanted at 200 keV, ^{10 13} / cm @ 2 order, followed by a second step, performing an implant, for example 75 keV, ^{10 12} / cm @ 2 order.

  In FIG. 26, as can be seen from the width of the gate electrode and the position 11x, according to the non-self-aligned P-type body region introduction process used here, the gate is already, for example, about 1 micrometer at the time of doping. Since it has penetrated into the portion to be the electrode, the subsequent heat treatment burden can be reduced, and as a result, undesired changes in the impurity distribution of the super junction can be reduced. However, as a side effect, the withstand voltage may decrease as a result of the depth of the P-type body region 12 becoming shallower. For this reason, as described above, this problem is avoided by performing ion implantation of the P-type body region 12 in two steps.

  As described above, when the introduction of the P-type body region 12 of the second conductivity type is performed before the formation of the gate polysilicon film, the introduction portion is not limited by the width and position of the gate. In addition to reducing the subsequent heat treatment burden, it is possible to share subsequent heat treatment (including formation of a gate polysilicon film). This non-self-aligned P-type body region introduction process can be similarly applied to a case where the normal epitaxy layer serving as a base for forming a super junction is not only a multilayer but also a single layer.

  Next, as shown in FIGS. 14 and 27, the gate oxide film 21 (having a film thickness of, for example, about 50 to 200 nm is formed on the surface 1a of the semiconductor wafer 1 by thermal oxidation (for example, wet oxidation at 950 degrees Celsius). ).

  As shown in FIGS. 15 and 28, a gate polysilicon film 11 (having a thickness of about 200 to 800 nm, for example) is formed on the gate oxide film 21 by, for example, low-pressure CVD (Chemical Vapor Deposition). As wafer cleaning before gate oxidation, for example, the first cleaning liquid, that is, ammonia: hydrogen peroxide: pure water = 1: 1: 5 (volume ratio), and the second cleaning liquid, that is, hydrochloric acid: hydrogen peroxide: Wet cleaning can be applied using pure water = 1: 1: 6 (volume ratio).

  Next, as shown in FIGS. 16 and 29, the gate electrode 11 is patterned by dry etching.

Subsequently, as shown in FIGS. 17 and 30, an N + source region introduction resist film 28 is formed by lithography, and using this as a mask, by ion implantation (for example, arsenic), the N + source region 19 and the chip edge N + A type channel stopper region 8 or the like is introduced (the dopant is, for example, arsenic, the dose amount is, for example, about 10 ¹⁵ / cm ² , and the implantation energy is, for example, about 40 keV. ). Thereafter, the resist film 28 that is no longer needed is entirely removed.

  Next, as shown in FIG. 18 and FIG. 31, a PSG (Phospho-Silicate-Glass) film 17 (interlayer insulating film) is formed on almost the entire surface 1a of the semiconductor wafer 1 by CVD or the like (the SOG film on the upper side). May be flattened). As the interlayer insulating film 17, in addition to the PSG film, a BPSG, TEOS film, SiN film, others, or a composite film thereof can be applied. Moreover, as a total film thickness of the interlayer insulation film 17, about 900 nm can be illustrated, for example.

  Next, as shown in FIGS. 19 and 32, a source contact hole opening resist film 29 is formed on the surface 1a of the semiconductor wafer 1, and using this as a mask, the source contact hole is formed by dry etching. A hole 20, a chip edge opening and the like are opened. Subsequently, the resist film 29 that is no longer needed is entirely removed.

Next, as shown in FIGS. 20 and 33, the substrate surface is etched by anisotropic dry etching (for example, a depth of about 0.3 μm) using the patterned interlayer insulating film 17 as a mask. A recess region is formed. Subsequently, ions are implanted into the recess region to form the P + type body contact region 18 and the outermost peripheral P + type region 7. Examples of the ion implantation conditions include dopant: BF2, implantation energy: about 30 keV, and dose: about 10 ¹⁵ / cm ² .

  Next, as shown in FIGS. 21 and 34, an aluminum-based metal layer is formed by sputtering or the like through a barrier metal film such as TiW, and patterned, so that the metal source electrode 5, the guard A ring electrode 3 and the like are formed.

  Thereafter, if necessary, for example, a final passivation film such as an inorganic final passivation film or an organic inorganic final passivation film is formed as an upper layer, and a pad opening and a gate opening are opened. As the final passivation film, in addition to a single layer film such as an inorganic final passivation film or an organic inorganic final passivation film, an organic inorganic final passivation film or the like may be laminated on a lower inorganic final passivation film. .

3. Description of a device structure (N / N-type two-stage normal epitaxy) of a planar power MOSFET which is an example of a semiconductor device according to a second embodiment of the present application (mainly FIGS. 35 and 36)
The following example shows the active cell structure (FIG. 5) and the entire region described in sections 1 and 2 (the N-type upper silicon epitaxial layer 1d has a thinner epitaxial layer than the N-type lower silicon epitaxial layer 1t). Of the N type silicon epitaxial layer structure (N type lower layer silicon epitaxial layer 1t and N type upper layer silicon epitaxial layer 1d in FIG. 3) The changed portion is in the drift region 30 in the active cell region, and appears only in the N-type silicon epitaxial layer 1n except for the active cell region. In the same section), in the active cell region 6 (FIG. 35) It will be described only.

  FIG. 35 is a device sectional view (second embodiment) corresponding to the B-B ′ section in FIGS. 1 and 2. FIG. 36 is an explanatory diagram of the charge distribution corresponding to the half pitch of the super junction structure of the drift region in the active cell region shown in FIG. 35 (the left side is the impurity region structure in the semiconductor substrate, the center is each charge distribution in the y direction, and the right side is (distribution of absolute value of electric field strength in y direction). Based on these, a device structure (N / N-type two-stage normal epitaxy system) of a planar power MOSFET which is an example of the semiconductor device according to the second embodiment of the present application will be described.

  Although the basic structure and purpose are the same as those shown in FIGS. 5 and 6, in this example, as shown in FIGS. 35 and 36, the N-type upper column region 10d (N-type upper silicon epitaxial layer 1d) The impurity concentration is set to a concentration that maintains a charge balance with the P-type column region 9 (this donor concentration is expressed as “Nd”, but does not correspond to the concentration notation other than the column). On the other hand, the impurity concentration of the N-type lower column region 10t (N-type lower silicon epitaxial layer 1t) is slightly lower than the impurity concentration of the N-type upper column region 10d (this donor concentration is expressed as “Nd−”). Is not compatible with concentration notation other than the column). In this example, the thickness of the N-type upper silicon epitaxial layer 1d can be, for example, about 30 micrometers, and the thickness of the N-type lower silicon epitaxial layer 1t can be, for example, about 20 micrometers.

4). Description of planar power MOSFET device structure (N + / N / N− type three-stage normal epitaxy system) which is an example of the semiconductor device of the third embodiment of the present application (mainly FIGS. 37 and 38)
FIG. 37 is a device cross-sectional view (third embodiment) corresponding to the BB ′ cross-section of FIGS. 1 and 2. FIG. 38 is an explanatory diagram of the charge distribution corresponding to the half pitch of the super junction structure of the drift region in the active cell region shown in FIG. 37 (the left side is the impurity region structure in the semiconductor substrate, the center is each charge distribution in the y direction, and the right side is (distribution of absolute value of electric field strength in y direction). Based on these, a planar type power MOSFET device structure (N + / N / N− type three-stage normal epitaxy system) which is an example of the semiconductor device of the third embodiment of the present application will be described.

  Although the basic structure and purpose are the same as those shown in FIGS. 5 and 6, in this example, as shown in FIGS. 37 and 38, the N-type silicon epitaxial layer 1n (N-type column region 10) has 3 layers. It is a layered structure. That is, the N-type middle-layer silicon epitaxial layer 1m (N-type middle-layer column region 10m), the upper N-type upper-layer silicon epitaxial layer 1d (N-type upper-layer column region 10d), and the lower N-type lower-layer silicon epitaxial layer 1t (N-type) The lower column region 10t). Here, as the thickness of each epitaxial layer, for example, about 16 micrometers, about 17 micrometers, and about 17 micrometers can be illustrated in order from the top.

  Here, the impurity concentration in the N-type middle layer column region 10m is a concentration that maintains a charge balance with the P-type column region 9 (this donor concentration is expressed as “Nd”, but corresponds to the concentration notation other than the column). The impurity concentration of the N-type lower layer column region 10t is slightly lower than the impurity concentration of the N-type middle layer column region 10m (this donor concentration is expressed as “Nd−”). (It does not correspond to concentration notation other than column). On the other hand, the impurity concentration in the N-type upper layer column region 10d is slightly higher than the impurity concentration in the N-type middle layer column region 10m (this donor concentration is expressed as “Nd +”, but corresponds to the concentration notation other than the column). Is not set).

  In the case of this example, as shown on the right side of FIG. 38, there are three vertices or maximum points of the electric field strength, so that a higher breakdown voltage can be ensured compared to the case of two.

5. Description of planar power MOSFET device structure (upper ion implantation N + / N type normal single epitaxy system) as an example of the semiconductor device of the fourth embodiment of the present application (mainly FIGS. 39 and 40)
FIG. 39 is a device cross-sectional view (fourth embodiment) corresponding to the BB ′ cross-section of FIGS. 1 and 2. FIG. 40 is an explanatory diagram of a charge distribution corresponding to a half pitch of the super junction structure of the drift region in the active cell region shown in FIG. 39 (the left side is the impurity region structure in the semiconductor substrate, the center is each charge distribution in the y direction, and the right side is (distribution of absolute value of electric field strength in y direction). Based on these, a planar type power MOSFET device structure (upper ion implantation N + / N type normal single epitaxy system) which is an example of the semiconductor device according to the fourth embodiment of the present application will be described.

  This example is structurally the same as that of section 1 (FIG. 5), except that the N-type upper column region 10d is not an upper layer of the multilayer epitaxy layer but a single-layer N-type silicon epitaxial layer. A high concentration portion is formed by ion implantation in the upper half of 1n. Accordingly, the N-type silicon epitaxial layer 1n remains a single layer in a region without a super junction. Here, as in the section 1, the impurity concentration of the N-type lower layer column region 10t is a concentration that maintains a charge balance with the P-type column region 9 (this donor concentration is expressed as “Nd”. (It is not compatible with other density notations). On the other hand, the impurity concentration in the N-type upper column region 10d is slightly higher than the impurity concentration in the N-type lower column region 10t (this donor concentration is expressed as “Nd +”, but corresponds to the concentration notation other than the column). Is not set). In the case of this example, as shown in FIG. 40, the breakdown voltage is almost the same as in FIG. Here, as the thickness (depth) of the N-type upper layer column region 10d, for example, about 16 micrometers can be exemplified.

  However, as in section 23, the impurity concentration of the N-type upper column region 10d (N-type upper silicon epitaxial layer 1d) is set to a concentration that maintains a charge balance with the P-type column region 9 (this donor concentration is “Nd”). The concentration of the N-type lower column region 10t (N-type lower-layer silicon epitaxial layer 1t) is set to the impurity concentration of the N-type upper-layer column region 10d. The donor concentration may be set slightly lower than this (this donor concentration is expressed as “Nd−”, but does not correspond to the concentration notation other than the column). In this case, the breakdown voltage is almost the same as that in FIG.

6). Description of principal part of wafer process in manufacturing method of semiconductor device of fourth embodiment of the present application (mainly FIGS. 41 to 44)
Here, the main part of the process corresponding to the active cell region described in section 5 will be described. The basic part is the same as that described in Section 2, and only the different part will be described.

  FIG. 10 is a device cross-sectional view (P-type column groove opening hard mask film patterning step) showing a process flow (fourth embodiment) corresponding to a device cross-section of q. FIG. 42 is a device sectional view (an oblique ion implantation step into an N-type column region) showing a process flow (fourth embodiment) corresponding to the device section in FIG. FIG. 43 is a device sectional view (epitaxy trench filling step) showing a process flow (fourth embodiment) corresponding to the device section in FIG. FIG. 44 is a device sectional view (planarization step) showing a process flow (fourth embodiment) corresponding to the device section in FIG. Based on these, the main part of the wafer process in the semiconductor device manufacturing method according to the fourth embodiment of the present application will be described.

  As shown in FIG. 41, by using the P-type column trench forming hard mask film 22 as a mask, the N epitaxial layer 1n (for example, a thickness of about 50 micrometers) or the like is dry-etched, thereby forming the P-type column trench 23. Form. Subsequently, the hard mask film 22 that has become unnecessary is removed.

Next, as shown in FIG. 42, by performing ion implantation (for example, dopant: phosphorus, implantation energy: about 30 keV, dose amount: about 10 ¹⁵ / cm ² ) from a plurality of oblique directions, N-type is performed. Impurity ion implantation region 31 is formed.

Next, as shown in FIG. 43, buried epitaxial growth is performed on the P-type column trench 23 to form a P-type buried epitaxial layer 24 (with a boron concentration of, for example, about 5 × 10 ¹⁵ / cm ³ ). .

  Next, as shown in FIG. 44, the P-type buried epitaxial layer 24 outside the P-type column trench 23 is removed by a flattening step, for example, CMP, and the surface 1a of the semiconductor wafer 1 is flattened.

  The subsequent steps are substantially the same as those in FIG. 26 and thereafter in section 2 (after FIG. 11 including other regions).

7). Description of the device structure (N + / N type two-stage normal epitaxy system) of a trench type power MOSFET which is a modification of the semiconductor device of the first embodiment of the present application (mainly FIG. 45)
In this section, the trench gate version of the active cell structure of FIG. 5 is described. A trench type vertical power MOSFET having a super junction is considered to be effective mainly for a source / drain withstand voltage of about 100 to 300 volts. Therefore, in the following description, a case where the source-drain breakdown voltage is about 200 volts will be described as an example (the same applies to the other sections below).

  FIG. 45 is a device sectional view (planarization step) showing a process flow (fourth embodiment) corresponding to the device section in FIG. 5. Based on this, a device structure (N + / N-type two-stage normal epitaxy system) of a trench type power MOSFET which is a modification of the semiconductor device according to the first embodiment of the present application will be described.

  As shown in FIG. 45, in this example, a linear polysilicon gate electrode 11 is embedded in a gate trench 34 (a linear groove for gate) via a gate insulating film 21. This trench gate structure has an advantage that a low on-resistance can be easily realized as compared with the planar type (example before section 6). On the other hand, there is a disadvantage in realizing a source / drain breakdown voltage of the order of 500 to 600 volts as in the planar type.

8). Description of essential parts of wafer process in manufacturing method of semiconductor device of first embodiment (variation example) of the present application (mainly FIGS. 46 to 61)
The trench gate structure is basically the same as that described in Section 2 as the whole device, except for the difference in the manufacturing method due to the difference in the structure of the active cell. Accordingly, the following description will focus on the different parts.

  46 is a device cross-sectional view (P-type column groove opening hard mask film patterning step) showing a process flow (a trench type power MOSFET which is a modification of the first embodiment) corresponding to the device cross section of FIG. . FIG. 47 is a device sectional view (P-type column groove opening step) showing a process flow (trench-type power MOSFET which is a modification of the first embodiment) corresponding to the device section of FIG. FIG. 48 is a device cross-sectional view (epitaxy trench filling step) showing a process flow (trench type power MOSFET which is a modification of the first embodiment) corresponding to the device cross-section of FIG. 45. FIG. 49 is a device sectional view (planarization step) showing a process flow (trench type power MOSFET which is a modification of the first embodiment) corresponding to the device section of FIG. 45. FIG. 50 is a device sectional view (insulating film hard mask removing step) showing a process flow (trench type power MOSFET which is a modification of the first embodiment) corresponding to the device section of FIG. 45. FIG. 51 is a device sectional view (trench etch insulating film forming step) showing a process flow (trench power MOSFET which is a modification of the first embodiment) corresponding to the device section of FIG. 45. 52 is a device sectional view showing a process flow corresponding to the device section of FIG. 45 (trench type power MOSFET which is a modification of the first embodiment) (insulating film formation trench etch anisotropic etch-back process). It is. FIG. 53 is a device sectional view (gate trench etch process) showing a process flow (trench type power MOSFET which is a modification of the first embodiment) corresponding to the device section of FIG. 45. FIG. 54 is a device sectional view (gate oxidation step) showing a process flow (trench-type power MOSFET which is a modification of the first embodiment) corresponding to the device section in FIG. 45. FIG. 55 is a device sectional view (gate polysilicon film forming step) showing a process flow (trench type power MOSFET which is a modification of the first embodiment) corresponding to the device section of FIG. 45. FIG. 56 is a device sectional view (gate polysilicon film patterning step) showing a process flow (trench-type power MOSFET which is a modification of the first embodiment) corresponding to the device section in FIG. 45. FIG. 57 is a device sectional view (N + type source region introduction step) showing a process flow (trench type power MOSFET which is a modification of the first embodiment) corresponding to the device section of FIG. FIG. 58 is a device sectional view (interlayer insulating film forming step) showing a process flow (trench type power MOSFET which is a modification of the first embodiment) corresponding to the device section of FIG. FIG. 59 is a device sectional view (contact hole forming step) showing a process flow corresponding to the device section in FIG. 45 (trench power MOSFET which is a modification of the first embodiment). FIG. 60 is a device sectional view (P + type body contact region introducing step) showing a process flow (trench type power MOSFET which is a modification of the first embodiment) corresponding to the device section of FIG. FIG. 61 is a device sectional view (aluminum-based metal electrode formation step) showing a process flow (trench-type power MOSFET which is a modification of the first embodiment) corresponding to the device section in FIG. Based on these, the main part of the wafer process in the manufacturing method of the semiconductor device according to the first embodiment (modified example) of the present application will be described.

As shown in FIG. 46 as in FIGS. 7 and 22, for example, an N + silicon single crystal substrate 1s doped with antimony (for example, about 10 ¹⁸ to 10 ¹⁹ / cm ³ ) (here, for example, a 200φ wafer, The wafer diameter may be 150φ, 300φ, or 450φ), for example, a phosphorus-doped N epitaxial layer 1n having a thickness of about 15 μm (a region to be a drift region as a device, and a concentration of, for example, 10 ¹⁵ / order of about cm ^3, i.e., thickness 9 micrometers of about N-type lower silicon epitaxial layer 1t, when the phosphorus concentration and 3x10 ¹⁵ / cm ³ or so, the thickness of 6 micrometer order of N-type upper silicon epitaxial layer 1d The phosphorus concentration is about 4 × 10 ¹⁵ / cm ³ ) A semiconductor wafer 1 is prepared. On the device surface 1a of the semiconductor wafer 1 (the main surface opposite to the back surface 1b), a P-type column trench forming hard mask film 22 made of, for example, P-TEOS (plasma-tetraethylorthosilicate) or the like is formed. Here, the width Wn of the N-type column region at the patterning level is, for example, about 2 micrometers, and the width Wp of the P-type column region is, for example, about 1 micrometer (that is, the pitch of the super junction is About 3 micrometers).

Next, as shown in FIG. 46, in the trench gate process, since the size of each part is smaller than that of the planar device, the introduction process of the P-type body region 12 with a large thermal burden is performed initially. The ion implantation for introducing the P-type body region 12 is performed, for example, in the following two steps. As a first step, for example, an injection is performed with an order of 200 keV, 10 ¹³ / cm 2, and subsequently, as a second step, an injection is performed with an order of 75 keV, 10 ¹² / cm 2, for example.

Next, as shown in FIG. 47, the N epitaxial layer 1n and the like are anisotropically dried using the P-type column trench forming hard mask film 22 (for example, a CVD silicon oxide film having a thickness of about 1 micrometer) as a mask. Etching (for example, a gas atmosphere is a mixed atmosphere of Ar, SF ₆ , O _2, etc., and an etching depth is, for example, about 18 μm), so that a P-type column trench 23 is formed. Form.

Next, as shown in FIG. 48, buried epitaxial growth is performed on the P-type column trench 23 to form a P-type buried epitaxial layer 24 (with a boron concentration of, for example, about 5 × 10 ¹⁵ / cm ³ ). . Here, examples of the source gas for buried epitaxial growth include silicon tetrachloride, trichlorosilane, dichlorosilane, and monosilane. As the processing pressure, for example, about 10 kPa to 110 kPa can be exemplified as a suitable range.

  Next, as shown in FIG. 49, a P-type buried epitaxial layer outside the P-type column trench 23 is formed by a planarization process, for example, CMP (Chemical Mechanical Polishing) using the P-type column groove processing hard mask film 22 as a stopper. 24 is removed and the surface 1a of the semiconductor wafer 1 is flattened.

  Next, as shown in FIG. 50, the P-type column groove processing hard mask film 22 that has become unnecessary is removed by wet etching.

  Next, as shown in FIG. 51, a trench processing hard mask film 33 (for example, a CVD silicon oxide film) is formed on substantially the entire front main surface 1a of the wafer 1.

  Next, as shown in FIG. 52, the trench processing hard mask film 33 is processed by anisotropic dry etching.

Next, as shown in FIG. 52, the silicon substrate region of the front main surface 1a of the wafer 1 is etched back by anisotropic dry etching (as the etching mixed gas atmosphere is argon, oxygen, SF ₆ or the like) A gate trench 34 (a linear groove for a gate) is formed.

  Next, as shown in FIG. 54, a gate oxide film 21 (having a thickness of about 20 to 100 nm, for example) is formed on the surface 1a of the semiconductor wafer 1 by thermal oxidation (for example, wet oxidation at 950 degrees Celsius). To do.

  As shown in FIG. 55, gate polysilicon film 11 (thickness is, for example, about 800 nm) is formed on gate oxide film 21 by, for example, low pressure CVD. As wafer cleaning before gate oxidation, for example, the first cleaning liquid, that is, ammonia: hydrogen peroxide: pure water = 1: 1: 5 (volume ratio), and the second cleaning liquid, that is, hydrochloric acid: hydrogen peroxide: Wet cleaning can be applied using pure water = 1: 1: 6 (volume ratio).

  Next, as shown in FIG. 56, the gate electrode 11 is patterned by anisotropic dry etching.

Next, as shown in FIG. 57, similarly to section 2, a N + source region introduction resist film is formed by lithography, and using this as a mask, ion implantation (for example, arsenic) is used to form N + source region 19 and chip edge portion. N + type channel stopper region 8 (see FIG. 30 and the like) and the like are introduced (the dopant is, for example, arsenic, the dose amount is, for example, on the order of 10 ¹⁵ / cm ² , and the implantation energy is, for example, For example, about 40 keV). Thereafter, the resist film that is no longer needed is entirely removed.

  Next, as shown in FIG. 58, a PSG (Phospho-Silicate-Glass) film 17 (interlayer insulating film) is formed on almost the entire surface 1a of the semiconductor wafer 1 by CVD or the like (the SOG film is overlaid on top). Flattening). As the interlayer insulating film 17, in addition to the PSG film, a BPSG, TEOS film, SiN film, others, or a composite film thereof can be applied. Moreover, as a total film thickness of the interlayer insulation film 17, about 900 nm can be illustrated, for example.

  Next, as shown in FIG. 59, a source contact hole opening resist film 29 is formed on the surface 1a of the semiconductor wafer 1, and using this as a mask, by dry etching, the source contact hole 20, A chip edge opening (see FIG. 32, etc.) is opened. Subsequently, the resist film 29 that is no longer needed is entirely removed.

Next, as shown in FIG. 60, the substrate surface is etched by anisotropic dry etching using the patterned interlayer insulating film 17 as a mask (for example, a depth of about 0.3 μm), thereby forming a recess region. Form. Subsequently, ions are implanted into the recess region to form a P + type body contact region 18 and an outermost peripheral P + type region 7 (see FIG. 33 and the like). Examples of the ion implantation conditions include dopant: BF2, implantation energy: about 30 keV, and dose: about 10 ¹⁵ / cm ² .

  Next, as shown in FIG. 61, an aluminum-based metal layer is formed by sputtering or the like through a barrier metal film such as TiW, and patterned, so that the metal source electrode 5 and the guard ring electrode 3 are formed. (See FIG. 34, etc.).

  Thereafter, if necessary, for example, a final passivation film such as an inorganic final passivation film or an organic inorganic final passivation film is formed as an upper layer, and a pad opening and a gate opening are opened. As the final passivation film, in addition to a single layer film such as an inorganic final passivation film or an organic inorganic final passivation film, an organic inorganic final passivation film or the like may be laminated on a lower inorganic final passivation film. .

9. Description of device structure (N / N-type two-stage normal epitaxy) of a trench type power MOSFET which is a modification of the semiconductor device of the second embodiment of the present application (mainly FIG. 62)
In this section, the trench gate version of the active cell structure of FIG. 35 is described.

  62 is a device sectional view corresponding to the B-B ′ section in FIGS. 1 and 2 (a trench type power MOSFET which is a modification of the second embodiment). Based on this, a device structure (N / N-type two-stage normal epitaxy system) of a trench type power MOSFET which is a modification of the semiconductor device of the second embodiment of the present application will be described.

  As shown in FIG. 62, in this example, a linear polysilicon gate electrode 11 is embedded in a gate trench 34 (a linear groove for gate) via a gate insulating film 21. This trench gate structure has an advantage that a low on-resistance can be easily realized as compared with the planar type (example before section 6). On the other hand, there is a disadvantage in realizing a source / drain breakdown voltage of the order of 500 to 600 volts as in the planar type.

10. Description of a trench type power MOSFET device structure (N + / N / N− type three-stage normal epitaxy system) which is a modification of the semiconductor device of the third embodiment of the present application (mainly FIG. 63)
In this section, the trench gate version of the active cell structure of FIG. 37 is described.

  63 is a device sectional view corresponding to the B-B ′ section in FIGS. 1 and 2 (a trench type power MOSFET which is a modification of the third embodiment). Based on this, a trench type power MOSFET device structure (N + / N / N− type three-stage normal epitaxy system) which is a modification of the semiconductor device of the third embodiment of the present application will be described.

  As shown in FIG. 63, in this example, a linear polysilicon gate electrode 11 is embedded in a gate trench 34 (a linear groove for gate) via a gate insulating film 21. This trench gate structure has an advantage that a low on-resistance can be easily realized as compared with the planar type (example before section 6). On the other hand, there is a disadvantage in realizing a source / drain breakdown voltage of the order of 500 to 600 volts as in the planar type.

11. Description of planar type power MOSFET device structure (upper ion implantation N + / N type normal single epitaxy system) which is an example of the semiconductor device of the fourth embodiment of the present application (mainly FIG. 64)
In this section, the trench gate version of the active cell structure of FIG. 39 is described.

  64 is a device sectional view corresponding to the B-B ′ section in FIGS. 1 and 2 (a trench type power MOSFET which is a modification of the fourth embodiment). Based on this, a planar type power MOSFET device structure (upper ion implantation N + / N type normal single epitaxy system) as an example of the semiconductor device of the fourth embodiment of the present application will be described.

  As shown in FIG. 64, in this example, a linear polysilicon gate electrode 11 is embedded in a gate trench 34 (a linear groove for gate) via a gate insulating film 21. This trench gate structure has an advantage that a low on-resistance can be easily realized as compared with the planar type (example before section 6). On the other hand, there is a disadvantage in realizing a source / drain breakdown voltage of the order of 500 to 600 volts as in the planar type.

12 Summary The invention made by the present inventor has been specifically described based on the embodiments. However, the present invention is not limited thereto, and it goes without saying that various changes can be made without departing from the scope of the invention.

  For example, in the above-described embodiment, an example in which the layout of the MOSFET is arranged in a stripe shape parallel to the pn column has been shown. However, it can be arranged in a direction orthogonal to the pn column, arranged in a lattice shape, or various applications. is there.

  In the above embodiment, the N channel device is mainly formed on the upper surface of the N epitaxial layer on the N + silicon single crystal substrate. However, the present invention is not limited to this, and P + silicon is used. A P channel device may be formed on the upper surface of the N epitaxial layer on the single crystal substrate.

  In the above-described embodiment, the power MOSFET has been specifically described as an example. However, the present invention is not limited thereto, and an IGBT (Insulated Gate Bipolar Transistor) power device having a super junction structure, that is, a diode, Needless to say, the present invention can also be applied to a bipolar transistor or the like. Needless to say, the present invention can also be applied to a semiconductor integrated circuit device incorporating these power MOSFETs, diodes, bipolar transistors and the like.

  Furthermore, in the above embodiment, the trench fill method has been specifically described as a method for forming the super junction structure. However, the present invention is not limited thereto, and for example, a multi-epitaxial method can be applied. Needless to say.

1 Wafer or semiconductor substrate 1a Surface of semiconductor substrate (source side surface)
1b Back surface of semiconductor substrate (drain side surface)
1d N-type upper silicon epitaxial layer (first conductivity type normal epitaxial region)
1m N-type middle silicon epitaxial layer 1n N-type silicon epitaxial layer 1s N + type single crystal silicon substrate part 1t N-type lower silicon epitaxial layer 2 Semiconductor chip (chip region)
3 Guard ring 4 Gate metal electrode 5 Source metal electrode 6 Active cell region 7 Outermost peripheral P + type region 8 N + type channel stopper region 9 P type column region (second conductivity type column region)
10 N-type column region (first conductivity type column region)
10d N-type upper layer column region (upper layer region)
10m N-type middle layer column region (middle layer region)
10t N-type lower layer column region (lower layer region)
11 Polysilicon gate electrode (polysilicon film)
11x Width and position of gate electrode 12 P-type body region (P-type body region of second conductivity type)
14 P-type RESURF region 15 Edge termination region (cell peripheral region)
16 Field insulating film 17 Interlayer insulating film 18 P + type body contact region 19 N + type source region 20 Contact hole 21 Gate insulating film 22 Hard mask film for P type column groove processing 23 P type column groove 24 P type buried epitaxial layer 25 RESURF region Introducing resist film 26 Field insulating film processing resist film 27 P-type body region introducing resist film 28 N + type source region introducing resist film 29 Contact hole opening resist film 30 Drift region 31 N-type impurity ion implantation region 32 Surface recess Part 33 Hard mask film for trench processing 34 Gate trench (linear groove for gate)
E Electric field strength in drift region Half width of N-type column at Ln, y y position Half width of P-type column at Lp, y position Nd Standard N-type impurity concentration of N-type column Nd + Higher N-type impurity concentration of N-type column Nd -Lower N-type impurity concentration of the N-type column Q _n (y) Donor surface density in a constant y plane Qn Total charge amount in the N-type column Q _p (y) Acceptor surface density in a constant y plane Qp P-type column Total charge R1 Cell edge and chip peripheral region cutout portion R2 Cell center cutout portion V _B Source drain breakdown voltage Wn Width of N-type column region at patterning level Wp Width of P-type column region at patterning level X P type Axis from column to N-type column and perpendicular to these Y Y Vertical axis from the front surface to the back surface of the semiconductor substrate

FIG. 41 is a device sectional view (P-type column groove opening hard mask film patterning step) showing a process flow (fourth embodiment) corresponding to the device section in FIG. FIG. 42 is a device sectional view (an oblique ion implantation step into an N-type column region) showing a process flow (fourth embodiment) corresponding to the device section in FIG. FIG. 43 is a device sectional view (epitaxy trench filling step) showing a process flow (fourth embodiment) corresponding to the device section in FIG. FIG. 44 is a device sectional view (planarization step) showing a process flow (fourth embodiment) corresponding to the device section in FIG. Based on these, the main part of the wafer process in the semiconductor device manufacturing method according to the fourth embodiment of the present application will be described.

Claims (16)

(A) a semiconductor chip having a first main surface and a second main surface and having a MOSFET formed thereon;
(B) a source electrode of the MOSFET provided on the first main surface side of the semiconductor chip;
(C) a drift region of the MOSFET having a first conductivity type provided in a surface on the first main surface side of the semiconductor chip;
(D) a plurality of trenches provided so as to penetrate the drift region from the first main surface side of the semiconductor chip;
(E) a plurality of second conductivity type column regions embedded in the plurality of trenches by epitaxial growth and having a second conductivity type opposite to the first conductivity type;
(F) In the method of manufacturing a semiconductor device having a plurality of first conductivity type column regions having the first conductivity type, which is between the plurality of second conductivity type column regions and forms a super junction structure with them.
Each of the plurality of first conductivity type column regions is:
(F1) a lower layer region having a first impurity concentration;
(F2) having an upper layer region between the lower layer region and the first main surface and having a second impurity concentration higher than the first impurity concentration;
Further, the concentration of the upper layer region is increased by ion-implanting the impurity having the first conductivity type into the outer surface of each of the plurality of first conductivity type column regions.   2. The method of manufacturing a semiconductor device according to claim 1, wherein the drift region is a base epitaxy layer. 3. The method of manufacturing a semiconductor device according to claim 2, wherein each of the plurality of first conductivity type column regions further includes:
(F3) An intermediate layer region between the lower layer region and the upper layer region and having a third impurity concentration intermediate between the first impurity concentration and the second impurity concentration.   3. The method of manufacturing a semiconductor device according to claim 2, wherein the first impurity concentration is a concentration that maintains a charge balance between the second conductivity type column region and the first conductivity type column region.   3. The method of manufacturing a semiconductor device according to claim 2, wherein the first impurity concentration is lower than a concentration at which the second conductivity type column region and the first conductivity type column region maintain a charge balance.   3. The method for manufacturing a semiconductor device according to claim 2, wherein the semiconductor chip is a silicon chip.   7. The method of manufacturing a semiconductor device according to claim 6, wherein the first conductivity type is an N type.   8. The method of manufacturing a semiconductor device according to claim 7, wherein the semiconductor chip constitutes a single or composite power active device.   9. The method of manufacturing a semiconductor device according to claim 8, wherein the semiconductor chip constitutes a power MOSFET single device.   10. The method of manufacturing a semiconductor device according to claim 9, wherein the power MOSFET is a planar type.   10. The method of manufacturing a semiconductor device according to claim 9, wherein the power MOSFET is a trench type.   12. The method of manufacturing a semiconductor device according to claim 11, wherein the second conductivity type column region has a wide inverted trapezoidal shape on the first main surface side.   5. The method of manufacturing a semiconductor device according to claim 4, wherein the lower layer region is thicker than the upper layer region.   6. The method of manufacturing a semiconductor device according to claim 5, wherein the lower layer region is thinner than the upper layer region. The method of manufacturing a semiconductor device according to claim 10, further comprising:
(G) a second conductivity type body region having the second conductivity type formed in a surface region of the drift region on the first main surface side of the semiconductor chip and constituting a channel region of the power MOSFET;
(H) a gate insulating film formed on the surface of the second conductivity type body region on the first main surface side of the semiconductor chip;
(I) A gate electrode whose main component is a polysilicon film formed on the opposite side of the second conductivity type body region across the gate insulating film.   16. The method of manufacturing a semiconductor device according to claim 15, wherein the introduction of the second conductivity type body region is performed prior to the formation of the polysilicon film.

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