JP2014137729A - Power supply circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a power supply circuit capable of preventing the malfunction of an object circuit during low power consumption mode transition or normal operation mode transition while achieving further low power consumption in a low power consumption mode.SOLUTION: During transition from a low power consumption mode to a normal operation mode, an ECU 1 accepts a wakeup signal WKUPB. When a latch circuit 12 outputs a wakeup signal WKUP, the operation of a reference voltage generation circuit 9 is validated, and the reference voltage generation circuit 9 generates a reference voltage V1. After the output voltage of the reference voltage generation circuit 9 reaches a predetermined voltage, a regulator circuit 8 is allowed to input the wakeup signal WKUP, and the regulator circuit 8 is started. The regulator circuit 8 is started, and until the output voltage is raised to a power-on reset voltage VPOR, a POR circuit 10 outputs a power-on reset signal PORB to a reset terminal RSN of a control logic circuit 6.

Description

  The present invention relates to a power supply circuit having a low power consumption mode and a normal operation mode.

  Some power supply circuits are provided with a power-on reset circuit (hereinafter, POR circuit) so that the operation of the logic circuit or the like does not become unstable immediately after startup. The POR circuit outputs a reset signal to the target circuit before the output voltage of the power supply circuit is stabilized, and cancels the reset signal after the power supply voltage is stabilized.

  On the other hand, the power supply circuit consumes a large amount of power when a logic circuit or the like is constantly operated. Therefore, a low power consumption mode is provided to operate the logic circuit when necessary and to supply a part of the power supplied to the circuit when not necessary. The power is cut off (see, for example, Patent Document 1).

JP 2006-303579 A

  For example, according to the technique described in Patent Document 1, the supply power of the RAM is always supplied, and the power supplied to the internal CPU is shut off. However, in the circuit configuration described in Patent Document 1, since the BGR circuit is always energized, the dark current increases, and the degree of improvement is low from the viewpoint of reducing power consumption.

  Further, if a large-capacity capacitor such as an external capacitor is added, the external power supply circuit takes time to discharge. For example, if the output voltage of the BGR circuit drops before the voltage output of the external power supply circuit in the circuit configuration, the POR circuit using the BGR circuit as a reference voltage may not operate normally. Then, malfunction occurs when the output voltage of the main power supply circuit falls below the operation guarantee lower limit voltage of the target circuit.

  An object of the present invention is to provide a power supply with a power-on reset function capable of preventing a malfunction of a target circuit when shifting to a low power consumption mode or when shifting to a normal operation mode while further reducing power consumption in the low power consumption mode. It is to provide a circuit.

  According to the first aspect of the present invention, the main power supply circuit and the reference voltage generation circuit stop operating in the low power consumption mode. Here, when a wake-up event is received, the activation instruction circuit validates the operation of the reference voltage generation circuit. Then, the reference voltage generation circuit gradually increases the output voltage, and after the output voltage reaches the predetermined voltage in the normal operation of the reference voltage from the initial value in the low power consumption mode, the start instruction circuit switches the main power supply circuit. to start.

  The power-on reset circuit generates a power-on reset signal according to the generated voltage of the reference voltage generation circuit and the output voltage of the main power supply circuit and outputs it to the target circuit. When the main power supply circuit is activated after the generated voltage reaches the predetermined voltage, a power-on reset signal is output to the target circuit until the output voltage of the main power supply circuit approaches the normal main power supply voltage.

  As a result, a power-on reset signal is given while the target circuit becomes unstable, and malfunction of the target circuit can be prevented. In addition, since the operations of the main power supply circuit and the reference voltage generation circuit are stopped in the low power consumption mode, the power consumption can be reduced.

  According to the invention described in claim 4, in the normal operation mode, the main power supply circuit supplies the main power supply voltage generated in accordance with the reference voltage of the reference voltage generation circuit to the target circuit. Here, when the normal operation mode is shifted to the low power consumption mode, the stop instruction circuit stops the operation of the main power supply circuit. The power-on reset circuit generates a power-on reset signal according to the level of the voltage generated according to the generated voltage of the reference voltage generating circuit and the output voltage of the main power circuit, and outputs it to the target circuit. When the voltage approaches the initial value from the main power supply voltage, a power-on reset signal is output to the target circuit.

  After this, the alternative reset circuit outputs a reset signal to the target circuit instead of the power-on reset circuit before it reaches a voltage at which the power-on reset circuit becomes unstable or before reaching a voltage with a margin added to the voltage. To do. As a result, even if the operation of the power-on reset circuit becomes unstable, the alternative reset circuit outputs a reset signal to the target circuit, so that the target circuit can be continuously reset. Then, the stop instruction circuit stops the operation of the reference voltage generation circuit at the timing when the alternative reset circuit outputs a reset signal to the target circuit. That is, even if the power-on reset circuit becomes unstable, the reset signal continues to be output to the target circuit. As a result, malfunction of the target circuit can be prevented. In addition, since the operations of the main power supply circuit and the reference voltage generation circuit are stopped in the low power consumption mode, the power consumption can be reduced.

  According to the tenth aspect of the present invention, when the output voltage of the main power supply circuit decreases in the normal operation mode, the reference voltage generation circuit sets the normal reference voltage while the alternative reset circuit does not output the reset signal. Continue to output. For this reason, even when the output voltage of the main power supply circuit decreases, the reset signal is normally output to the target circuit, and the target circuit continues to be reset.

1 is a circuit block diagram schematically showing an electrical configuration of a first embodiment of the present invention. Electrical configuration diagram showing a specific example of a regulator circuit Electrical configuration diagram showing a specific example of a reference voltage generation circuit Electrical configuration diagram showing a specific example of a power-on reset circuit Electrical configuration diagram showing a specific example of a Vt power-on reset circuit (part 1) Electrical configuration diagram showing a specific example of a Vt power-on reset circuit (part 2) Electrical configuration diagram showing a specific example of the Vt power-on reset circuit (part 3) Timing chart schematically showing temporal changes of signals at each node Electrical configuration diagram showing a circuit example before countermeasures FIG. 9 is a timing chart schematically showing temporal changes in signals at each node when the circuit example of FIG. 9 is applied. The circuit block diagram which shows schematically an electric structure about 2nd Embodiment of this invention FIG. 9 is a timing chart schematically showing an operation at the time of instantaneous power interruption when the circuit shown in FIG. 9 is applied to the third embodiment of the present invention. FIG. 1 is a timing chart schematically showing the operation at the moment of power interruption when the circuit shown in FIG. FIG. 9 is a timing chart schematically showing the operation at the moment of power interruption when the circuit shown in FIG. 9 is applied (part 2). FIG. 2 is a timing chart schematically showing the operation at the moment of power interruption when the circuit shown in FIG. 1 is applied (part 2).

  Several embodiments are described below. Components that are the same or similar in the embodiments are denoted by the same or similar reference numerals, description thereof is omitted as necessary, and description will be made focusing on the characteristic portions of the embodiments.

(First embodiment)
Hereinafter, a first embodiment of the present invention applied to a power supply circuit for supplying power to a control logic circuit of a vehicle motor will be described with reference to FIGS.

  An ECU (Electronic Control Unit) 1 for a vehicle targeted by this embodiment is equipped with a semiconductor integrated circuit device A. The semiconductor integrated circuit device A includes a microcomputer chip 2 that outputs a command signal, a power supply circuit, and various types of devices. A control chip 3 incorporating a circuit is incorporated.

  The microcomputer chip 2 mainly includes an MCU (Micro Controller Unit) 4. In the microcomputer chip 2, a regulator circuit, a reference voltage generation circuit, a level shift circuit, a power-on reset circuit (none of which are shown), an I / O 5 and the like are configured. When the microcomputer chip 2 transmits a standby signal as a command signal to the control chip 3, the control chip 3 changes its power consumption mode from the normal operation mode to the low power consumption mode. Details of this will be described later.

  In the control chip 3, a control logic circuit 6 for motor control is configured. In addition, a constant power circuit 7, for example, a regulator circuit (equivalent to a main power circuit) 8 having a DC 5V output, a reference voltage generating circuit 9, a power-on A power control system circuit such as a reset circuit (hereinafter referred to as POR circuit) 10, a Vt power-on reset circuit (hereinafter referred to as VtPOR circuit) 11, and a latch circuit 12 is configured.

  The constant power supply circuit 7 inputs the battery power supply + B as the power supply IGIN through the terminal IB through the backflow prevention diode D1, generates the standby power supply voltage CVCC_STB according to the power supply IGIN, and operates in both the low power consumption mode and the normal operation mode. The standby power supply voltage CVCC_STB is supplied to (for example, the latch circuit 12, the standby power-on reset circuit 13, various gate circuits G1 to G7, etc.).

  The regulator circuit 8 inputs the battery power supply + B through the diode D1 and generates the main power supply voltage CVCC of, for example, DC 5V, and operates in the normal operation mode according to the reference voltage V1 generated by the reference voltage generation circuit 9. The main power supply voltage CVCC with high voltage stability is supplied to the circuits (for example, the circuits 4 and 5 in the microcomputer chip 2, the control logic circuit (corresponding to the target circuit) 6, the POR circuit 10, the VtPOR circuit 11, etc.).

  As shown in a specific example of the regulator circuit 8 in FIG. 2, the regulator circuit 8 is a stabilized power circuit in which a current source 14, an operational amplifier 15, resistors R1 to R3, an NMOS transistor Mn1, and a PMOS transistor Mp1 are connected in the illustrated form. The power supply IGIN is input and the main power supply voltage CVCC is variably output according to the change of the reference voltage V1 of the reference voltage generation circuit 9.

  The regulator circuit 8 is configured by connecting an NMOS transistor Mn1 to the power supply path of the power supply IGIN. By inputting the wake-up / standby signal WKUP / STBB to the gate of the NMOS transistor Mn1, the output of the main power supply voltage CVCC is obtained. Can be switched on / off (valid / invalid). That is, when the wake-up signal WKUP is applied to the gate of the NMOS transistor Mn1, the NMOS transistor Mn1 is turned on, and the power source of the operational amplifier 15 is supplied through the current source 14.

  When the standby signal STBB is applied to the gate of the NMOS transistor Mn1, the NMOS transistor Mn1 is turned off, the power supply path by the current source 14 to the operational amplifier 15 is cut off, the PMOS transistor Mp1 is turned off, and the main power supply voltage CVCC Stop the output of.

  A reference voltage generation circuit 9 shown in FIG. 3 is a circuit that inputs a power supply IGIN and outputs a reference voltage V1, and mainly includes a so-called band gap reference voltage circuit. The reference voltage generation circuit 9 is configured by combining a constant current generation circuit 16, a constant voltage generation circuit 17, and a reference voltage generation circuit 18.

  The constant current generating circuit 16 is configured by combining, for example, resistors R4 to R7, PNP transistors Tp1 to Tp4, NPN transistors Tn1 to Tn2, and NMOS transistor Mn2 in the illustrated form, and a current with reference to the base emitter voltage of the NPN transistor Tn2. The source 19 is configured in the first stage, and a current mirror circuit 20 is connected in the subsequent stage to output a predetermined current.

  The current source 19 includes a resistor R4, transistors Tp1, Tn1, Tn2, resistor R5, and a transistor Mn2. The current mirror circuit 20 is configured by connecting the transistor Tp1 on the input side and connecting the transistors Tp3 and Tp4 on the output side.

  The constant current generation circuit 16 is configured by connecting an NMOS transistor Mn2 for on / off switching of current generation by the current source 19 to the supply path of the power supply IGIN, and a wakeup / standby signal WKUP / STBB is connected to the gate of the NMOS transistor Mn2. The constant current output can be switched on / off (valid / invalid). The constant current generation circuit 16 outputs the output current of the current mirror circuit 20 to the constant voltage generation circuit 17 and the reference voltage generation circuit 18.

  The constant voltage generation circuit 17 is configured by combining, for example, NPN transistors Tn3 and Tn4 and a Zener diode Dz having a Zener voltage Vz = 5V, for example. The constant voltage generation circuit 17 receives the constant current from the constant current generation circuit 16, generates a constant voltage corresponding to the Zener diode Dz, and outputs the constant voltage to the reference voltage generation circuit 18. When the constant current generation circuit 16 is turned on / off in response to the application of the wakeup / standby signal WKUP / STBB, the constant voltage output by the constant voltage generation circuit 17 is also turned on / off at the same time.

  The reference voltage generation circuit 18 includes a plurality of current mirror circuits 21 and 22 in which NPN and PNP transistors Tn5 to Tn6 and Tp5 to Tp8 are combined, an operational amplifier 23, resistors R8 to R10, NPN transistors Tn7 to Tn9, and an NMOS transistor Mn3. A band gap reference voltage circuit 24 connected as shown in the figure is provided.

  A transistor Tn9, a resistor R8, and a diode-connected NPN transistor Tn7 are connected between the output node No of the constant voltage generation circuit 17 and the ground. The non-inverting input terminal of the operational amplifier 23 is connected to a common connection node between the resistor R8 and the collector of the transistor Tn7. The output node NV1 of the reference voltage V1 is set at a common connection point between the emitter of the transistor Tn9 and the resistor R8.

  A resistor R9, a collector-emitter of the transistor Tn8, and a resistor R10 are connected in series between the output node NV1 and the ground. The inverting input terminal of the operational amplifier 23 is connected to a common connection node between the resistor R9 and the collector of the transistor Tn8. The band gap reference voltage circuit 24 is configured by connecting the output of the operational amplifier 23 to the gate of the NMOS transistor Mn3. The output of the NMOS transistor Mn3 is fed back to the transistor Tn9, and the reference voltage V1 is stabilized from the output node NV1. To do.

  An NMOS transistor Mn4 that mirrors the output current of the NMOS transistor Mn3 is connected to the output side of the bandgap reference voltage circuit 24. A capacitor C1 is connected between the drain and source of the NMOS transistor Mn4.

  The POR circuit 10 shown in FIG. 1 prevents indefinite operation of the control logic circuit 6 mainly during startup from the low power consumption mode to the normal operation mode and during the transition from the normal operation mode to the low power consumption mode. Therefore, the power-on reset signal PORB (low active) is output to the control logic circuit 6.

  As shown in a specific example of the POR circuit 10 in FIG. 4, the POR circuit 10 is configured by combining a current source 25, a comparator 26, and voltage dividing resistors R 11 and R 12, and a reference voltage V 1 generated by the reference voltage generation circuit 9. Is input to the inverting input terminal of the comparator 26, and the voltage divided by the voltage dividing resistors R11 and R12 of the main power supply voltage CVCC is input to the non-inverting input terminal, and the comparison result of the voltage is output. Therefore, when the main power supply voltage CVCC falls below the POR voltage VPOR corresponding to the predetermined ratio of the reference voltage V1, the power-on reset signal PORB is output to the control logic circuit 6 through the AND gate G7 (see FIG. 1).

  Also, the VtPOR circuit 11 is provided to prevent the operation of the control logic circuit 6 from being unstable by outputting a reset signal to the control logic circuit 6 instead while the POR circuit 10 is operating at a power supply voltage at which the operation is indefinite. It has been. The VtPOR circuit 11 can output the reset signal POR2B (low active) to the control logic circuit 6 through the AND gate G7.

  5 to 7 show specific examples of the VtPOR circuit 11 with reference numerals 11a to 11c. In the VtPOR circuit 11a shown in FIG. 5, a resistor R13 and a diode-connected NMOS transistor Mn5 are connected between the output node Na of the main power supply voltage CVCC and the ground, and the resistor R13 and the drain of the NMOS transistor Mn5 are connected. The gate of the PMOS transistor Mp2 is connected to the common connection node. Between the output node Na of the main power supply voltage CVCC and the ground, the source and drain of the PMOS transistor Mp2 and the resistor R14 are connected in series, and the signal at the common connection node is output as the reset signal POR2B.

  That is, while the regulator circuit 8 normally supplies the main power supply voltage CVCC at about 5V, the NMOS transistor Mn5 is turned on and the current flows through the resistor R13, so that the gate-source voltage of the PMOS transistor Mp2 also exceeds the threshold voltage Vtp. As a result, the PMOS transistor is turned on. The VtPOR circuit 11 outputs a voltage level comparable to the main power supply voltage CVCC. That is, if the regulator circuit 8 outputs the main power supply voltage CVCC at a level of about 5 V, a voltage that can be regarded as “H” level can be output.

  When the output voltage of the regulator circuit 8 decreases, the NMOS transistor Mn5 is turned on when the output voltage is equal to or higher than the threshold voltage Vtn of the transistor Mn5, but the energization current of the resistor R13 decreases. For this reason, the gate-source voltage of the PMOS transistor Mp2 decreases, but when this voltage becomes lower than the threshold voltage Vtp of the PMOS transistor Mp2, the PMOS transistor Mp2 is turned off. When the PMOS transistor Mp2 is turned off, the drain-source current of the PMOS transistor Mp2 becomes minimum, and thus substantially 0 V (“L” level) is output.

  Therefore, the VtPOR circuit 11a shown in FIG. 5 is at the “L” level when the output voltage of the regulator circuit 8 becomes less than the added voltage Vtp + Vtn obtained by adding the threshold voltage Vtp of the PMOS transistor Mp2 and the threshold voltage Vtn of the NMOS transistor Mn5. Is output.

  In the VtPOR circuit 11b shown in FIG. 6, the source and drain of the PMOS transistor Mp3, the resistor R15, and the drain and source of the NMOS transistor Mn6 are connected in series between the output node Na of the main power supply voltage CVCC and the ground. The gate and drain of the transistor Mp3 are connected in common.

  The gate of the NMOS transistor Mn6 is connected to the output node Na of the output voltage of the regulator circuit 8. The gates of the two PMOS transistors Mp3 and Mp4 are commonly connected, and the source and drain of the PMOS transistor Mp4 and the resistor R16 are connected in series between the output node Na and the ground. The PMOS transistors Mp3 and Mp4 form a current mirror circuit M1, and outputs a voltage at a common connection node between the PMOS transistor Mp4 and the resistor R16 as a reset signal POR2B.

  That is, when the regulator circuit 8 outputs the main power supply voltage CVCC normally at about 5 V, both the NMOS transistor Mn6 and the PMOS transistor Mp3 are turned on, and a current obtained by mirroring the energization current of the resistor R15 connected to these energization paths is set as the resistance. Can flow to R16. Then, the terminal voltage of the resistor R16 rises and outputs a voltage level comparable to the main power supply voltage CVCC. In other words, if the regulator circuit 8 outputs the main power supply voltage CVCC normally at 5V, the VtPOR circuit 11b outputs a voltage that can be regarded as “H” level.

  That is, in the VtPOR circuit 11b, when the output voltage of the regulator circuit 8 decreases and falls below the higher one of the threshold voltages Vtn and Vtp, the final output PMOS transistor Mp4 is turned off, so that the output voltage is almost 0V. ("L" level) is output.

  For example, when the threshold voltage Vtn of the NMOS transistor Mn6 is 0.8 [V] and the threshold voltage Vtp of the PMOS transistors Mp3 and Mp4 is 1.5 [V], the output voltage of the regulator circuit 8 is 1.5 [V]. V], the VtPOR circuit 11b outputs a voltage of the same level as the output voltage of the regulator circuit 8, but when the output voltage of the regulator circuit 8 becomes less than 1.5V, the PMOS transistor Mp3 is turned off. The output of the circuit 11b becomes “L” level.

  Conversely, when the threshold voltage Vtn of the NMOS transistor Mn6 is 1.5 [V] and the threshold voltage Vtp of the PMOS transistor Mp4 is 0.8 [V], the output voltage of the regulator circuit 8 is 1.5 [V]. ], The NMOS transistor Mn6 is turned off, and the VtPOR circuit 11b outputs almost 0 [V] ("L" level).

  In the VtPOR circuit 11c shown in FIG. 7, three or more voltage dividing resistors R17 to R19 are connected in series between the output node Na of the regulator circuit 8 and the ground. Further, between the output node Na and the ground, the source and drain of the PMOS transistor Mp5, the diode-connected PMOS transistor Mp6, the resistor R20, and the drain and source of the NMOS transistor Mn7 are connected.

  Further, between the common connection node Nb of the two PMOS transistors Mp5 and Mp6 and the ground, the source and drain of the PMOS transistor Mp7 and the resistor R21 are connected in series. The VtPOR circuit 11c outputs the voltage at the common connection node between the transistor Mp7 and the resistor R21 as the reset signal POR2B. The PMOS transistors Mp6 and Mp7 constitute a current mirror circuit M2.

  The voltage dividing node Na1 on the high voltage side of these voltage dividing resistors R17 to R19 is connected to the gate of the NMOS transistor Mn7, and the voltage dividing node Na2 on the low voltage side of the voltage dividing resistors R17 to R19 is connected to the gate of the PMOS transistor Mp5. ing.

  Therefore, it is possible to set the threshold voltages (αVtp, βVtn: where α> 1, β> 1) of the PMOS transistor Mp5 and the NMOS transistor Mn7 in consideration of the margin according to the voltage dividing ratio of the voltage dividing resistors R17 to R19, respectively. When the output voltage of the circuit 8 becomes lower than any one of these threshold voltages, the circuit 8 outputs a reset signal POR2B that is substantially 0 V (“L” level). The VtPOR circuit 11 shown in FIG. 1 may apply any of these VtPOR circuits 11a to 11c shown in FIGS.

  As shown in FIG. 1, the control logic circuit 6 includes a motor control function, for example, and operates when a main power supply voltage CVCC of 5 V is supplied from the regulator circuit 8. The control logic circuit 6 includes a reset terminal RSN, and inputs reset signals RSTB, PORB, and POR2B from the MCU 4, the POR circuit 10, and the VtPOR circuit 11 of the microcomputer chip 2 through the AND gate G7. Note that the reset output of the microcomputer chip 2 is pulled down by the resistor R22.

  In this embodiment, since the circuit of the power supply system is characterized, detailed internal description of the control logic circuit 6 is omitted. However, when the standby entry signal STB_ENT of the microcomputer chip 2 is input, the D flip-flop (register) 27, level shift Output through the circuit 28.

  The ECU 1 inputs the battery voltage + B through the terminal IB through the diode D1. Further, the input terminal IN1 of the ECU 1 is pulled up to the battery voltage + B through the diodes D2 and D1 and the resistor R23, and the wake-up signal WKUPB that operates at the battery level is lowered from the other ECU (not shown) through the input terminal IN1. In response to active reception, the control chip 3 starts its power consumption mode from the low power consumption mode to the normal operation mode.

  The standby entry signal STB_ENT output from the control logic circuit 6 is input to the latch circuit 12 through various gate circuits (including delay gates) G6. When the standby entry signal STB_ENT is given, the latch circuit 12 outputs a standby signal STBB (low active) from the Q terminal.

  The latch circuit 12 has a reset terminal RST. The reset terminal RST receives a wake-up signal WKUPB from an external ECU, a power-on reset signal VtPORSTB from the standby power-on reset circuit 13, and various abnormal signals (for example, an overvoltage detection signal) through various gates (including delay gates) G3 to G5. It is designed to be entered.

  When the wake-up signal WKUPB is input from the external ECU at the battery voltage level, the operating voltage level is adjusted through the level shift circuit 29 and is supplied to the reset terminal RST of the latch circuit 12 through the AND gates G4 and G5. Then, the latch circuit 12 outputs a wakeup signal WKUP (high active) from the Q terminal.

  The Q output of the latch circuit 12 is given to the wakeup / standby terminal WKUP / STB of the reference voltage generation circuit 9 through the OR gate G2. The Q output of the latch circuit 12 is given to the wakeup / standby terminal WKUP / STB of the regulator circuit 8 through the AND gate G1.

  The drain output of the NMOS transistor Mn4 on the output side of the reference voltage generation circuit 9 and the terminal voltage output of the capacitor C1 are applied to the negative input of the AND gate G1 while being pulled up to the standby power supply voltage CVCC_STB by the resistor R24.

  Thereby, at the time of start-up when the semiconductor integrated circuit device A shifts from the low power consumption mode to the normal operation mode, the output voltage V1 of the reference voltage generation circuit 9 is increased to a predetermined voltage V1o determined in the normal operation. The wake-up signal WKUP given to the regulator circuit 8 is blocked by an AND gate (validation circuit: digital gate circuit) G1. This detailed operation will be described later.

  On the other hand, the output POR2B of the VtPOR circuit 11 is applied to the gate of the NMOS transistor Mn8, and the drain output of the transistor Mn8 is applied to the negative input of the OR gate G2 while being pulled up to the standby power supply voltage CVCC_STB by the resistor R25. Yes.

  Thus, when the semiconductor integrated circuit device A shifts from the normal operation mode to the low power consumption mode, the reference voltage is generated until the output voltage of the regulator circuit 8 reaches the Vt power-on reset (VtPOR) voltage of the VtPOR circuit 11. The standby signal STB supplied to the circuit 9 is blocked by the OR gate G2 (invalidation circuit: digital gate circuit). Here, the VtPOR voltage is a voltage in consideration of (added to) the lower limit voltage or margin of the output voltage of the regulator circuit 8 at which the POR circuit 10 can normally operate, and circuit examples are shown in the VtPOR circuits 11a to 11c described above. As described above, the voltage is set to about the threshold voltage of 1 or 2 of the transistor. This detailed operation will be described later.

  The output POR2B of the VtPOR circuit 11 is given to the control logic circuit 6 through the AND gate G7. This is because the POR before the output voltage of the regulator circuit 8 drops to the power supply voltage at which the operation of the POR circuit 10 becomes unstable. This is because the VtPOR circuit 11 outputs the reset signal POR2B to the control logic circuit 6 instead of the circuit 10.

  The operation of the above configuration will be described. First, the operation state in the normal operation mode will be described. The constant power supply circuit 7 supplies the standby power supply voltage CVCC_STB to the latch circuit 12, the standby power-on reset circuit 13, and the various gates G1 to G7 regardless of the mode state (normal operation mode, low power consumption mode).

  In the normal operation mode, since the latch circuit 12 outputs the “L” level Q, the “H” level is given to the inputs of the AND gate G1 and the OR gate G2. The “H” level of this output is applied to the wake-up / standby terminal WKUP / STB of the reference voltage generation circuit 9 through the OR gate G2. Therefore, the NMOS transistor Mn2 in the reference voltage generation circuit 9 shown in FIG. 3 is turned on, and the constant current generation circuit 16, the constant voltage generation circuit 17, and the reference voltage generation circuit 18 all operate normally and output the reference voltage V1. .

  At this time, since the operational amplifier 23 in the reference voltage generation circuit 18 drives the output NMOS transistor Mn3, a current proportional to the drain output current of the NMOS transistor Mn3 flows to the drain source of the NMOS transistor Mn4. Then, the electric charge accumulated at the terminal of the capacitor C1 being pulled up is discharged.

  When the capacitor C1 is discharged, the negative input of the AND gate G1 becomes “L” level, and the AND gate G1 uses the “H” level of the Q output of the latch circuit 12 as the wakeup signal WKUP. Passes to standby terminal WKUP / STB. The regulator circuit 8 starts to start, and the regulator circuit 8 outputs a voltage corresponding to the output voltage V1 of the reference voltage generation circuit 9. In the normal operation mode, the regulator circuit 8 normally outputs the main power supply voltage CVCC (= 5 V) to the microcomputer chip 2, the control logic circuit 6, the POR circuit 10, and the VtPOR circuit 11.

  In the POR circuit 10 shown in FIG. 4, a voltage obtained by dividing the output voltage (main power supply voltage CVCC) of the regulator circuit 8 according to a voltage dividing resistor is set as a POR voltage VPOR, and this POR voltage VPOR is output from the reference voltage generation circuit 9. The result compared with the voltage V1 is output. Further, as described above, the VtPOR circuit 11 is a predetermined voltage of a circuit using various MOS transistors (for example, 1 or 2 times the threshold voltage of the transistor, or a voltage (Vtn + Vtp, MAX (Vtn, Vtp ), MAX (αVtn, βVtp))) is output.

<Transition from normal operation mode to low power consumption mode>
The operation when shifting from the normal operation mode to the low power consumption mode will be described with reference to the left column of FIG.

  When the MCU 4 of the microcomputer chip 2 outputs the standby entry signal STB_ENT, the DFF 27 of the control logic circuit 6 raises the standby entry STB_ENT to “H” level. The control logic circuit 6 shifts the level by the level shift circuit 28 and outputs the standby entry signal STB_ENT to the latch circuit 12 through the AND gate G6. Then, the latch circuit 12 outputs a standby signal STBB (low active) to the AND gate G1 in the previous stage of the regulator circuit 8 and the OR gate G2 in the previous stage of the reference voltage generation circuit 9.

  Then, the standby signal STBB is applied to the wakeup / standby terminal WKUP / STB of the regulator circuit 8, the NMOS transistor Mn1 of the regulator circuit 8 is turned off, and the regulator circuit 8 stops outputting the main power supply voltage CVCC. Since the power supply voltage stabilizing capacitor C2 is externally attached to the outside of the control chip 3, the accumulated charge in the capacitor C2 is completely discharged even when the output of the regulator circuit 8 is turned off. The output voltage gradually decreases (see the timing after (1) in FIG. 8).

  The POR circuit 10 compares the output voltage V1 of the reference voltage generation circuit 9 with the proportional voltage of the output voltage of the regulator circuit 6, and outputs a power-on reset signal PORB according to the result. That is, when the output voltage of the regulator circuit 8 falls below the POR voltage VPOR, the POR circuit 10 outputs the power-on reset signal PORB (see timing (2) in FIG. 8).

  On the other hand, even if the latch circuit 12 outputs the standby signal STBB to the OR gate G2 in the preceding stage of the reference voltage generation circuit 9 at the timing (1) in FIG. 8, it is given to the negative input of the OR gate G2 through the VtPOR circuit 11. The standby signal STBB is invalidated due to the influence of the “L” level, and the reference voltage generation circuit 9 holds the output at the voltage V1.

  That is, since the output voltage V1 of the reference voltage generation circuit 9 is stably output during this period, the POR circuit 10 operates normally and the power-on reset signal PORB is normally output. As a result, the control logic circuit 6 is reliably reset. Although the output voltage of the regulator circuit 8 continues to decrease, this state continues until the VtPOR circuit 11 outputs the reset signal POR2B (low active) (see period (3) in FIG. 8).

  When the output voltage of the regulator circuit 8 reaches the VtPOR voltage VtPOR, the VtPOR circuit 11 outputs the reset signal POR2B to the control logic circuit 6 through the AND gate G7. As a result, even if the POR circuit 10 subsequently operates indefinitely, this influence is not exerted on the control logic circuit 6, and the control logic circuit 6 continues to be reset normally.

  The “L” level signal output from the VtPOR circuit 11 is simultaneously applied to the gate of the NMOS transistor Mn8. Then, the NMOS transistor Mn8 is turned off. When the NMOS transistor Mn8 is turned off, the drain of the NMOS transistor Mn8 is pulled up. Therefore, the “H” level is input to the negative input of the OR gate G2, and the standby signal STBB previously applied to the OR gate G2 is received. Enabled. As a result, the standby signal STBB is input to the wakeup / standby terminal WKUP / STB of the reference voltage generation circuit 9. When the standby signal STBB is supplied to the reference voltage generation circuit 9, the reference voltage generation circuit 9 sets the output voltage V1 to 0 [V] (see period (4) in FIG. 8).

  At this time, the operational amplifier 23 in the reference voltage generation circuit 9 gradually stops driving the output NMOS transistor Mn3, and when the output of the operational amplifier 23 is inverted, the NMOS transistor Mn3 is also turned off. The output ENO of the operational amplifier 23 serves as an operation instruction signal for the regulator circuit 8. At the same time, the NMOS transistor Mn4 is turned off. A current is supplied to the capacitor C1 through the pull-up resistor R24, and an “H” level is given to the negative input of the AND gate G1. Then, the output of the AND gate G1 is invalidated.

  Even if the output of the AND gate G1 is invalidated, the “L” level is continuously applied to the wakeup / standby terminal WKUP / STB of the regulator circuit 8, so that the regulator circuit 8 is lowered without starting. The output voltage is continuously set to 0 [V]. At the time of standby transition, the OR gate G2 and the AND gate G1 constitute a stop instruction circuit 30.

<Return from low power consumption mode to normal operation mode>
The operation when returning from the low power consumption mode to the normal operation mode will be described with reference to the right column of FIG.
When shifting to the low power consumption mode, the main power supply voltage CVCC is no longer supplied from the regulator circuit 8 to the microcomputer chip 2, the control logic circuit 6, the POR circuit 10, and the VtPOR circuit 11. However, the constant power supply circuit 7 continues to supply the standby power supply voltage CVCC_STB to the various gate circuits G1 to G7 and the latch circuit 12.

  Thereafter, the external ECU outputs a wakeup signal WKUPB (low active) as a wakeup event (see timing (5) in FIG. 8). When the wake-up signal WKUPB is received by the latch circuit 12 of the ECU 1, the latch circuit 12 outputs the wake-up signal WKUP (“H”: high active) as the Q output, the AND gate G1 in the previous stage of the regulator circuit 8, and the reference voltage generation. This is output to the OR gate G2 at the previous stage of the circuit 9.

  Then, the wakeup signal WKUP is given to the wakeup / standby terminal WKUP / STB of the reference voltage generation circuit 9, and the NMOS transistor Mn2 in the reference voltage generation circuit 9 is turned on. Then, the reference voltage generation circuit 9 outputs a standard reference voltage V1, and accordingly, the operational amplifier 23 of the reference voltage generation circuit 18 drives the NMOS transistor Mn3. And the accumulated charge in the capacitor C1 is gradually discharged.

  When the output voltage of the reference voltage generation circuit 9 reaches the predetermined voltage V1o, the output of the capacitor C1 decreases as the voltage V1 increases to 0 [V] (“L” level) (the terminal of the capacitor C1 in FIG. 8). See voltage ENO1).

  Since the “L” level is given to the negative input of the AND gate G1, the AND gate G1 activates the wakeup signal WKUP and gives the “H” level to the wakeup / standby terminal WKUP / STB of the regulator circuit 8. Then, the regulator circuit 8 starts to start, and the regulator circuit 8 increases the output voltage.

  At this time, since it takes time to charge the external capacitor C2, the output voltage of the regulator circuit 8 gradually increases. Since the VtPOR circuit 11 continues to give the reset signal POR2B to the control logic circuit 6 at the start timing of the regulator circuit 8, the control logic circuit 6 continues to be reset. Further, the POR circuit 10 does not have a possibility of indefinite operation when the output voltage of the regulator circuit 8 reaches a voltage exceeding the lower limit voltage of the operation guarantee of the POR circuit 10. At this time, since the POR circuit 10 inputs the voltage V1 from the reference voltage generation circuit 9 to the inverting input terminal of the comparator 26, the "L" level is supplied to the control logic circuit 6 as the reset signal PORB through the AND gate G7.

  Even if the output voltage of the regulator circuit 8 rises, the POR circuit 10 continues to output the power-on reset signal PORB to the control logic circuit 6, so that the control logic circuit 6 continues to be reset (see period (6) in FIG. 8).

  Thereafter, the output voltage of the regulator circuit 8 continues to rise, but when the POR voltage VPOR is reached, the POR circuit 10 stops outputting the power-on reset signal PORB, and the reset input to the reset terminal RSN of the control logic circuit 6 is released. Is done. Along with this, the control logic circuit 6 is activated. At startup, the OR gate G2 and the AND gate G1 constitute a startup instruction circuit 30.

  9 and 10 show a circuit configuration and its operation as a comparative example. The similar constituent elements shown in FIG. 9 are given the same reference numerals as described above. In this circuit configuration, the wakeup / standby signal WKUP / STBB output from the latch circuit 12 is used as the regulator circuit 8 and the reference voltage generator. Since it is directly applied to the wake-up / standby terminal WKUP / STB of the circuit 9, the regulator circuit 8 and the reference voltage generation circuit 9 are activated simultaneously.

  Since the regulator circuit 8 outputs a power supply voltage according to the voltage V1 of the reference voltage generation circuit 9, as shown in the timing chart of FIG. 10, the output voltage V1 of the reference voltage generation circuit 9 and the output voltage of the regulator circuit 8 are Depending on the relationship, the POR circuit 10 may not normally output the power-on reset signal PORB stably as a normal row active signal, and the control logic circuit 8 may not be reset normally and may become unstable. (See (7) Period in FIG. 10).

  According to the present embodiment, when shifting from the low power consumption mode to the normal operation mode, when the wakeup signal WKUPB is received, the latch circuit 12 outputs the wakeup signal WKUP in a high active state, and the reference voltage generation circuit 9 The action is activated. Then, the reference voltage generation circuit 9 generates the reference voltage V1, and the output voltage of the reference voltage generation circuit 9 is a predetermined voltage (in the normal operation of the reference voltage V1 from the initial value (0V) in the low power consumption mode) ( After reaching the specified voltage (V1o), the wake-up signal WKUP is input to the regulator circuit 8 to start the regulator circuit 8.

  Then, until the regulator circuit 8 is activated and its output voltage rises to the POR voltage VPOR, the POR circuit 10 continues to output the reset signal PORB to the reset terminal RSN of the control logic circuit 6, and the control logic circuit 6 is normal. Reset to. Thereby, malfunction of the control logic circuit 6 can be prevented. When the regulator circuit 8 normally outputs the main power supply voltage CVCC that is equal to or higher than the VPOR voltage VPOR, the control logic circuit 6 can normally operate.

  The AND gate G1 as a digital gate circuit blocks the wakeup signal WKUP transmitted to the regulator circuit 8 until the output voltage of the reference voltage generation circuit 9 reaches a predetermined voltage V1o. As a result, the digital gate circuit can be used to perform a sequence operation and can be reliably reset.

  Further, according to the present embodiment, when shifting from the normal operation mode to the low power consumption mode, the control chip 3 receives the standby entry signal STB_ENT from the microcomputer chip 2 and shifts to the standby mode (low power consumption mode). When the latch circuit 12 outputs the standby signal STBB in a low active state, the operation of the regulator circuit 8 is first invalidated and the output voltage of the regulator circuit 8 is lowered.

  When the output voltage of the regulator circuit 8 becomes less than the POR voltage VPOR, the POR circuit 10 outputs the power-on reset signal PORB, and the control logic circuit 6 receives the reset signal RSN as a reset signal. Thereby, the control logic circuit 6 is normally reset.

  Thereafter, when the output voltage of the regulator circuit 8 reaches the VtPOR voltage VtPOR, the VtPOR circuit 11 outputs a reset signal POR2B to the reset terminal RSN of the control logic circuit 6 through the AND gate G7. This is because the control logic circuit 6 continues to be reset normally even if the output voltage of the regulator circuit 8 drops and the POR circuit 10 becomes unstable.

  When the VtPOR circuit 11 outputs the reset signal POR2B, the OR gate G2 activates the standby signal STBB and stops the operation of the reference voltage generation circuit 9. In the low power consumption mode, since the operations of the regulator circuit 8 and the reference voltage generation circuit 9 are stopped, the power consumption can be reduced. Furthermore, in the low power consumption mode, the control logic circuit 6 and the microcomputer chip 2 are also disconnected, so that the power consumption can be further reduced.

  The OR gate G2 as a digital gate circuit blocks the standby signal STBB transmitted to the reference voltage generation circuit 9 until the VtPOR circuit 11 outputs the reset signal POR2B. Thus, the sequence operation can be performed using the digital gate circuit, and the reset signal can be reliably continued to be supplied to the control logic circuit 6 until the output voltage of the regulator circuit 8 decreases.

  The VtPOR circuit 11a shown in FIG. 5 employs an added voltage Vtp + Vtn obtained by adding the threshold voltage Vtp of the PMOS transistor Mp2 and the threshold voltage Vtn of the NMOS transistor Mn5 as the VtPOR voltage. Further, the VtPOR circuit 11b shown in FIG. 6 employs the higher one of the threshold voltage Vtp of the PMOS transistor Mp4 and the threshold voltage Vtn of the NMOS transistor Mn6 as the VtPOR voltage. Also, the VtPOR circuit 11c shown in FIG. 7 employs a higher voltage of αVtp or βVtn as the VtPOR voltage. As a result, the VtPOR voltage can be selected as appropriate in accordance with the configuration of the POR circuit 10 and can be flexibly handled.

(Second Embodiment)
FIG. 11 shows the second embodiment. The difference from the previous embodiment is that a delay circuit 31 is provided between the reference voltage generation circuit 9 and the regulator circuit 8 to constitute a start instruction circuit and a stop instruction circuit. There is.

  In this embodiment, instead of the AND gate G1, the NMOS transistor Mn4, the capacitor C1, and the pull-up resistor R24 shown in FIG. 1, the output voltage V1 of the reference voltage generation circuit 9 is regulated via a delay circuit 31 as shown in FIG. This is given to the circuit 8.

That is, even in such a configuration, since the output voltage V1 of the reference voltage generation circuit 9 is started before the regulator circuit 8, the regulator circuit 8 can output the output voltage with a delay, which is almost the same as in the above-described embodiment. The effect is obtained.
The delay circuit 31 may be configured by an analog circuit such as a CR delay circuit, or may be configured by a digital circuit such as a timer.

(Third embodiment)
12-15 shows description of 3rd Embodiment. In the third embodiment, the operation at the momentary power interruption (instant interruption) will be described.
FIG. 12 is a timing chart showing the operation when the output voltage of the regulator circuit 8 drops to the vicinity of the VPOR voltage VPOR when the circuit shown in FIG. 9 is applied. When the circuit shown in FIG. 9 is applied, when the output voltage of the regulator circuit 8 starts to decrease, the output voltage of the reference voltage generation circuit 9 immediately decreases. For this reason, the output voltage of the regulator circuit 8 continues to drop below the POR voltage VPOR.

  At this time, when the output voltage of the regulator circuit 8 falls below the POR voltage VPOR, the output voltage of the reference voltage generation circuit 9 has already dropped, so the POR circuit 10 cannot output the reset signal PORB ((8) in FIG. 12). Period reference). As a result, the operation of the control logic circuit 6 may become unstable.

  FIG. 13 is a timing chart showing the operation when the output voltage of the regulator circuit 8 drops to the vicinity of the VPOR voltage VPOR when the circuit described in the first embodiment (FIG. 1) is applied. Even if the output voltage of the regulator circuit 8 is momentarily cut off, when the VPOR voltage VPOR is equal to or higher than the VPOR voltage VPOR, the reference voltage generation circuit 9 continuously outputs the standard reference voltage V1 ((10) in FIG. 13). Period reference). Therefore, normal operation can be maintained.

  FIG. 14 is a timing chart showing an operation when the circuit shown in FIG. 9 is applied and the output voltage of the regulator circuit 8 drops to near the VtPOR voltage VtPOR which is lower than the VPOR voltage VPOR. When the circuit shown in FIG. 9 is applied, when the output voltage of the regulator circuit 8 starts to decrease, the output voltage of the reference voltage generation circuit 9 immediately decreases (see the period (11) in FIG. 14).

  When the output voltage of the regulator circuit 8 is lower than the POR voltage VPOR, the output voltage of the reference voltage generation circuit 9 has already decreased, so that the output voltage of the POR circuit 10 continues to decrease gradually. The on-reset signal PORB (“L” level) is not output (see the period (12) in FIG. 14). As a result, the operation of the control logic circuit 6 may become unstable.

  Note that when the output voltage of the regulator circuit 8 drops to near the VtPOR voltage VtPOR, the reference voltage generation circuit 9 is not activated, so the output voltage of the regulator circuit 8 continues to drop below the VtPOR voltage VtPOR. After that, when the power is restored, the output voltage of the POR circuit 10 inverts and rises, so that the POR circuit 10 does not output the power-on reset signal PORB and the power is restored.

  FIG. 15 is a timing chart showing an operation when the output voltage of the regulator circuit 8 is reduced to the vicinity of the VPOR voltage VPOR when the circuit described in the first embodiment (FIG. 1) is applied. When the output voltage of the regulator circuit 8 is momentarily cut off and the output voltage becomes less than the VPOR voltage VPOR, the POR circuit 10 outputs the power-on reset signal PORB. Then, since a reset signal is given to the reset terminal RSN of the control logic circuit 6, the control logic circuit 6 is reset during this period (see period (13) in FIG. 15).

  However, if the output voltage of the regulator circuit 8 is equal to or higher than the VtPOR voltage VtPOR, the reference voltage generation circuit 9 continues to output a standard reference voltage (specified voltage) V1 at a constant level. Continue to work. Thereafter, when the wake-up signal WKUP is received in a state where the output voltage of the regulator circuit 8 does not become less than the VtPOR voltage VtPOR, the regulator circuit 8 returns to the power supply (see (14) in FIG. 15).

  As long as the output voltage of the regulator circuit 8 does not exceed the VPOR voltage VPOR, the power-on reset signal PORB continues to be output. During this time, the control logic circuit 6 can be normally reset (see (15) in FIG. 15).

  That is, according to the configuration of the above-described embodiment, the reference voltage generation circuit 6 is a normal standard if the output voltage of the regulator circuit 8 is equal to or higher than the VtPOR voltage VtPOR even if the power supply is momentarily shut off. Continue to output the reference voltage V1. Therefore, when the output voltage of the regulator circuit 8 is lower than the VPOR voltage VPOR, the reset signal can be normally given to the control logic circuit 6. As a result, when the regulator circuit 8 returns to the power source, the control logic circuit 6 can return to the operation, and substantially the same operation and effect as in the above-described embodiment can be obtained.

(Other embodiments)
The present invention is not limited to the above-described embodiment, and can be modified or expanded as follows, for example.
Although the embodiment in which the regulator circuit 8 that outputs the positive power supply voltage and the reference voltage generation circuit 9 are applied has been described, the regulator circuit 8 and the reference voltage generation circuit 9 may be a circuit that outputs the negative power supply voltage.

In the drawing, 8 is a regulator circuit (main power supply circuit), 9 is a reference voltage generation circuit, 10 is a power-on reset circuit, 11, 11a to 11c are Vt power-on reset circuits (alternative reset circuits), 31 is a delay circuit,
G1 is an AND gate (first digital gate circuit), G2 is an OR gate (second digital gate circuit), G1 and G2 are a stop instruction circuit and a start instruction circuit, and G2 and 31 are a stop instruction circuit and a start instruction circuit.

Claims (10)

A reference voltage generation circuit (9) for generating a reference voltage;
A main power supply circuit (8) for outputting a power supply voltage generated according to the generated voltage of the reference voltage generating circuit to the target circuit (6);
A power-on reset circuit (10) for generating a power-on reset signal according to the level of the voltage generated according to the generated voltage of the reference voltage generating circuit and the output voltage of the main power supply circuit and outputting the signal to the target circuit; With
In the normal operation mode, the main power supply circuit supplies a main power supply voltage generated according to the reference voltage of the reference voltage generation circuit to the target circuit. In the low power consumption mode, the main power supply circuit and the reference voltage generation circuit A power supply circuit that stops operation,
When a wake-up event is received in the low power consumption mode, the operation of the reference voltage generation circuit is validated, and the output voltage of the reference voltage generation circuit is changed from an initial value in the low power consumption mode to a predetermined value during normal operation of the reference voltage. A power supply circuit comprising a start instruction circuit (G1 and G2, G2 and 31) for starting the main power supply circuit after reaching a voltage. The power supply circuit according to claim 1,
The start instruction circuit (G1 and G2)
A circuit for instructing activation of the main power supply circuit by transmitting a wake-up signal to the main power supply circuit;
A power supply circuit comprising a first digital gate circuit (G1) for cutting off the wake-up signal transmitted to the main power supply circuit until an output voltage of the reference voltage generation circuit reaches the predetermined voltage. The power supply circuit according to claim 1,
The start instruction circuit (G2 and 31)
A power supply circuit comprising a delay circuit (31) for delaying output of a generated voltage of the reference voltage generating circuit, which is a source of the main power supply voltage. The power supply circuit according to any one of claims 1 to 3,
When shifting from the normal operation mode to the low power consumption mode, the reset signal is output before the power-on reset circuit (10) reaches a voltage at which the operation becomes indefinite or before reaching a voltage in which a margin is added to the voltage. Substitute reset circuits (11, 11a to 11c) for outputting to the target circuit instead of the power-on reset circuit (10),
When a transition to the low power consumption mode is made in the normal operation mode, the operation of the main power supply circuit is stopped and the operation of the reference voltage generation circuit is stopped at the timing when the alternative reset circuit outputs a reset signal. And G2). The power supply circuit according to claim 4, wherein
The alternative reset circuit (11, 11a to 11c) includes a transistor, and outputs a power-on reset signal when the output voltage of the main power supply circuit is less than one or twice the threshold voltage of the transistor. A power supply circuit that outputs to the target circuit. The power supply circuit according to claim 4 or 5,
The stop instruction circuit (G1 and G2) is a circuit that instructs the reference voltage generation circuit to stop by transmitting a standby signal to the reference voltage generation circuit,
A second digital gate circuit (G2) that cuts off the standby signal transmitted to the reference voltage generation circuit until a timing at which the alternative reset circuit (11, 11a to 11c) outputs a reset signal is provided. Power supply circuit. The power supply circuit according to any one of claims 4 to 6,
The alternative reset circuit (11a)
A diode-connected first NMOS transistor (Mn5);
A first resistor (R13) connected between an output terminal of the main power supply circuit and a drain of the first NMOS transistor;
A first PMOS transistor (Mp2) having a gate connected to a common connection node of the first resistor and the first NMOS transistor;
A second resistor (R14) connected in series with the drain and source of the first PMOS transistor and pulled down to ground;
A power supply circuit, wherein a common connection node between the first PMOS transistor and the second resistor is used as an output of a determination result. The power supply circuit according to any one of claims 4 to 6,
The alternative reset circuit (11b)
A second NMOS transistor (Mn6) connected between the gate and the source between the output terminal of the main power supply circuit and the ground;
A first current mirror circuit (M1) having an energization current of the second NMOS transistor as an input current;
A third resistor (R16) for energizing the output current of the first current mirror circuit,
A power supply circuit, wherein a common connection point between the third resistor and the first current mirror circuit is used as an output of a determination result. The power supply circuit according to any one of claims 4 to 6,
The alternative reset circuit (11c)
A voltage dividing resistor (R17 to R19) having two or more voltage outputs connected between the output terminal of the main power supply circuit and the ground;
A third NMOS transistor (Mn7) for inputting the first voltage output of the voltage dividing resistor to the gate;
A second PMOS transistor (Mp5) for inputting the second voltage output of the voltage dividing resistor to the gate;
A second current mirror circuit (M2) having an energization current of the third NMOS transistor and the second PMOS transistor as an input current;
A fourth resistor (R21) for energizing the output current of the second current mirror circuit,
A power supply circuit, wherein a common connection point between the fourth resistor and the second current mirror circuit is used as an output of a determination result. The power supply circuit according to any one of claims 1 to 3,
When shifting from the normal operation mode to the low power consumption mode, the power-on reset circuit outputs a reset signal before reaching a voltage at which the power-on reset circuit becomes indefinite or before reaching a voltage with a margin added to the voltage. An alternative reset circuit (11, 11a to 11c) for outputting to the target circuit instead of (10),
When the output voltage of the main power supply circuit decreases in a normal operation mode, the reference voltage generation circuit continues to output a normal reference voltage while the alternative reset circuit does not output a reset signal. circuit.

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