JP5482419B2 - Semiconductor integrated circuit for regulator - Google Patents

Description

  The present invention relates to a technique for reducing a rush current in a DC power supply apparatus and further a voltage regulator for converting a DC voltage, for example, a technique effective for use in a semiconductor integrated circuit (regulator IC) constituting a series regulator.

  There is a series regulator (hereinafter abbreviated as a regulator) as a power supply device that outputs a DC voltage of a desired potential by controlling a transistor provided between a DC voltage input terminal and an output terminal. A capacitor having a relatively large capacitance value is connected to the output terminal of the regulator IC that constitutes such a regulator in order to keep the output voltage constant regardless of the load variation.

  For this reason, it is known that a relatively large inrush current (so-called rush current) flows when trying to charge the capacitor in a discharged state at once when the regulator is started. As an invention for reducing the rush current at the start-up of the regulator, there are inventions described in Patent Document 1 and Patent Document 2, for example.

Japanese Utility Model Publication No. 59-178720 JP-A-6-4157

  In the regulator, in order to control the output voltage, as shown in FIG. 5, the output voltage is divided by the bleeder resistors R1 and R2 to generate the feedback voltage VFB, and the error amplifier AMP responds to the potential difference from the reference voltage Vref. A voltage is generated to control the gate terminal of the voltage control transistor Tr0. The reference voltage Vref supplied to the error amplifier is often generated using a Zener diode Dz. In the power supply devices described in Patent Document 1 and Patent Document 2, a rush current is prevented by providing a capacitor C1 in parallel with the Zener diode Dz so as to moderate the rise of the reference voltage Vref. .

  By the way, in addition to the method of turning on the power switch at the time of startup and directly raising the input voltage as in the power supply devices described in Patent Document 1 and Patent Document 2, in recent years, a system control device such as a microcomputer has been used. A method of starting up a regulator by raising a control signal such as a chip enable signal supplied from the factory has been adopted. This has the advantage that a power switch is not required. In addition, in such a start-up type regulator, it is possible to suppress the rush current by regulating the rising speed of the control signal, and to realize the same rising characteristic even in systems having different input voltage potentials. be able to.

  However, since the control signal output from the microcomputer is generally a signal having a high rise speed, it is necessary to provide a time constant circuit composed of a resistor and a capacitor as an external circuit in order to moderate the rise of the control signal. As the number of components increases, it is necessary to add a circuit for suppressing the rush current inside the chip.

  The present invention has been made paying attention to the problems as described above, and the object thereof is to constitute a DC power supply device such as a series regulator having a control terminal for externally turning on / off the circuit. In a semiconductor integrated circuit, a rush current is prevented from flowing toward an output terminal immediately after activation by a control signal.

  Another object of the present invention is to prevent a rush current from flowing toward an output terminal immediately after startup by a control signal without increasing current consumption.

To achieve the above object, the present invention controls a voltage control element connected between a voltage input terminal to which a DC voltage is input and an output terminal, and the voltage control element in accordance with an output feedback voltage. A control circuit including an error amplifier, a constant voltage generation circuit that generates a reference voltage input to the error amplifier, and an external control terminal to which a control signal that instructs on / off of the control circuit is input from the outside. A regulator semiconductor integrated circuit, wherein the constant voltage generation circuit includes a current source including a depletion type MOS transistor connected in series between the voltage input terminal or the output terminal and a ground potential terminal, and a reference voltage comprising a circuit, a connection node between the current source and the reference voltage circuit, an external for adjusting the rise time of the output voltage outputted to the output terminal The reference voltage circuit has a depletion type MOS transistor and an enhancement type MOS transistor connected in series, and a voltage determined by the threshold voltage of these transistors is used as the reference voltage. It is configured to output.

  According to the regulator semiconductor integrated circuit having the above-described configuration, the reference voltage generated by the constant voltage generation circuit at the time of start-up by the control signal is prevented from rising rapidly and the voltage control element from being turned on rapidly. Accordingly, it is possible to prevent a rush current from flowing toward the output terminal.

  Preferably, the current source and the reference voltage circuit are connected in series between the output terminal and a ground potential terminal, and a connection node between the voltage input terminal, the current source and the reference voltage circuit. And an activation circuit that temporarily supplies a current from the voltage input terminal to the connection node at the time of activation when the control signal changes to a state instructing ON.

  According to the above configuration, since the current source and the reference voltage circuit are connected in series between the output terminal and the ground potential terminal, a stable voltage is output without being affected by noise included in the input voltage. can do. In addition, since the activation circuit is provided, even if the current source and the reference voltage circuit are connected between the output terminal and the ground potential terminal, the activation circuit can be reliably activated.

  Further, preferably, an ON state is established between the external terminal to which an external capacitor is connected and the ground potential terminal when the control signal input to the external control terminal changes to a state instructing OFF. Then, the switch element for discharging the charge of the capacitor connected to the external terminal is connected. Thereby, when the control signal changes to a state instructing to turn off, the charge of the capacitor is discharged, so that the reference voltage can be quickly lowered to cut off the output voltage.

Preferably, the start-up circuit includes a normally-on first depletion type MOS transistor connected in series between the voltage input terminal and a connection node between the current source and the reference voltage circuit, and An enhancement-type MOS transistor having a voltage corresponding to the control signal applied to the gate terminal;
Between the gate terminal of the enhancement type MOS transistor and the ground potential terminal, the enhancement type MOS transistor is turned on after a reference voltage is controlled and rises according to a feedback voltage supplied to the error amplifier, and the start circuit The second switch element that cuts off the current flowing from is connected. As a result, the startup circuit can be realized with a small number of elements, and after the reference voltage rises, the current of the startup circuit can be cut off to reduce the current consumption.

  Further, preferably, between the gate terminal of the enhancement type MOS transistor and the output terminal of the logic gate circuit for inverting the control signal input to the external control terminal or the external control terminal, the gate terminal and the source A second depletion type MOS transistor having a terminal coupled is connected. Thereby, current consumption when the MOS transistor (Tr7) is turned on can be suppressed.

  As described above, according to the present invention, in a semiconductor integrated circuit constituting a DC power supply device such as a series regulator having a control terminal for externally turning on and off the circuit, an output terminal immediately after startup by a control signal It is possible to prevent a rush current from flowing toward Further, there is an effect that it is possible to prevent a rush current from flowing toward the output terminal immediately after startup by the control signal without increasing the current consumption.

It is a circuit block diagram which shows one Embodiment of IC for regulators to which this invention is applied. 2 is a timing chart showing changes in voltages at various parts of the regulator IC in FIG. 1. FIG. 6 is a circuit configuration diagram showing a modification of the regulator IC of FIG. 1. It is a circuit block diagram which shows 2nd Embodiment of IC for regulators to which this invention is applied. It is a circuit diagram which shows an example of the conventional stabilized power supply circuit (series regulator).

  DESCRIPTION OF EXEMPLARY EMBODIMENTS Hereinafter, preferred embodiments of the invention will be described with reference to the drawings.

  FIG. 1 shows an embodiment of a series regulator to which the present invention is applied. In the figure, a portion surrounded by a one-dot chain line is formed as a semiconductor integrated circuit (regulator IC) 10 on a semiconductor chip such as single crystal silicon.

  In the regulator IC 10 of this embodiment, a P-channel MOSFET (insulated gate field effect transistor: hereinafter referred to as a MOS transistor) is provided between a voltage input terminal IN to which a DC voltage VDD is applied and an output terminal OUT. The voltage control transistor Tr0 is connected, and bleeder resistors R1 and R2 for dividing the output voltage are connected in series between the output terminal OUT and the ground terminal GND to which the ground potential is applied.

  The voltage VFB divided by the bleeder resistors R1 and R2 is fed back to the non-inverting input terminal of the error amplifier 11 that controls the gate terminal of the voltage control transistor Tr0. The error amplifier 11 controls the voltage control transistor Tr0 in accordance with the potential difference between the feedback voltage VFB and the reference voltage Vref so as to control the output voltage Vout to a desired potential.

  Further, the regulator IC 10 of the present embodiment includes a bias circuit 12 for supplying a bias current to the error amplifier 11 and a reference voltage generation circuit 13 using a depletion type MOS transistor for generating a reference voltage Vref to be supplied to the error amplifier 11. An activation circuit 14 for activating the reference voltage generation circuit 13 when the power is turned on is provided.

  Further, the regulator IC 10 of the present embodiment includes a chip enable terminal CE to which a control signal for controlling on / off of the chip from the outside is input, and the error amplifier at the rise of the control signal input to the terminal. An external terminal CS is provided for connecting a capacitor C1 for delaying the rise of the reference voltage Vref applied to the inverting input terminal 11 to prevent a rush current from outside the chip.

  The bias circuit 12 is configured to be turned on / off by a signal input to the chip enable terminal CE. Further, between the external terminal CS and the ground point, when the input signal of the terminal CE falls, the charge of the capacitor C1 is discharged, the reference voltage Vref is lowered, and the voltage control transistor Tr0 is quickly turned off. In order to shut off the output in the state, a switch MOS transistor Tr4 made of an N-channel MOSFET is provided. Note that in this specification, a depletion type MOS transistor and a MOS transistor that is not distinguished from each other mean an enhancement type transistor.

  The reference voltage generation circuit 13 includes depletion type MOS transistors Tr1 and Tr2 and an enhancement type MOS transistor Tr3 connected in series between the output terminal OUT and the ground terminal GND. The gate terminals of the depletion type MOS transistor Tr2 and the enhancement type MOS transistor Tr3 are coupled to each other, the gate terminal and the source terminal are coupled to Tr2, and the gate terminal and the drain terminal are coupled to Tr3. The transistor Tr1 functions as a current source for flowing an operating current to the reference voltage circuit.

  In this reference voltage circuit, the potential of the connection node N2 between the transistors Tr2 and Tr3 is taken out as the reference voltage Vref. A connection node N1 between the transistor Tr1 as the current source and the reference voltage circuit (Tr2, Tr3) is connected to an external terminal CS to which the capacitor C1 is connected.

  Conventionally, a circuit in which a depletion type MOSFET in which a gate and a source are coupled and an enhancement type MOS transistor in which a gate and a drain are coupled is connected in series, the depletion type MOS transistor operates as a constant current source, and the enhancement type MOS transistor It is known as a reference voltage circuit that outputs a constant voltage generated between a source and a drain as a reference voltage. The reference voltage Vref generated by this reference voltage circuit is expressed as a difference Vt (e) −Vt (d) between the threshold voltages Vt (d) and Vt (e) of the two MOS transistors.

  The startup circuit 14 includes a depletion type MOS transistor Tr5 and an enhancement type MOS transistor Tr6 connected in series between the DC voltage input terminal IN and the node N1 of the reference voltage generation circuit 13, and a gate terminal of the transistor Tr6. Between the MOS transistor Tr7 connected between the ground point and the output terminal of the subsequent INV2 of the inverters INV1 and INV2 for inverting the control signal input to the chip enable terminal CE and the gate terminal of the transistor Tr6. A depletion type MOS transistor Tr8 is connected. The transistor Tr7 is an enhancement type MOSFET.

  The depletion type MOS transistor Tr5 functions as a normally-on switch in which a gate and a source are coupled. Tr6 is controlled to be in an ON state at the rising edge of the control signal input to the chip enable terminal CE. The transistor Tr7 is an element for turning off the transistor Tr6 after the reference voltage circuit is activated. The transistor Tr8 has a gate and a source coupled to each other, and limits the current flowing from the Tr8 to the Tr7 when the Tr7 is turned on, thereby suppressing current consumption. Therefore, a combination of the transistors Tr5, Tr6, Tr7, and Tr8 is a starting circuit.

  As described above, the depletion type MOS transistor Tr1 connected to the output terminal OUT is provided in addition to the normally-on transistor Tr5, so that the operating current of the reference voltage circuit for generating the reference voltage Vref flows from the output voltage side. The reason is that even if noise is present on the input DC voltage VDD, it is absorbed by the voltage control transistor Tr0 and almost no noise appears in the output voltage Vout. Therefore, the noise in which the reference voltage Vref is on the input voltage. It is because it becomes difficult to be influenced by. The start circuit 14 is provided because the output voltage Vout is 0 V before the rising voltage control transistor Tr0 of the control signal of the terminal CE is turned on, and even if the transistor Tr1 is turned on, the reference voltage circuit is provided. This is because no current flows and the reference voltage Vref does not rise.

  Next, the operation of the regulator IC of FIG. 1 will be described using the timing chart of FIG.

  As shown in FIG. 2A, when the control signal EN input to the chip enable terminal CE changes from the low level to the high level (VDD), the error amplifier 11 is activated by the current flowing from the bias circuit 12. . On the other hand, since the MOS transistor Tr6 of the starter circuit 14 is also turned on when the control signal EN becomes high level, the current I1 flows from the input terminal IN side through the normally-on transistor Tr5 and the transistor Tr6, so Capacitor C1 is charged.

  When the potential of the node N1 becomes high to some extent, the reference voltage circuit (Tr2, Tr3) operates and the reference voltage Vref rises. Before the reference voltage Vref rises, the output of the error amplifier 11 is at a high level and the voltage control transistor Tr0 is turned off. However, when the reference voltage Vref rises, the output of the error amplifier 11 falls and the voltage control transistor Tr0 is turned off. The output voltage Vout starts to rise after being turned on.

  When the output voltage Vout increases to some extent, the current I2 starts to flow from the depletion type MOS transistor Tr1 to the reference voltage circuit (Tr2, Tr3), and the voltage VFB divided by the bleeder resistors R1, R2 also increases, and the MOS transistor Tr7. Is turned on, and the gate voltage of the transistor Tr6 is lowered to the ground potential. Then, the transistor Tr6 is turned off, and the current I1 flowing to the node N1 decreases rapidly (timing t1).

  On the other hand, the current I2 flowing to the node N1 through the transistor Tr1 increases because it is consumed for charging the capacitor C1 for a while after that, but decreases as the capacitor C1 approaches a fully charged state. When fully charged and the output voltage Vout completely rises, only the current I3 flowing to the reference voltage circuit (Tr2, Tr3) is obtained. Therefore, even if C1 is added, the current consumption in the steady state does not increase.

  According to the regulator IC including the reference voltage generating circuit 13 and the starting circuit 14 configured as described above, as shown in FIG. 2, even if the control signal at the terminal CE rises rapidly, the output voltage Vout gradually increases. Even if a large smoothing capacitor is connected to the output terminal OUT, the rush current flowing toward the output terminal is suppressed. Compared to the case where the capacitor C1 is not provided, the rush current can be reduced to 1/10 or less.

  In addition, the regulator IC of this embodiment has an advantage that the rise time of the output voltage Vout can be adjusted by changing the capacitance value of the capacitor C1 connected to the external terminal CS. Furthermore, the regulator IC of the present embodiment has an advantage that the current consumption of the IC in a steady state does not increase because the current of the startup circuit 14 is cut off when VFB increases until Tr7 is turned on.

  Next, a case where the input control signal of the chip enable terminal CE falls from the high level to the low level at the time of activation will be described. When the control signal at the terminal CE falls, the outputs of the inverters INV1 to INV3 that invert this signal change to a high level, the transistor Tr4 is turned on, and the charge of the capacitor C1 is extracted, so that the potential of the node N1 rapidly As a result, the reference voltage Vref falls, the output of the error amplifier 11 increases, and the voltage control transistor Tr0 is turned off.

  FIG. 3 shows a modification of the regulator of the above embodiment.

  The regulator of this modification uses a resistor R3 instead of the depletion type MOS transistor Tr1 of the reference voltage generation circuit 13 in the embodiment of FIG. The resistor R3 functions as a current source that supplies an operating current to the reference voltage circuit (Tr2, Tr3), and that current is consumed to charge the capacitor C1 during startup. Therefore, in the regulator of this modified example, as in the regulator of FIG. 1, the rising of the reference voltage Vref input to the error amplifier 11 at the time of activation by the control signal can be moderated to suppress the rush current. There is.

  In this modification, a limiter circuit 15 is provided for limiting the output current, which is connected to the gate terminal of the voltage control transistor Tr0. The limiter circuit 15 causes the gate voltage to exceed a certain level when the output current increases due to a short circuit of the load, the output voltage decreases, and the error amplifier 11 attempts to decrease the gate voltage so that more current flows through the transistor Tr0. The output current is limited by clamping so that it does not fall. Therefore, it is possible to protect the overcurrent from flowing through the voltage control transistor Tr0. Such a limiter circuit may also be provided in the regulator of the embodiment of FIG.

  FIG. 4 shows a second embodiment of the regulator according to the present invention.

  In this embodiment, the regulator is provided with the reference voltage generation circuit 13 including the depletion type MOS transistors Tr1 and Tr2 and the enhancement type MOS transistor Tr3 in the embodiment of FIG. 1 on the input terminal side. Also in the regulator of this embodiment, by providing the external terminal CS for connecting the capacitor C1 to the connection node N1 of the transistors Tr1 and Tr2, as in the regulator of FIG. Thus, there is an effect that the rise of the reference voltage Vref can be moderated and the rush current can be suppressed.

  Further, the regulator according to the second embodiment has an advantage that the starting circuit 14 is not necessary. However, there is a problem in that it is more susceptible to noise on the input DC voltage Vin than the regulator of FIG. Therefore, the regulator of this embodiment is effective when used in a system in which the input DC voltage Vin is originally a voltage from a power source with little noise.

  Although the invention made by the present inventor has been specifically described based on the embodiment, the present invention is not limited to the above embodiment. For example, in the circuit of FIG. 1, the MOS transistor Tr8 is provided between the gate terminal of the transistor Tr6 and the output terminal of the inverter INV2, but may be provided between the gate terminal of the transistor Tr6 and the chip enable terminal CE. Good.

  Furthermore, in the above-described embodiment, a MOSFET is used as the voltage control transistor Tr0. However, a bipolar transistor may be used instead of the MOSFET. In the above embodiment, an on-chip element is used as the voltage control transistor Tr0. However, since a relatively large current flows through the transistor, the transistor is configured to be connected as an external element. You may do it.

  In the above embodiment, the bleeder resistors R1 and R2 that divide the output voltage are provided inside the chip. However, an external resistor is provided and the voltage divided outside the chip is input from the external terminal to the error amplifier 11. It is also possible to configure it.

  In the above description, the example in which the present invention is applied to a series regulator has been described. However, the present invention is not limited to the present invention. For example, the present invention is applied to a regulator such as a charging device that charges a secondary battery such as a lithium ion battery. Can be used.

10 Regulator IC
11 Error amplifier 12 Bias circuit 13 Reference voltage generation circuit 14 Startup circuit CE External control terminal (chip enable terminal)
Tr0 Voltage control transistor Tr2, Tr3 Reference voltage circuit

Claims (5)

A voltage control element connected between a voltage input terminal to which a DC voltage is input and an output terminal; a control circuit including an error amplifier that controls the voltage control element in accordance with an output feedback voltage; and the error A regulator semiconductor integrated circuit comprising a constant voltage generation circuit for generating a reference voltage input to an amplifier, and an external control terminal for receiving a control signal for instructing on / off of the control circuit from the outside,
The constant voltage generation circuit includes a current source and a reference voltage circuit including a depletion type MOS transistor connected in series between the voltage input terminal or the output terminal and a ground potential terminal, and the current source and the reference voltage The connection node with the circuit is connected to an external terminal to which an external capacitor for adjusting the rise time of the output voltage output to the output terminal can be connected,
The reference voltage circuit is configured such that a depletion type MOS transistor and an enhancement type MOS transistor are connected in series, and a voltage determined by a threshold voltage of these transistors is output as the reference voltage. A semiconductor integrated circuit for regulators. The current source and the reference voltage circuit are connected in series between the output terminal and a ground potential terminal,
Provided between the voltage input terminal and a connection node between the current source and the reference voltage circuit, and from the voltage input terminal to the connection node at start-up when the control signal changes to a state instructing ON. 2. The regulator semiconductor integrated circuit according to claim 1, further comprising a start-up circuit that allows current to flow temporarily.   Between the external terminal to which an external capacitor is connected and the ground potential terminal, the external control terminal is turned on when the control signal input to the external control terminal changes to the off instruction state, and the external 3. The regulator semiconductor integrated circuit according to claim 2, wherein a switching element for discharging the charge of the capacitor connected to the terminal is connected. The start-up circuit controls the normally-on first depletion type MOS transistor and gate terminal connected in series between the voltage input terminal and a connection node between the current source and the reference voltage circuit. An enhancement type MOS transistor to which a voltage according to a signal is applied is provided,
Between the gate terminal of the enhancement type MOS transistor and the ground potential terminal, the enhancement type MOS transistor is turned on after a reference voltage is controlled and rises according to a feedback voltage supplied to the error amplifier, and the start circuit The regulator semiconductor integrated circuit according to claim 3, wherein a second switch element that cuts off a current flowing from the second switch element is connected.   A gate terminal and a source terminal are coupled between the gate terminal of the enhancement type MOS transistor and the output terminal of the logic control circuit that inverts the control signal input to the external control terminal or the external control terminal. 5. The semiconductor integrated circuit for a regulator according to claim 4, wherein a second depletion type MOS transistor is connected.

Images