JP2017041139A - LDO circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an LDO circuit controlling the rise time of output voltage of an LDO.SOLUTION: An LDO circuit 10 comprises a reference voltage generation circuit 11, a reference voltage rising control circuit 12 and an LDO 13. The reference voltage generation circuit 11 generates first reference voltage VREF from power supply voltage VDD1. The reference voltage rising control circuit 12 generates second reference voltage VREFSTUP on the basis of the first reference voltage VREF generated by the reference voltage generation circuit 11. The LDO 13, to which power supply voltage VDD2 is supplied, outputs output voltage LDOOUT on the basis of the second reference voltage VREFSTUP generated by the reference voltage rising control circuit 12.SELECTED DRAWING: Figure 1

Description

  The present invention relates to an LDO (Low Drop Out) circuit, and more particularly to an LDO circuit that controls a rise time of an output voltage of an LDO.

  Traditionally, one important decision in the design of electronic circuit systems is to determine the power supply voltage level. The optimum power supply voltage level differs from system to system, and therefore a circuit for converting the external power supply voltage into a specific value of the internal power supply voltage is required. A circuit used for this purpose is a regulator. In particular, a regulator having a small difference between the input voltage and the output voltage is referred to as an LDO (Low Drop Out Regulator), and this type of LDO is often used in a circuit in which the voltage difference between the input and the output is small. .

In general, the rise time of the output voltage of the LDO circuit is determined by the output load and the drive current. Therefore, conventionally, in order to control the rise of the output voltage of an LDO or the like, the control is performed by switching the drive current as the drive capability.
For example, Patent Document 1 discloses a first FET (field effect transistor) having a relatively high current driving capability between an input terminal and an output terminal, and a second FET having a relatively low current driving capability connected in parallel thereto. An FET is provided. In a predetermined period immediately after the power is turned on, only the second FET is driven to restrict the output current and prevent the rush current. A switch circuit that switches the connection destination of the gate of the first FET operates after a predetermined period of time to supply a drive voltage to the gate of the first FET to drive the first FET.

FIG. 6 is a block configuration diagram of a conventional LDO and its peripheral circuits, and FIG. 7 is a circuit configuration diagram of an LDO having a function of switching a conventional driving capability.
As shown in FIG. 6, a conventional LDO circuit 20 includes a reference voltage generation circuit 21 that outputs a reference voltage VREF from a power supply voltage VDD1 and a ground voltage GND, and an LDO based on the reference voltage VREF from the reference voltage generation circuit 21. LDO22 which outputs.
As shown in FIG. 7, the conventional LDO has an amplifier 221 in which a reference voltage VREF is input to a non-inverting input terminal (+) and a feedback voltage is input to an inverting input terminal (−), and an output signal of the amplifier 221. Are input to the gate, and have resistance dividers R1 and R2 connected between the output terminal LDOOUT and the ground voltage. A switch S is connected between the output terminal of the amplifier 221 and the gate terminal of the PMOS 2.
When the power is turned on, the switch S is turned off to start up with a low driving capability. In the normal state, the switch S is turned on to increase the driving capability. Thus, a configuration is known in which the number of PMOSs that operate at the time of power-on and during normal operation is switched.

JP 2009-146130 A

When an output voltage such as LDO is suddenly raised, there is a possibility of adversely affecting an external circuit that uses the output voltage as a power source.
Further, when the LDO is activated, if the difference between the voltage to be output by the LDO and the output terminal voltage is large, if the driving capability is large, a large current flows from the output of the LDO, and the LDO from the PMOS to the output terminal and from the output terminal to the LDO. There is also a possibility of the destruction of the wiring due to the current accompanied by a sudden change to the IC on the output receiving side.
For this reason, in order to suppress a steep change in the output voltage, there is a case in which switching is performed to reduce the drive capability of the LDO at the start-up to avoid the effects mentioned above.

However, when the LDO output voltage obtained by the configuration is used as a power supply for an external circuit, the LDO needs to have a driving capability for driving a current flowing in the external circuit at the time of startup. Since the slope of the rise voltage of the LDO depends on the drive capability of the LDO, it is difficult to moderate the rise voltage of the LDO without lowering the drive capability, which is the magnitude of the drive current of the LDO, in the conventional configuration. there were.
The present invention has been made in view of such problems, and an object of the present invention is to provide an LDO circuit capable of controlling the rise time of the output voltage of the LDO.

  A first aspect of the present invention includes a reference voltage generation circuit that generates a first reference voltage from a power supply voltage, a current generation circuit connected between the first reference voltage and a ground potential, and the current generation circuit And a reference voltage start-up control circuit that generates a second reference voltage from a node between the current generation circuit and the capacitance element, and And an LDO that outputs an output voltage based on the reference voltage.

  According to the present invention, the rising voltage can be moderated while ensuring the driving capability required when using the output voltage of the LDO as a power source without reducing the driving capability of the LDO at the time of startup.

It is a block block diagram for demonstrating Embodiment 1 of the LDO circuit which concerns on this invention. FIG. 2 is a specific circuit configuration diagram of a reference voltage rising control circuit shown in FIG. 1. It is a block block diagram for demonstrating Embodiment 2 of the LDO circuit which concerns on this invention. FIG. 4 is a specific circuit configuration diagram of a reference voltage start-up control circuit when the switch control circuit shown in FIG. 3 is added. FIG. 4 is a circuit configuration diagram of an LDO that does not have a function of switching a general driving capability and is used in the LDO circuit according to the first embodiment illustrated in FIG. 1 or the LDO circuit according to the second embodiment illustrated in FIG. 3. It is a block block diagram of the conventional LDO and its peripheral circuit. It is a circuit block diagram of LDO which has the function to switch the conventional drive capability.

In the following detailed description, numerous specific specific configurations are described to provide a thorough understanding of embodiments of the invention. However, it will be apparent that other embodiments may be practiced without limitation to such specific specific configurations. Further, the following embodiments do not limit the invention according to the claims, but include all combinations of characteristic configurations described in the embodiments.
Hereinafter, each embodiment of the present invention will be described with reference to the drawings.

<Embodiment 1>
FIG. 1 is a block diagram for explaining a first embodiment of an LDO circuit according to the present invention. The LDO circuit 10 according to the first embodiment includes a reference voltage generation circuit 11, a reference voltage rise control circuit 12, and an LDO 13.
The reference voltage generation circuit 11 generates a first reference voltage VREF from the power supply voltage VDD1. The reference voltage startup control circuit 12 generates a second reference voltage VREFSTUP based on the first reference voltage VREF generated by the reference voltage generation circuit 11. The LDO 13 is supplied with the power supply voltage VDD2, and outputs the output voltage LDOOUT based on the second reference voltage VREFSTUP generated by the reference voltage rising control circuit 12.

FIG. 2 is a specific circuit configuration diagram of the reference voltage start-up control circuit shown in FIG. As shown in FIG. 2, the reference voltage rising control circuit 12 includes a current generation circuit 121 connected between the first reference voltage VREF and the ground potential GND, and between the current generation circuit 121 and the ground potential GND. The second reference voltage VREFSTUP is generated from a node between the current generation circuit 121 and the capacitor C.
The current generation circuit 121 includes a reference current generation circuit 121a, a first PMOS transistor PM1, and a second PMOS transistor PM2.

The first PMOS transistor PM1 has a source terminal SP1 connected to the first reference voltage VREF, a drain terminal DP1 connected to the reference current generation circuit 121a, and a gate terminal GP1 connected to the drain terminal DP1. The second PMOS transistor PM2 has a source terminal SP2 connected to the first reference voltage VREF, a drain terminal DP2 connected to the capacitor C, and a gate terminal GP2 connected to the gate terminal GP1 of the first PMOS transistor PM1. It is connected.
The reference current generation circuit 121a includes an input terminal to which a reference current IREF is input, a first NMOS transistor NM1, and a second NMOS transistor NM2.
The first NMOS transistor NM1 has a drain terminal DN1 connected to the reference current IREF, a source terminal SN1 connected to the ground potential GND, and a gate terminal GN1 connected to the drain terminal DN1. The second NMOS transistor NM2 has a drain terminal DN2 connected to the drain terminal DP1 of the first PMOS transistor PM1, a source terminal SN2 connected to the ground potential GND, and a gate terminal GN2 connected to the first NMOS transistor NM1. It is connected to the gate terminal GN1.

That is, FIG. 1 shows a configuration example of an LDO and its peripheral circuit for relaxing the rising voltage while ensuring the necessary drive capability. A reference voltage generation circuit 11 using the power supply voltage VDD1 as a power supply, a reference voltage rise control circuit 12 using the output of the reference voltage generation circuit 11 as a power supply, and an output of the reference voltage rise control circuit 12 as inputs. The LDO 13 uses the voltage VDD2 as a power source. Note that VDD1 = VDD2 may be used.
With such a configuration, the reference voltage VREF is generated by the reference voltage generation circuit 11 and is input to the reference voltage start-up control circuit 12, and the reference voltage VREF is used as a power source for the reference voltage control circuit. By inputting the output VREFSTUP of the reference voltage rising control circuit 12 to the LDO, an output LDOOUT corresponding to the output VREFSTUP is output from the LDO 13.

FIG. 2 shows the reference voltage rise control circuit 12 that gradually starts up the reference voltage as described above. The reference voltage start-up control circuit 12 is composed of a current mirror and an output capacitance using the reference voltage VREF from the reference voltage generation circuit 11 as a power source. Further, the input terminal to which the reference current IREF is input, the first NMOS transistor NM1, and the second NMOS transistor NM2 constitute a reference current generation circuit 121a.
With such a configuration, a reference current that is a desired current is generated from the reference current IREF by a current mirror, and a current is output from the second PMOS transistor PM2. The reference current from the second PMOS transistor PM2 is stored in a capacitor to be converted into a voltage VREFSTUP. The slope of the output voltage VREFSTUP is determined by this current and capacity.

The reference voltage start-up control circuit 12 uses the reference voltage VREF as a power source, and when the output voltage VREFSTUP becomes substantially equal to the reference voltage VREF used as the power source, the drain / source voltage Vds of the second PMOS transistor PM2 cannot be obtained. . Therefore, when the current from the second PMOS transistor PM2 automatically stops, the output voltage VREFSTUP≈the reference voltage VREF is stably output.
As shown in FIG. 1, by combining the reference voltage start-up control circuit 12 and the LDO 13, the output of the LDO 13 outputs a voltage based on the output voltage VREFSTUP input to the LDO 13. Regardless of the MOS size of the stage, the slope of the output is determined by the slope of the reference voltage rising control circuit 12. That is, in the rise period, the output voltage of the LDO 13 rises following the rise of the output voltage VREFSTUP input to the LDO 13. The slope of the output voltage VREFSTUP and the slope of the output voltage of the LDO 13 may be the same or different values, and the output voltage of the LDO 13 rises in correlation with the slope of the output voltage VREFSTUP.

Therefore, since the slope of the output voltage of the LDO 13 is determined by the current mirror current and the capacity of the reference voltage rising control circuit 12, the slope of the output of the LDO 13 is designed with a high degree of freedom without impairing the driving capability of the LDO 13. I can do it.
By setting the current mirror current to be small, the capacity can be made sufficiently small, so that it can be mounted on the LSI chip instead of an external capacity without difficulty.
In addition, since it can be realized with a simple circuit, a circuit for determining that the output voltage of the LDO 13 has become a voltage in the vicinity of a desired value in order to generate a signal for switching the conventional driving capability (eg, a comparator). Since it is unnecessary, the circuit scale can be reduced.

When switching the driving capability of the LDO from small to large as in the conventional LDO circuit, the gate voltage of the MOS having a large driving capability is instantaneously lowered immediately after switching, so that the output of the LDO is jumped up and output. The voltage can overshoot. However, by adopting the circuit configuration of the present invention, there is no discontinuous point, and there is no need to switch the driving capability, so such a phenomenon does not occur.
The LDO is required to have at least a driving capability for driving a current flowing in the external circuit at the time of startup. However, since the slope of the output voltage of the LDO depends on the driving capability, the conventional switching configuration has a limit in reducing the slope of the output voltage. According to this embodiment, it is possible to reduce the slope of the output voltage of the LDO without reducing the drive capability of the LDO. As a result, it is possible to prevent adverse effects on the external circuit while the LDO retains the necessary driving capability for driving the external circuit at the time of startup. For example, an external circuit that uses the output voltage of the LDO as a power supply at startup can prevent a through current inside the external circuit due to a sharp power supply rise.

<Embodiment 2>
FIG. 3 is a block diagram for explaining a second embodiment of the LDO circuit according to the present invention. FIG. 3 is a block configuration diagram in which a switch control circuit 14 is provided in the reference voltage rising control circuit 12 of the LDO circuit according to the first embodiment shown in FIGS. 1 and 2. That is, in FIG. 3, the switch control circuit 14 for controlling the switch 141 inserted in FIG. 4 is added to the first embodiment shown in FIG.

FIG. 4 is a specific circuit configuration diagram of the reference voltage rising control circuit when the switch control circuit shown in FIG. 3 is added. A circuit configuration diagram is shown in which a switch 141 for connecting the output voltage VREFSTUP and the reference voltage VREF is inserted after waiting for a certain period after the output voltage VREFSTUP is started (≈reference voltage VREF).
That is, the reference voltage rising control circuit 12 in FIG. 4 includes the switch 141 connected between the first reference voltage VREF and a node between the current generation circuit 121 and the capacitor C.
The switch 141 connecting the output voltage VREFSTUP and the reference voltage VREF in FIG. 4 has the effect that the voltage of the output voltage VREFSTUP can be made to match the reference voltage VREF more than the case without the switch 141 as shown in FIG. is there.

The switch control circuit 14 shown in FIG. 3 receives, for example, a power down release signal from the reference voltage rise control circuit 12 and the reference voltage rise control circuit 12 is fully activated by a digital counter, an analog delay circuit, or the like. Control such as turning on the switch 141 is performed after waiting for the above delay time.
Based on the control signal STUP from the switch control circuit 14, the switch 141 is connected so that the node to which the reference voltage VREF is input and the node from which the output voltage VREFSTUP is output have the same potential (so as to be short-circuited). .

FIG. 5 is a circuit configuration diagram of an LDO that does not have a function of switching a general driving capability and is used in the LDO circuit of the first embodiment shown in FIG. 1 or the LDO circuit of the second embodiment shown in FIG.
The LDO 13 has an amplifier 131 in which a reference voltage VREF is input to a non-inverting input terminal (+) and a feedback voltage is input to an inverting input terminal (−), a PMOS in which an output signal of the amplifier 131 is input to a gate, Resistance dividers R1 and R2 connected between the output terminal LDOOUT and the ground voltage GND are provided.
As mentioned above, although each embodiment of this invention was described, the technical scope of this invention is not limited to the technical scope as described in embodiment mentioned above. It is possible to add various changes or improvements to the above-described embodiments, and it is possible to add such changes or improvements to the technical scope of the present invention. it is obvious.

10, 20 LDO circuits 11, 21 Reference voltage generation circuit 12 Reference voltage rise control circuits 13, 22 LDO
14 switch control circuit 121 current generation circuit 121a reference current generation circuit 131, 221 amplifier 141 switch

Claims (4)

A reference voltage generation circuit for generating a first reference voltage from the power supply voltage;
A current generation circuit connected between the first reference voltage and a ground potential; and a capacitance element connected between the current generation circuit and the ground potential; and the current generation circuit, the capacitance element, A reference voltage rising control circuit for generating a second reference voltage from a node between
An LDO that outputs an output voltage based on the second reference voltage;
An LDO circuit comprising: The current generating circuit is
A reference current generation circuit;
A first PMOS transistor having a source terminal connected to the first reference voltage, a drain terminal connected to the reference current generation circuit, and a gate terminal connected to the drain terminal;
A second PMOS transistor having a source terminal connected to the first reference voltage, a drain terminal connected to the capacitive element, and a gate terminal connected to the gate terminal of the first PMOS transistor;
The LDO circuit according to claim 1, comprising: The reference current generating circuit is
A first NMOS transistor having a drain terminal connected to a reference current, a source terminal connected to the ground potential, and a gate terminal connected to the drain terminal;
A second NMOS transistor having a drain terminal connected to the drain terminal of the first PMOS transistor, a source terminal connected to the ground potential, and a gate terminal connected to the gate terminal of the first NMOS transistor;
The LDO circuit according to claim 2, comprising:   4. The LDO circuit according to claim 2, further comprising a switch connected between the first reference voltage and a node between the current generation circuit and the capacitor. 5.

Images