JP2014135454A - Semiconductor device and manufacturing method of the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device in which a photodiode and a transistor are formed on the same semiconductor substrate via an insulation film and which has less parasitic capacitance; and provide a manufacturing method of the semiconductor device.SOLUTION: A semiconductor device comprises: a photodiode 30 including a second semiconductor layer 15 of one conductivity type and a semiconductor region 231 of an opposite conductivity type which is provided on a principal surface 151 of the second semiconductor layer on a first region 51; a first semiconductor layer 11 which is provided on the one principal surface 151 of the second semiconductor layer on a second region 61 different from the first region 51 and includes a transistor element; a third semiconductor layer 13 which is provided between the first semiconductor layer 11 and the second semiconductor layer 15, and to which fixed potential is applied; an insulation layer 12 provided between the first semiconductor layer 11 and the third semiconductor layer 13; and an insulation layer 14 provided between the second semiconductor layer 15 and the third semiconductor layer.

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to an X-ray sensor in which a photodiode and a transistor for X-ray detection are mixed on the same SOI (Slicon On Insulator) substrate and a manufacturing method thereof.

  Patent Documents 1 and 2 disclose a semiconductor device having a structure in which a sensor and a peripheral circuit are formed on the same semiconductor substrate via an insulating film.

JP 2009-170615 A JP 2008-130795 A

  In a semiconductor device having a structure in which a sensor and a peripheral circuit are formed on the same semiconductor substrate, an X-ray sensor having a structure in which a photodiode for X-ray detection and a transistor are formed on the same semiconductor substrate Uses a low-concentration, high-resistance semiconductor substrate on the semiconductor substrate on which an X-ray detection photodiode is formed, or a bias of several hundred volts is applied to the back surface of the semiconductor substrate in order to increase the detection sensitivity upon radiation incidence. The whole semiconductor substrate may be depleted by a method such as application.

  At this time, by using an SOI (Silicon On Insulator) substrate, as shown in FIG. 10, the first semiconductor layer 11 above the buried oxide film 4 has a high concentration for forming an element such as a MOS transistor 1 for circuit operation. An X-ray sensor including peripheral circuits on a single wafer 10 by using a low-resistance substrate and the second semiconductor layer 15 below the buried oxide film 4 as a low-concentration high-resistance substrate for forming the photodiode 2. Can be configured.

  However, the voltage 3 applied to the back surface of the second semiconductor layer 15 to deplete the second semiconductor layer 15 is formed on the buried oxide film 4 via the buried oxide film 4. In the MOS transistor 1 formed in the first semiconductor layer 11, the current is transmitted from the second semiconductor layer 15 separately from the current path 6 controlled by the gate electrode 5 originally formed of a polysilicon film. The problem is that the channel region on the buried oxide film 4 side operates as a current path 7 due to voltage, and the channel region on the buried oxide film 4 side becomes a current path because the buried oxide film 4 is positively charged by X-ray irradiation. There was a problem that it operated as 7.

  In order to solve these problems, as shown in FIG. 11, the conductivity type opposite to the impurity doped in the second semiconductor layer 15 is formed on the surface of the second semiconductor layer 15 immediately below the MOS transistor 1. And a diffusion layer 8 having a conductivity type opposite to that of the diffusion layer 8 is formed on the inner side thereof, and these potentials are grounded to the GND, thereby forming the second layer. In order to deplete the semiconductor layer 15, it is conceivable that the voltage 3 applied to the back surface of the second semiconductor layer 15 is prevented from being transmitted to the first semiconductor layer 11 and the radiation resistance is further increased.

  However, in this structure, as shown in FIG. 11, there is a parasitic capacitance 101 between the first semiconductor layer 11 and the diffusion layer 8, and the sensor pixel formed in the second semiconductor layer 15. In the diode, the parasitic capacitance 102 is provided between the diffusion layer 8 and the diffusion layer 9, which causes an increase in noise and a decrease in speed for the sensor.

  A main object of the present invention is to provide a semiconductor device having a small parasitic capacitance, in which a photodiode and a transistor are formed on the same semiconductor substrate via an insulating film, and a method for manufacturing the same.

According to the present invention,
A second semiconductor layer of one conductivity type, and a semiconductor region of opposite conductivity type provided in a first region of one main surface of the second semiconductor layer and having a conductivity type opposite to the one conductivity type; A photodiode comprising,
A first semiconductor layer provided on a second region different from the first region on the one principal surface of the second semiconductor layer and having a transistor element formed thereon;
A third semiconductor layer provided between the first semiconductor layer and the second semiconductor layer, to which a fixed potential is applied;
A first insulating layer provided between the first semiconductor layer and the third semiconductor layer;
A second insulating layer provided between the second semiconductor layer and the third semiconductor layer;
A semiconductor device is provided.

Moreover, according to the present invention,
A second semiconductor layer of one conductivity type; a second insulating layer on the second semiconductor layer; a third semiconductor layer on the second insulating layer; and a second semiconductor layer on the third semiconductor layer. Preparing a laminate comprising: 1 insulating layer; and an active region including a first semiconductor layer selectively provided on the first insulating layer;
Forming a transistor element in the active region;
An opening exposing the second semiconductor layer is formed in the first insulating layer, the third semiconductor layer, and the second insulating layer, and at the same time, the third semiconductor layer is separated from the third semiconductor layer. Forming a semiconductor layer isolation region;
Introducing an impurity of an opposite conductivity type, which is an opposite conductivity type to the one conductivity type, into the second semiconductor layer through the opening;
A method for manufacturing a semiconductor device is provided.

  According to the present invention, a photodiode and a transistor are formed on the same semiconductor substrate via an insulating film, and a semiconductor device with a small parasitic capacitance and a method for manufacturing the same are provided.

FIG. 1 is a schematic longitudinal sectional view for explaining a semiconductor device according to a preferred embodiment of the present invention. FIG. 2 is a schematic longitudinal sectional view for explaining a method for manufacturing a semiconductor device according to a preferred embodiment of the present invention. FIG. 3 is a schematic longitudinal sectional view for explaining a method for manufacturing a semiconductor device according to a preferred embodiment of the present invention. FIG. 4 is a schematic longitudinal sectional view for explaining a method for manufacturing a semiconductor device according to a preferred embodiment of the present invention. FIG. 5 is a schematic longitudinal sectional view for explaining a method for manufacturing a semiconductor device according to a preferred embodiment of the present invention. FIG. 6 is a schematic longitudinal sectional view for explaining a method for manufacturing a semiconductor device according to a preferred embodiment of the present invention. FIG. 7 is a schematic longitudinal sectional view for explaining a method for manufacturing a semiconductor device according to a preferred embodiment of the present invention. FIG. 8 is a schematic longitudinal sectional view for explaining a method for manufacturing a semiconductor device according to a preferred embodiment of the present invention. FIG. 9 is a schematic longitudinal sectional view for explaining a method for manufacturing a semiconductor device according to a preferred embodiment of the present invention. FIG. 10 is a schematic longitudinal sectional view for explaining a conventional semiconductor device. FIG. 11 is a schematic longitudinal sectional view for explaining a related semiconductor device.

  Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings.

  Referring to FIG. 1, a semiconductor device 100 according to a preferred embodiment of the present invention includes a first semiconductor layer 11 in which a peripheral circuit MOS transistor 40 is formed, a sensor pixel, and a second semiconductor layer. 15 and the semiconductor region 231, the third semiconductor layer 13 provided between the first semiconductor layer 11 and the second semiconductor layer 15, the first semiconductor layer 11 and the third semiconductor layer 231. A buried oxide film 12 provided between the semiconductor layer 13 and a buried oxide film 14 provided between the second semiconductor layer 11 and the third semiconductor layer 13.

  The first semiconductor layer 11 and the third semiconductor layer 13 are formed of a P-type semiconductor substrate, and the second semiconductor layer 15 is formed of an N-type semiconductor substrate. A P-type semiconductor region 231 is provided in the region 51 of the main surface 151 of the second semiconductor layer 15. The P-type semiconductor region 231 and the N-type second semiconductor layer 15 form an X-ray photodiode 30 that functions as a sensor pixel. Note that a high-concentration N-type extraction region 232 is provided in the region 51 of the main surface 151 of the second semiconductor layer 15. An electrode 280 is provided on the main surface 152 opposite to the main surface 151 of the second semiconductor layer 15. The active region 111 of the first semiconductor layer 11 in which the MOS transistor 40 is formed is provided on a region 52 different from the region 51 of the main surface 151 of the second semiconductor layer 15. The third semiconductor layer 13 provided between the active region 111 of the first semiconductor layer 11 and the second semiconductor layer 15 is provided with a high-concentration P-type extraction region 24.

  The N-type second semiconductor layer 15 includes an electrode 280 provided on the main surface 152 of the second semiconductor layer 15 and a high-concentration N-type extraction region provided on the main surface 151 of the second semiconductor layer 15. It is connected to the positive electrode side of the power supply 28 via the extraction electrode 275 connected to H.232. The P-type semiconductor region 231 provided on the main surface 151 of the second semiconductor layer 15 is connected to the negative electrode side of the power supply 28 and the GND 90 via the extraction electrode 274. The P-type third semiconductor layer 13 is connected to the GND 90 via an extraction electrode 271 connected to the high-concentration P-type extraction region 24.

  In order to deplete the N-type second semiconductor layer 15 constituting the X-ray photodiode 30, the back surface (main surface 152) of the second semiconductor layer 15 and the high-concentration N-type extraction region 232 (cathode) A positive high voltage is applied to the electrode) from the power source 28. At this time, the third semiconductor layer 13 and the P-type semiconductor region 231 serving as the anode electrode of the diode are grounded to the GND 90.

  A high voltage is applied to the back surface (main surface 152) of the second semiconductor layer 15 in order to deplete the second semiconductor layer 15 by fixing the third semiconductor layer 13 formed of the P-type substrate to the GND potential. Even when is applied, the high voltage 28 applied to the back surface of the second semiconductor layer 15 is not transmitted to the interface of the active region 111 of the first semiconductor layer 11 on the buried oxide film 12 side.

  As described above, the third semiconductor layer fixed to GND is provided between the MOS transistor 40 formed in the active region 111 of the first semiconductor layer 11 and the diode 30 as the sensor pixel formed in the second semiconductor layer 15. 13, the parasitic capacitance to the sensor pixel is very small. In addition, crosstalk that affects the MOS transistor 40 of the first semiconductor layer 11 when a signal is input to the sensor pixel is almost negligible.

  Next, a method for manufacturing the semiconductor device 100 according to a preferred embodiment of the present invention will be described.

  First, as shown in FIG. 2, a first semiconductor layer 11 having a thickness of 100 nm is sandwiched between the buried oxide films 10 and 14 having a thickness of approximately 100 to 200 nm, and a first semiconductor layer 11 having a thickness of approximately 700 μm is disposed on the lower side. A double-SOI (Double-Silicon On Insulator) substrate having two semiconductor layers 15 and a third semiconductor layer 13 having a thickness of 100 nm in the center is used. At this time, for example, the first semiconductor layer 11 and the third semiconductor layer 13 are formed of a P-type semiconductor substrate having a specific resistance of 10 Ω · cm, and the second semiconductor layer 15 is formed of an N-type semiconductor substrate having a specific resistance of 10 kΩ · cm.

  After forming a pad oxide film (not shown) and a nitride film (not shown) on the surface of the first semiconductor layer 11 and forming a field oxide film by the LOCOS formation method, as shown in FIG. The nitride film and the pad oxide film are removed. As a result, an active region 111 is formed in the first semiconductor layer 11.

  Further, as shown in FIG. 4, a gate oxide film 16 is formed on the surface of the active region 111 of the first semiconductor layer 11, a polysilicon film is deposited, and polysilicon is patterned with a photoresist (not shown). The film is dry-etched to form the gate electrode 18.

  Thereafter, as shown in FIG. 5, after removing the photoresist (not shown), LDD (not shown) is ion-implanted into the active region 111 of the first semiconductor layer 11 to form the sidewall spacer 20. After that, an ion implantation process of the high concentration source / drain 19 is performed to form the MOS transistor 40.

  After that, as shown in FIG. 6, a photoresist (see FIG. 6) is provided except for the P-type semiconductor region 231, the N-type extraction region 232, and the third semiconductor layer 13 separation region 131 to be formed in the second semiconductor layer 15. The buried oxide films 12 and 14 and the third semiconductor layer 13 are etched to form the openings 211 and 212 and the isolation region trench 213, respectively, and then the photoresist is removed. Further, a portion other than the P-type extraction electrode region 24 to be formed in the third semiconductor layer 13 is covered with a photoresist (not shown), the buried oxide film 12 is etched, and the opening 22 is formed. Remove the resist.

For example, an impurity 31P ⁺ having an implantation energy of 60 kev and a dose of about 5.0 × 10 ¹⁵ cm ⁻² is implanted through the opening 212 into the N-type extraction region 232 that also serves as the diode cathode. For example, an impurity 11B ⁺ having an implantation energy of 40 keV and a dose amount of about 5.0 × 10 ¹⁵ cm ⁻² is implanted into the P-type semiconductor region 231 that also serves as the impurity. Further, an impurity 49BF ₂ ⁺ having an implantation energy of ¹⁵ kev and a dose of about 5.0 × 10 ¹⁵ cm ⁻² is implanted into the P-type extraction region 24 of the third semiconductor layer 13 through the opening 22.

  Thereafter, as shown in FIG. 7, an interlayer film is formed by depositing a CVD film 25. Thereafter, by etching the active region 111 of the first semiconductor layer 11, the second semiconductor layer 15, and the place where the extraction electrode of the third semiconductor layer 13 is formed, as shown in FIG. 262, 263, 264, and 265 are formed. Finally, the metal layer formed by sputtering is etched at portions other than the electrode formation region, thereby forming extraction electrodes 271, 272, 273, 274, 275 as shown in FIG. An electrode 280 is also formed on the back surface of the second semiconductor layer 15.

  As a method of forming the isolation region in the third semiconductor layer 13, when forming the P-type semiconductor region 231 and the N-type extraction region on the main surface 151 of the second semiconductor layer 15 as shown in FIG. At the same time, the portion of the third semiconductor layer 13 where the isolation region 131 is formed is etched, so that the isolation region 131 of the third semiconductor layer 13 is formed without performing a special process or preparing a mask or the like. Accordingly, the third semiconductor layers 13 can be electrically separated from each other.

  In the above embodiment, the case where the second semiconductor layer 15 is an N-type substrate is described. However, the second semiconductor layer 15 can also be applied to a P-type semiconductor device. In other regions, the P type is defined as the N type, and the P type is defined as the N type.

  While various typical embodiments of the present invention have been described above, the present invention is not limited to these embodiments. Accordingly, the scope of the invention is limited only by the following claims.

11 First semiconductor layer 12 Buried oxide film 13 Third semiconductor layer 14 Buried oxide film 15 Second semiconductor layer 16 Gate oxide film 18 Gate electrode 19 Source / drain 22 Opening 24 P-type extraction region 28 Power supply 30 Photodiode 40 MOS transistor 51 area 90 GND
100 Semiconductor device 111 Active region 131 Isolation region 151 Main surface 152 Main surface 211, 212 Opening 213 Separation region groove 231 P-type semiconductor region 232 N-type extraction region 261, 262, 263, 264, 265 Contact holes 271, 272 273, 274, 275 Extraction electrode 280 Electrode

Claims (6)

A second semiconductor layer of one conductivity type, and a semiconductor region of opposite conductivity type provided in a first region of one main surface of the second semiconductor layer and having a conductivity type opposite to the one conductivity type; A photodiode comprising,
A first semiconductor layer provided on a second region different from the first region on the one principal surface of the second semiconductor layer and having a transistor element formed thereon;
A third semiconductor layer provided between the first semiconductor layer and the second semiconductor layer, to which a fixed potential is applied;
A first insulating layer provided between the first semiconductor layer and the third semiconductor layer;
A second insulating layer provided between the second semiconductor layer and the third semiconductor layer;
A semiconductor device comprising:   The semiconductor device according to claim 1, wherein the fixed potential is a ground potential.   3. The semiconductor device according to claim 2, wherein the one conductivity type is an N type, and the opposite conductivity type is a P type.   The semiconductor device according to claim 1, wherein the photodiode is an X-ray detection photodiode. A second semiconductor layer of one conductivity type; a second insulating layer on the second semiconductor layer; a third semiconductor layer on the second insulating layer; and a second semiconductor layer on the third semiconductor layer. Preparing a laminate comprising: 1 insulating layer; and an active region including a first semiconductor layer selectively provided on the first insulating layer;
Forming a transistor element in the active region;
An opening exposing the second semiconductor layer is formed in the first insulating layer, the third semiconductor layer, and the second insulating layer, and at the same time, the third semiconductor layer is separated from the third semiconductor layer. Forming a semiconductor layer isolation region;
Introducing an impurity of an opposite conductivity type, which is an opposite conductivity type to the one conductivity type, into the second semiconductor layer through the opening;
A method for manufacturing a semiconductor device comprising:   A first extraction electrode connected to the third semiconductor layer through a first insulating layer is provided, and the second semiconductor layer is formed through the first insulating layer and the second insulating film. 6. The method for manufacturing a semiconductor device according to claim 5, further comprising a step of providing a second extraction electrode connected to the region into which the impurity of the opposite conductivity type is introduced.

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