JP2014132600A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To resolve a problem that, although a bouncing voltage is generated at switching in a power system active element having an insulation gate, such as a power MOSFET, used for a power supply or a power conversion device and the like, this bouncing voltage becomes noise for a power-supplied circuit, such as a digital signal processing circuit, which may be a factor of malfunction of a logic circuit and the like.SOLUTION: In a semiconductor device that has a power system active element having an insulation gate such as a power MOSFET, a sub active cell region having a threshold voltage lower than that of the other region and having a relatively narrow occupied area is provided in an active cell region.

Description

  The present invention relates to a semiconductor device (or a semiconductor integrated circuit device effective in a semiconductor integrated circuit device) that is effective in a semiconductor device (or a semiconductor integrated circuit device) such as a power MOSFET (Metal Oxide Field Effect Transistor) or a MISFET (Metal Insulator Semiconductor Field Effect Transistor).

  Japanese Patent Application Laid-Open No. 2003-133557 (Patent Document 1) or US Pat. No. 6,806,548 (Patent Document 2) corresponding thereto discloses a trench gate type vertical gate used for power supply circuit switching and the like. In a channel (vertical channel) power MOSFET, a technique for reducing the area occupied by a SBD (Schottky Barrier Diode) incorporated in a semiconductor chip is disclosed.

  Japanese Patent Application Laid-Open No. 2006-24690 (Patent Document 3) or US Pat. No. 6,967,374 (Patent Document 4) corresponding thereto discloses a super-junction structure used for switching a power supply circuit. A technique of incorporating an SBD having characteristics suitable for a soft switching system into a semiconductor chip in a planar type vertical power MOSFET having the above structure is disclosed.

JP 2003-133557 A US Pat. No. 6,806,548 JP 2006-24690 A US Pat. No. 6,967,374

  A power system active element having an insulated gate such as a power MOSFET used for a power source or a power conversion device generates a jumping voltage during switching. This jumping voltage causes noise to a power supply circuit such as a digital signal processing circuit and causes a malfunction of a logic circuit or the like. This problem is not limited to a single power MOSFET or the like, but an IGBT (Insulated Gate Bipolar Transistor) and CMOS (Complementary Metal Oxide Semiconductor), etc., to which a similar structure is applied, and these power active devices can be combined into a single unit. This is an important problem even in an integrated circuit device integrated on a chip.

  The present invention has been made to solve these problems.

  An object of the present invention is to provide a highly reliable semiconductor device.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  The following is a brief description of an outline of typical inventions disclosed in the present application.

  That is, according to one aspect of the present invention, in a semiconductor device having a power system active element having an insulated gate such as a power MOSFET, the active cell region has a lower threshold voltage than other regions, and the occupied area is relatively small. A narrow sub-active cell region is provided.

  The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

  That is, in a semiconductor device having a power system active element having an insulated gate such as a power MOSFET, a sub-active cell region having a threshold voltage lower than other regions and a relatively small occupation area is provided in the active cell region. As a result, since the sub-active cell region is turned on first when it is turned on, generation of a jumping voltage can be reduced.

It is a schematic circuit diagram which shows the circuit structure of the DC-DC converter for computers which is the main application field of the semiconductor device of each embodiment of this application. It is the whole semiconductor chip top view of power MOSFET which is an example of the semiconductor device of one embodiment of this application. It is a chip | tip schematic cross section corresponding to the X-X 'cross section of FIG. It is a semiconductor chip whole upper surface schematic diagram which shows the distribution condition (single ring-shaped distribution) of the subactive area | region inside the active area | region in the semiconductor chip upper surface of the power MOSFET which is an example of the semiconductor device of the said one Embodiment of this application. FIG. 5 is a partial cross-sectional view of a semiconductor chip corresponding to an A-A ′ cross section of a main and sub active region boundary peripheral cutout region R <b> 3 of FIG. 4. FIG. 6 is a detailed cross-sectional view of a unit cell region 20m of the main active region of FIG. FIG. 6 is a detailed cross-sectional view of a unit cell region 20s of the sub-active region of FIG. FIG. 3 is an enlarged top view of a gate electrode lead-out region R1 in FIG. 2. FIG. 6 is a partial cross-sectional view of a wafer during a manufacturing process (epitaxial growth process) of a part corresponding to FIG. 5. FIG. 6 is a partial cross-sectional view of the wafer during the manufacturing process (trench formation process) of the part corresponding to FIG. 5. FIG. 6 is a partial cross-sectional view of a wafer during a manufacturing process (gate insulating film formation and polysilicon electrode embedding process) of a part corresponding to FIG. 5. FIG. 6 is a partial cross-sectional view of a wafer in the middle of a manufacturing process (a P-type body region introduction step for a main active region) corresponding to FIG. 5. FIG. 6 is a partial cross-sectional view of a wafer during a manufacturing process of a portion corresponding to FIG. 5 (P-type body region introduction step of a sub-active region). FIG. 6 is a partial cross-sectional view of the wafer in the middle of the manufacturing process (N-type source region introduction process) of the part corresponding to FIG. 5. FIG. 6 is a partial cross-sectional view of the wafer in the middle of the manufacturing process (interlayer insulating film formation and contact hole formation step) of the portion corresponding to FIG. 5. FIG. 6 is a partial cross-sectional view of a wafer during a manufacturing process (contact hole extending process) of a part corresponding to FIG. 5. FIG. 6 is a partial cross-sectional view of a wafer in the middle of the manufacturing process (P-type body contact region introducing step) corresponding to FIG. 5. FIG. 6 is a partial cross-sectional view of the wafer in the middle of the manufacturing process of the part corresponding to FIG. 5 (metal film formation and metal source electrode patterning process). FIG. 6 is a partial cross-sectional view of a wafer during a manufacturing process (back grinding process) of a portion corresponding to FIG. 5. FIG. 6 is a partial cross-sectional view of the wafer during the manufacturing process (back surface metal electrode film forming step) of the portion corresponding to FIG. 5. FIG. 7 shows a subactive region corresponding to FIG. 7 relating to the first modification of the active cell structure of the power MOSFET which is an example of the semiconductor device according to the embodiment of the present application (a structure in which the gate insulating film is relatively thin in the subactive region). It is a detailed sectional view of a unit cell region 20s. The active region on the upper surface of the semiconductor chip of the power MOSFET corresponding to FIG. 4 relating to the modification 1 (multiple ring-shaped distribution) regarding the distribution of the sub-active region in the active region of the power MOSFET which is an example of the semiconductor device of the one embodiment of the present application It is a semiconductor chip whole upper surface schematic diagram which shows the distribution condition of an internal subactive region. The active region on the upper surface of the semiconductor chip of the power MOSFET corresponding to FIG. 4 relating to the modification 2 (dot dispersion distribution) relating to the distribution of the sub-active region in the active region of the power MOSFET which is an example of the semiconductor device of the one embodiment of the present application It is a semiconductor chip whole upper surface schematic diagram which shows the distribution condition of an internal subactive region. On the upper surface of the semiconductor chip of the power MOSFET corresponding to FIG. 4 relating to the modification 3 (two-dimensional single-connection concentrated distribution) relating to the distribution of the sub-active region in the active region of the power MOSFET which is an example of the semiconductor device of the one embodiment of the present application It is a semiconductor chip whole upper surface schematic diagram which shows the distribution condition of the subactive area | region inside an active area | region. The active region on the upper surface of the semiconductor chip of the power MOSFET corresponding to FIG. 4 relating to the modification 4 (multiple single connection distribution) regarding the distribution of the sub-active region in the active region of the power MOSFET which is an example of the semiconductor device of the one embodiment of the present application It is a semiconductor chip whole upper surface schematic diagram which shows the distribution condition of an internal subactive region. The power MOSFET semiconductor chip corresponding to FIG. 4 relating to the modification 5 (two-dimensional single-connected end concentration distribution) regarding the distribution of the sub-active region in the active region of the power MOSFET which is an example of the semiconductor device according to the embodiment of the present application. It is a semiconductor chip whole upper surface schematic diagram which shows the distribution condition of the subactive area | region inside the active area | region in an upper surface. The power MOSFET semiconductor chip corresponding to FIG. 4 relating to the modification 6 (the linear dispersion distribution in the gate extending direction) regarding the distribution of the sub-active region in the active region of the power MOSFET which is an example of the semiconductor device according to the embodiment of the present application. It is a semiconductor chip whole upper surface schematic diagram which shows the distribution condition of the subactive area | region inside the active area | region in an upper surface. The upper surface of the semiconductor chip of the power MOSFET corresponding to FIG. 4 relating to the modified example 6 (linear dispersion distribution in the gate orthogonal direction) regarding the distribution of the sub-active region in the active region of the power MOSFET which is an example of the semiconductor device of the one embodiment of the present application FIG. 2 is a schematic top view of the entire semiconductor chip showing the distribution of sub-active areas inside the active area in FIG. It is a schematic circuit diagram which shows the circuit structure of the DC-DC converter for computers corresponding to FIG. 1 for demonstrating the modification of the whole chip | tip structure of the power MOSFET which is an example of the semiconductor device of the said one Embodiment of this application. . FIG. 30 is an overall top view of the power MOSFET semiconductor chip corresponding to FIG. 2 for the low-side SW power MOSFET (Qhl) of FIG. 29; FIG. 31 is a schematic top view of the entire semiconductor chip showing the distribution of sub-active regions inside the active region on the top surface of the semiconductor chip of the power MOSFET corresponding to FIG. 30 (two-dimensional single-connected end concentration distribution corresponding to FIG. 26); FIG. 32 is a chip local enlarged top view corresponding to the gate electrode lead-out region cutout region R1 of FIGS. 30 and 31; It is a terminal arrangement diagram of an IGBT (Insulated gate Bipolar Transistor) which is an example of another active device to which the embodiments and the like described in the present application are applied. FIG. 7 is a unit cell cross-sectional view of an IGBT which is an example of another active device to which the embodiments and the like described in the present application corresponding to FIG. 6 are applied. FIG. 2 is a chip top view layout diagram of an integrated power supply element in which main parts of the circuit elements in FIG. 1 are integrated on a single chip. FIG. 39 is a chip partial schematic cross-sectional view corresponding to the Y-Y ′ cross section of FIG. 38. It is an effect explanatory view which shows the occupancy rate dependency of the jumping voltage and power loss for demonstrating the effectiveness of the semiconductor device of each embodiment of this application of the subactive region. It is a package drawing of the semiconductor chip of power MOSFET which is an example of the semiconductor device of one embodiment of this application.

[Outline of Embodiment]
First, an outline of a typical embodiment of the invention disclosed in the present application will be described.

1. Semiconductor devices including:
(A) a semiconductor substrate having a first main surface and a second main surface;
(B) a drift region provided in the semiconductor substrate and having a first conductivity type;
(C) an active region provided on the first main surface;
(D) a plurality of unit cell regions provided in the active region in plan view;
Here, each unit cell region has the following:
(D1) a body region provided in the semiconductor substrate on the first main surface side of the drift region and having a second conductivity type opposite to the first conductivity type;
(D2) a gate insulating film provided in a surface region of the semiconductor substrate on the first main surface side so as to be in contact with the body region;
(D3) a gate electrode provided in the surface region of the semiconductor substrate via the gate insulating film;
(D4) an interlayer insulating film provided on the gate electrode;
(D5) A source region having the first conductivity type provided on the first main surface side surface of the semiconductor substrate so as to be in contact with the gate insulating film;
(D7) a metal source electrode provided on the first main surface of the semiconductor substrate so as to cover the interlayer insulating film,
Here further, the active area comprises:
(C1) a main active region having a first threshold voltage and a first occupied area;
(C2) A sub-active region having a second threshold voltage lower than the first threshold voltage and a second occupied area smaller than the first occupied area.

  2. In the semiconductor device according to the item 1, the ratio of the second occupied area to the sum of the first occupied area and the second occupied area is 1% or more and 20% or less.

  3. In the semiconductor device according to the item 1, the ratio of the second occupied area to the sum of the first occupied area and the second occupied area is 5% or more and 20% or less.

  4). 4. In the semiconductor device according to any one of items 1 to 3, the difference between the first threshold voltage and the second threshold voltage is caused by an impurity concentration of the body region in the main active region and the sub active region. .

  5. 5. In the semiconductor device according to any one of 1 to 4, the difference between the first threshold voltage and the second threshold voltage is a difference in thickness of the gate insulating film in the main active region and the sub active region. caused by.

  6). 6. In the semiconductor device according to any one of 1 to 5, the planar shape of the sub active region is a single or a plurality of ring shapes.

  7). 6. In the semiconductor device as described above in any one of 1 to 5, the planar shape of the sub active region is a plurality of dot shapes.

  8). 6. In the semiconductor device according to any one of 1 to 5, the sub-active region forms a single region as a two-dimensional single connection region.

  9. 6. In the semiconductor device according to any one of 1 to 5, the sub-active region is a plurality of linear regions.

  10. 10. In the semiconductor device as described above in any one of 1 to 9, the value of the second threshold voltage is 45% or more and 85% or less of the value of the first threshold voltage.

  11. In the semiconductor device according to any one of Items 1 to 9, the value of the second threshold voltage is 55% or more and 75% or less of the value of the first threshold voltage.

12 The semiconductor device according to any one of 1 to 11 further includes the following:
(E) a gate pad provided on the first main surface of the semiconductor substrate;
(F) a first current path between the gate pad and each gate electrode in the main active region;
(G) a second current path between the gate pad and each gate electrode in the sub-active region;
Here, the resistance value of the second current path is larger than the resistance value of the first current path.

[Description format, basic terms, usage in this application]
1. In the present application, the description of the embodiment may be divided into a plurality of parts and sections for convenience, if necessary. However, unless otherwise specified, they are not independent from each other. Rather, each part of a single example, one of which is a partial detail of the other or a part or all of a modification. Moreover, as a general rule, the same part is not repeated. In addition, each component in the embodiment is not indispensable unless specifically stated otherwise, unless it is theoretically limited to the number, and obviously not in context.

  Further, in the present application, the term “semiconductor device” mainly refers to various transistors (active elements) alone, or a device in which resistors, capacitors, etc. are integrated on a semiconductor chip or the like (for example, a single crystal silicon substrate). Say. Here, as a representative of various transistors, a MISFET (Metal Insulator Semiconductor Effect Transistor) typified by a MOSFET (Metal Oxide Field Effect Transistor) can be exemplified. At this time, typical examples of various single transistors include power MOSFETs and IGBTs (Insulated Gate Bipolar Transistors). Note that power active elements such as power MOSFETs described in the present application are normally-off type unless otherwise specified.

  In the present application, “semiconductor active element” refers to a transistor, a diode, or the like.

  Also, it is cumbersome to use the expression “MOS” and the expression “MIS” separately, and unless otherwise specified, the word “MOS” is used, including the case where an insulating film other than an oxide is used. The expression shall be used.

  2. Similarly, in the description of the embodiment and the like, the material, composition, etc. may be referred to as “X consisting of A”, etc., except when clearly stated otherwise and clearly from the context, except for A It does not exclude what makes an element one of the main components. For example, as for the component, it means “X containing A as a main component”. For example, “silicon member” is not limited to pure silicon, but also includes SiGe alloys, other multi-component alloys containing silicon as a main component, and members containing other additives. Needless to say. Similarly, “silicon oxide film”, “silicon oxide insulating film”, etc. are not only relatively pure undoped silicon oxide (FS), but also FSG (Fluorosilicate Glass), TEOS-based silicon oxide ( Thermal oxide films such as TEOS-based silicon oxide), SiOC (Silicon Oxicarbide) or Carbon-doped Silicon oxide or OSG (Organosilicate glass), PSG (Phosphorus Silicate Glass), BPSG (Borophosphosilicate Glass), CVD Oxide film, SOG (Spin ON Glass), nano-clustering silica (Nano-Clustering Silica: NCS) and other coating-type silicon oxide, silica-based low-k insulating film (porous insulating) Needless to say, a film) and a composite film with other silicon-based insulating films including these as main constituent elements are included.

  In addition to silicon oxide insulating films, silicon nitride insulating films that are commonly used in the semiconductor field include silicon nitride insulating films. Materials belonging to this system include SiN, SiCN, SiNH, SiCNH, and the like. Here, “silicon nitride” includes both SiN and SiNH unless otherwise specified. Similarly, “SiCN” includes both SiCN and SiCNH, unless otherwise specified.

  Note that SiC has similar properties to SiN, but SiON is often rather classified as a silicon oxide insulating film.

  3. Similarly, suitable examples of graphics, positions, attributes, and the like are given, but it is needless to say that the present invention is not strictly limited to those cases unless explicitly stated otherwise, and unless otherwise apparent from the context.

  4). In addition, when a specific number or quantity is mentioned, a numerical value exceeding that specific number will be used unless specifically stated otherwise, unless theoretically limited to that number, or unless otherwise clearly indicated by the context. There may be a numerical value less than the specific numerical value.

  5. “Wafer” usually refers to a single crystal silicon wafer on which a semiconductor device (same as a semiconductor integrated circuit device and an electronic device) is formed, but an insulating substrate such as an epitaxial wafer, an SOI substrate, an LCD glass substrate, and the like. Needless to say, a composite wafer such as a semiconductor layer is also included.

  6). The structure of the IGBT is such that a semiconductor region opposite to the drift region is interposed on the drain side of a normal vertical power MOSFET. Therefore, the gate and the source are structurally almost the same as the vertical power MOSFET, but in practice, the portion corresponding to the terminal with the bipolar transistor is called the emitter terminal. Yes. However, in the present application, unless otherwise specified, each element of the IGBT corresponding to the source of the vertical power MOSFET is referred to as a “source region”, “source electrode”, and “source terminal”. To.

  7). In the present application, values such as “threshold voltage” when referred to as “first threshold voltage”, “second threshold voltage”, etc. mean that this is not the case, and unless otherwise stated, the average value in the target set Shall be pointed to.

  In addition, when referring to the value of “threshold voltage” or the like, the absolute value is compared on the assumption that the sign is the same, not the value itself.

[Details of the embodiment]
The embodiment will be further described in detail. In the drawings, the same or similar parts are denoted by the same or similar symbols or reference numerals, and description thereof will not be repeated in principle.

  In the accompanying drawings, hatching or the like may be omitted even in a cross section when it becomes complicated or when the distinction from the gap is clear. In relation to this, when it is clear from the description etc., the contour line of the background may be omitted even if the hole is planarly closed. Furthermore, even if it is not a cross section, it may be hatched to clearly indicate that it is not a void.

  For example, Japanese Patent Application Laid-Open No. 2009-22106 (or corresponding US Patent Publication No. 2009-15224) discloses a prior patent application by the present inventors regarding a DC-DC converter used for a computer power supply or the like. Japanese Unexamined Patent Publication No. 2010-16035 (or corresponding US Patent Publication No. 2010-1790).

1. Description of main application fields and the like of the semiconductor device of each embodiment of the present application (mainly FIG. 1)
The power MOSFET and the like described in the following embodiments are exemplified mainly for low-side switches in a DC-DC converter or the like, but it goes without saying that these are also effective for other applications. .

  FIG. 1 is a schematic circuit diagram showing a circuit configuration of a DC-DC converter for a computer, which is a main application field of the semiconductor device of each embodiment of the present application. Based on this, main application fields of the semiconductor device of each embodiment of the present application will be described.

  As shown in FIG. 1, a power supply to a microprocessor or the like in a PC (Personal Computer) or the like is normally a constant voltage source (DC power supply Vin ) Using a VRM (Voltage Regulator Module) such as the DC-DC converter 50, for example, at a low voltage of about 1 volt (currently, for example, about 20 amperes). This amount of current may exceed 100 amperes. For example, a switching signal of about 200 kHz (a typical range is about 300 kHz to about 500 kHz, and a range applied in the past and the near future is about 20 kHz to about 1 MHz) is sent from the control circuit unit 53 to the high side. Complementary pulse signals drive the high-side SW power MOSFET (Qhh) and the low-side SW power MOSFET (Qhl) through the driver 51 and the low-side driver 52, respectively. When the high-side SW power MOSFET (Qhh) is on, a current is supplied through the high-side SW power MOSFET (Qhh) and passes through a smoothing circuit including an output smoothing inductor 54, an output smoothing capacitor 55, and the like. The power supply output terminal Vdd and the ground terminal Vss are supplied to the microprocessor or the like. On the other hand, when the high-side SW power MOSFET (Qhh) is off, the low-side SW power MOSFET (Qhl) is on, and current is supplied through the current path from the low-side SW power MOSFET (Qhl) to the output smoothing inductor 54. . At this time, the voltage is controlled by the length of time during which the high-side SW power MOSFET (Qhh) is turned on. Accordingly, the high-side SW power MOSFET (Qhh) is required to have as low on-resistance characteristics as possible from the viewpoint of supplying a large current.

  On the other hand, since the low-side SW power MOSFET (Qhl) is a synchronous rectification switch that is turned on only when the high-side SW power MOSFET (Qhh) is off, a fast switching speed is required. However, there is a problem that the steep switching operation becomes a factor that increases the jumping voltage.

  Therefore, in this example, the low-side SW power MOSFET (Qhl) is internally divided into a standard threshold voltage portion Qhlm that occupies most and a relatively low threshold voltage portion Qhls that occupies a relatively small portion. Thus, the low-side SW power MOSFET (Qhl) alleviates the steep rise when turning on, and suppresses the jumping voltage.

  FIG. 38 shows an example of the chip arrangement and wire bonding arrangement of the package configuration example of the actual semiconductor device of the circuit shown in FIG. This package configuration example is an embodiment employing a QFN (Quad Flat Non-leaded package package) which is one of non-lead surface mount packages.

Specifically, a semiconductor chip 102 of a high-side SW power MOSFET (Qhh), a semiconductor chip 103 of a low-side SW power MOSFET (Qhl), and a driver IC having functions of a high-side driver 51 and a low-side driver 52 ( 106) with a resin and mounted as one system-in-package gauge 101 so that a switching signal from the control circuit unit 53 outside the system-in-package 101 is sent to the driver IC (106) via a terminal. It has become. The package tabs (die pads) 115, 116, 117 are divided into three, and the high side MOSFET (102) is provided with a source pad 118 and a gate pad 119, and a corresponding bonding pad BP of the driver IC (106). Are connected via wires 107 and 108, respectively. The low-side MOSFET (103) is connected via a wire 123 and a tab. The low-side MOSFET (103) is provided with source pads 120 and 122 and a gate pad 121, and is connected to the driver IC (106) via wirings 109 and 110 using wires, respectively. Further, it is connected to the power ground terminal 127 via a wire 124.
The potential of the tab 117 on which the driver IC (106) is mounted is connected to the logic ground via the logic ground terminal 128. In such a configuration, it is also possible to connect with a metal clip instead of wiring with the wires 123 and 124. In this way, by adopting the system-in-package configuration, it is possible to reduce the parasitic inductance of the wiring and realize further high efficiency.

2. Outline description of structure of semiconductor chip of semiconductor device of each embodiment of the present application (mainly FIG. 2 to FIG. 8)
In this section, an outline of the structure of the power MOSFET particularly adapted to the low-side switch described in section 1 (also corresponding to the low-side SW power MOSFET Qhl in FIG. 1) will be described.

  FIG. 2 is an overall top view of a semiconductor chip of a power MOSFET which is an example of a semiconductor device according to each embodiment of the present application. FIG. 3 is a chip schematic cross-sectional view corresponding to the X-X ′ cross section of FIG. 2. FIG. 4 is a schematic top view of the entire semiconductor chip showing the distribution of sub-active regions (single ring distribution) inside the active region on the top surface of the semiconductor chip of the power MOSFET that is an example of the semiconductor device according to the embodiment of the present application. is there. FIG. 5 is a partial cross-sectional view of the semiconductor chip corresponding to the A-A ′ cross section of the main and sub active region boundary peripheral cutout region R <b> 3 of FIG. 4. FIG. 6 is a detailed sectional view of the unit cell region 20m of the main active region of FIG. FIG. 7 is a detailed cross-sectional view of the unit cell region 20s of the sub-active region of FIG. FIG. 8 is an enlarged top view of the gate electrode lead-out region cutout region R1 of FIG. Based on these, the outline of the structure of the semiconductor chip of the semiconductor device of each embodiment of the present application will be described.

  First, the upper surface structure of the semiconductor chip will be described. As shown in FIG. 2, a ring-shaped guard ring 27 (for example, an aluminum-based metal) that circulates the end is provided at the peripheral end of the semiconductor chip 2 (for example, the chip size is about 3 mm in length and about 5 mm in width). The electrode film 30 is composed of the same layer as the electrode film 30, and almost all of the inner part of the gate film part 24 and the metal source electrode 15 (these are also the same as the aluminum metal electrode film 30, for example) Is composed of one layer). A part of the gate wiring portion 24 is a gate pad portion 25 for attaching a bonding wire or the like, and the vicinity of the center of the metal source electrode 15 is similarly a source pad portion 26 for attaching a bonding wire or the like. Yes. In addition, below the metal source electrode 15 in the main part of the upper surface of the semiconductor chip 2, mainly, for example, a planar band-shaped unit cell region 20 (the repetition cycle of the unit cell, that is, the width of the unit cell is, for example, 0.4 micron). For example, a gate polysilicon film (that is, the gate electrode 7) is embedded in the linear trench 5 in the active region 12 (active cell region).

  Next, FIG. 3 shows an X-X ′ cross section of FIG. 2. As shown in FIG. 3, the lower half of the semiconductor chip 2 is, for example, a relatively high concentration N-type semiconductor substrate region 1s (for example, an N-type single crystal silicon substrate), and the surface of the N-type semiconductor substrate region 1s. On the 1a (first main surface) side, that is, on the opposite side of the back surface 1b, an N-epitaxial region 1e having a thickness corresponding to the required breakdown voltage is provided, and the main part corresponds to the N-drift region 3. doing. The peripheral portion of the semiconductor chip 2 is mainly an edge termination region 28, and the active region 12 is almost occupied by the internal region of the semiconductor chip 2, and the active region 12 has a strip shape (three-dimensional) in plan view. Specifically, a unit cell region 20 (width, that is, a repetition period is, for example, about 400 nm) of a rectangular parallelepiped is spread.

  Next, a chip plan view corresponding to FIG. 2 for explaining the global structure in the active region 12 is shown in FIG. As shown in FIG. 4, the active region 12 is provided with a sub-active region 12s whose threshold voltage is set lower than other regions, that is, the main active region 12m. For example, the shape is a ring shape.

  Next, FIG. 5 shows a chip local cross-sectional view corresponding to the A-A ′ cross section of the main and sub active region boundary peripheral cutout region R <b> 3 in FIG. 4. As shown in FIG. 5, a back surface metal electrode 4 (drain electrode) is provided on the back surface 1b (second main surface) side of the N-type semiconductor substrate region 1s, and the front surface 1a of the N-type semiconductor substrate region 1s. A P-type body region 9 is provided in the surface region of the N-drift region 3 on the (first main surface) side. A large number of trenches 5 penetrating the P-type body region 9 are provided on the semiconductor surface of the chip 2, and a trench gate electrode 7 a is embedded in each trench 5 via a gate insulating film 6. . An N-type source region 11 is provided in the semiconductor surface between the trenches 5, and a P-type body contact region 14 is provided in the semiconductor region at the lower end portion of the source contact portion 29a. An interlayer insulating film 8 such as a silicon oxide insulating film is provided on the semiconductor surface on the surface 1a (first main surface) side of the chip 2, and an electrode film such as a metal source electrode 15 is provided thereon. And is electrically connected to the P-type body contact region 14 and the N-type source region 11 through the source contact portion 29a and the like.

  As described above, the active region 12 includes the main active region 12m and the sub active region 12s. In this example, the P type body region 9m of the main active region 12m and the P type body region 9s of the sub active region 12s. The threshold voltages are made different by changing the impurity concentration of each. That is, the impurity concentration of the P-type body region 9s of the sub-active region 12s is set relatively low. Therefore, the structure of the unit cell region 20 (device structure including the impurity concentration) is different between the unit cell region 20m of the main active region 12m and the unit cell region 20s of the sub active region 12s.

  Next, FIG. 6 shows a detailed cross-sectional structure of the unit cell region 20m of the main active region 12m of FIG. As shown in FIG. 6, a back surface metal electrode 4 (for example, a drain electrode) is provided on the back surface 1b side of the N-type semiconductor substrate region 1s of the semiconductor chip 2, and the front surface 1a side of the N-type semiconductor substrate region 1s. Is provided with an N- drift region 3 (a drift region having the first conductivity type). A P-type body region 9m (9) (having the second conductivity type) is provided on the surface 1a side of the N-drift region 3, and in the semiconductor surface region on the surface 1a side of the N-drift region 3, Source region 11 and P-type body contact region 14 are provided. A trench 5 is provided from the surface 1a (first main surface) side of the semiconductor substrate 2 so as to penetrate the P-type body region 9 and reach the N-drift region 3. A trench gate electrode 7a such as polysilicon is embedded through the insulating film 6. An interlayer insulating film 8 is provided on the surface 1a of the semiconductor substrate 2, and a metal source electrode 15 composed of an aluminum-based metal film or the like is provided on the interlayer insulating film 8, via a source contact portion 29a. The source region 11 and the P-type body contact region 14 are electrically connected.

  Next, FIG. 7 shows a detailed cross-sectional structure of the unit cell region 20s of the sub-active region 12s of FIG. As shown in FIG. 7, the geometric structure is the same as in FIG. 6, but the device structure including the impurity concentration is the unit cell region 20m of the main active region 12m and the unit cell region 20s of the sub active region 12s. Is different. That is, the impurity concentration of the P-type body region 9s of the sub-active region 12s is set lower than the impurity concentration of the P-type body region 9m of the unit cell region 20m of the main active region 12m.

  Next, FIG. 8 shows a detailed plan structure of the gate electrode lead-out region R1 in FIG. 2 (the same applies to the main active region 12m and the sub active region 12s). As shown in FIG. 8, the gate polysilicon film 7 constituting the trench gate electrode 7a constitutes a gate lead-out polysilicon wiring portion 7b outside the trench 5, and a metal is formed in the gate contact portion 29b. It is electrically connected to the gate wiring portion 24 (a part of the aluminum-based metal electrode film 30).

3. Description of a manufacturing process of a power MOSFET which is an example of the semiconductor device according to the embodiment of the present application (mainly FIGS. 9 to 20)
In this section, an example of a device manufacturing method for the structure of Section 2 is described. In this example, the threshold voltage is lowered by relatively thinning the same portion of the P-type body region where the threshold voltage should be lowered.

  FIG. 9 is a partial cross-sectional view of the wafer during the manufacturing process (epitaxial growth process) of the part corresponding to FIG. FIG. 10 is a partial cross-sectional view of the wafer during the manufacturing process (trench formation process) of the part corresponding to FIG. FIG. 11 is a partial cross-sectional view of the wafer in the middle of the manufacturing process of the part corresponding to FIG. 5 (gate insulating film formation and polysilicon electrode embedding process). FIG. 12 is a partial cross-sectional view of the wafer during the manufacturing process of the portion corresponding to FIG. 5 (P-type body region introduction step of the main active region). FIG. 13 is a partial cross-sectional view of the wafer in the middle of the manufacturing process of the portion corresponding to FIG. 5 (P-type body region introduction step of the sub-active region). FIG. 14 is a partial cross-sectional view of the wafer in the middle of the manufacturing process (N-type source region introduction process) of the part corresponding to FIG. FIG. 15 is a partial cross-sectional view of the wafer in the middle of the manufacturing process (interlayer insulating film formation and contact hole formation process) of the part corresponding to FIG. FIG. 16 is a partial cross-sectional view of the wafer during the manufacturing process (contact hole extending process) of the part corresponding to FIG. FIG. 17 is a partial cross-sectional view of the wafer in the middle of the manufacturing process (P-type body contact region introduction process) corresponding to FIG. FIG. 18 is a partial cross-sectional view of the wafer in the middle of the manufacturing process of the part corresponding to FIG. 5 (metal film formation and metal source electrode patterning process). FIG. 19 is a partial cross-sectional view of the wafer in the middle of the manufacturing process (back grinding process) of the part corresponding to FIG. FIG. 20 is a partial cross-sectional view of the wafer in the middle of the manufacturing process (back surface metal electrode film forming step) of the portion corresponding to FIG. Based on these, a manufacturing process of a power MOSFET which is an example of the semiconductor device according to the embodiment of the present application will be described.

  First, for example, a 200φ N-type silicon single crystal wafer 1s with a plane orientation of (100) (300 phi, 450 phi, or other diameter wafer may be used as required. The resistivity is, for example, 1 9 to 2 mΩ · cm), depending on the required breakdown voltage (here, the source-drain breakdown voltage is about 30 volts as an example), as shown in FIG. A wafer with an epitaxial layer by depositing a silicon epitaxial layer of N type (for example, phosphorus doping, resistivity is, for example, about 0.1 to 0.3 mΩ · cm) of, for example, about 1.3 to 3.3 micrometers Set to 1.

  Next, as shown in FIG. 10, a silicon oxide film having a thickness of, for example, about 450 nm is formed on almost the entire device surface 1a of the wafer 1 by, for example, low pressure CVD (Chemical Vapor Deposition). The silicon oxide film is patterned by, for example, ordinary lithography to form a trench processing hard mask film 10. Subsequently, the trench processing hard mask film 10 is used for anisotropic dry etching (the etching atmosphere is, for example, a halogen-based gas atmosphere such as HBr). A trench 5 of about 15 micrometers) is formed.

Next, as shown in FIG. 11, a gate oxide film 6 (gate insulating film) of, eg, about 40 nm is formed by thermal oxidation or the like. Subsequently, the gate polysilicon film 7 (for example, the thickness is formed by CVD (Chemical Vapor Deposition), for example, so as to cover almost the entire surface of the semiconductor wafer 1 on the gate oxide film 6 on the surface 1a side and fill the trench 5. About 500 nm). Further, the gate polysilicon film 7 is etched back by dry etching using an etching gas such as SF ₆ . Thereby, the trench gate electrode 7a is formed. The configuration of the gate insulating film 6 may be a thermal oxide film (silicon oxide film by thermal oxidation), a silicon oxide insulating film by CVD, or the like. Further, a part of the whole (a part in contact with the silicon substrate) is a thermal oxide film (for example, a thickness of about 15 nm), and the remaining part (a part not in contact with the silicon substrate) is a silicon oxide insulating film by CVD or the like (for example, , About 25 nm thick).

Next, as shown in FIG. 12, a P-type body region 9m of the main active region 12m is introduced. That is, for example, the P-type body region 9m (P-type well region or channel region) is introduced by ion implantation from the device surface 1a side of the wafer 1 in a state where the sub-active region 12s is covered with a resist film or the like. . As the ion implantation conditions, for example, ion species: boron, implantation energy: about 200 keV, concentration: about 7 × 10 ¹² / cm ² can be exemplified as preferable ones. Thereafter, the resist film that has become unnecessary is removed by ashing or the like.

Next, as shown in FIG. 13, a P-type body region 9s of the sub-active region 12s is introduced. That is, for example, a P-type body region 9s (P-type well region or channel region) is introduced by ion implantation from the device surface 1a side of the wafer 1 with the main active region 12m or the like covered with a resist film or the like. . As the ion implantation conditions, for example, ion species: boron, implantation energy: about 200 keV, concentration: about 2 × 10 ¹² / cm ² can be exemplified as preferable ones. Thereafter, the resist film that has become unnecessary is removed by ashing or the like.

Next, as shown in FIG. 14, for example, the N-type source region 11 is introduced by ion implantation from the device surface 1 a side of the wafer 1. As the ion implantation conditions, for example, ion species: arsenic, implantation energy: about 45 keV, concentration: about 3 × 10 ¹⁵ / cm ² can be exemplified as a preferable one.

  Next, as shown in FIG. 15, an interlayer insulating film 8 is formed on almost the entire device surface 1a of the wafer 1 by, for example, CVD. As the interlayer insulating film 8, for example, an insulating film made of a PSG (Phospho-Silicate Glass) film (for example, a thickness of about 300 nm) can be exemplified as a suitable example. Next, an etching mask pattern such as a resist film is formed on the device surface 1a of the wafer 1 by ordinary lithography, and anisotropic dry etching is performed using the resist mask pattern as a mask to form the source contact portion 29a (contact A hole or contact groove) is opened. Subsequently, the contact groove 29a is extended deeper than the source region 11 by anisotropic dry etching (the etching amount is about 200 nm, for example).

Next, as shown in FIG. 17, a P-type body is formed in the surface region of the semiconductor substrate in a self-aligned manner by, for example, ion-implanting P-type impurities into almost the entire surface from the surface 1a side of the semiconductor wafer 1. Contact region 14 (P-type high-concentration contact impurity region) is introduced. As the ion implantation conditions, for example, ion species: BF ₂ , implantation energy: about 30 keV, and concentration: about 1 × 10 ¹⁵ / cm ² can be exemplified as preferable ones.

  Next, as shown in FIG. 18, a TiW film having a thickness of, for example, about 300 nm (a large portion of titanium in the TiW film is formed by sputtering film formation, for example, on almost the entire surface of the semiconductor wafer 1 on the surface 1a side. Subsequent heat treatment moves to the silicon interface to form silicide and contributes to improving contact characteristics, but these processes are complicated and are not shown in the drawing). In the same manner as described above, an aluminum-based metal film having a thickness of, for example, about 3 μm to 5 μm (several percent silicon) is formed on almost the entire surface of the semiconductor wafer 1 on the TiW film on the surface 1a side by, for example, sputtering. Etc. to which aluminum is added). The TiW film and the aluminum metal film constitute an aluminum metal electrode film 30. Thereafter, by patterning the aluminum-based metal electrode film 30 by normal lithography, as shown in FIG. 2, the metal source electrode 15, the gate wiring portion 24, the guard ring 27, and the like are formed. If necessary, subsequently, as a final passivation film, for example, an organic film containing polyimide as a main component (for example, about 2.5 micrometers in thickness) or the like is applied to almost the entire device surface 1a of the wafer 1. . Further, the final passivation film in portions such as the source pad opening 26 and the gate pad opening 25 in FIG. 2 is removed by ordinary lithography.

  Next, as shown in FIG. 19, by performing a back grinding process on the back surface 1b of the wafer 1, for example, a wafer thickness of about 500 to 900 micrometers is required, for example, about 30 to 300 micrometers. Thin film.

  Next, as shown in FIG. 20, a back electrode 4 (for example, a titanium film / nickel film / gold film from the side closer to the wafer) is formed by, for example, sputtering film formation. Further, the wafer 1 is divided into individual chips 2 (FIG. 2) by dicing or the like.

4). Description of Modification 1 of Active Cell Structure of Power MOSFET which is an Example of Semiconductor Device of One Embodiment of the Present Application (Structure in which Gate Insulating Film is Relatively Thinned in Subactive Region) (Mainly FIG. 21)
In this section, a modification of the structure of the unit cell region 20s of the sub-active region 12s of FIG. 5 will be described. In this example, a relatively low threshold voltage is obtained by reducing the thickness of the gate insulating film in the portion where the threshold voltage is to be lowered to about half of the normal portion.

  FIG. 21 shows a sub-corresponding to FIG. 7 relating to Modification 1 (a structure in which the gate insulating film is relatively thin in the sub-active region) of the active cell structure of the power MOSFET which is an example of the semiconductor device according to the embodiment of the present application. It is a detailed sectional view of a unit cell region 20s of an active region. Based on this, a first modification of the active cell structure of the power MOSFET which is an example of the semiconductor device according to the embodiment of the present application (a structure in which the gate insulating film is relatively thin in the sub-active region) will be described.

  In the example of FIG. 7, the geometric structure is the same, and the threshold voltage of the sub-active region 12s is changed to the main active region by making the impurity concentration of the P-type body region 9 different between the main active region 12m and the sub-active region 12s. Although the threshold voltage is set lower than the threshold voltage of the region 12m, in this example, the impurity concentrations of the P-type body regions 9m and 9s are the same, and the thickness of the gate insulating film 6 of the sub-active region 12s is relative. The threshold voltage is set low by reducing the thickness (for example, a thermal oxide film having a thickness of about 20 nm) (the gate insulating film 6 in the sub-active region 12s is a relatively thin gate insulating film 6t). Here, the configuration of the gate insulating film 6t may be a thermal oxide film (silicon oxide film by thermal oxidation), a silicon oxide insulating film by CVD, or the like. Further, a part of the whole (part in contact with the silicon substrate) is a thermal oxide film (for example, a thickness of about 10 nm), and the remaining part (part not in contact with the silicon substrate) is a silicon oxide insulating film or the like by CVD or the like (for example, Or a laminated film having a thickness of about 10 nm).

  It is possible to make both the impurity concentration of the P-type body region 9 different from the thickness of the gate insulating film 6. However, the process is complicated accordingly. In addition, the thickness of the gate insulating film may be varied to vary the equivalent thickness of the silicon oxide film with respect to the thermal oxide film (silicon oxide film). That is, the threshold voltage may be varied by changing the material of the gate insulating film 6 or a part thereof between the main active region 12m and the sub active region 12s.

5. Description of various modifications relating to the distribution of the sub-active region in the active region of the power MOSFET which is an example of the semiconductor device according to the embodiment of the present application (mainly FIGS. 22 to 28)
In this section, a modified example of the distribution or layout of the sub-active region 12s (region in which the threshold voltage is set relatively low) in the active region 12m described with reference to FIG. 4 will be described.

  FIG. 22 is a top view of a semiconductor chip of a power MOSFET corresponding to FIG. 4 relating to Modification 1 (multiple ring-shaped distribution) relating to the distribution of sub-active regions in the active region of the power MOSFET which is an example of the semiconductor device according to the embodiment of the present application. FIG. 2 is a schematic top view of the entire semiconductor chip showing the distribution of sub-active areas inside the active area in FIG. FIG. 23 is a top view of the semiconductor chip of the power MOSFET corresponding to FIG. 4 relating to Modification 2 (dot dispersion distribution) relating to the distribution of the sub-active region in the active region of the power MOSFET which is an example of the semiconductor device according to the embodiment of the present application. FIG. 2 is a schematic top view of the entire semiconductor chip showing the distribution of sub-active areas inside the active area in FIG. FIG. 24 is a power MOSFET semiconductor corresponding to FIG. 4 relating to the modification 3 (two-dimensional single-connection concentrated distribution) regarding the distribution of the sub-active region in the active region of the power MOSFET which is an example of the semiconductor device according to the embodiment of the present application. It is a semiconductor chip whole upper surface schematic diagram which shows the distribution condition of the subactive area | region inside the active area | region in a chip | tip upper surface. FIG. 25 is a top view of the semiconductor chip of the power MOSFET corresponding to FIG. 4 relating to Modification 4 (multiple single connection distribution) relating to the distribution of the sub-active regions in the active region of the power MOSFET which is an example of the semiconductor device according to the embodiment of the present application. FIG. 2 is a schematic top view of the entire semiconductor chip showing the distribution of sub-active areas inside the active area in FIG. FIG. 26 is a power MOSFET corresponding to FIG. 4 relating to the modification 5 (two-dimensional single connection end concentration distribution) regarding the distribution of the sub-active region in the active region of the power MOSFET which is an example of the semiconductor device according to the embodiment of the present application. It is a semiconductor chip whole upper surface schematic diagram which shows the distribution condition of the subactive area | region inside the active area | region in the semiconductor chip upper surface. FIG. 27 is a power MOSFET corresponding to FIG. 4 relating to the modification 6 (linear extension distribution in the gate extending direction) regarding the distribution of the sub-active region in the active region of the power MOSFET which is an example of the semiconductor device according to the embodiment of the present application. It is a semiconductor chip whole upper surface schematic diagram which shows the distribution condition of the subactive area | region inside the active area | region in the semiconductor chip upper surface. FIG. 28 is a diagram of a power MOSFET corresponding to FIG. 4 relating to Modification 6 (linear distribution distribution in the direction perpendicular to the gate) regarding the distribution of the sub-active region in the active region of the power MOSFET which is an example of the semiconductor device according to the embodiment of the present application. It is a semiconductor chip whole upper surface schematic diagram which shows the distribution condition of the subactive area | region inside the active area | region in a semiconductor chip upper surface. Based on these, various modifications relating to the distribution of the sub-active regions in the active region of the power MOSFET which is an example of the semiconductor device according to the embodiment of the present application will be described.

(1) Multiple ring distribution (mainly FIG. 22):
The layout shown in FIG. 22 is obtained by dividing the ring-shaped sub-active region 12s of FIG. 4 into a plurality of ring-shaped regions. This has the merit that the temperature distribution of the entire active region 12 can be made relatively uniform, like the single ring-shaped sub-active region 12s. That is, the portion corresponding to the sub-active region 12s is on for a long time, so the amount of heat generated is larger than the other portions.

  The number of rings is not limited to two, but may be three or more.

(2) Dot distribution (mainly FIG. 23):
The layout shown in FIG. 23 is a layout in which a large number of dot-like sub-active regions 12s having a relatively small area are dispersed. This layout has an advantage that the temperature distribution of the entire active region 12 can be made more uniform.

(3) Single connection concentration distribution (mainly Figure 24):
In the layout shown in FIG. 24, the sub-active region 12s is a single two-dimensional single connection region provided in the center of the active region 12. Such a centralized arrangement has the advantage that the layout can be made relatively simple.

(4) Multiple single connected distribution (mainly FIG. 25):
The layout shown in FIG. 25 is obtained by dividing the sub-active region 12s, which is a two-dimensional single connection region, into two in the example of FIG. The number of two-dimensional single connected regions is not limited to two, but may be three or more.

(5) Single connection one end concentration distribution (mainly FIG. 26):
The layout shown in FIG. 26 is similar to that shown in FIG. 24, except that the location is not the center of the active region 12 but the end of the active region 12 opposite to the gate pad portion 25. It is a feature. Such a concentrated layout is advantageous when it is desired to treat the sub-active area 12s differently from the main active area 12m in relation to the outside of the active area 12 (see, for example, section 6).

  Further, there is a merit that the interaction between the main active region 12m and the sub active region 12s can be reduced as much as possible.

  Further, the advantage of this layout is that the boundary between both regions can be arranged on the trench gate electrode 7 substantially. That is, there is an advantage that the boundary line between both regions does not pass through the channel region or the source region.

(6) Gate-direction linear dispersion distribution (mainly FIG. 27):
In the layout shown in FIG. 27, a large number of linear regions parallel to the extending direction of the trench gate 7 are dispersed to form sub-active regions 12s. The merit of this layout is that, in addition to uniform temperature, the boundary between both regions can be arranged on the trench gate electrode 7 substantially. That is, there is an advantage that the boundary line between both regions does not pass through the channel region or the source region.

  Usually, the number of trenches of a single chip, that is, the number of cells is around 10,000 (preferably, about several thousand to several tens of thousands). The single element is, for example, a bundle of adjacent cells of about 100 (preferably about several tens to several hundreds).

(7) Linear dispersion distribution in the gate orthogonal direction (mainly FIG. 28):
The layout shown in FIG. 28 is obtained by rotating the layout of FIG. 27 by 90 degrees. This layout has a merit that it is a relatively simple layout and that the temperature distribution of the entire active region 12 can be made uniform.

6). Description of Modification of Whole Chip Structure of Power MOSFET as an Example of Semiconductor Device of One Embodiment of the Present Application (Mainly FIGS. 29 to 32)
The example of this section is a modification of the DC-DC converter shown in FIG. 1 and a modification of the power system active element corresponding to the low-side SW power MOSFET (Qhl). The example in this section is also an application example of the layout of the sub-active region 12s in FIG.

  FIG. 29 is a schematic circuit diagram showing a circuit configuration of a DC-DC converter for a computer corresponding to FIG. 1 for explaining a modification of the whole chip structure of a power MOSFET which is an example of the semiconductor device according to the embodiment of the present application. FIG. 30 is a top view of the entire semiconductor chip of the power MOSFET corresponding to FIG. 2 relating to the low-side SW power MOSFET (Qhl) of FIG. 31 is a schematic top view of the entire semiconductor chip showing the distribution of sub-active regions inside the active region on the top surface of the semiconductor chip of the power MOSFET corresponding to FIG. 30 (two-dimensional single connection end concentration distribution corresponding to FIG. 26). . 32 is a locally enlarged top view of the chip corresponding to the gate electrode lead-out region cutout region R1 in FIGS. 30 and 31. FIG. Based on this, a modification of the whole chip structure of the power MOSFET which is an example of the semiconductor device according to the embodiment of the present application will be described.

  As shown in FIG. 29, in the DC-DC converter, the low-side SW power MOSFET (Qhl) is divided into a part Qhlm corresponding to the main active region 12m and a part Qhls corresponding to the sub active region 12s in terms of circuit. ing. An additional resistor PR is inserted into the gate electrode (gate terminal) of the portion Qhls corresponding to the sub-active region 12s (other circuit configuration is exactly the same as that of FIG. 1). . That is, each of the gate pad 25 and the sub active region 12s is compared with the first current path P1 between the gate pad 25 and each gate electrode of the main active region 12m (the gate electrode of the portion Qhlm corresponding to the main active region). Since an additional resistance component PR is inserted in the second current path P2 between the gate electrodes (the gate electrode of the portion Qhls corresponding to the sub-active region), the resistance value of the second current path P2 (for example, (About 5 to 20Ω) is larger than the resistance value of the first current path P1 (for example, about 1 to 2Ω). In other words, the gate resistance of the portion Qhls corresponding to the sub-active region is higher than the gate resistance of the portion Qhlm corresponding to the main active region.

  By the insertion of this additional resistor PR, the gate of the portion Qhls corresponding to the sub-active region 12s in the low-side SW power MOSFET (Qhl) becomes unstable along with the original low threshold voltage. That is, when the high-side SW power MOSFET (Qhh) is turned on, the portion Qhls corresponding to the sub-active region 12s in the low-side SW power MOSFET (Qhl) is self-turned on, so that the low-side SW power MOSFET (Qhl) is partially Since the low-side SW power MOSFET (Qhl) is turned on as a whole, the drain voltage can be prevented from jumping up.

  Here, in the case of this example, the low-side SW power MOSFET (Qhl) has a single gate terminal as an external terminal, and the gate branches in the inside. This is advantageous in that it can be handled as a normal power MOSFET from the outside. However, the external gate terminal can actually be divided into two. In that case, an additional resistor PR can be installed outside.

  Next, the device structure of the MOSFET (Qhl) in which such an additional resistor PR is inserted will be described with reference to FIGS. FIG. 30 shows an overall top view of the chip corresponding to FIG. The difference from FIG. 2 is that the internal division structure of the active region 12 is displayed. That is, the layout of the sub active area 12s of the active area 12 corresponds to the layout of FIG.

  Next, FIG. 31 shows a layout of main elements on the top surface of the chip such as the main active region 12m and the sub active region 12s on the top surface of the chip corresponding to FIG. As shown in FIG. 31, in this example, as in FIG. 26, the active region 12 is divided into a main active region 12 m and a sub active region 12 s, and the sub active region 12 s is active on the side opposite to the gate pad portion 25. A two-dimensional single connected region (rectangular region) occupying the region 12 is formed, and the remaining two-dimensional single connected region is the main active region 12m. Further, the metal gate wiring portion 24 has a U-shape along the three sides of the active region 12, and a gate lead-out polysilicon wiring portion 7b (shown here) having a similar shape is formed below the metal gate wiring portion 24. The metal gate wiring portion 24 and the gate lead-out polysilicon wiring portion 7b are mutually connected in a number of gate contact portions 29b in a portion close to the main active region 12m. Are connected to each other, but are not connected to each other in the vicinity of the sub-active region 12s.

  Next, an enlarged plan view of the gate electrode lead-out region R1 in FIGS. 30 and 31 is shown in FIG. As shown in FIG. 32, the additional resistance portion 34 substantially corresponds to (or forms part of) the additional resistance component PR of FIG. As for the additional resistance portion 34, a desired resistance value may be obtained by, for example, narrowing the width of the doped polysilicon film as in this example. High resistance may be formed by ion implantation of a type impurity. In that case, the area occupied by the additional resistance portion 34 can be reduced. Further, when the gate polysilicon film 7 is formed not by the doped polysilicon film but by the non-doped polysilicon film and the resistance value is controlled later by ion implantation, only the additional resistance portion 34 may be reduced in implantation concentration.

  In this example, the low threshold voltage region and the destabilization of a part of the gates by gate division are used together, but the threshold voltage of the sub active region 12s may be the same as that of the main active region 12m. In that case, there is an advantage that the process can be simplified.

7). Description of application to other active devices such as each embodiment described in the present application (mainly FIGS. 33 to 36)
The examples described so far have been specifically described mainly using power MOSFETs as an example, but it is needless to say that the concept of each embodiment can be applied to all insulated gate power system active elements. In addition to the power MOSFET, the insulated gate power system active element includes, for example, an IGBT (Insulated gate Bipolar Transistor), an insulated gate power system active element, a CMOS (Complementary Metal Oxide Semiconductor), or a CMIS (Complementary Semiconductor Metal). There are an integrated circuit and the like and an integrated power device integrated on a single chip. These will be briefly described below.

  FIG. 33 is a terminal layout diagram of an IGBT which is an example of another active device to which the embodiments and the like described in the present application are applied. FIG. 34 is a unit cell cross-sectional view of an IGBT which is an example of another active device to which the embodiments and the like described in the present application corresponding to FIG. 6 are applied. FIG. 35 is a chip top surface layout diagram of an integrated power supply element in which main parts of the circuit elements in FIG. 1 are integrated on a single chip. 36 is a chip partial schematic cross-sectional view corresponding to the Y-Y ′ cross section of FIG. 35. Based on these, application to other active devices such as each embodiment described in the present application will be described.

(1) Application to IGBT (mainly FIG. 33 and FIG. 34):
As shown in FIG. 33, each terminal of the IGBT is normally referred to as a circuit name in a pin-corresponding relationship with the bipolar transistor. The terminal corresponding to the base is the gate terminal G, the terminal corresponding to the emitter is the emitter terminal E, and the collector. The terminal corresponding to is the collector terminal C. From the structural and operational viewpoint, it is natural that the emitter terminal E is called the source terminal as a structural name.

  That is, as shown in FIG. 34, the IGBT is between the back surface 1b side of the N-type semiconductor substrate region 1s of the same portion R2 and the back surface metal electrode 4 (collector electrode) structurally identical to the power MOSFET described in FIG. The P-type collector region 18 is inserted. Therefore, in the structural name, the source system portion, that is, the source region 11, the N-type substrate source region 11a, the poly-Si source region 11b, the metal source electrode 15, the source pad portion 26, the source contact portion 29a, etc. Can be used. Since the gate system part corresponds as it is, it can be used as it is.

(2) Application to devices in which power system active elements and the like are integrated (mainly FIGS. 35 and 36):
FIG. 35 shows an example of the top surface layout of the chip 2 of a one-chip DC-DC converter for personal computers (corresponding to FIG. 1), which is an example of an integrated power device. As shown in FIG. 35, the device surface 1a of the chip 2 has a high side SW power MOSFET (Qhh), a low side SW power MOSFET (Qhl), a high side driver 51 for driving the high side SW power MOSFET (Qhh), and a low side. A low side driver 52 for driving the SW power MOSFET (Qhl), a control circuit unit 53 for controlling the high side driver 51 and the low side driver 52 (for example, the circuit has a CMOS circuit configuration), etc. are laid out. . Here, the high-side SW power MOSFET (Qhh) is specifically one of the power system active elements (insulated gate type power system active elements) described in FIG. 6, FIG. 7, FIG. 21, FIG. is there. Note that the low-side SW power MOSFET (Qhl) can also be composed of any of these.

  Next, a partial cross section (Y-Y 'cross section) of the active region 12 of the high side SW power MOSFET (Qhh) and the CMOS control circuit section 53 will be described with reference to FIG.

  As shown in FIG. 36, the one-chip type DC-DC converter is made on, for example, a P-type semiconductor substrate 1p. That is, for example, an N-epitaxial region 1e is provided on the surface 1a (first main surface or device surface) side of the P-type semiconductor substrate 1p (P-type semiconductor substrate region) by epitaxial growth or the like. An N + buried region 19 is provided near the boundary between the epitaxial region 1e and the P-type semiconductor substrate region 1p. A P + element isolation region 22 is provided in the N− epitaxial region 1e such as between the CMOS region Rc and the power MOS region Rh, and a field insulating film 23 (LOCOS type or STI type insulating film) is provided.

  Next, each device area will be described. In the region where the power MOS region Rh, that is, the power MOSFET (Qh) is formed, an N + drain extraction region 21 for extracting a drain or the like to the upper surface 1a of the chip 2 is provided, and a semiconductor on the upper surface 1a of the chip 2 is provided. In the surface region, a trench 5, a gate insulating film 6, a P-type body region 9, a source region 11, a P-type body contact region 14 and the like are provided.

  On the other hand, in the CMOS region Rc, a P-well region 31p and an N-well region 31n are provided below the surface of the N-epitaxial region 1e on the upper surface 1a side of the chip 2. A P-type source / drain region 32 is provided. Further, on the upper surface 1a of the chip 2, together with the N-type and P-type source / drain regions 32, a gate electrode 33 constituting an N-channel MOSFET (Qn) and a P-channel MOSFET (Qp) is provided. ing.

8). General consideration of the present application and supplementary explanation regarding each embodiment (mainly FIG. 1, FIG. 4, FIG. 29 and FIG. 37)
FIG. 37 is an effect explanatory diagram showing the occupancy ratio dependency of the jumping voltage and the power loss for explaining the effectiveness of the semiconductor device of each embodiment of the present application in the sub-active region. Based on this, a general consideration of the present application and a supplementary explanation regarding each embodiment will be given.

  The basic concept of each embodiment described so far is based on the consideration as shown in FIG. That is, generally, the relationship between the power loss and the jumping voltage of a power system active element (low-side SW power MOSFET) such as a power MOSFET in a DC-DC converter or the like is a trade-off relationship. However, as shown in FIG. 37, for example, if a portion having a low threshold voltage is provided in a part of the power MOSFET (relatively narrow region compared to the whole), the power loss does not increase so much. It can be seen that there is a portion where a relatively large improvement can be obtained with respect to the jumping voltage. In other words, in some way, a part of the power MOSFET (a part of the whole cell, or at least a part of the part of the cell) is compared with the other part to make it easy to turn on. The idea is to reduce the jumping voltage caused by a steep rise in exchange for power loss.

  One way to achieve this is to create a low threshold voltage in part of the low-side SW power MOSFET (Qhl) as described in sections 2-5. In this way, when the low-side SW power MOSFET (Qhl) is turned on, first, the portion with the lower threshold voltage is turned on first, and then the main portion is turned on. Is reduced.

  Here, the threshold voltage (second threshold voltage) of the portion Qhls corresponding to the sub-active region based on the threshold voltage (first threshold voltage) of the portion Qhlm corresponding to the main active region of the low-side SW power MOSFET (Qhl). ) Is generally 45% or more and 85% or less of the reference value. Further, when it is necessary to further reduce the loss, the preferable range of the threshold voltage is 55% or more and 75% or less of the reference value.

  Further, a suitable range (area ratio) of the area ratio of the sub-active area 12s based on the area of the entire active area 12 is 1% or more and 20% or less. This is because power loss increases rapidly when the area ratio exceeds 20%.

  Further, when it is necessary to more reliably suppress the jumping voltage, the preferable range of this ratio is 5% or more and 20% or less. For example, when the area ratio is about 5% to 10%, the power loss rate is estimated to be about 1 to 3%.

  On the other hand, another idea is that some gates of the low-side SW power MOSFET (Qhl) are separated from other gates, and an additional resistor is added thereto to destabilize the capacitive coupling. This is to induce self-turn-on. Self-turn-on is a very harmful phenomenon when it occurs in the entire low-side SW power MOSFET (Qhl), but even if it occurs in a limited relatively small part, it does not pose a problem in itself.

  As a method for reducing the jump voltage, a method of incorporating an SBD in the chip of the low-side SW power MOSFET (Qhl) (SBD built-in method) is known, but the SBD built-in method suppresses self-turn-on and the jump voltage. However, there is a demerit that greatly increases the chip area.

  However, the present invention does not exclude the combined use of each embodiment of the present invention and the SBD built-in method.

9. Summary The invention made by the present inventor has been specifically described based on the embodiments. However, the present invention is not limited thereto, and it goes without saying that various changes can be made without departing from the scope of the invention.

  For example, in the above-described embodiment, the N channel device is mainly formed on the upper surface of the N epitaxial layer on the N + silicon single crystal substrate. However, the present invention is not limited thereto, and P + silicon A P channel device may be formed on the upper surface of the N epitaxial layer on the single crystal substrate.

  In the above-described embodiment, the power MOSFET has been specifically described as an example. However, the present invention is not limited thereto, and it is needless to say that the present invention can be applied to a bipolar transistor (including IGBT). Needless to say, the present invention can also be applied to a semiconductor integrated circuit device incorporating such power MOSFETs, bipolar transistors, and the like.

  In the above-described embodiments, devices mainly made on a silicon-based semiconductor substrate have been specifically described. However, the present invention is not limited thereto, and a GaAs-based semiconductor substrate, a silicon carbide-based semiconductor substrate, and a silicon nitride. Needless to say, the present invention can be applied almost as it is to a device made on a ride-type semiconductor substrate.

  In the above-described embodiment, the gate electrode or the like that uses a polysilicon film has been specifically described. However, the present invention is not limited thereto, and may be a polycide film, a silicide film, or the like. Needless to say.

  Further, in the above-described embodiment, the metal electrode and the aluminum-based metal film as the main constituent film have been specifically described. However, the present invention is not limited thereto, and titanium, tungsten, and the like are used. Needless to say, the present invention can also be applied to a film using a refractory metal film or a gold film as a main component film of a metal electrode.

  Further, in the above-described embodiment, the drift region constituted by a single conductivity type region has been specifically described. However, the present invention is not limited to this, and a superconducting region in which the opposite conductivity type regions are alternately replaced is described. Needless to say, the present invention can also be applied to one having a super-junction type drift region.

1 Wafer 1a Wafer or semiconductor chip surface (first main surface or device surface)
1b Wafer or semiconductor chip surface (second main surface)
1e N-epitaxial region 1p P-type semiconductor substrate region 1s N-type semiconductor substrate region 2 semiconductor chip 3 N-drift region 4 back metal electrode 5 trench 6 gate insulating film 6t relatively thin gate insulating film 7 gate polysilicon film (gate) electrode)
7a Trench gate electrode 7b Gate lead polysilicon wiring part 8 Interlayer insulating film 9 P-type body region 9m P-type body region of main active region 9s P-type body region of sub-active region 10 Hard mask film for trench formation 11 N-type source region 12 Active region 12m Main active region 12s Sub active region 14 P type body contact region 15 Metal source electrode 18 P type collector region 19 N + buried region 20 Unit cell region 20m Unit cell region of main active region 20s Unit cell region of sub active region 21 N + drain extraction region 22 P + element isolation region 23 field insulating film 24 metal gate wiring portion 25 gate pad portion 26 source pad portion 27 guard ring 28 edge termination region 29a source Contact portion 29b Gate contact portion 30 Aluminum-based metal electrode film 31p P-well region of CMOS region 31n N-well region of CMOS region 32 Source / drain region of CMOS region 33 Gate electrode of CMOS region 34 Additional resistance portion 50 DC-DC converter DESCRIPTION OF SYMBOLS 51 High side driver 52 Low side driver 53 Control circuit part 54 Output smoothing inductor 55 Output smoothing capacitor 101 System in package 102 High side MOSFET semiconductor chip 103 Low side MOSFET semiconductor chip 106 Driver chip 107, 108, 109, 110 Bonding wire ( Connection wiring)
115, 116, 117 Die pad (tab)
118 Source Pad 119 Gate Pad 120 Source Pad 121 Gate Pad 122 Interconnection Source Pad 123, 124 Bonding Wire (Connection Wiring)
127 Power ground terminal 128 Logic ground terminal BP Driver chip bonding pad C Collector terminal E Emitter terminal G Gate terminal P1 First current path P2 Second current path PR Additional resistance component Qh Power MOSFET
Qhh High-side SW power MOSFET
Qhl Low-side SW power MOSFET
Part corresponding to the main active area of the Qhlm low-side SW power MOSFET (standard threshold voltage part)
Qhls Low-side SW power MOSFET corresponding to the sub-active region (relatively low threshold voltage)
N-channel MOSFET in Qn CMOS region
P-channel MOSFET in Qp CMOS region
R1 Gate electrode lead-out region R2 Structurally the same as the power MOSFET R3 Main and sub active region boundary peripheral region Rc CMOS region Rh Power MOS region S Source terminal Vdd Power supply output terminal Vin DC power supply Vss Ground terminal

Claims (12)

Semiconductor devices including:
(A) a semiconductor substrate having a first main surface and a second main surface;
(B) a drift region provided in the semiconductor substrate and having a first conductivity type;
(C) an active region provided on the first main surface;
(D) a plurality of unit cell regions provided in the active region in plan view;
Here, each unit cell region has the following:
(D1) a body region provided in the semiconductor substrate on the first main surface side of the drift region and having a second conductivity type opposite to the first conductivity type;
(D2) a gate insulating film provided in a surface region of the semiconductor substrate on the first main surface side so as to be in contact with the body region;
(D3) a gate electrode provided in the surface region of the semiconductor substrate via the gate insulating film;
(D4) an interlayer insulating film provided on the gate electrode;
(D5) A source region having the first conductivity type provided on the first main surface side surface of the semiconductor substrate so as to be in contact with the gate insulating film;
(D7) a metal source electrode provided on the first main surface of the semiconductor substrate so as to cover the interlayer insulating film,
Here further, the active area comprises:
(C1) a main active region having a first threshold voltage and a first occupied area;
(C2) A sub-active region having a second threshold voltage lower than the first threshold voltage and a second occupied area smaller than the first occupied area.     In the semiconductor device according to the item 1, the ratio of the second occupied area to the sum of the first occupied area and the second occupied area is 1% or more and 20% or less.     In the semiconductor device according to the item 1, the ratio of the second occupied area to the sum of the first occupied area and the second occupied area is 5% or more and 20% or less.     In the semiconductor device according to the item 2, the difference between the first threshold voltage and the second threshold voltage is caused by an impurity concentration of the body region in the main active region and the sub active region.     In the semiconductor device of the item 2, the difference between the first threshold voltage and the second threshold voltage is caused by a difference in thickness of the gate insulating film in the main active region and the sub active region.     In the semiconductor device according to the item 3, the planar shape of the sub-active region is a single or a plurality of ring shapes.     In the semiconductor device of the item 3, the planar shape of the sub-active region is a plurality of dot shapes.     In the semiconductor device according to the item 3, the sub-active region forms a single region as a two-dimensional single connection region.     In the semiconductor device of the item 3, the sub-active region is a plurality of linear regions.     In the semiconductor device of the item 1, the value of the second threshold voltage is 45% or more and 85% or less of the value of the first threshold voltage.     In the semiconductor device of the item 1, the value of the second threshold voltage is 55% or more and 75% or less of the value of the first threshold voltage. The semiconductor device according to the item 1, further includes the following:
(E) a gate pad provided on the first main surface of the semiconductor substrate;
(F) a first current path between the gate pad and each gate electrode in the main active region;
(G) a second current path between the gate pad and each gate electrode in the sub-active region;
Here, the resistance value of the second current path is larger than the resistance value of the first current path.

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